JP2003163370A - Method of manufacturing semiconductor crystal - Google Patents

Method of manufacturing semiconductor crystal

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Publication number
JP2003163370A
JP2003163370A JP2002210805A JP2002210805A JP2003163370A JP 2003163370 A JP2003163370 A JP 2003163370A JP 2002210805 A JP2002210805 A JP 2002210805A JP 2002210805 A JP2002210805 A JP 2002210805A JP 2003163370 A JP2003163370 A JP 2003163370A
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Japan
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semiconductor crystal
layer
crystal
seed layer
semiconductor
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JP2002210805A
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Japanese (ja)
Inventor
Toshio Hiramatsu
Seiji Nagai
Yuuta Tezeni
Kazuyoshi Tomita
Shiro Yamazaki
一義 冨田
史郎 山崎
敏夫 平松
雄太 手銭
誠二 永井
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Toyoda Gosei Co Ltd
Toyota Central Res & Dev Lab Inc
株式会社豊田中央研究所
豊田合成株式会社
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Priority to JP2001-274376 priority
Application filed by Toyoda Gosei Co Ltd, Toyota Central Res & Dev Lab Inc, 株式会社豊田中央研究所, 豊田合成株式会社 filed Critical Toyoda Gosei Co Ltd
Priority to JP2002210805A priority patent/JP2003163370A/en
Publication of JP2003163370A publication Critical patent/JP2003163370A/en
Application status is Pending legal-status Critical

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Abstract

<P>PROBLEM TO BE SOLVED: To obtain a high-quality semiconductor crystal independent of a base substrate. <P>SOLUTION: A seed layer which consists of a GaN layer 103 (a second layer of the seed layer) and an AlN buffer layer 102 (a first layer of the seed layer) is formed on a sapphire substrate 101. The surface of the seed layer is etched into a stripe geometry having a stripe width (the seed layer width S) nearly equal to 5 μm, a wing width W nearly equal to 15 μm, and a depth of about 0.5 μm. After the etching, mesas having a nearly rectangular cross-sectional shape are formed, and the remainder of erosion having the multilayer seed layer in their flat top parts are disposed at a cycle L nearly equal to 20 μm, exposing part of the sapphire substrate 101 in a valley of each wing. The ratio S/W of the seed width to the wing is preferably about 1/3 to 1/5. Then, a semiconductor crystal A is grown to 50 μm or larger, and then separated from the base substrate to obtain a high-quality monocrystal independent of the base substrate. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は、下地基板上に III BACKGROUND OF THE INVENTION [0001] [Technical Field of the Invention The present invention is, III on a base substrate
族窒化物系化合物半導体から成る半導体結晶を成長させ、下地基板から独立した良質の半導体結晶を得る方法に関する。 Grown semiconductor crystal made of Nitride-based compound semiconductor, to a method of obtaining a high-quality semiconductor crystal which is independent from the underlying substrate. また、本発明は、LED等に代表される各種の半導体素子の結晶成長基板の製造等に適用することができる。 Further, the present invention can be applied to the production or the like of the crystal growth substrate for various semiconductor elements typified by LED or the like. 【0002】 【従来の技術】下地基板上に III族窒化物系化合物半導体から成る半導体結晶を成長させ、その下地基板から独立した半導体結晶を得る従来技術としては、例えば、公開特許公報「特開平7−202265: III族窒化物半導体の製造方法」に記載されている湿式エッチングによる方法や、或いは、サファイア基板上にHVPE法等により厚膜のGaN(目的の半導体結晶)を成長させ、レーザ照射や研磨等によりサファイア基板を取り除く方法等が一般に知られている。 [0002] grown semiconductor crystal made of Group III nitride-based compound semiconductor on a base substrate, as the prior art to obtain the independent semiconductor crystal from the starting substrate, for example, Patent Publication "JP 7-202265: a method by wet etching as described in preparation method "group III nitride semiconductor, or grown thick film GaN by HVPE method or the like on a sapphire substrate (object of semiconductor crystal), laser irradiation and a method of removing the sapphire substrate are generally known by or polishing. 【0003】 【発明が解決しようとする課題】しかしながら、これらの従来技術においては、下地基板(例:サファイア等) [0003] [0005] However, in these prior art, the underlying substrate (e.g. sapphire)
と III族窒化物系化合物半導体との間の熱膨張率差や格子定数差等に起因して、結晶成長工程完了後の降温時等に目的の単結晶(例:GaN等)に応力が加わり、目的の単結晶に転位やクラックが多数発生すると言う問題がある。 And due to the difference in coefficient of thermal expansion and lattice constant difference or the like between the Group III nitride-based compound semiconductor, a single crystal of interest upon cooling or the like after the crystal growth process completed: stress is applied to (e.g. GaN, etc.) , there is a problem that the dislocations and cracks in the single crystal of the desired number occurs. 【0004】例えば上記の様な従来技術を用いた場合、 [0004] If, for example, using such conventional techniques described above,
サファイアや或いはシリコン(Si)等から形成された下地基板上に窒化ガリウム(GaN)等の窒化物半導体を結晶成長させ、その後常温まで冷却すると、熱膨張係数差や或いは格子定数差等に起因する応力により窒化物半導体層に転位やクラックが多数入る。 Sapphire, or silicon (Si) or the like a nitride semiconductor such as gallium nitride (GaN) is grown on the formed base substrate from caused thereafter when cooled to room temperature, the thermal expansion coefficient difference and or the lattice constant difference, etc. dislocations and cracks in the nitride semiconductor layer enters a number by stress. 【0005】この様に、成長層(窒化物半導体層)に転位やクラックが多数入ると、その上にデバイスを作製した場合に、デバイス中に格子欠陥や転位、変形、クラック等が多数生じる結果となり、デバイス特性の劣化を引き起こす原因となる。 [0005] Thus, the dislocations and cracks in the grown layer (nitride semiconductor layer) enters a number, the result of the case of manufacturing a device thereon, lattice defects and dislocations in the device, variations, occurring cracks number , and becomes a cause of deterioration of the device characteristics. また、下地基板を除去し、成長層のみを残して独立した基板(結晶)を得ようとする場合、上記の転位やクラック等の作用により、大面積のものが得られない。 Moreover, the base substrate is removed, in order to obtain a substrate grown only independently leaving layer (crystalline), by the action such as the dislocation and cracks, not be obtained in a large area. また、厚膜成長の場合には、成長中にさえ目的の単結晶にクラックが入り、部分的に小片剥離が発生する等の問題が非常に生じ易い。 In the case of a thick film growth, cracks are for the purposes of the single crystal even during the growth, partially like pieces peeling occurs a problem is very liable to occur. 【0006】本発明は、上記の課題を解決するために成されたものであり、その目的は、下地基板から独立した良質の半導体結晶を得ることである。 [0006] The present invention has been made to solve the above problems, its object is to obtain a high-quality semiconductor crystal which is independent from the underlying substrate. 【0007】 【課題を解決するための手段、並びに、作用及び発明の効果】上記の課題を解決するためには、以下の手段が有効である。 [0007] SUMMARY OF as well as the effect of the action and the Invention In order to solve the aforementioned problem, the following measures are effective. 即ち、第1の手段は、下地基板上に III族窒化物系化合物半導体から成る半導体結晶を成長させ、その下地基板から独立した良質の半導体結晶Aを得る製造工程において、下地基板上に単層又は複層のシード層を積層するシード積層工程と、下地基板のシード層が成膜されている側の面の一部を化学的若しくは物理的に侵食処理して、シード層を下地基板上に部分的或いは分散的に残留させる侵食残骸部形成工程と、シード層の侵食残骸部の露出面を半導体結晶Aが結晶成長し始める最初の結晶成長面とし、この結晶成長面が結晶成長により各々互いに連結されて少なくとも一連の略平面に成長するまで半導体結晶Aを結晶成長させる結晶成長工程と、侵食残骸部を破断することにより半導体結晶Aと下地基板とを分離する分離工程とを設ける That is, single-layer first means, to grow a semiconductor crystal made of Group III nitride-based compound semiconductor on a base substrate, in the manufacturing process to obtain a semiconductor crystal A of high quality which is independent from the underlying substrate, on a base substrate or a seed laminating step of laminating a seed layer of a double layer, a portion of the surface where the seed layer of the base substrate is deposited by chemical or physical erosion process, a seed layer on an underlying substrate partially or distributively erosion debris portion forming step of the residual, the first crystal growth surface of the semiconductor crystal a of the exposed surface of the erosion debris portion of the seed layer begins to crystal growth, each to each other by the crystal growth surface crystal growth a crystal growth step of crystal growing a semiconductor crystal a to grow to at least a series of substantially planar coupled, provided a separation step of separating the semiconductor crystal a and the base substrate by breaking erosion debris portion ことである。 It is. 【0008】ただし、ここで言う「 III族窒化物系化合物半導体」一般には、2元、3元、又は4元の「Al [0008] However, in this case it refers to the "Group III nitride compound semiconductor" generally, binary, ternary, or quaternary "Al
1-xy Ga y In x N;0≦x≦1,0≦y≦1,0≦ 1-xy Ga y In x N ; 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦
1−x−y≦1」成る一般式で表される任意の混晶比の半導体が含まれ、更に、p型或いはn型の不純物が添加された半導体も、本明細書の「 III族窒化物系化合物半導体」の範疇とする。 1-x-y ≦ 1 "includes semiconductors any mixing ratio represented by the general formula comprising, further, even a semiconductor with a p-type or n-type impurity is added," group III nitride hereof the category of object-based compound semiconductor. " また、上記の III族元素(Al, Further, the group III elements (Al,
Ga,In)の内の少なくとも一部をボロン(B)やタリウム(Tl)等で置換したり、或いは、窒素(N)の少なくとも一部をリン(P)、砒素(As)、アンチモン(Sb)、ビスマス(Bi)等で置換したりした半導体等もまた、本明細書の「 III族窒化物系化合物半導体」の範疇とする。 Ga, In) or replaced with boron (B), thallium (Tl) or the like at least a portion of the, or nitrogen (N), phosphorus (P) at least a portion of, arsenic (As), antimony (Sb ), semiconductors or replaced with bismuth (Bi) or the like, etc. are also a category of "group III nitride compound semiconductor" in this specification. また、上記のp型の不純物としては、例えば、マグネシウム(Mg)や、或いはカルシウム(Ca)等を添加することができる。 As the p-type impurity of the above, for example, it can be added magnesium (Mg) or, or calcium (Ca) or the like. また、上記のn In addition, the above-mentioned n
型の不純物としては、例えば、シリコン(Si)や、硫黄(S)、セレン(Se)、テルル(Te)、或いはゲルマニウム(Ge)等を添加することができる。 The type impurity, for example, silicon (Si), sulfur (S), selenium (Se), can be added tellurium (Te), or germanium (Ge) or the like. また、 Also,
これらの不純物は、同時に2元素以上を添加しても良いし、同時に両型(p型とn型)を添加しても良い。 These impurities may be added two or more elements simultaneously, it may be added both types (p-type and n-type) at the same time. 【0009】また、上記の下地基板の材料としては、サファイア、スピネル、酸化マンガン、酸化ガリウムリチウム(LiGaO 2 )、硫化モリブデン(MoS)、シリコン(Si)、炭化シリコン(SiC)、AlN,G Further, as the material of the underlying substrate, sapphire, spinel, manganese oxide, gallium oxide lithium (LiGaO 2), molybdenum sulfide (MoS), silicon (Si), silicon carbide (SiC), AlN, G
aAs,InP,GaP,MgO,ZnO、又はMgA aAs, InP, GaP, MgO, ZnO, or MgA
24等を用ることができる。 The l 2 O 4 or the like can Yeoul. 即ち、これらの下地基板の材料としては、 III族窒化物系化合物半導体の結晶成長に有用な、公知或いは任意の結晶成長基板を使用することができる。 That is, as the material of these base substrate, useful in the Group III nitride compound semiconductor crystal growth, it is possible to use known or any crystal growth substrate. 【0010】尚、下地基板の材料は、GaNとの反応、 [0010] In addition, the material of the base substrate, the reaction of GaN,
熱膨張係数差、及び高温での安定性の観点から、サファイアを選択することがより望ましい。 Thermal expansion coefficient difference, and from the viewpoint of the stability at high temperatures, it is more desirable to select a sapphire. 【0011】多数の侵食残骸部を有する下地基板上に I [0011] I on the base substrate having a large number of erosion debris part
II族窒化物系化合物より成る目的の半導体結晶Aを成長させる場合、下地基板と半導体結晶Aとは侵食残骸部のみで接続される。 When growing a semiconductor crystal A of interest consisting of II-nitride compound, the starting substrate and the semiconductor crystal A is connected only by the erosion debris section. このため、半導体結晶Aの厚さを十分に大きくすれば、内部応力または外部応力がこの侵食残骸部に集中的に作用し易くなる。 Therefore, if sufficiently large thickness of the semiconductor crystal A, internal stress or external stress is likely to act intensively on the erosion debris section. その結果、特にこれらの応力は、侵食残骸部に対する剪断応力等として作用し、この応力が大きくなった時に、侵食残骸部が破断する。 As a result, in particular, these stresses act as shear stress or the like against erosion debris unit, when this stress is increased, the erosion debris unit is broken. 【0012】即ち、上記の本発明の手段に従ってこの応力を利用すれば、容易に下地基板と半導体結晶Aとを分離(剥離)することが可能となる。 Namely, given the benefit of this stress according means of the present invention described above, it becomes possible to easily and underlying substrate and the semiconductor crystal A separate (peel). この手段により、下地基板から独立した単結晶(半導体結晶A)を得ることができる。 This means, it is possible to obtain separate single crystal from the starting substrate (semiconductor crystal A). 【0013】また、上記の様な侵食残骸部を形成し、横方向成長させることにより、下地基板と半導体結晶Aとの格子定数差に基づく歪が生じ難くなり、「下地基板と半導体結晶Aの間の格子定数差に基づく応力」が緩和される。 Further, to form the erosion debris portion such as described above, by lateral growth, distortion is unlikely to occur based on the difference in lattice constant between the underlying substrate and the semiconductor crystal A, "the starting substrate and the semiconductor crystal A stress "is relaxed based on the difference in lattice constant between. このため、所望の半導体結晶Aが結晶成長する際に、成長中の半導体結晶Aに働く不要な応力が抑制されて転位やクラックの発生密度が低減される。 Therefore, when the desired semiconductor crystal A is crystal-grown, generation density of dislocations and cracks unnecessary stress can be suppressed to act on the semiconductor crystal A in growth is reduced. 【0014】尚、上記の「多数の侵食残骸部」とは、少なくとも例えば図1の様な垂直断面から見る限りにおいて「多数」であれば良く、その平面形状としては一つに繋がっていても差し支えない。 [0014] The above and "a large number of erosion debris portion" may be a "large number" in as far as at least example such vertical section of Figure 1, even if connected to one as its planar shape no problem. したがって、例えば、一次元的な一繋がりの矩形波形状や急峻なsin波形状、 Thus, for example, a rectangular wave of one-dimensional single monolithic shapes and steep sin wave shape,
或いは渦巻き状等にストライプ(侵食残骸部)の平面形状を形成しても、本発明の作用・効果を得ることは可能である。 Or even to form a planar shape of the stripe (erosion debris section) in a spiral shape or the like, it is possible to obtain the operation and effect of the present invention. また、ストライプ形状に限らず、略円形、略楕円形、略多角形、又は略正多角形等の任意の島型の形状等に上記の侵食残骸部の平面形状を形成しても、勿論本発明の作用・効果を得ることは可能である。 Further, not limited to the stripe shape, substantially circular, substantially oval, substantially polygonal, or even to form a planar shape of the erosion debris portion substantially any islands shape of such a regular polygon, of course the present possible to obtain the actions and effects of the invention are possible. 【0015】また、下地基板と半導体結晶Aとを分離(剥離)する際に、下地基板側に半導体結晶Aの一部が残っても良いし、或いは、半導体結晶A側に下地基板の一部(例:侵食残骸部の破断残骸)が残っても良い。 Furthermore, when separating (peeling) of the starting substrate and the semiconductor crystal A, it may remain part of the semiconductor crystal A underlying substrate side, or a portion of the underlying substrate to the semiconductor crystal A side (example: broken debris of erosion debris portion) may remain. 即ち、上記の分離工程は、これらの材料の一部の残骸を皆無とする様な各材料の完全な分離を前提(必要条件)とするものではない。 That is, the separation step is not intended to complete separation of each such as to eradicate some debris of these materials materials assuming (necessary condition). 【0016】また、第2の手段は、上記の第1の手段の結晶成長工程において、半導体結晶Aの膜厚を50μm Further, second means, 50 [mu] m in the crystal growth process of the first means described above, the thickness of the semiconductor crystal A
以上にすることである。 It is to be at least. 結晶成長させる目的の半導体結晶Aの厚さは、約50μm以上が望ましく、この厚さが厚い程、半導体結晶Aを強固にでき、更に、上記の剪断応力を上記の侵食残骸部に集中させ易くなる。 The thickness of the semiconductor crystal A purpose of crystal growth is preferably not less than about 50 [mu] m, as the thickness is thick, can the semiconductor crystal A strong, further, easily the shear stress is concentrated on the erosion debris part of the Become. また、これらの作用により、格子定数差に基づいて結晶成長中等の高温状態においても剥離現象は生じ得るため、その剥離後には、熱膨張係数差に起因する応力が殆ど半導体結晶Aに対して作用しなくなり、よって、転位やクラックが発生せず、高品質の半導体結晶A(例:GaN単結晶)が得られる。 Furthermore, these actions, since that may also occur delamination phenomena in a high temperature state of the crystal growth moderate based on the lattice constant difference, act on its After stripping, thermal stress caused by the expansion coefficient difference is most semiconductor crystal A longer, therefore, not occur dislocations and cracks, a high quality semiconductor crystal a (eg: GaN single crystals) is obtained. 【0017】また、第3の手段は、上記の第1又は第2 Further, the third means, the first of the above or the second
の手段において、半導体結晶Aと下地基板とを冷却または加熱することにより、半導体結晶Aと下地基板との熱膨張係数差に基づく応力を発生させ、この応力を利用して侵食残骸部を破断することである。 In the means, by cooling or heating the semiconductor crystal A and the base substrate, to generate a stress based on the difference in thermal expansion coefficient between the semiconductor crystal A and the base substrate, breaking the erosion debris portion by utilizing the stress it is. 即ち、上記の破断(剥離)は、半導体結晶Aと下地基板との熱膨張係数差に基づく応力(剪断応力)によるものとしても良い。 That is, the breaking (release) may be due to stress based on the difference in thermal expansion coefficient between the semiconductor crystal A and the base substrate (shear stress). また、この手段によれば、特に、半導体結晶Aの膜厚を5 Further, according to this means, in particular, the thickness of the semiconductor crystal A 5
0μm以上に形成した場合に、半導体結晶Aの結晶性を高く維持しつつ、確実に半導体結晶Aと下地基板とを破断することができる。 When forming above 0 .mu.m, while high maintaining the crystallinity of the semiconductor crystal A, it is possible to reliably break the semiconductor crystal A and the base substrate. 【0018】また、第4の手段は、上記の第1乃至第3 Further, the fourth means, the first to third above
の何れか1つの手段において、シード層を、単層又は複層から成る III族窒化物系化合物半導体としたことである。 In any one means, a seed layer is that the Group III nitride compound semiconductor consisting of a single layer or multiple layers. 【0019】また、第5の手段は、上記の第4の手段において、シード層、又はシード層の最上層を窒化ガリウム(GaN)から形成することである。 Further, the fifth means, the fourth means described above, is to form a seed layer, or the top layer of the seed layer gallium nitride (GaN). 半導体結晶Aの具体的な組成としては、半導体の結晶成長基板等に最適で非常に有用な窒化ガリウム(GaN)が、今のところ産業上最も利用価値が高いものと考えられる。 The specific composition of the semiconductor crystal A, semiconductor optimum very useful gallium nitride crystal growth substrate, etc. (GaN) is considered to have the highest utility value on the moment industry. したがって、この様な場合、シード層、又はシード層の最上層を窒化ガリウム(GaN)から形成することにより、目的の半導体結晶A(GaN単結晶)の結晶成長を最も良好に実施することができる。 Therefore, such a case, by forming the seed layer, or the top layer of the seed layer of gallium nitride (GaN), can be best conducted crystal growth of interest of the semiconductor crystal A (GaN single crystal) . ただし、AlGaNや、或いはAlGaInN等についても、勿論産業上の利用価値は大きいので、半導体結晶層Aのより具体的な組成としてこれらを選択しても良い。 However, AlGaN or, or for even AlGaInN etc., since of course industrial value is great, it may select them as more specific composition of the semiconductor crystal layer A. これらの場合にも、目的の単結晶(半導体結晶層A)の組成に比較的近い組成の半導体( III族窒化物系化合物半導体)か或いは略同組成の半導体からシード層、又はシード層の最上層を形成することが望ましい。 In these cases, most of a semiconductor single crystal is relatively close composition to the composition of the (semiconductor crystal layer A) a semiconductor (III-V nitride compound semiconductor) or substantially the same composition object of the seed layer, or a seed layer it is preferable to form the upper layer. 【0020】また、第6の手段は、上記の第4の手段において、シード層、又はシード層の最下層を窒化アルミニウム(AlN)から形成することである。 Further, a sixth means, in the fourth means described above, is to form a seed layer, or lowest layer of the seed layer aluminum nitride (AlN). これにより、窒化アルミニウム(AlN)から所謂バッファ層を形成することができるので、このバッファ層(AlN) Thus, it is possible to form a so-called buffer layer away from the aluminum nitride (AlN), the buffer layer (AlN)
の積層に基づいた公知の作用を得ることができる。 It can be obtained known effects based on the stack. 即ち、格子定数差に起因して目的の半導体結晶層Aに働く応力を緩和できる等の周知の作用原理により、目的の半導体結晶層Aの結晶性を向上させることが容易又は可能となる。 In other words, by a well-known operating principle of such can reduce the stress due to the lattice constant difference acting on the purpose of the semiconductor crystal layer A, it becomes easy or possible to improve the crystallinity of the semiconductor crystal layer A of interest. 【0021】また、この手段によれば、AlNバッファ層と下地基板間の応力をより大きくすることができるため、下地基板の分離を更に容易にすることができる。 [0021] According to this means, it is possible to further increase the stress between AlN buffer layer and the underlying substrate, it is possible to further facilitate the separation of the underlying substrate. 更に、上記の作用効果を十分に得るためには、例えばシード層を2層から形成し、その下層をAlNバッファ層(シード層第1層)とし、その上層をGaN層(シード層第2層)とする複層のシード層の層構成等が非常に有効である。 Furthermore, in order to sufficiently obtain the effect of the above, for example, a seed layer is formed of two layers, and the underlying AlN buffer layer (seed layer a first layer), the upper GaN layer (the seed layer a second layer ) and the layer configuration of the seed layer of the double layer is very effective. この組み合わせによれば、上記の第5及び第6の手段の作用・効果を両方同時に良好に得ることができる。 According to this combination, it is possible to obtain both simultaneously good operation and effect of the fifth and sixth means of the. 【0022】また、第7の手段は、上記の第1乃至第3 Further, seventh means, the first to third above
の何れか1つの手段において、シード層、又はシード層の最上層又は最下層を酸化亜鉛(ZnO)又は窒化チタン(TiN x )から形成したことを特徴とする。 In any one means, seed layer, or wherein the top layer or the bottom layer of the seed layer formed from zinc oxide (ZnO) or titanium nitride (TiN x). これら化合物のような、 III族窒化物系化合物半導体を異種基板にエピタキシャル成長させる際のバッファ層となり得る化合物は、本願発明の単層のシード層又は複層のシード層の最上層又は最下層として用いることができる。 Such as these compounds, III-nitride-based compound semiconductor can be a buffer layer during epitaxial growth on a heterogeneous substrate compound is used as the uppermost layer or the lowermost layer of the seed layer of the seed layer or layers of a single layer of the present invention be able to. 【0023】また、第8の手段は、上記の第1乃至第7 Further, the eighth means, the first to seventh above
の何れか1つの手段において、侵食残骸部形成工程において、侵食残骸部の配置間隔を1μm以上、50μm以下にすることである。 In any one means, in erosion debris portion forming step, the arrangement interval of the erosion debris portion 1μm or more is to 50μm or less. より望ましくは、結晶成長の実施条件にも依存するが、侵食残骸部の配置間隔は、5〜3 More preferably, although depending on the implementation conditions of crystal growth, the arrangement interval of the erosion debris portion, 5 to 3
0μm程度が良い。 About 0μm is good. ただし、この配置間隔とは、互いに接近する各侵食残骸部の中心点間の距離のことを言う。 However, the the arrangement interval refers to the distance between the center points of the erosion debris portions approaching each other. 【0024】この手段により、侵食残骸部間の谷部の上方を半導体結晶Aで覆うことが可能となる。 [0024] By this means, it is possible to cover the upper valley between erosion debris portion in the semiconductor crystal A. また、この値が大きくなり過ぎると、確実に侵食残骸部間の谷部の上方を半導体結晶Aで覆うことができなくなり、結晶性が均質かつ良質の結晶(半導体結晶A)が得られなくなる。 Also, if this value is too large, certainly above the valley between erosion debris portion can not be covered by the semiconductor crystal A, crystallinity homogeneous and good quality crystal (semiconductor crystal A) can not be obtained. 或いは、この値が更に大き過ぎると、結晶方位のズレが顕著となり望ましくない。 Alternatively, if this value is too further large deviation of crystal orientation undesirably remarkable. 【0025】また、侵食残骸部の頭頂部の横方向の太さ、幅又は直径をSとし、上記の配置間隔(配置周期) Further, the lateral thickness of the top portion of the erosion debris portion, the width or diameter and S, said arrangement interval (arrangement period)
をLとすると、S/Lの値は1/4〜1/6程度が望ましい。 The When is L, the value of S / L is preferably about 1 / 4-1 / 6. この様な設定により、所望の半導体結晶Aの横方向成長(ELO)が十分に促進されるため、高品質の単結晶を得ることができる。 By such setting, since the lateral growth of the desired semiconductor crystal A (ELO) is sufficiently promoted, it is possible to obtain a high-quality single crystal. 以下、互いに向かい合う侵食残骸部の側壁間の距離をW(=L−S)とし、この側壁間の領域(即ち、侵食された凹部とその上方領域)をウイングと呼ぶことがある。 Hereinafter, the distance between the side walls of the erosion debris portions facing each other and W (= L-S), the region between the side wall (i.e., eroded recess and its upper region) may be referred to as the wings. また、以下、上記の幅Sをシード幅と呼ぶことがある。 Further, hereinafter sometimes it referred to as the width S of the seed width. したがって、ウイングに対するシード幅の比S/Wは1/3〜1/5程度が望ましい。 Accordingly, the ratio S / W of the seed width to the wing is preferably about 1 / 3-1 / 5. 【0026】また、侵食残骸部が略等間隔又は略一定周期で配置される様に上記の侵食処理を実施することがより望ましい。 Further, it is more desirable to perform the erosion process as the erosion debris portion are arranged at substantially equal intervals or substantially constant period. これにより、横方向成長の成長条件が全体的に略均等となり、結晶性の良否や成長膜厚にムラが生じ難くなる。 Thus, growth conditions of lateral growth overall becomes substantially uniform, crystalline quality and growth film uneven thickness hardly occurs. また、侵食残骸部間の谷部の上方が、半導体結晶Aによって完全に覆われるまでの時間に、局所的なバラツキが生じ難くなるため、例えば、結晶成長速度の遅い結晶成長法から、結晶成長速度の速い結晶成長法に、途中で結晶成長法を変更する場合に、その時期を的確に、早期に、或いは一意に決定することが容易となる。 Further, the upper valley between erosion debris part, the time until completely covered by the semiconductor crystal A, it becomes difficult to cause local variation, for example, from the slow crystal growth rate crystal growth method, crystal growth the fast velocity crystal growth method, when changing the crystal growth method in the middle, precisely the time, early, or can be easily determined uniquely. また、この様な方法により、上記の剪断応力を各侵食残骸部に略均等に分配することが可能となるため、全侵食残骸部の破断がムラなく生じ、下地基板と半導体結晶Aとの分離が確実に実施できる様になる。 Further, by such a method, since the shear stress becomes possible to substantially uniformly distributed to the erosion debris portions, breaking occurs evenly in all erosion debris portion, the separation between the base substrate and the semiconductor crystal A becomes like can be carried out reliably. 【0027】したがって、例えば、侵食残骸部をストライプ状のメサ型に形成し、これを等方向、等間隔に配置する様にしても良い。 [0027] Thus, for example, erosion debris portion formed in a stripe shape mesa, etc direction this may be as equally spaced. この様な侵食残骸部の形成は、容易かつ確実に実施できる等の、現行一般のエッチング加工の技術水準の現状に照らしたメリットがある。 Formation of such erosion debris section, such that can be implemented easily and reliably, there is a merit in the light of state of the art of the current general etching. この時、メサ(侵食残骸部)の方向は、半導体結晶の<1− At this time, the direction of the mesa (erosion debris unit) of the semiconductor crystal <1-
100>か<11−20>で良い。 100> or may be the <11-20>. 【0028】また、1辺が0.1μm以上の略正三角形を基調とする2次元三角格子の格子点上に侵食残骸部を形成する方法も有効である。 Further, one side is a method of forming a corrosion debris portion on a lattice point of a two-dimensional triangular lattice of tones and substantially equilateral triangle than 0.1μm is also effective. この方法によれば、下地基板との接触面積をより小さくできるため、上記の作用に基づいて、転位数を確実に低減できると共に下地基板の分離を容易にすることができる。 According to this method, since it is possible to further reduce the contact area with the underlying substrate, based on the action of the above, it is possible to facilitate the separation of the underlying substrate is possible reliably reduce the number of dislocations. 【0029】また、侵食残骸部の水平断面形状を、略正三角形、略正六角形、略円形、又は四角形に形成する方法も有効である。 Further, the horizontal cross-sectional shape of the erosion debris portion, a substantially equilateral triangle, substantially regular hexagon, substantially circular, or a method of forming a square effect. この方法により、 III族窒化物系化合物半導体より形成される結晶の結晶軸の方向が各部で揃い易くなるため、或いは、任意の水平方向に対して侵食残骸部の水平方向の長さ(太さ)を略一様に制限できるため、転位の数を抑制することができる。 In this way, since the direction of the crystal axis of the crystal formed from the Group III nitride compound semiconductor is easily aligned with each unit, or the horizontal length of the erosion debris portion for any horizontal direction (thickness ) because it substantially uniformly limit, it is possible to suppress the number of dislocations. 特に、正六角形や正三角形は、半導体結晶の結晶構造と合致し易いのでより望ましい。 In particular, regular hexagon or an equilateral triangle is more preferable because it is easy to match the crystal structure of the semiconductor crystal. また、円形や四角形は製造技術の面で形成し易いと言う、現行一般のエッチング加工の技術水準の現状に照らしたメリットが有る。 Further, the circular or square say easily formed in terms of manufacturing technology, there is merit in the light of state of the art of the current general etching. 【0030】また、本発明の第9の手段は、上記下地基板を0.01μm以上侵食処理することである。 Further, a ninth aspect of the present invention is to erosion process above 0.01μm to the underlying substrate. また、上記の侵食処理(エッチング加工等)により、下地基板の一部まで侵食すれば、その後の結晶成長工程において、 Further, by the above erosion process (etching, etc.), if erosion until a portion of the underlying substrate, in the subsequent crystal growth step,
目的の半導体結晶Aの表面(結晶成長面)をより平坦化し易くなり、更に、侵食残骸部の側方に「空洞」を形成することが容易となる。 Becomes easier to flatten the surface (crystal growth plane) of the object of the semiconductor crystal A, further, it becomes easy to form a "void" on the side of the erosion debris section. この「空洞」は、大きく形成される程、侵食残骸部に応力(剪断応力)が集中し易くなる。 This "cavity" is degree is larger, the stress on the erosion debris section (shear stress) is apt to concentrate. 【0031】また、第10の手段は、上記の第1乃至第9の何れか1つの手段の侵食残骸部形成工程において、 Further, means 10, in the erosion debris portion forming step of any one of the first to ninth mentioned above,
侵食残骸部の横方向の太さ、幅又は直径を0.1μm以上、20μm以下にすることである。 Lateral thickness of the erosion debris portion, the width or diameter of 0.1μm or more is to 20μm or less. より望ましくは、 More preferably,
結晶成長の実施条件にも依存するが、侵食残骸部の横方向の太さ、幅、又は直径は、0.5〜10μm程度が良い。 Although depending on the implementation conditions of crystal growth, the lateral thickness of the erosion debris portion, width, or diameter, of about 0.5~10μm good. この太さが太過ぎると、格子定数差に基づいて半導体結晶Aに働く応力の影響が大きくなり、半導体結晶A When the thickness is too thick, it increases the influence of the stress acting on the semiconductor crystal A based on the lattice constant difference, the semiconductor crystal A
の転位数が増加し易くなる。 Dislocation number is likely to increase in the. また、細過ぎると、侵食残骸部自身の形成が困難となるか、或いは、侵食残骸部の頭頂部の結晶成長速度bが遅くなり、望ましくない。 Also, if too thin, or the formation of erosion debris section itself becomes difficult, or the crystal growth rate b of the top portion of the erosion debris portion becomes slow, undesirable. 【0032】また、応力(剪断応力等)により侵食残骸部を破断させる際にも、侵食残骸部の横方向の太さ、 Further, the stress (shear stress, etc.) by the time of breaking the erosion debris unit also erosion debris portion lateral width of,
幅、又は直径が大き過ぎると、下地基板との接触面積が大きくなるため、確実に破断されない部分が生じ易くなり、望ましくない。 Width, or the diameter is too large, the contact area between the underlying substrate is large, easily not be reliably ruptured portion occurs, undesirable. また、格子定数差に基づいて半導体結晶Aに働く応力の影響の大小は、侵食残骸部の横方向の太さ(長さ)だけに依るものではなく、侵食残骸部の配置間隔等にも依存する。 Also, the magnitude of the influence of the stress acting on the semiconductor crystal A based on the lattice constant difference, erosion lateral thickness of the debris portion (length) and not due only, also depends on the arrangement interval or the like of the erosion debris portion to. そして、これらの設定範囲が不適切であれば、上記の様に格子定数差に基づく応力の影響が大きくなり、半導体結晶Aの転位数が増加し易くなり、望ましくない。 Then, if improperly these set range, influence of stress based on the lattice constant difference as described above becomes large, easily rearrangement number of the semiconductor crystal A is increased, undesirably. 【0033】また、侵食残骸部の頭頂部付近の横方向の太さ、幅、又は直径には、上記の様に最適値又は適正範囲があるため、侵食残骸部の上面、底面、又は水平断面の形状は、少なくとも局所的に閉じた形状(島状)、更には、外側に向かって凸状に閉じた形状が良く、より望ましくは、この上面、底面、又は水平断面の形状は、略円形や略正多角形等が良い。 Further, the lateral thickness of the vicinity of the top portion of the erosion debris portion, width, or diameter, because of the optimum value or the proper range as described above, the upper surface of the erosion debris portion, bottom or horizontal section, the shape, at least locally closed shape (island shape), and further, good shape closed convex outwardly, more preferably, the top surface, bottom surface, or the shape of the horizontal cross-section, substantially circular and a substantially regular polygon, etc. is good. この様な設定により、任意の水平方向に対して確実に、上記の最適値又は適正範囲を実現することが容易となる。 With such setting, to ensure against any horizontal direction, it is easy to realize the optimum value or the proper range. 【0034】また、第11の手段は、上記の第1乃至第9の何れか1つの手段の結晶成長工程において、結晶成長速度の遅い結晶成長法から、結晶成長速度の速い結晶成長法に、途中で結晶成長法を変更することである。 Further, the eleventh means, in the crystal growth step of the first to ninth any one means described above, the slow crystal growth rate crystal growth method, the fast crystal growth rate epitaxy method, it is to change the crystal growth method in the middle. 例えば、横方向成長の速い結晶成長法から、縦方向成長の速い結晶成長法に途中で結晶成長法を変更することにより、短時間に結晶性の良質な半導体結晶Aを得ることができる。 For example, the lateral growth fast crystal growth method, by changing the crystal growth method in the middle in the vertical growth fast crystal growth method, it is possible to obtain a high quality semiconductor crystal A brief crystallinity. 【0035】また、第12の手段は、上記の第1乃至第11の何れか1つの手段において、少なくとも分離工程よりも後に、半導体結晶Aの裏面に残った侵食残骸部の破断残骸をエッチング等の、化学的或いは物理的な加工処理により除去する残骸除去工程を設けることである。 Further, a twelfth means, in any one of the first to eleventh mentioned above, later than at least the separation step, etching the fracture remains of erosion debris portion remaining on the back surface of the semiconductor crystal A, etc. of, it is to provide a debris removing step of removing by chemical or physical processing.
この手段によれば、半導体結晶Aの裏面(下地基板を剥離させた側の面)に、半導体発光素子等の電極を形成した際に、電極と半導体結晶Aとの界面付近に生じる電流ムラや電気抵抗を抑制でき、よって駆動電圧の低減や、 According to this means, the back surface of the semiconductor crystal A (surface on the side was peeled underlying substrate), when forming the electrode such as a semiconductor light-emitting device, Ya current unevenness occurring near the interface between the electrode and the semiconductor crystal A can suppress the electric resistance, thus reducing or driving voltage,
或いは発光強度の向上等を図ることができる。 Or the like can be improved in emission intensity. 【0036】更に、侵食残骸部の破断残骸を除去することにより、電極を半導体発光素子等の反射鏡としても利用する際には、鏡面付近での光の吸収や散乱が低減されて反射率が向上するので、発光強度が向上する。 Furthermore, by removing the broken remnants of erosion debris portion, when also used an electrode as a reflector, such as a semiconductor light emitting device, the reflectance is reduced absorption and scattering of light in the vicinity of the mirror surface since improved, the emission intensity is improved. また、 Also,
例えば、研磨等の物理的な加工処理によりこの残骸除去工程を実施した場合等には、半導体結晶Aの裏面のバッファ層までをも取り除いたり、或いは、半導体結晶Aの裏面の平坦度を向上したりすることもできるので、電流ムラや電気抵抗の抑制、或いは、鏡面付近での光の吸収や散乱の低減等の、上記の作用効果を更に補強することができる。 For example, the like when embodying the debris removal process by physical processing such as polishing, or even removed to the back surface of the buffer layer of the semiconductor crystal A, or to improve the back surface flatness of the semiconductor crystal A since it is also possible to or suppression of the current unevenness and electrical resistance, or a reduction of the light absorption and scattering in the vicinity of the mirror surface can further reinforce the effect of the above. 【0037】尚、上記の加工処理は、熱処理であっても良い。 [0037] Incidentally, processing described above may be heat treated. 目的の半導体結晶Aの昇華温度よりも、除去したい部分の昇華温度の方が低い場合等には、昇温処理やレーザ照射等によっても不要な部分を除去することができる。 Than the sublimation temperature of the object of the semiconductor crystal A, in case it is less like a sublimation temperature of the portion to be removed, it can also remove unnecessary portions by heating treatment or laser irradiation or the like. 【0038】また、第13の手段は、 III族窒化物系化合物半導体発光素子において、上記の第1乃至第12の何れか1つの手段に依る半導体結晶の製造方法を用いて製造された半導体結晶を結晶成長基板として備えることである。 Further, means 13, in the group III nitride compound semiconductor light-emitting device, a semiconductor crystal manufactured using the manufacturing method of a semiconductor crystal according to the first to twelfth any one means of the it is to include as a crystal growth substrate. この手段によれば、結晶性が良質で、内部応力の少ない半導体より、 III族窒化物系化合物半導体発光素子を製造することが可能又は容易となる。 According to this means, a good crystallinity, less semiconductor internal stress becomes possible or easier to manufacture a Group III nitride compound semiconductor light-emitting device. 【0039】また、第14の手段は、上記の第1乃至第12の何れか1つの手段に依る半導体結晶の製造方法を用いて製造された半導体結晶を結晶成長基板とした結晶成長により、 III族窒化物系化合物半導体発光素子を製造することである。 Further, it means 14 is a crystal growth of the manufactured semiconductor crystal was crystal growth substrate by using the manufacturing method of the semiconductor crystal according to the first to twelfth any one means of the, III it is to produce a nitride-based compound semiconductor light-emitting device. この手段によれば、結晶性が良質で、内部応力の少ない半導体より、 III族窒化物系化合物半導体発光素子を製造することが可能又は容易となる。 According to this means, a good crystallinity, less semiconductor internal stress becomes possible or easier to manufacture a Group III nitride compound semiconductor light-emitting device. 【0040】尚、シード層を複層とする場合、最初に積層する半導体層として、「Al x Ga 1-x N(0≦x< [0040] In the case of the seed layer and multi-layer, as a semiconductor layer of first laminated, "Al x Ga 1-x N ( 0 ≦ x <
1)」より成るバッファ層を成膜することが望ましい。 It is desirable to deposit a buffer layer composed of 1) ".
ただし、このバッファ層とは別に、更に、上記のバッファ層と略同組成(例:AlNや、AlGaN)の中間層を周期的に、又は他の層と交互に、或いは、多層構造が構成される様に、積層しても良い。 However, apart from this buffer layer, further, the above buffer layer and substantially the same composition (eg and AlN, AlGaN) intermediate layer periodically, or alternating with other layers, or a multilayer structure is formed as that may be laminated. この様なバッファ層(或いは、中間層)の積層により、格子定数差に起因する半導体結晶Aに働く応力を緩和できる等の従来と同様の作用原理により、結晶性を向上させることが可能である。 Such buffer layer (or intermediate layer) by stacking, the conventional manner of working principle, such as that can alleviate the stress acting on the semiconductor crystal A due to lattice constant difference, it is possible to improve the crystallinity . 【0041】また、前記の分離工程において、下地基板と半導体結晶Aを降温する際には、これらを成長装置の反応室に残し、略一定流量のアンモニア(NH 3 )ガスを反応室に流したままの状態で、概ね「−100℃/min Further, in the separation step, when cooling the starting substrate and the semiconductor crystal A is left in the reaction chamber of the deposition apparatus was flushed with approximately constant flow rate of ammonia (NH 3) gas into the reaction chamber in the state of the remains, generally "-100 ℃ / min
〜−0.5℃/min」程度の冷却速度で略常温まで冷却する方法が望ましい。 How to cooling to substantially room temperature at ~-0.5 ℃ / min "about the cooling rate is desirable. 例えば、この様な方法により、半導体結晶Aの結晶性を安定かつ良質に維持したまま、確実に前記の分離工程を実施することができる。 For example, by such a method, while the crystallinity of the semiconductor crystal A was maintained stable and good quality, it can be carried out reliably the separation step. 以上の本発明の手段により、前記の課題を効果的、或いは合理的に解決することができる。 By means of the present invention described above, effectively the aforementioned drawbacks can be reasonably resolved. 【0042】 【発明の実施の形態】以下、本発明を具体的な実施例に基づいて説明する。 [0042] PREFERRED EMBODIMENTS Hereinafter will be described with reference to specific embodiments thereof. ただし、本発明は以下に示す実施例に限定されるものではない。 However, the present invention is not intended to be limited to the following examples. 【0043】(第1実施例)図1は、本実施例の半導体結晶の製造工程を例示する、半導体結晶の模式的な断面図である。 [0043] (First Embodiment) FIG. 1 illustrates a manufacturing process of a semiconductor crystal of the present embodiment, a schematic sectional view of a semiconductor crystal. 本実施例では、シード層第1層(AlNバッファ層102)とシード層第2層(GaN層103)より成るシード層( III族窒化物系化合物半導体)を、有機金属化合物気相成長法(以下「MOVPE」と示す) In this embodiment, the seed layer a first layer (AlN buffer layer 102) and the seed layer a second layer seed layer made of (GaN layer 103) (III nitride compound semiconductor) and metal organic vapor phase epitaxy ( hereinafter referred to as "MOVPE")
による気相成長により成膜した。 It was formed by vapor-phase growth by. そこで用いられたガスは、アンモニア(NH 3 )とキャリアガス(H 2又はN So used were gas, ammonia (NH 3) and a carrier gas (H 2 or N
2 )とトリメチルガリウム(Ga(CH 3 ) 3 ,以下「TMG」 2) with trimethyl gallium (Ga (CH 3) 3, hereinafter "TMG"
と記す)とトリメチルアルミニウム(Al(CH 3 ) 3 ,以下「TMA」と記す)である。 Is the abbreviated) and trimethylaluminum (Al (CH 3) 3, hereinafter referred to as "TMA"). 【0044】1. [0044] 1. シード積層工程まず最初に、1インチ四方で厚さ約250μmのサファイア基板101(下地基板)を有機洗浄及び熱処理(ベーキング)によりクリーニングした。 First seed lamination process, and cleaned by one inch sapphire substrate square at a thickness of about 250 [mu] m 101 (base substrate) and the organic cleaning and heat treatment (baking). そして、この単結晶の下地基板101のa面を結晶成長面として、H 2を10リットル/分、NH 3を5リットル/分、TMAを20μmol/分で供給し、AlNバッファ層102(シード層第1層)を約200nmの厚さにまで結晶成長させた。 Then, as a crystal growth surface a surface of the base substrate 101 of single crystal, the H 2 10 liters / min, the NH 3 5 l / min, supplying TMA at 20 [mu] mol / min, AlN buffer layer 102 (seed layer the first layer) to a thickness of about 200nm grown crystal. 尚、この時の結晶成長温度は、約400℃とした。 The crystal growth temperature at this time was about 400 ° C.. 【0045】更に、サファイア基板101の温度を10 [0045] In addition, the temperature of the sapphire substrate 101 10
00℃に昇温し、H 2を20リットル/分、NH 3を1 The temperature was raised to 00 ° C., the H 2 20 liters / min, the NH 3 1
0リットル/分、TMGを300μmol/分で導入し、膜厚約1.5μmのGaN層103(シード層第2層)を成膜した(図1(a))。 0 l / min, introducing TMG at 300 [mu] mol / min, thereby forming a GaN layer 103 having a thickness of about 1.5 [mu] m (seed layer second layer) (Figure 1 (a)). 【0046】2. [0046] 2. 侵食残骸部形成工程次に、ハードベークレジストマスクを使用して、反応性イオンエッチング(RIE)を用いた選択ドライエッチングにより、配置周期L≒20μmのストライプ状の侵食残骸部を形成した(図1(b))。 Erosion debris forming step Next, using a hard bake resist mask, selective dry etching using reactive ion etching (RIE), to form a stripe-shaped erosion debris of the arrangement period L ≒ 20 [mu] m (Fig. 1 (b)). 即ち、ストライプ幅(シード幅S)≒5μm、ウイング幅W≒15μmで、基板が約0.1μmエッチングされるまでストライプ状にエッチングすることにより、断面形状が略矩形の侵食残骸部を形成した。 That is, the stripe width (seed width S) ≒ 5 [mu] m, in the wing width W ≒ 15 [mu] m, by etching in a stripe pattern to the substrate is about 0.1μm etching, the cross-sectional shape to form the erosion debris of the substantially rectangular. また、上記のレジストマスクは、ストライプ状に残留した侵食残骸部の側壁が、GaN層103(シード層第2層)の{11−2 Further, the resist mask, the sidewall of the erosion debris portion remaining in stripes, {11-2 GaN layer 103 (the seed layer a second layer)
0}面と成る様に形成した。 0} plane and formed as made. 本エッチングにより、Ga This etching, Ga
N層103(シード層第2層)とAlNバッファ層10 N layer 103 (the seed layer a second layer) and AlN buffer layer 10
2(シード層第1層)とから成るシード層を平頂部に有するストライプ状の侵食残骸部が略周期的に形成され、 2 striped erosion debris portion having a seed layer consisting of the (first layer seed layer) on the flat-top portion is substantially periodically formed,
ウイングの谷部にサファイア基板101の一部が露出した。 Some of the sapphire substrate 101 is exposed to the wing of the valley. 【0047】3. [0047] 3. 結晶成長工程次に、ストライプ状に残留した侵食残骸部の露出面を最初の結晶成長面としてGaN単結晶から成る目的の半導体結晶AをHVPE法により形成した。 The crystal growth process following, the semiconductor crystal A purpose of GaN single crystal exposed surface erosion debris portion remaining in stripes as the first crystal growth surface was formed by HVPE. 【0048】最終的に目的の半導体結晶Aは250μm [0048] Finally, the semiconductor crystal A of purpose 250μm
程度まで結晶成長させる。 Extent to crystal growth. このとき成長初期はGaNが横方向と縦方向に成長し、一旦各部が連結されて一連の略平面状に平坦化された後は、GaN結晶は縦方向に成長する。 In this case the initial growth stage is GaN is grown in the lateral direction and the longitudinal direction, once after each part has been flattened is connected to a series of substantially flat, GaN crystal is grown in a vertical direction. このHVPE法においては、横型のHVPE装置を用いた。 In this HVPE method, using a horizontal of the HVPE apparatus. また、V族原料にはアンモニア(NH 3 )を、 Also, the Group V material ammonia (NH 3),
III族原料にはGaとHClとを反応させて得られたG The III group material obtained by reacting a Ga and HCl G
aClを用いた。 Using aCl. 【0049】こうして主に、横方向エピタキシャル成長によりシード層の側方が埋められ、その後は、縦方向成長により、目的の膜厚の半導体結晶A(GaN単結晶) [0049] Thus primarily laterally of the seed layer are filled by lateral epitaxial growth, then, the vertical growth, the thickness of the object semiconductor crystal A (GaN single crystal)
が得られた(図1(c))。 It was obtained (FIG. 1 (c)). 尚、図中の符号Rは「空洞」を示している。 Reference numeral R in the figure shows the "cavity". 尚、上記条件においては、GaNの膜厚が250μmを超えると、結晶成長工程においてA In the above conditions, the film thickness of GaN is more than 250 [mu] m, in the crystal growth step A
lNバッファ層102(シード層第1層)付近での剥離が観測される。 Peeling in the vicinity of lN buffer layer 102 (the seed layer a first layer) is observed. これは格子定数差に起因するものであり、以下の分離工程を省略することができる。 This is due to the lattice constant difference, it is possible to omit the following separation steps. この場合、高温での剥離が可能であり、冷却時の熱膨張係数差による欠陥発生を防止することができる。 In this case, it can be peeled off at a high temperature, it is possible to prevent occurrence of defects due to thermal expansion coefficient difference during cooling. 【0050】4. [0050] 4. 分離工程上記の半導体結晶Aを1.5℃/分の冷却速度で1100 In the separation step the semiconductor crystal A of 1.5 ° C. / min cooling rate 1100
℃から略室温までゆっくりと冷却する。 Slow cooling to approximately room temperature ° C.. これにより、A As a result, A
lNバッファ層102(シード層第1層)付近で剥離が生じ、下地基板101から独立した目的の膜厚の半導体結晶A(GaN単結晶)が得られた(図1(d))。 lN buffer layer 102 (the seed layer a first layer) peeling occurs in the vicinity of the semiconductor crystal A (GaN single crystal) having a thickness of independent interest from the starting substrate 101 is obtained (FIG. 1 (d)). 【0051】(第2実施例)図2は、本実施例の半導体結晶の製造工程を例示する、半導体結晶の模式的な断面図である。 (Second Embodiment) FIG 2 illustrates a manufacturing process of a semiconductor crystal of the present embodiment, a schematic sectional view of a semiconductor crystal. 本実施例では、シード層をZnOとし、スパッタリングにより形成した他は、第1実施例と同様である。 In this embodiment, the seed layer and ZnO, other formed by sputtering, the same as in the first embodiment. 【0052】1. [0052] 1. シード積層工程まず最初に、1インチ四方で厚さ約250μmのサファイア基板201(下地基板)を有機洗浄及び熱処理(ベーキング)によりクリーニングした。 First seed laminating step, and cleaned by one inch square with a thickness of about 250μm of the sapphire substrate 201 (base substrate) and the organic cleaning and heat treatment (baking). そして、この単結晶の下地基板201のa面に、スパッタリングにより膜厚約200nmのZnO層202(シード層)を成膜した(図2(a))。 Then, this a surface of the base substrate 201 of single crystal was deposited a ZnO layer 202 with a thickness of about 200 nm (seed layer) by sputtering (FIG. 2 (a)). 【0053】2. [0053] 2. 侵食残骸部形成工程次に、ハードベークレジストマスクを使用して、反応性イオンエッチング(RIE)を用いた選択ドライエッチングにより、配置周期L≒20μmのストライプ状の侵食残骸部を形成した(図2(b))。 Erosion debris forming step Next, using a hard bake resist mask, selective dry etching using reactive ion etching (RIE), to form a stripe-shaped erosion debris of the arrangement period L ≒ 20 [mu] m (FIG. 2 (b)). 即ち、ストライプ幅(シード幅S)≒3μm、ウイング幅W≒15μm In other words, the stripe width (seed width S) ≒ 3μm, wing width W ≒ 15μm
で、基板が約0.1μmエッチングされるまでストライプ状にエッチングすることにより、断面形状が略矩形の侵食残骸部を形成した。 In, by etching in a stripe pattern to the substrate is about 0.1μm etching, the cross-sectional shape to form the erosion debris of the substantially rectangular. 本エッチングにより、ZnO層2 This etching, ZnO layer 2
02(シード層)から成るシード層を平頂部に有するストライプ状の侵食残骸部が略周期的に形成され、ウイングの谷部にサファイア基板201の一部が露出した。 02 striped erosion debris portion having a seed layer on flat-top portion consisting of (a seed layer) is formed substantially periodically, a portion of the sapphire substrate 201 to the wings of the valley is exposed. 【0054】3. [0054] 3. 結晶成長工程次に、ストライプ状に残留した侵食残骸部の露出面を最初の結晶成長面としてGaN単結晶から成る目的の半導体結晶AをHVPE法により形成した。 The crystal growth process following, the semiconductor crystal A purpose of GaN single crystal exposed surface erosion debris portion remaining in stripes as the first crystal growth surface was formed by HVPE. 【0055】最終的に目的の半導体結晶Aは300μm [0055] Finally, the semiconductor crystal A of purpose 300μm
程度まで結晶成長させる。 Extent to crystal growth. このとき成長初期はGaNが横方向と縦方向に成長し、一旦各部が連結されて一連の略平面状に平坦化された後は、GaN結晶は縦方向に成長する。 In this case the initial growth stage is GaN is grown in the lateral direction and the longitudinal direction, once after each part has been flattened is connected to a series of substantially flat, GaN crystal is grown in a vertical direction. このHVPE法においては、横型のHVPE装置を用いた。 In this HVPE method, using a horizontal of the HVPE apparatus. また、V族原料にはアンモニア(NH 3 )を、 Also, the Group V material ammonia (NH 3),
III族原料にはGaとHClとを反応させて得られたG The III group material obtained by reacting a Ga and HCl G
aClを用いた。 Using aCl. 【0056】こうして主に、横方向エピタキシャル成長によりシード層の側方が埋められ、その後は、縦方向成長により、目的の膜厚の半導体結晶A(GaN単結晶) [0056] Thus primarily laterally of the seed layer are filled by lateral epitaxial growth, then, the vertical growth, the thickness of the object semiconductor crystal A (GaN single crystal)
が得られた(図2(c))。 It was obtained (FIG. 2 (c)). 尚、図中の符号Rは「空洞」を示している。 Reference numeral R in the figure shows the "cavity". 【0057】4. [0057] 4. 分離工程上記の半導体結晶Aを1.5℃/分の冷却速度で1100 In the separation step the semiconductor crystal A of 1.5 ° C. / min cooling rate 1100
℃から略室温までゆっくりと冷却する。 Slow cooling to approximately room temperature ° C.. これにより、Z As a result, Z
nO層202(シード層)付近で剥離が生じ、下地基板201から独立した目的の膜厚の半導体結晶A(GaN nO layer 202 (seed layer) around at occur peeling of the film thickness of independent interest from the starting substrate 201 a semiconductor crystal A (GaN
単結晶)が得られた(図2(d))。 Single crystal) were obtained (Figure 2 (d)). 【0058】(第3実施例)シード層202を、スパッタリングにより形成した厚さ40nmのTiN xとした他は第2実施例と同様にして300μmの膜厚の半導体結晶A(GaN単結晶)をサファイア基板上に形成した。 [0058] (Third Embodiment) The seed layer 202, except that the TiN x thickness of 40nm formed by sputtering with a thickness of 300μm in the same manner as in the second embodiment semiconductor crystal A (GaN single crystal) It was formed on a sapphire substrate. 1.5℃/分の冷却速度で1100℃から略室温までゆっくりと冷却すことにより、TiN x層(シード層) By be cooled slowly to about room temperature from 1100 ° C. at a 1.5 ° C. / min cooling rate, TiN x layer (seed layer)
付近で剥離が生じ、下地基板から独立した目的の膜厚の半導体結晶A(GaN単結晶)が得られた。 Peeling occurs in the vicinity of the semiconductor crystal A (GaN single crystal) having a thickness of independent interest from the starting substrate was obtained. 【0059】尚、第1実施例におけるバッファ層とは別に、更に、上記のバッファ層と略同組成(例:AlN [0059] Note that, apart from the buffer layer in the first embodiment, further, the above buffer layer and substantially the same composition (eg: AlN
や、AlGaN)の中間層を周期的に、又は他の層と交互に、或いは、多層構造が構成される様に、積層しても良い。 And, an intermediate layer periodically in AlGaN), or alternating with other layers, or, as the multilayer structure is constituted, may be stacked. この様なバッファ層(或いは、中間層)の積層により、格子定数差に起因する半導体結晶Aに働く応力を緩和できる等の従来と同様の作用原理により、結晶性を向上させることが可能である。 Such buffer layer (or intermediate layer) by stacking, the conventional manner of working principle, such as that can alleviate the stress acting on the semiconductor crystal A due to lattice constant difference, it is possible to improve the crystallinity . 【0060】また、前記の分離工程において、下地基板と半導体結晶Aを降温する際には、これらを成長装置の反応室に残し、略一定流量のアンモニア(NH 3 )ガスを反応室に流したままの状態で、概ね「−100℃/min [0060] Further, in the separation step, when cooling the starting substrate and the semiconductor crystal A is left in the reaction chamber of the deposition apparatus was flushed with approximately constant flow rate of ammonia (NH 3) gas into the reaction chamber in the state of the remains, generally "-100 ℃ / min
〜−0.5℃/min」程度の冷却速度で略常温まで冷却する方法でも良い。 In ~-0.5 ℃ / min "about the cooling rate may be a method of cooling to approximately room temperature. この冷却速度が速過ぎると、半導体結晶Aにワレ、クラックが発生する恐れがある。 When the cooling rate is too fast, cracking in the semiconductor crystal A, cracks may occur. 【0061】上記各実施例では、半導体結晶Aのエピタキシャル成長は主としてHVPEにより行ったが、半導体結晶Aのエピタキシャル成長を初期段階ではMOCV [0061] In the embodiments described above, the epitaxial growth of the semiconductor crystal A is primarily conducted by the HVPE, in the initial stage of epitaxial growth of the semiconductor crystal A MOCV
Dとし、その後HVPEに切り換えても良い。 And D, may then be switched to HVPE. この場合、初期段階では結晶性良く半導体結晶Aの下層部分を形成し、その後エピタキシャル成長を早めて全体の結晶成長時間を冗長とせずに結晶性の良い半導体結晶Aを得ることが可能となる。 In this case, in the initial stage to form the lower part of the good crystallinity semiconductor crystal A, then without epitaxial growth early in the overall redundant crystal growth time becomes possible to obtain good crystallinity semiconductor crystal A.

【図面の簡単な説明】 【図1】本発明の第1の実施例に係わる半導体結晶の製造工程を例示する、半導体結晶の模式的な断面図。 Illustrating the process of manufacturing the semiconductor crystal according to a first embodiment of the BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] The present invention, schematic sectional view of a semiconductor crystal. 【図2】本発明の第2の実施例に係わる半導体結晶の製造工程を例示する、半導体結晶の模式的な断面図。 Illustrating the process of manufacturing the semiconductor crystal according to a second embodiment of the present invention; FIG, schematic sectional view of a semiconductor crystal. 【符号の説明】 101、201 … 下地基板(例:サファイア等) 102 … AlNバッファ層(シード層第1層) 103 … GaN層(シード層第2層) 202 … ZnO層(シード層) A … 目的の半導体結晶( III族窒化物系化合物半導体) R … 空洞L … 侵食残骸部の配置周期S … シード幅W … ウイング幅 [EXPLANATION OF SYMBOLS] 101, 201 ... base substrate (e.g. sapphire, etc.) 102 ... AlN buffer layer (seed layer a first layer) 103 ... GaN layer (the seed layer a second layer) 202 ... ZnO layer (seed layer) A ... the purpose of the semiconductor crystal (III-nitride compound semiconductor) R ... cavity L ... arranged cycle of erosion debris section S ... seed width W ... wing width

フロントページの続き (72)発明者 永井 誠二 愛知県西春日井郡春日町大字落合字長畑1 番地 豊田合成株式会社内(72)発明者 山崎 史郎 愛知県西春日井郡春日町大字落合字長畑1 番地 豊田合成株式会社内(72)発明者 手銭 雄太 愛知県西春日井郡春日町大字落合字長畑1 番地 豊田合成株式会社内(72)発明者 平松 敏夫 愛知県西春日井郡春日町大字落合字長畑1 番地 豊田合成株式会社内(72)発明者 冨田 一義 愛知県愛知郡長久手町大字長湫字横道41番 地の1 株式会社豊田中央研究所内Fターム(参考) 5F041 AA40 CA40 CA64 CA65 CA77 Of the front page Continued (72) inventor Seiji Nagai Aichi Prefecture Nishikasugai District Kasuga-cho Oaza Ochiai Jichohatake 1 address Toyoda Gosei Co., Ltd. in the (72) inventor Shiro Yamazaki Oaza, Aichi Prefecture Nishikasugai District Kasuga-cho, Ochiai Jichohatake 1 address Toyoda Gosei stock within the company (72) inventor Tezeni Yuta, Aichi Prefecture Nishikasugai District Kasuga-cho Oaza Ochiai Jichohatake 1 address Toyoda Gosei Co., Ltd. in the (72) inventor Toshio Hiramatsu Aichi Prefecture Nishikasugai District Kasuga-cho Oaza Ochiai Jichohatake 1 address Toyoda Gosei Co., Ltd. the inner (72) inventor Kazuyoshi Tomita Aichi Prefecture Aichi-gun Nagakute Oaza Nagakute-shaped side street No. 41 land of 1 Co., Ltd. Toyota central R & D Labs in the F-term (reference) 5F041 AA40 CA40 CA64 CA65 CA77

Claims (1)

  1. 【特許請求の範囲】 【請求項1】下地基板上に III族窒化物系化合物半導体から成る半導体結晶を成長させ、前記下地基板から独立した良質の半導体結晶Aを得る方法であって、 前記下地基板上に単層又は複層のシード層を積層するシード積層工程と、 前記下地基板の前記シード層が成膜されている側の面の一部を化学的若しくは物理的に侵食処理して、前記シード層を前記下地基板上に部分的或いは分散的に残留させる侵食残骸部形成工程と、 前記シード層の侵食残骸部の露出面を前記半導体結晶A Claims We claim: 1. A grown semiconductor crystal made of Group III nitride-based compound semiconductor on a base substrate, a method for obtaining a semiconductor crystal A of high quality which is independent from the underlying substrate, the underlying a seed laminating step of laminating a seed layer of single-layer or multi-layer on the substrate, wherein the seed layer of the base substrate is chemically or physically erode handle portion of the surface of the side that has been deposited, and erosion debris portion forming step of partially or distributed manner to leave the seed layer on the base substrate, the exposed surface of the erosion debris portion of the seed layer and the semiconductor crystal a
    が結晶成長し始める最初の結晶成長面とし、この結晶成長面が結晶成長により各々互いに連結されて少なくとも一連の略平面に成長するまで、前記半導体結晶Aを結晶成長させる結晶成長工程と、 前記侵食残骸部を破断することにより、前記半導体結晶Aと前記下地基板とを分離する分離工程とを有することを特徴とする半導体結晶の製造方法。 There is a first crystal growth surface begins to crystal growth until the growth on at least a series of substantially flat crystal growth surface is respectively connected to each other by crystal growth, crystal and growth step of crystal growth of the semiconductor crystal A, the erosion by breaking the debris portion, the manufacturing method of the semiconductor crystal, characterized in that it comprises a separation step of separating the base substrate and the semiconductor crystal a. 【請求項2】前記結晶成長工程において、 前記半導体結晶Aの膜厚を50μm以上としたことを特徴とする請求項1に記載の半導体結晶の製造方法。 2. A wherein the crystal growth step, method for producing a semiconductor crystal according to claim 1, characterized in that the thickness of the semiconductor crystal A as above 50 [mu] m. 【請求項3】前記半導体結晶Aと前記下地基板とを冷却または加熱することにより、前記半導体結晶Aと前記下地基板との熱膨張係数差に基づく応力を発生させ、この応力を利用して前記侵食残骸部を破断することを特徴とする請求項1又は請求項2に記載の半導体結晶の製造方法。 By wherein cooling or heating and the underlying substrate and the semiconductor crystal A, wherein the semiconductor crystal A and the to generate stress due to difference in thermal expansion coefficient between the base substrate, wherein by utilizing the stress the method of manufacturing a semiconductor crystal according to claim 1 or claim 2, characterized in that breaking the erosion debris section. 【請求項4】前記シード層は単層又は複層の III族窒化物系化合物半導体から成ること特徴とする請求項1乃至3の何れか1項に記載の半導体結晶の製造方法。 Wherein said seed layer manufacturing method of the semiconductor crystal according to any one of claims 1 to 3, wherein the Group III nitride compound semiconductor single layer or multiple layers. 【請求項5】前記シード層又は前記シード層の最上層を窒化ガリウム(GaN)から形成したことを特徴とする請求項4に記載の半導体結晶の製造方法。 5. The process for producing a semiconductor crystal according to claim 4, characterized in that the formation of the uppermost layer of the seed layer or the seed layer gallium nitride (GaN). 【請求項6】前記シード層又は前記シード層の最下層を窒化アルミニウム(AlN)から形成したことを特徴とする請求項4に記載の半導体結晶の製造方法。 6. A manufacturing method of a semiconductor crystal according to claim 4, characterized in that the formation of the bottom layer of the seed layer or the seed layer aluminum nitride (AlN). 【請求項7】前記シード層又は前記シード層の最上層又は最下層を酸化亜鉛(ZnO)又は窒化チタン(TiN 7. A top layer or the bottom layer of zinc oxide (ZnO) of the seed layer or the seed layer or a titanium nitride (TiN
    x )から形成したことを特徴とする請求項1乃至3の何れか1項に記載の半導体結晶の製造方法。 The method of manufacturing a semiconductor crystal according to any one of claims 1 to 3, characterized in that formed from x). 【請求項8】前記侵食残骸部形成工程において、前記侵食残骸部の配置間隔を1μm以上、50μm以下とすることを特徴とする請求項1乃至請求項7の何れか1項に記載の半導体結晶の製造方法。 8. The erosion debris forming step, the erosion debris part arrangement interval 1μm or more, the semiconductor crystal according to any one of claims 1 to 7, characterized in that the 50μm or less the method of production. 【請求項9】前記侵食残骸部形成工程において、前記下地基板を0.01μm以上侵食処理したことを特徴とする請求項1乃至請求項8の何れか1項に記載の半導体結晶の製造方法。 9. The erosion debris portion forming step, the manufacturing method of the semiconductor crystal according to any one of claims 1 to 8, characterized in that said base substrate and the erosion process than 0.01 [mu] m. 【請求項10】前記侵食残骸部形成工程において、前記侵食残骸部の横方向の太さ、幅、又は直径を0.1μm以上、20μm以下とすることを特徴とする請求項1乃至請求項9の何れか1項に記載の半導体結晶の製造方法。 10. The erosion debris forming step, the lateral thickness of the erosion debris part, width, or diameter 0.1μm or more, claims 1 to 9, characterized in that the 20μm or less the method of manufacturing a semiconductor crystal according to any one of. 【請求項11】前記結晶成長工程において、 結晶成長速度の遅い結晶成長法から、結晶成長速度の速い結晶成長法に、途中で結晶成長法を変更することを特徴とする請求項1乃至請求項10の何れか1項に記載の半導体結晶の製造方法。 11. The crystal growth process, the slow crystal growth rate crystal growth method, the fast crystal growth rate epitaxy method, according to claim 1 to claim, characterized in that to change the crystal growth method in the middle the method of manufacturing a semiconductor crystal according to any one of 10. 【請求項12】少なくとも前記分離工程よりも後に、 前記半導体結晶Aの裏面に残った前記侵食残骸部の破断残骸をエッチング等の、化学的或いは物理的な加工処理により除去する残骸除去工程を有することを特徴とする請求項1乃至請求項11の何れか1項に記載の半導体結晶の製造方法。 Later than 12. At least the separation step, having a fracture debris of the erosion debris portion remaining on the back surface of the semiconductor crystal A such as etching, chemical or physical debris removal step of removing the processing the method of manufacturing a semiconductor crystal according to any one of claims 1 to 11, characterized in that. 【請求項13】請求項1乃至請求項12の何れか1項に記載の半導体結晶の製造方法を用いて製造された、前記半導体結晶Aを結晶成長基板として有することを特徴とする III族窒化物系化合物半導体発光素子。 13. manufactured using the manufacturing method of the semiconductor crystal according to any one of claims 1 to 12, III-nitride, characterized in that it comprises the semiconductor crystal A as a crystal growth substrate -based compound semiconductor light-emitting device. 【請求項14】請求項1乃至請求項12の何れか1項に記載の半導体結晶の製造方法を用いて製造された、前記半導体結晶Aを結晶成長基板とした結晶成長により製造されたことを特徴とする III族窒化物系化合物半導体発光素子。 14. manufactured using the manufacturing method of the semiconductor crystal according to any one of claims 1 to 12, in that the semiconductor crystal A prepared by crystal growth and crystal growth substrate group III nitride-based compound semiconductor light emitting device characterized.
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