TW575908B - Method for producing semiconductor crystal and semiconductor light-emitting element - Google Patents

Method for producing semiconductor crystal and semiconductor light-emitting element Download PDF

Info

Publication number
TW575908B
TW575908B TW91102216A TW91102216A TW575908B TW 575908 B TW575908 B TW 575908B TW 91102216 A TW91102216 A TW 91102216A TW 91102216 A TW91102216 A TW 91102216A TW 575908 B TW575908 B TW 575908B
Authority
TW
Taiwan
Prior art keywords
substrate
manufacturing
protrusions
item
protrusion
Prior art date
Application number
TW91102216A
Other languages
Chinese (zh)
Inventor
Seiji Nagai
Kazuyoshi Tomita
Original Assignee
Toyoda Gosei Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Gosei Kk filed Critical Toyoda Gosei Kk
Application granted granted Critical
Publication of TW575908B publication Critical patent/TW575908B/en

Links

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Led Devices (AREA)

Description

575908 五、發明說明(l) 【發明所屬技術領域】 本發明係關於利用橫向結晶成長作用,並藉由在基底基 板上形成由第瓜族氮化物系化合物半導體所構成的基板 層,而獲得結晶成長基板的半導體結晶之製造方法。 【習知技術】 如圖5所例示般,已知在由如矽(si)等所構成的基底基 板上,結晶成長氮化鎵(GaN)等氮化物半導體,然後當冷 卻至常溫為止的時候,在氮化物半導體層上將產生多數的 錯位與龜裂現象。 【發明欲解決之課題】 如此若成長層(氮化物半導層)上產生多數 話’當在其上製作裝置的情況時,裝置中便將產生= 格缺陷、錯位、變形、龜裂等,結果便將形成導致裝置 性劣化的原因。 、 再者 僅殘留 述錯位 本發 錯排密 【解決 即, 形成由 獲得從 徵在於 ,當將 成長層 與龜裂 明乃為 度較低 課題之 第一手 第HI族 此基底 包括有 叫寻所構成基底基板予以去除,欲 丄而獲侍獨立的基板(結晶)之情況時,因上 等=作用,便無法獲得大面積(icffl2以上)。 6二、t ί :題,其目的在於獲得無龜裂,且 導體結晶(結晶成長基板)。 手段、以及作用與發明效果】 段係利用橫向纟吉晶&且 氮化物系化::以:,在基底基板上 基板獨立出的半導。3斤構成的基板層,而 :在基底基板上心?日上製造步驟’其特 力成多數突起部的突起部575908 V. Description of the Invention (l) [Technical Field of the Invention] The present invention relates to the use of lateral crystal growth and the formation of a crystal by forming a substrate layer composed of a Group III nitride compound semiconductor on a base substrate. Method for manufacturing semiconductor crystal of growth substrate. [Known Technology] As shown in FIG. 5, it is known that a nitride semiconductor such as gallium nitride (GaN) is crystal-grown on a base substrate made of silicon (si) or the like, and then cooled to room temperature. Most dislocations and cracks will occur on the nitride semiconductor layer. [Problems to be Solved by the Invention] In this way, if the growth layer (nitride semiconducting layer) has a large number of words, when a device is fabricated thereon, lattice defects, dislocations, deformations, cracks, etc. will occur in the device. As a result, the cause of the deterioration of the device will be formed. Furthermore, only the dislocations are left in the wrong place and the problem is solved. The solution is to obtain the characteristics. When the growth layer and the crack are the first-hand family of HI, this base includes the so-called search. In the case where the base substrate is removed, and an independent substrate (crystal) is to be served, it is impossible to obtain a large area (more than icffl2) because of high quality = effect. 62. t ί: The purpose is to obtain crack-free and crystallized conductor (crystal growth substrate). Means, function, and effect of the invention] The segment system utilizes the lateral crystalline silicon and < Nitride system :: to: on the base substrate, and the semiconductor independently of the substrate. 3 kg of substrate layer, and: on the base substrate? Manufacturing steps on the ground ’, the protrusions of which have a large number of protrusions

575908 五、發明說明(2) 形成步驟;將此突起部表面的至少其中一部分,設定為基 板層開始結晶成長的最初成長面,並使基板層進行結晶成 長,直到此成長面分別相互連結且至少成長至一連串大致 平面為止的結晶成長步驟,以及利用將突起部予以斷裂, 而將基板層與基底基板予以分離的分離步驟。 其中,所謂的「第ΠΙ族氮化物系化合物半導體」,一般 係指包含由二元、三元或四元之「AlxGay Ιη(1κΝ ; 〇 $ 1,0 $ y € 1,0 S x + y S 1」所構成一般式所示的任意混晶比 的半導體’此外,經添加p型或n型雜質的半導體亦涵蓋於 本說明書中的「弟Π族氣化物系化合物半導體」範嘴内。 再者,上述第ΙΠ族元素(Al,Ga,In)内至少其中一部分, 利用硼(B)、鉈(T 1 )等取代,或氮(n )中至少其中一部分, 利用磷(P)、砷(As) '銻(Sb)、鉍(Bi)等取代的半導體^ 等,亦仍涵蓋於本說明書中的「第m族氮化物系化合物 導體」範疇内。 干 再者,上述P型雜質係可添加如鎂(Mg)、或鈣(Ca)等。 再者,上述η型雜質係可添加如矽(Si)、硫⑻ '硒 (Se)、碲(Te)、或鍺(Ge)等。 再者’該等雜質可同時添加素 二型(P型與η型)。 兀京以上’亦可同時添加 譬如圖1所例示般,♦力且夕 成县田在具夕數犬起部的基底基板上, ΐ長由弟m私鼠化物系化合物所構成的基板層(半導〜 晶)的情況時’藉由突起部大小、;s扳層』”體結 條件等的調整,便可在 &lt; B隔、,,口日日成長諸 文』在各犬起部間(突起部側邊),形成未575908 V. Description of the invention (2) Formation steps; set at least a part of the surface of the protrusion as the initial growth surface of the substrate layer to start crystal growth, and crystal growth of the substrate layer until the growth surfaces are connected to each other and at least A crystal growth step until a series of substantially flat surfaces, and a separation step of separating the substrate layer from the base substrate by breaking the protrusions. Among them, the so-called "Group III nitride-based compound semiconductor" generally refers to the "AlxGay Ιη (1κN; 〇 $ 1.00 $ y. 1,0Sx + y) "S 1" constitutes a semiconductor with an arbitrary mixed crystal ratio shown in the general formula. In addition, semiconductors to which p-type or n-type impurities are added are also included in the scope of the "brother-II group gaseous compound semiconductors" in this specification. In addition, at least a part of the above-mentioned group III elements (Al, Ga, In) is substituted with boron (B), thorium (T 1), or the like, or at least a part of nitrogen (n) is substituted with phosphorus (P), Substituted semiconductors, such as arsenic (As), antimony (Sb), bismuth (Bi), etc., are also included in the category of "m-nitride-based compound conductors" in this specification. Furthermore, the aforementioned P-type impurities For example, magnesium (Mg), calcium (Ca), etc. may be added. In addition, the η-type impurity system may be added for example, silicon (Si), thallium selenium (Se), tellurium (Te), or germanium (Ge). Etc. In addition, 'these impurities can be added at the same time as prime type II (P-type and η-type). Above Wujing' can also be added at the same time, such as illustrated in Figure 1, In the case of Tiancheng County, on the base substrate with a canine starting portion, the substrate layer (semiconductor ~ crystal) made of a compound consisting of a compound of a mouse compound is grown long. Layer "" adjustment of body and knot conditions, etc., can be formed in the <B septum ,, and the daily growth of the text "between the dog's rise (the side of the protrusion),

9ll〇22l6.Ptd 第6頁 575908 五、發明說明(3) 大::t: t曰曰的空洞」。因此’若基板層厚度充分的 中作2於::ί Γ '舌,内部應力或外部應力便將輕易的集 部作用剪切2 2 j上二結果,特別係該等應力’便對突起 Μ 怎力寻,當此應力增大時,突起部便斷裂。所 Ϊ以:=:力?話,便可輕易的將基底基板與基板層 二基 容Π中i!起Ϊ:」。形成越大的話’應力(剪切應力)越 a ϊ ί板::中得知,藉由形成如上述突起部因為 :制二狹ΐίΞ使广需半導體結晶層)間的接觸部位被 二:便較難產生因二者晶袼常數差而衍生的 G:的ϊ:和。ί ΐ ί基板與基板層間之晶格常數差而所 曰)之/ /當在結晶成長基板層(所需半導體結 曰曰)之Ρ示,便抑制作用於成長中之基板 而減少錯位或龜裂的產生密度。 ]不而要應力’ 再者,當基底基板與基板層分離(剥離)之際, ,基板上殘留基板層的其中—部分,或在基板層上殘留^ 底基板的其中一部分(譬如:突起部的斷裂殘骸)。換句年土 况,上述分離步驟並非以該等材料連一部份均未殘留的 各材料完全分離為前提(必要條件)。 、 再者,解決上述課題的第二手段,係該等第一手段中, 藉由將基板層與基底基板予以冷卻或加熱,而產生隨 層與基底基板間的熱膨脹係數差所衍生出的應力,並矛^用9ll22l6.Ptd Page 6 575908 V. Description of the invention (3) Big: t: t is empty. Therefore, if the thickness of the substrate layer is sufficient, the middle stress will be 2 :: Γ Γ. The internal or external stress will easily be sheared by 2 2 j. As a result, the stress is particularly important for the protrusion M. How to find, when this stress increases, the protruding part will break. So: =: force? Then, you can easily combine the base substrate and the substrate layer in the second base i! The larger the formation, the greater the 'stress (shear stress)'. 板 The plate :: It is known that by forming the protrusions as described above, the contact sites between the widely needed semiconductor crystal layers are made by the two: It is more difficult to generate G: ϊ: and due to the difference between the crystal 袼 constants of the two. ί ΐ The difference in the lattice constant between the substrate and the substrate layer is referred to as) // When the P is shown in the crystalline growth substrate layer (required semiconductor junction), it suppresses the action on the growing substrate and reduces misalignment or turtles. The density of cracks. ] Not only stress' In addition, when the base substrate is separated (peeled off) from the substrate layer, part of the substrate layer remains on the substrate, or part of the base substrate remains on the substrate layer (for example: protrusions Broken wreckage). In other words, the above-mentioned separation step is not based on the premise of the complete separation of each material that does not have a part of these materials (a necessary condition). Furthermore, the second means for solving the above-mentioned problems is that in the first means, the substrate layer and the base substrate are cooled or heated to generate a stress derived from a difference in thermal expansion coefficient between the layer and the base substrate. And use spear ^

575908 五、發明說明(4) 此應力實施上述突起部的斷裂。 依照此手段的話,便可輕^的產 再者,第三手段係利用橫向結晶 2應力。 上形成由第m族氮化物系化人:長作用,在基底基板 而獲得半導體結晶之掣-牛二、,導體所構成的基板層, 〜衣&amp;步驟,i 曰 底基板上’形成多數突起部办 ;匕括有:在基 部表面的至少其中一部分,执=起部形成步驟;將此突起 最初成長面,並使基板二推Γ1為基板層開始結晶成長的 別相互連結且至少成長^ 一 =、、、°晶成長,直到此成長面分 步驟;其中,在此結晶成县牛串大致平面為止的結晶成長 物系化合物半導體的原料供二=中,藉由調整第瓜族氮化 間之谷部至少其中一部八里q ’而將基底基板突起部 合物半導體結晶成長速’露^區域的第瓜族氮化物系化 速度b間的差分(b-a),二# $與突起部頭頂部的結晶成長 依照此手段的話,突t為大致最大值。 對性的增大,並比較性碩頂部附近的結晶成長速度相 長,而支配著從頭制上述露出區域附近的結晶成 頭頂部附近開始的美搞屏^的結晶成長。結果,從突起部 基板層結晶成長時Ϊ待;,向成長(EL〇)便將變顯著,在 基板與基板層間之曰林If和作用於基板層上的「隨基底 板層的結晶構造穩差而衍生出的應力」。故’基 現象。 暴板層上較難產生錯位與龜裂的 再者’基板層的橫向忐 有可能在突起部側邊(l^(LE0)若變顯著的話,譬如亦 、合犬起部間)形成比較大空洞的情 91102216.ptd 五、發明說明(5) 況0 壁附近的周圍部八以外卢月^ μ',一般在基底基板外緣側 容雖亦依“結=== 適當,便可:::差:(== 再去,哲 工制成大致隶大值。 驟中,藉由;或第二手段的結晶成長步 量q ’而將基底基板突起%間之\化合物半導體的原料供給 出區域的第冚族氮〗之至少其中一部分,露 與突起部頭頂部的社曰成;:半導體結晶成長速度a ’ 大致最大值。 曰曰成長逮度b間的S分(b-a),控制為 在此情況下,亦如同上述 可緩和作用於基板層上 基板層結晶成長時, 常數差而衍生出的應力,基板與基板層間之晶格 f板層上較難產生錯位i龜“】f的結晶構造穩定’且 f各突起部間(突起部側邊)二同僅二此作用、功效係當 者況下,”比較顯著在橫向成長較顯 可輕易的利用剪切廡上述分離步驟中,便 作用、功效俜告i r力將基底基板與基板層予以分離。此 效係田在各突起部間(突起部側邊)的空洞越大: 575908 五、發明說明(6) 話,越顯著 再者,第五手段係在上述第三或第四手段中,將上述原 料供給量q設定在1 //mol/min以上,且1〇〇 以 下。 最好上述原料供給量q設定在5 #m〇1/min以上,且9〇 /zmol/min以下。更佳的範圍值,雖依存於所形成突起部 的大小或形狀、配置間隔等基底基板規格、供給原料的種 =供給流動方向、及結晶成長法等諸條件,但大約在 10〜80#m〇1/min左右為更理想。此範圍值’因為若 m交難將上述差分(b_a)控制為大致最大值,因此在 各犬起4間(突起部側邊)便較難形成空 況下,便隨晶格常數差而衍生的姓曰向“…在此種11 和,並產生錯位等,而容易導:二3力便較難獲緩 化現象,所以最好不要。 基板層早結晶的結晶性劣 上分^力人剪Λ應力),即便在將基底基板與基板 增卞以刀離犄,右突起部侧邊允 々…、 話,應力便較難集中於突起部’、、、1 s二洞較小的 斷裂,故最好不要。“上,而較不易引起突起部的 此外’若原料供給量q過小的 久,將不利於生產i生,故最好不要“曰成長時間將過長 再者,第六手段係上述第—至 基板材料係採用矽(Si)或碳化矽(弟sic)勺任思手段中,基底 再者’其他基底基板材料可椟1 InP、GaP、MgG、ZnQ、MgA&amp; 用 ^NUGaAs、 2〇4寺,此外亦可採用藍寶石、575908 V. Description of the invention (4) This stress implements the fracture of the protrusions. According to this method, it can be lightly produced. In addition, the third method is to use the lateral crystal 2 stress. Formed by group m nitrides: long-acting, semiconductor substrate on the base substrate to obtain crystals-Niu Er, the substrate layer composed of conductors, ~ clothing &amp; steps, i. The protrusions are made; at least a part of the surface of the base, the step of forming the protrusion; the protrusions are initially grown, and the substrate is pushed to Γ1 as the substrate layer begins to crystallize, and at least ^ A = ,,, ° crystal growth, until this growth surface is divided into steps; wherein, here the crystal growth of the ox kebab is approximately flat, the raw material of the compound semiconductor for the crystal growth of the second = medium, by adjusting the nitride The difference between the basal substrate protrusions and the semiconductor crystal growth rate of the base substrate protrusions at least one part of the interval between the three valleys ("ba"), the difference (ba) between the second group nitride formation rate b and the protrusions According to this method, the crystal growth at the top of the head is approximately maximum. The increase of the opposite sex and the growth rate of the crystal near the top of the sex are relatively strong, and dominate the crystal growth near the top of the head from the above-mentioned exposed area. As a result, waiting for the crystal growth of the substrate layer from the protrusion portion, the growth toward the EL0 will become significant, and if the substrate between the substrate and the substrate layer is forested, and "the crystal structure of the substrate layer is stable with the substrate layer" Bad stress. " So ‘base phenomenon. It is more difficult to produce dislocations and cracks on the lamellae layer. The lateral ridges of the substrate layer may be relatively large on the side of the protrusion (if l ^ (LE0) becomes significant, such as the gap between the dogs). Hollow love 91102216.ptd V. Description of the invention (5) Case 0 The surrounding part near the wall is more than eight months ^ μ '. Generally, although the side surface of the outer edge of the base substrate is also based on "knot === appropriate, you can: : Difference: (== Go again, the philosopher makes a roughly large value. In this step, the crystal growth step q 'of the second means is used to supply the raw material of the compound semiconductor between the substrate substrate and the substrate. At least a part of the Group III nitrogen in the region is exposed to the top of the head of the protrusion; the semiconductor crystal growth rate a 'is approximately the maximum. The S-score (ba) between the growth degree b is controlled to be In this case, as described above, the stress derived from the constant difference when the substrate layer crystal grows on the substrate layer can be relieved. The lattice f between the substrate and the substrate layer is harder to produce a misalignment. The crystal structure is stable, and the two protrusions (sides of the protrusions) are the same. In this case, the effect and effect are “significant.” In the case of lateral growth, the shearing can be easily used. In the above separation step, the effect and effect can be used to separate the base substrate and the substrate layer. This effect is The larger the gap between Tian's protrusions (the sides of the protrusions): 575908 V. Description of the Invention (6) The more significant, the fifth means is the third or fourth means to supply the above raw materials The amount q is set to 1 // mol / min or more and 100 or less. It is preferable that the raw material supply amount q is set to 5 # m〇1 / min or more and 90 / zmol / min or less. A better range value Although it depends on various conditions such as the size and shape of the formed protrusions, the base substrate specifications such as the placement interval, the type of raw material to be supplied = the direction of the flow of the supply, and the crystal growth method, it is about 10 ~ 80 # m〇1 / min. It is more ideal. The value of this range is' if the intersection between m and the above-mentioned difference (b_a) is controlled to the approximate maximum value, so it is difficult to form a space between the four dogs (side of the protrusion), and the lattice The constant difference derived from the surname to "... in this 11 sum, and dislocation However, it is easy to guide: the second and third forces are more difficult to mitigate, so it is best not to. The early crystallinity of the substrate layer is poor due to the poor crystallinity (shear stress), even if the base substrate and the substrate are increased by a knife. Away, the side of the right protruding part is allowed to ... If it is difficult, the stress will be harder to concentrate on the small part of the protruding part ', 2 and 1 s, so it is better not to. "On the other hand, it is less likely to cause protrusions." If the amount of raw material supply q is too small for a long time, it will not be conducive to production, so it is best not to say "the growth time will be too long. The sixth means is the first to the above." The substrate material is made of silicon (Si) or silicon carbide (Si). In addition, the substrate can be used for other substrate materials: InP, GaP, MgG, ZnQ, MgA &amp; ^ NUGaAs, 204 , In addition, sapphire,

第10頁 575908 五、發明說明(7) 尖晶石、氧化猛、氧化鎵鐘(L i G a 〇2 )、硫化鉬(μ 0 s )等。 其中’採用隨熱膨脹係數差所衍生的剪切應力,而分離 基底基板與基板層的情況時,最好選擇二材料間的埶膨脹 係數差不致變小的搭配。再者,基底基板最好較 斷裂的材料。 &amp;评早乂合勿 再者,第七手段係在上述第一至第六的任— 料採用Sl(111),而在突起部形又土 ^基板犬起部間的谷部區域上,形成未露 突起部。 面的 依照本手段的話,因為可控制將上述谷 成長速度a變小,因此可將上述差分(b〜i姓路出面結晶 穩定的大致最大化。 、·隹持結晶性,並 再者,第八手段係在上述第一至第七 部形成步驟後,設置有至少於突起部表—手段之突起 A^xfai-xN(0 &lt;X g 1)」所構成緩衝層的步驟。形成由 但是’除此緩衝層之外,亦可更將盥 如:MN、或A1GaN)的中間層週期、層大致同 他2又疊層,或者形成多層構造的方式y層層/或與其 二由此種緩衝層(或中間層)的疊層,便 的ί所衍生作用於基板層(成長層)上的庫力Ϊ m常 的作用原,里,便可提昇結晶性。 心力寺’如同習知 定=ΐ,第九手段係在上述第八手段中,將缓# ® ρ β 突起部縱向高度以下。再者,絕對^衝層厚度設 最奸在約〇·〇_,乂上,且…以下。仏丰則緩衝層厚度Page 10 575908 V. Description of the invention (7) Spinel, oxide, gallium oxide clock (L i G a 〇2), molybdenum sulfide (μ 0 s), etc. Among them, when the shear stress derived from the difference in thermal expansion coefficient is used to separate the base substrate and the substrate layer, it is best to choose a combination that does not make the difference in the expansion coefficient between the two materials smaller. Furthermore, the base substrate is preferably a relatively broken material. &amp; Comment on the early morning and no more, the seventh means is in any of the first to sixth mentioned above-using Sl (111), and in the valley area between the raised part and the base of the dog, Unexposed protrusions are formed. According to this method, since the valley growth rate a can be controlled to be small, the above-mentioned difference (b ~ i) can be substantially maximized. The crystallinity is stable. Also, the crystallinity is controlled, and The eight means is a step of forming a buffer layer composed of protrusions A ^ xfai-xN (0 &lt; X g 1) "which is at least less than the protrusion surface after the steps of forming the first to seventh parts. 'In addition to this buffer layer, the intermediate layer period such as: MN or A1GaN) can also be used, and the layers are roughly laminated with other layers, or a multilayer structure is formed. The stacking of the buffer layer (or the middle layer) can increase the crystallinity by the constant force acting on the substrate layer (growth layer). Xinli Temple ’is the same as the conventional method = ΐ, and the ninth means is in the eighth means described above, and will reduce the length of the protrusions to less than or equal to the longitudinal direction. Moreover, the absolute thickness of the punching layer is set to be about 0.000, 乂, and below. Pu Fengze buffer layer thickness

911〇2216 Ptd 第11頁 575908 五、發明說明(8) 藉由此手段,便可僅使形成於緩衝層上的所需結晶層 (如:G a N層),優越的朝橫向成長。即,藉由士主 q凡于+又,便可 減少緩衝層上所形成結晶層,在結晶成長時66「 , T 丨过晶格常 數所衍生的應力」,並可有效的減少錯位货# =缓衝層等的A1N或應等’較容易;:於基底基板 鉻出表面的大致整面上,再者,原本形成所兩 日. 高ΒΘ之成县 層等的GaN ’雖較MNSA1GaN等具有更容易橫向成長的傾 上述手段的話,更可確實的在突起部侧邊形 成較大的「空洞」。 再者,藉由此手段,當從基底基板分離出基板層 基板層背面(具基底基板之一面)上,結晶層(3 層上的所需層)亦將廣範圍的裸露出。所以,者,^緩衝 背面形成電極之際,便可輕易的控制電阻抗。田土板層 再者,緩衝層的厚度,雖如上述大約在^ 右屬較適當的範圍,但尤以在以上,=〜’左 為佳。若此厚度過厚的㊣,空洞將容易變小:=下 層。特別在;近便=;:rr的緩衝 =膜的部位)的話…性亦將容化 再者,本發明第十手段係在上 結晶成長步驟中,將^ 々任一手段之 便、、、口日日成長的基板層(第m族 上 度最好在約5。_以上。此厚户:=化合物半導體)厚 予度越厚的活,便基板層的拉911〇2216 Ptd Page 11 575908 V. Description of the invention (8) By this means, only the required crystalline layer (such as the G a N layer) formed on the buffer layer can be grown laterally. That is, by using the master to increase the number of crystal layers formed on the buffer layer, 66 ", T 丨 stress derived from the lattice constant" during crystal growth, and can effectively reduce the misplaced goods # = A1N of buffer layer and so on. 'Easier ;: on the entire surface of the base substrate chromium exit surface, and two days before the original formation. If the above-mentioned means are easier to grow horizontally, it is possible to more surely form a larger "void" on the side of the protrusion. Furthermore, by this means, when the substrate layer is separated from the base substrate, the crystal layer (the required layer on the three layers) will be exposed in a wide range on the back of the substrate layer (one side with the base substrate). Therefore, when the electrodes are formed on the back of the buffer, the electrical impedance can be easily controlled. Field soil layer. Although the thickness of the buffer layer is about ^ right as described above, it is a more appropriate range, but it is particularly preferably above. If this thickness is too thick, the cavity will easily become smaller: = lower layer. Especially in the case of; near stool = ;: rr's buffer = part of the membrane) ... sex will also be accommodated. Furthermore, the tenth means of the present invention is in the step of crystal growth, and it is convenient to use any means ,,,, The substrate layer that grows day by day (the degree of the m group is preferably about 5. _ or more. This thick household: = compound semiconductor) The thicker the thickness is, the more the substrate layer is pulled.

91102216.ptd 第12頁 575908 五、發明說明(9) 伸應力便將被緩和,而可減少基板層的錯位或龜裂產生 i中辻”可堅固基板層’而輕易的將上述剪切應力 市甲於上述突起部。 山再者,第十—手段係在上述第一至十的任一手段之处曰 成長步驟中,在中途便將結晶成 =曰曰 ς ^、、Ό阳成長法,變更為結晶成長速度較快的結晶成長 容Π: ί ΐ ί i成長面形成一連串大致平面狀為止,採用 ( L刀(b — a)予以大致最大化的結晶成長、、去 (如:M0VPE法),之後便採用有效的輕易將厚度成形長1 得長法(如:_法),藉此便可在短時間内, 侍釔晶性優質的半導體結晶。 才π内獲 再者,第十二手段係在卜 部形成步驟中,你作刼t 十的任一手段之突起 置,方式,形成上述突起:大致寻間…定週期進行配 藉此’橫方向成長的成長條 生結晶性優劣上產生不 j致均4 ’便較難產 上方,在利用基板層完全覆止=:突起部間的谷部 生局部不均的現象,因此嬖如:將:d’ ’因為較難產 ;結晶成長度較緩慢的結晶法,於中途便 較快的結晶成長法的主 又更為結晶成長速度 專心的決定此時Γ 0”便可輕易的正確、提早、或 再者’依照本手段, 等,而可將上述剪切# :D將上述各空洞形成大致均 q切應力大致均勾的分配於各突起部上, 9ll022l6.ptd 第13頁 57590891102216.ptd Page 12 575908 V. Description of the invention (9) The tensile stress will be alleviated, and the misalignment or cracking of the substrate layer can be reduced to produce “intensified substrate layer” and the above shear stress can be easily removed. In the above-mentioned protruding part. Shan again, the tenth means is the growth step in any one of the means from the first to the tenth, and will be crystallized in the middle of = growth method, Ό ς, 法 yang growth method, change To increase the crystal growth capacity of the crystal with a faster crystal growth rate: ί ΐ ί until the growth surface forms a series of approximately flat shapes, use (L knife (b — a) to maximize the crystal growth, and remove (eg: M0VPE method) Then, an effective method for easily forming the thickness by 1 (such as the _ method) is adopted, so that semiconductor crystals of good yttrium quality can be crystallized in a short period of time. The means is in the formation step of the Bu Department. You can use any of the means of t 十 to place the means to form the above-mentioned protrusions: roughly find the time ... at regular intervals to match the 'horizontal growth of the growth of the growth of the crystalline quality. It will be more difficult to give birth above 4 ' Using the substrate layer to completely cover =: The unevenness between the valleys of the protrusions causes local unevenness, so for example: d '' because it is difficult to produce; crystallization into a slower crystallization method, the crystallization is faster in the middle The master of the growth method is more crystalline and the growth rate is determined intently. At this time, Γ 0 "can be easily correct, early, or again. According to this method, etc., the above cut #: D will form the above holes. Approximately uniform q-shear stress is distributed approximately equally on each protrusion, 9ll022l6.ptd Page 13 575908

因此全部突起部的斷裂不致產生不均 底基板與基板層的分離。 而可確實的實施基 再者,第十三手段係在上述第十二手$ &amp; α 驟中’在以-邊狀〗_上的大致=步 次ί三角格子之格子點上形成突起部。為基礎之二 〜猎,此手段’便可較上述第十二手段,粬 貫的實施,並可確實的減少錯位數。 八胆 、確 致正六角形、大致圓形、或四角形。 藉由此手段,因 物系化合物半導體 將突起部的水平方 均大致一樣,因此 三角形,因為容易 為恰當。此外,圓 易形成,此相對於 屬於優點。 為可輕易在各部位 所形成結晶的結晶 向長度(粗度)限制 便可抑制錯位數。 合致於半導體結晶 形或四角形就製造 現行一般蝕刻加工 整合利用第m族氮化 軸方向,或者因為可 為在任意水平方向上 特別係正六角形或正 的結晶構造,因此最 技術觀點而言,較容 技術水準現況下,便 再者’弟十五手段係在上述第十四手段的突起部形成步 驟中,將突起部配置間隔(配置週期)設定在0 · 1 “ m以上且 1 0 // m以下。雖依存於結晶成長的實施條件,但最好將突 起部的配置間隔設定在〇·5〜8 /zm左右。其中,所謂此配置 間隔,係指相互接近的各突起部中心點間的距離。 藉此手段,便可利用基板層覆蓋突起部的谷部上方,同Therefore, breakage of all the protrusions does not cause uneven separation of the base substrate and the substrate layer. And it can be surely implemented that the thirteenth means is to form protrusions on the lattice points of the triangular lattice in roughly equal to the number of steps in the tenth second-hand $ &amp; α step above. . Based on the second method, hunting, this method can be implemented more consistently than the twelfth method mentioned above, and the number of misplacements can be reduced reliably. Eight gall, true hexagon, approximately round, or quadrangular. By this means, since the compound semiconductors have approximately the same horizontal level of the protrusions, the triangles are easy to be appropriate. In addition, the ease of formation is a relative advantage. In order to easily limit the length (thickness) of the crystals that can form crystals at various locations, the number of dislocations can be suppressed. Due to the semiconductor crystal shape or the quadrangle shape, the current general etching process is used to integrate the direction of the m-group nitride axis, or because it can be a regular hexagon or a positive crystalline structure in any horizontal direction, so in the most technical point of view, In the current state of technological standards, the '15th means is the protrusion forming step of the 14th means, and the protrusion arrangement interval (arrangement period) is set to 0 · 1 "m or more and 1 0 // m or less. Although it depends on the implementation conditions of crystal growth, it is best to set the arrangement interval of the protrusions at about 0.5 to 8 / zm. The arrangement interval refers to the center points of the protrusions that are close to each other. By this means, the substrate layer can be used to cover the upper part of the valley of the protrusion, the same as

91102216.ptd 第14頁 χ59〇8 丨 - 五、發明說明(11) 時可在突起部間形成空洞。 :此值過小的話’幾乎無法獲得EL〇的作用, 另化。此外,所形成空洞若過小 ~ b日性將 過所需厚度以上的情況下,突起部將4=層厚度未超 再者,此值若過大的話,便無法確實 犬起部的谷部上方,而無法獲得結晶性 :蓋 (基板層)。 、仏越的結晶 法ί=二此々值過大的話’谷部露出面將過廣,而幾乎盈 ,化。此外,在基板層厚度未超過所u 下,突起部將不易斷裂。 而与度以上的情況 =者,第十六手段係在上述第十五手段的突起 下’將突起部的縱向高度設定在0.5心以上,2〇 乂以乂 # η高度過低的言舌’便如同無突起部的情況,幾乎盔法 “ELO的作用,且結 匕 戍十…法 的話,便無法形成上述空洞。 …度過低 突的ϊϊ高度過高的話’突起部本身便較難形成,在 亦將消耗所-上便需要相當以上的時間’ i基底基板材料 話,C以上,故最好不要。此外,若此高度過高的 斷裂突ϋ力便將分散於突起部的縱向χ ’而車交難確實的 再者,第十七手段係在上述第十六手段的突起部形成步 91102216.ptd 第15頁 575908 五、發明說明(12) 驟中’將突起却&amp; ^ 上、且1〇 /卩的k向粗度、寬度或直徑設定在0.1 以 好將突起Γ二二;7、存,结晶成長,實_ 右。 又 丸度或直径设疋在0.5〜5/zm左 若此粗度過^日ώΛι &amp; 長層)上的應力,隨晶格常數差而作用於基板層(成 錯位數。反\ 將變得較大,而較容易增加基板層的 困難,或突起邻Ϊ過於細腻的話,突起部本身形成便較為 好不要。 。碩頂部的結晶成長速度b將便遲緩,故最 再者,gp便利用 若突起部的橫向剪切應力等)而使突起部斷裂時, 易產生益法確者鼢二、寬度、或直徑過大的話,因為較容 再者rip _裂的部分,故最好不要。 影響力大小,並非差而作用於基板層(成長層)上的應力 依存於突起部的存於突起部的橫向粗度(長度),亦 當的話,如上述,ρ ί ί ί。所以,若該等設定範圍不適 容易增加基板声Μ二曰曰σ系數差的應力影響將變大,而較 再者,突:::數,故最好不要。 因為如上述設定、=部附近的橫向粗度、寬度、或直徑, 面、底面、或水平2恰當值或適當範圍,因此突起部的上 狀),尤以朝向外相截面的形狀,至少局部封閉的形狀(島 面、底面、或水、 凸出封閉形狀者為佳。尤以此上 等形狀者為佳7。面的形狀呈大致圓形或大致正多角形 向,確實的且輕县3由ib種設定,便可相對於任意水平方 的貫現上述最恰當值或適當範圍。91102216.ptd Page 14 χ59〇8 丨-Explanation of the invention (11) A cavity can be formed between the protrusions. : If this value is too small, the effect of EL0 is hardly obtained, and it is different. In addition, if the formed cavity is too small ~ b will exceed the required thickness by day, the protrusion will be 4 = the thickness of the layer is not over, if this value is too large, the upper part of the valley of the dog's rising part cannot be determined. It is not possible to obtain crystallinity: cover (substrate layer). The crystallizing method of 仏, 二 = 2. If the value of 过 is too large, the exposed surface of the valley will be too wide, and it will almost become profitable. In addition, when the thickness of the substrate layer does not exceed 50 μs, the protrusions are less likely to break. In the case where the degree is equal to or higher, the sixteenth means is under the protrusions of the fifteenth means 'set the longitudinal height of the protrusions to be more than 0.5 centimeters, and 20% is a speech that is too low in height.' Just like in the case of no protrusions, the helmet method "ELO" is almost used, and the above mentioned cavities cannot be formed if the method is used.… If the height of the ridges that pass through the low protrusions is too high, the protrusions themselves are difficult to form. It will take a considerable amount of time for the substrate to be consumed. 'I The base substrate material is more than C, so it is best not to use it. In addition, if the fracture protrusion force is too high, it will be dispersed in the longitudinal direction of the protrusion χ 'And the traffic accident is truly true, the seventeenth means is the step of forming the protrusion of the sixteenth means 91102216.ptd page 15 575908 5. In the description of the invention (12) step' will be raised &amp; ^ And the k-direction thickness, width, or diameter of 10 / 卩 is set to 0.1 so that the protrusion Γ is 22; 7, the crystal grows, and the solid is right. The shot size or diameter is set to 0.5 to 5 / zm. Zuo Ruo this rough through the stress on ^ 日 ώΛι &amp; long layer), with the lattice constant And acting on the substrate layer (into the wrong number of bits. The reverse will become larger, and it is easier to increase the difficulty of the substrate layer, or if the protrusions are too delicate, the protrusions themselves will be better formed. The growth rate b will be slow, so most of all, gp is convenient to use when the protrusion is broken, etc.) and the protrusion is broken, it is easy to produce the effective method. If the width, or diameter is too large, because It is best not to allow the rip _ cracked part. The magnitude of the influence is not bad, and the stress acting on the substrate layer (growth layer) depends on the lateral thickness (length) of the protruding part that exists in the protruding part. If so, as mentioned above, ρ ί ί ί. Therefore, if the setting range is not suitable, it is easy to increase the stress effect of the difference in the σ coefficient of the substrate sound, and more importantly, the sudden :: number, so the most It ’s okay. Because of the above settings, the horizontal thickness, width, or diameter near the part, the appropriate value or range of the surface, bottom, or level (the upper part of the protrusion), especially the shape of the cross section of the external phase, At least partially sealed The shape of the island (island, bottom, or water, protruding and closed shape is preferred. Especially the first-class shape is better. 7. The shape of the surface is approximately circular or approximately regular polygonal direction. By setting ib, the above-mentioned optimum value or appropriate range can be realized with respect to any level.

第16頁 575908Page 16 575908

五、發明說明(13) B曰 再者,帛十八手段係在上述第十七的任_手段中 ::广刻處理、電子束照射處理、 田射寺先子處理、化孚處理、或者切削或 理,、藉由使基底基板突起部谷部之至少其中_ 5域之結晶性或分子構造,產生劣化或變化,便可降;此 出。區域中的第m族氮化物系化合物半導體之結晶成長速 藉由此手段,上述結晶成長速度的差分(b—a)便可變得 更大。故’依照此手段的話阳太办』 J古因為犬起部頭頂部附近的結 曰曰成長速度相對性的變大,因此藉由如同上述的作用,便 可緩和在基板層結晶成長時,作用於基板層上 基板與基板層間之晶格常數差而衍生出的應力」,且基板 層上較難產生錯位與龜裂。 再者’第十九手段係在上述任一分離步驟中,在將由基 底基板與基板層所構成的基板’歹隻留於成長裝置的反應室 中,並在將大致一定流量的氨(NH3)氣流通於反應室内的 狀態下,依大約「-10(rc/nlln—0.5t:/min」左右的冷卻 速度,冷卻至大致常溫。 譬如藉由此種手段,便可優質的維持基板層的結晶性, 並可確實的實施上述分離步驟。 再者,第一十手段係至少在上述任一分離步驟更後面, 没置有將殘留於基板層背面的突起部斷裂殘骸,利用蝕刻 等化學或物理加工處理而予以去除的殘骸去除步驟。 依照此手段的話,當在基板層背面(剝離基底基板的面)V. Description of the invention (13) B means again that the eighteenth means are in any of the seventeenth means mentioned above :: wide-cut processing, electron beam irradiation processing, Tianshe Temple ancestor processing, chemical treatment, or Cutting or cutting can be reduced by causing deterioration or changes in the crystallinity or molecular structure of at least one of the _ 5 domains in the valley portion of the base substrate protrusion; Crystal growth rate of the group m nitride-based compound semiconductor in the region By this means, the difference (b-a) of the crystal growth rate can be made larger. Therefore, "Yangtaiban if you follow this method" J Gu because the growth rate of the knot near the top of the dog's head is relatively large, so by the effect as described above, the effect of the substrate layer crystal growth can be eased The stress derived from the difference in lattice constant between the substrate and the substrate layer on the substrate layer ", and it is more difficult to cause dislocations and cracks on the substrate layer. Furthermore, in the nineteenth means, in any of the above-mentioned separation steps, the substrate consisting of the base substrate and the substrate layer is left in the reaction chamber of the growth device, and ammonia (NH3) is supplied at a substantially constant flow When the air flow is in the reaction chamber, it is cooled to about normal temperature at a cooling rate of about "-10 (rc / nlln-0.5t: / min". For example, by this method, the substrate layer can be maintained with high quality. It is crystalline, and the above-mentioned separation step can be carried out with certainty. Furthermore, the tenth means is at least after any of the above-mentioned separation steps. Debris removal step to remove by physical processing. According to this method, when the substrate layer is on the backside (the surface on which the base substrate is peeled off)

91102216.ptd 第17頁 575908 五、發明說明(14) 上形成半導體發光元件等電極時,便可抑制在電極與基板 〗的界面附近,產生電流不均或電阻抗,藉此便可達驅 動電壓的,低、或提昇發光強度等。 再者’藉由去除突起部的斷裂殘骸,當將電 ,體發光元件等的反射鏡時,因為將減少在鏡面附二= 吸收與散亂而提昇反射率,因此可提昇發光強度。 =者’譬如當利用研磨等物理加工處理,而實施此殘骹 除步,,情況時’因為亦可去除至基板層背面的緩衝z 二丄或提昇基板層背面的平坦度,因此便可抑制電流不 或電阻抗,或者減少鏡面附近的光吸收與散亂等,而走 強上述作用功效。 更補 再者,第二十一手段係在第m族氮化物系化合物半導_ 發光元件+,具備有:將採用上述第一至第二十中物丰二體 ϊ: m f晶之製造方法’而所製得的半導體結晶當作 &amp;晶成長基板。 曰α ,照此手段的話,藉由結晶性優質’且内部 便可輕易的製造第m族氮化物系化合物半導體5 尤兀件。 冰 再者,第二十二手段係藉由將採用上述第一至二 任=手段的半導體結晶之製造方法,而所製得的5二= 晶當作結晶成長基板的結晶成長,而製造第物了 化合物半導體發光元件。 私乳化物乐 、依照此手段的話,藉由結晶性優質且内部應力較 導體,便可輕易的製造第m族氮化物系化合物半導體發光91102216.ptd Page 17 575908 V. Description of the invention (14) When electrodes such as semiconductor light-emitting elements are formed on the electrode, it is possible to suppress the occurrence of current unevenness or electrical impedance near the interface between the electrode and the substrate, thereby achieving the driving voltage. , Low, or increase luminous intensity. Furthermore, by removing the broken debris of the protrusions, when the reflectors such as electricity, light emitting elements, etc., will be reduced on the mirror surface. Absorption and scattering will increase the reflectance, so the luminous intensity can be improved. = "For example, when using physical processing such as grinding to implement this residual removal step, when the situation occurs", because the buffer z can be removed to the back of the substrate layer or the flatness of the back of the substrate layer can be improved, it can be suppressed The current does not affect electrical impedance, or reduces light absorption and scattering near the mirror surface, and strengthens the above-mentioned effects. Furthermore, the twenty-first means is based on a group m nitride compound semiconducting light-emitting element +, and is provided with: the above-mentioned first to twentieth Zhongfeng Feng Di-body ϊ: mf crystal manufacturing method 'The resulting semiconductor crystal is used as an &amp; crystal growth substrate. In this case, α, according to this method, it is possible to easily manufacture the m-group nitride compound semiconductor 5 especially by using high crystallinity. In addition, the twenty-second means is a method for manufacturing a semiconductor crystal using the above-mentioned first to second methods, and the 52-crystal produced is used as the crystal growth of the crystal growth substrate to manufacture the first method. A compound semiconductor light-emitting element is realized. According to this method, by using this method, m group nitride compound semiconductor light-emitting materials can be easily manufactured by using high-quality crystallinity and relatively high internal stress.

91102216.ptd 第18頁 575908 五、發明說明(15) 元件。 藉由j述手⑫,便可解決0 【發明實施形態】 、 以下針對本發明根據具體每f ^ 明並不僅限於以下實施例。焉也列進行说明。惟,本發 以下便例示本發明實施 之製造順序概要。 蛉脰結晶(結晶成長基板) [1 ]突起部形成步驟 如圖2所示,在由矽所構91102216.ptd Page 18 575908 V. Description of the Invention (15) Elements. With the help of the hand description, 0 can be solved. [Inventive embodiments] The following description of the present invention is not limited to the following embodiments.焉 is also listed for explanation. However, the present invention exemplifies the outline of the manufacturing sequence in which the present invention is implemented.蛉 脰 Crystal (crystal growth substrate) [1] Protrusion formation steps As shown in Figure 2,

Si(m)面上,利用微影的乾= : = $基底基板Ml之 m、高度約1 // m的大致圓柱狀L』處理,將直徑約1 # 置間隔形成。配置形態係以一大起:1〇la,依約2 _的配 基礎的二次元三角形格子,於之大致正三角形為 的圓柱底面中心,而形 、Q拉子點配置在突起部〗〇la 101的厚度約20 0 _。 已部10 la。其中,基底基板 [2] 長步驟 物2:==:中,如圖4所示,利用有機金屬化合 二期狀態)起分別相互連接,並成長為-連串大致平 (hvpe w的成長步驟’然後’依循氫化物氣相成長法 m p κ ,施彳丁直到此基層板(結晶層)成長至2 0 0 // m左右 与度為止的成長步驟。 f 外λ,在本結晶成長步驟中,係採用氨(NH3)、載體氣 、三甲基鎵(Ga(CH3)3,以下稱「ΤΜ(ί」)、及三甲 575908 五、發明說明(16) 基铭(A1(CH3)3 ’以下稱「TMA」)。 (a) 首先’將設置有上述突起部101a的基底基板1〇1(圖 2 ),利用有機洗淨與酸處理進行洗淨,然後裝接於載置在 結晶成長裝置的反應室内之晶座上,接著在常壓下,使&amp; 一邊流入於反應室内,一邊在溫度丨丨〇 (pc下,將基底基板 1 0 1施行烘乾。 (b) 其次,在上述基底基板ι〇ΐΛ,依照M〇vpE法,供應 H2、NH3、TMG、TMA,而形成AiGaN緩衝層(基板層第一 層)102a。此AlGaN緩衝層102a的結晶成長溫度約11〇〇它, 厚度約0.3//m(圖3)。 (c) 在此AiGaN緩衝層(基板層第一層)1〇23上,供應&amp;、 NI、及T M G,使基板層弟二層的其中一部分(即,厚度約5 //m的GaN層102b),在成長溫度;[07 5 下進行結晶成長。 藉由此步驟,如圖4所示,基板層第二層(GaN層丨〇2b)的其 中一部分將朝橫向成長,而在谷部(即突起部丨〇丨a側邊)便 將形成較大的空洞。 此外,此時的TMG供應速度大約4〇 vmoi/min左右,基板 層第二層(GaN層102b)的結晶成長速度則約} 左右。 (d) 然後,依照氫化物氣相成長法(HVpE法),使上述GaN 層(基板層第二層)l〇2b更結晶成長至200 //m。此HVPE法的 GaN層102b之結晶成長速度約45 //m/Hr。 [3 ]分離步,驟 (a)在上述結晶成長步驟之後,將氨(NH3)氣體流入於結 晶成長裝置的反應室内,並將基底基板1〇1與(由A1GaN緩On the Si (m) surface, the photolithography is used to treat the dry =: = $ m of the base substrate M1 and a substantially cylindrical L ′ with a height of about 1 // m, and the diameters are formed at intervals of 1 #. The configuration pattern is based on a large: 10a, a two-dimensional triangular lattice based on a distribution of about 2 _, which is approximately the center of the cylindrical bottom surface of the regular triangle, and the shape and Q pull sub-points are arranged at the protrusions. 〇la The thickness of 101 is about 20 0 _. Has been 10 la. Among them, the base substrate [2] is a long-step product 2: == :, as shown in FIG. 4, using the organometallic compound two-phase state) are connected to each other and grow into a series of approximately flat (hvpe w growth steps) 'Then' follow the hydride vapor phase growth method mp κ, Shi Zhiding until the base plate (crystal layer) grows to about 2 0 0 // m and the degree of growth steps. F outer λ, in this crystal growth step It uses ammonia (NH3), carrier gas, trimethylgallium (Ga (CH3) 3, hereinafter referred to as "TM (ί"), and trimethyl 575908.) V. Description of the invention (16) Keming (A1 (CH3) 3 ' (Hereinafter referred to as "TMA"). (A) First, the base substrate 101 (FIG. 2) on which the protrusions 101a are provided is cleaned by organic cleaning and acid treatment, and then mounted on a crystal for growth. On the crystal seat in the reaction chamber of the device, and under normal pressure, while &amp; flowing into the reaction chamber, the base substrate 101 was dried at a temperature of 丨 (pc). (B) Next, The base substrate ι〇ΐΛ is supplied with H2, NH3, TMG, and TMA according to the MovpE method to form an AiGaN buffer layer (substrate The first layer) 102a. The crystal growth temperature of this AlGaN buffer layer 102a is about 1100 and the thickness is about 0.3 // m (Fig. 3). (C) Here the AiGaN buffer layer (the first layer of the substrate layer) 1023 In the above, supply &amp;, NI, and TMG, so that a part of the second layer of the substrate layer (that is, the GaN layer 102b with a thickness of about 5 // m) is grown at a growth temperature; [07 5. By this Step, as shown in FIG. 4, a part of the second layer of the substrate layer (GaN layer 丨 〇2b) will grow laterally, and a large cavity will be formed in the valley (ie, the side of the protrusion 丨 〇 丨 a). In addition, the TMG supply rate at this time is about 40 vmoi / min, and the crystal growth rate of the second substrate layer (GaN layer 102b) is about}. (D) Then, according to the hydride vapor phase growth method (HVpE Method) to make the above GaN layer (substrate layer second layer) 102b more crystalline and grow to 200 // m. The crystal growth rate of the GaN layer 102b of this HVPE method is about 45 // m / Hr. [3] Separation step Step (a) After the above crystal growth step, ammonia (NH3) gas is flowed into the reaction chamber of the crystal growth device, and the base substrate 101 and (from A1GaN slow

575908 五、發明說明(17) 衝層102a與GaN層102b所構成的)基板層102,冷卻至大致 常溫。此時的冷卻速度大約「-50°C/min〜_5°C/min」左 右。 (b )然後,當將其由結晶成長裝置的反應室中取出之 後,便獲得從基底基板1 0 1剝離出的GaN結晶。但是,此結 晶係在G a N層1 〇 2 b的背面上,仍殘留著A1 G a N緩衝層1 〇 2 a很 小的一部份殘骸,與突起部1 〇 1 a斷裂殘骸。 [4 ]直裂殘骸去除步驟 在上述分離步驟之後,藉由採用在氟酸中添加有硝酸的 混合液之蝕刻處理,將殘留於GaN結晶背面上,由s丨所構 成的AlGaN緩衝層1 〇2a之斷裂殘骸予以去除。 藉由以上的製造方法,可獲得厚度約2〇〇 之結晶性極 優越的優質GaN結晶(GaN層102b),即獲得從基底基板1〇1 獨立出的所需半導體基板。 再者’在上述實施例中,如圖2所例示般,雖基底基板 突起部或谷部係由鉛垂面與水平面所構成,但是亦可將該 等形成任意的斜面或曲面等。故,形成於圖2 ( c )所例示基 底基板上的谷部截面形狀,除大致矩形的凹字型之外,尚 可為如大致U字型或大致V字型等形狀,一般該等的形狀、 大小、間隔、配置、偏向等均可為任意。 【元件編號之說明】 101 基底基板(Si基板) 1 0 1 a 突起部 102 基板層(氮化物半導體層)575908 V. Description of the invention (17) The substrate layer 102 composed of the punched layer 102a and the GaN layer 102b is cooled to approximately normal temperature. The cooling rate at this time is about "-50 ° C / min ~ _5 ° C / min". (b) Then, after taking it out of the reaction chamber of the crystal growth apparatus, a GaN crystal peeled from the base substrate 101 was obtained. However, in this crystal system, a small part of the A1 G a N buffer layer 10 2 a remains on the back surface of the Ga N layer 1 02 b, and the debris is fractured from the protruding portion 101 a. [4] Straight crack debris removal step After the above separation step, an AlGaN buffer layer composed of s 丨 remaining on the back surface of the GaN crystal is formed by an etching treatment using a mixed solution of nitric acid added to hydrofluoric acid. The fracture remains of 2a were removed. By the above manufacturing method, a high-quality GaN crystal (GaN layer 102b) having a thickness of about 200 and excellent crystallinity can be obtained, that is, a desired semiconductor substrate independently obtained from the base substrate 101 can be obtained. Furthermore, in the above-mentioned embodiment, as shown in FIG. 2, although the projection or valley portion of the base substrate is composed of a vertical plane and a horizontal plane, it may be formed into an arbitrary inclined surface or curved surface. Therefore, the cross-sectional shape of the valley formed on the base substrate illustrated in FIG. 2 (c) may have a shape such as a generally U-shape or a substantially V-shape in addition to a generally rectangular concave shape, and generally such The shape, size, interval, arrangement, orientation, etc. can be arbitrary. [Explanation of element number] 101 Base substrate (Si substrate) 1 0 1 a Projection 102 Substrate layer (nitride semiconductor layer)

575908575908

91102216.ptd 第22頁 575908 圖式簡單說明 圖1係說明本發明作用的具突起部之基底基板,與成長 於其上的半導體結晶之部分片段的模式立體圖。 【2 係相 βπηρ明之實基icrmn-分片段模式立體圖(a )、俯視圖(b)、及剖視圖(c )。 圖3係基板層第一層(a 1G a N緩衝層)1 〇 2 a成膜的基底基板 101之模式立體圖(a)、俯視圖(b)、及剖視圖(c)。 圖4係豐層基板層ι〇2(層l〇2a與層l〇2b)之基底基板1〇1 的模式立體圖(a)、俯視圖(b)、及剖視圖(c )。 圖5係習知基底基板上之半導體結晶的模式剖視圖。91102216.ptd Page 22 575908 Brief description of the drawings Fig. 1 is a schematic perspective view of a base substrate with protrusions and a portion of a semiconductor crystal grown thereon, which illustrates the effect of the present invention. [2 System phase βπηρ Real solid icrmn-fragment mode perspective view (a), top view (b), and cross-sectional view (c). FIG. 3 is a schematic perspective view (a), a top view (b), and a cross-sectional view (c) of a base substrate 101 on which a first layer of the substrate layer (a 1G a N buffer layer) 1 02 is formed. FIG. 4 is a schematic perspective view (a), a top view (b), and a cross-sectional view (c) of the base substrate 101 of the rich-layer substrate layer ι02 (layers 102a and 102b). FIG. 5 is a schematic cross-sectional view of a conventional semiconductor crystal on a base substrate.

91102216.ptd 第23頁91102216.ptd Page 23

Claims (1)

575908 、申請專利範圍 1 · 種半導體結晶之製造方法’係利用橫向結晶成長作 用’在基底基板上形成由第in族氮化物系化合物半導體所 構成的基板層,而獲得從上述基底基板獨立出的半導體結 晶之方法,其特徵在於包括有: 在上述基底基板上,形成多數突起部的突起部形成步 驟; 將上述突起部表面的至少其中一部分,設定為上述基板 層開始結晶成長的最初成長面,並使上述基板層進行結晶 成長’直到此成長面分別相互連結且至少成長至一連串大 致平面為止的結晶成長步驟;以及 利用將上述突起部予以斷裂,而將上述基板層與上述基 底基板予以分離的分離步驟。 2 ·如申請專利範圍第1項之半導體結晶之製造方法,其 中,藉由將上述基板層與基底基板予以冷卻或加熱,而產 生隨基板層與基底基板間的熱膨脹係數差所衍生出的應 力’並利用此應力實施上述突起部的斷裂。 〜 3 ·種半導體結晶之製造方法,係利用橫向結晶成長作 用’在基底基板上形成由第Π族氮化物系化合物半導體所 構成的基板層,而獲得半導體結晶之方法,其特徵在於勺 括有: ' υ 在上述基底基板上,形成多數突起部的突起部形成步 將上述突起部表面的至少其中一部分,設定為上述美板 層開始結晶成長的最初成長面,並使基板層進彳^纟士曰成575908, patent application scope 1 · A method for manufacturing semiconductor crystals "uses lateral crystal growth" to form a substrate layer composed of a group in nitride-based compound semiconductor on a base substrate, and obtain an independent substrate from the above-mentioned base substrate The method for semiconductor crystallization includes: a protrusion forming step for forming a plurality of protrusions on the base substrate; and setting at least a part of the surface of the protrusions as an initial growth surface of the substrate layer to start crystal growth. And crystal growth of the substrate layer 'until the growth surfaces are connected to each other and grow at least to a series of substantially flat surfaces; and the substrate layer and the base substrate are separated by breaking the protrusions. Separation step. 2 · The method for manufacturing a semiconductor crystal according to item 1 of the scope of patent application, wherein the substrate layer and the base substrate are cooled or heated to generate a stress derived from a difference in thermal expansion coefficient between the substrate layer and the base substrate. 'And use this stress to break the protrusions. ~ 3 · A method for manufacturing a semiconductor crystal, which uses a lateral crystal growth effect to form a substrate layer composed of a group III nitride compound semiconductor on a base substrate to obtain a semiconductor crystal, which is characterized by the following: : Υ On the base substrate, a protrusion forming step that forms a large number of protrusions sets at least a part of the surface of the protrusions as the initial growth surface where the US plate layer starts crystal growth, and the substrate layer is advanced. Shi Yuecheng 575908 六、申請專利範圍 長,直到此成長面分別相互連結且至少成長至 平面為止的結晶成長步驟;其中, 致 在上述結晶成長步驟中,藉由調整上 化合物半導體的原料供給量q, 、: 勿糸 將上述基底基板的上述突#部間《 的露出區域之上述第m族氮化物系化合物半導體1晶^ 速度β,與上述突起部頭頂部6紝日 千V餵、、、口日日成長 π ^i = 的結晶成長速度b間的差分 (b - a ),控制為大致最大值。 4 ·如申請專利範圍第1項之半導 中,在上述結晶成長步驟中,::、,、°曰曰之製造方法,其 .^ Λ,^ ^ AA I^ 猎由調整上述第Π[族氮化物 糸化a物半v體的原料供給量q, 將上述基底基板的上诫穿4 ^ Ψ ^ ^ ^ m . ^ I邛間奋部至少其中一部分的 Λ ΛΛ 化物系化合物半導體結晶成長速度 λ’' Ϊ 2 ΐ ^頭頂部的結晶成長速❹間的差分 (b a) ’控制為大致最大值。 5.如申請專利範圍第3項之半導體結晶之製造方法,其 中,將上述原料供給量Q設定在1 μ mol/min以上,且100 //mol/min 以下。 由6 · t t :專利叙圍第1項之半導體結晶之製造方法,其 7 ^广底基板材料係採用矽(S i :)或碳化矽(S i C)。 •如、、=專利範圍第丨項之半導體結晶之製造方法,其 ,上述土底基板材料係採用S i (1 11), 在f述大起部形成步驟中,於上述基底基板的上述突起 間合部區域上’形成未露出S i (1 11)面的突起部。575908 VI. A crystal growth step with a long patent application range until the growth planes are connected to each other and at least grow to a flat surface; wherein, in the above crystal growth step, the raw material supply amount q of the compound semiconductor is adjusted by adjusting: Do not sacrifice the first group m nitride-based compound semiconductor 1 in the exposed area of the protrusion #interval of the base substrate ^ with a speed β of 6 纴 V, V, 突起, 日, 日, 日, 日, 日, 日, 日, 日, 日, 日, 日, 日, 日, 日, 日, 日, 日, 日, 日, 日, dai, 日, and 口 at the exposed area of the protrusion #part of the base substrate, and the group m nitride-based compound semiconductor 1 at a speed β, and the top part of the protrusion part 6 纴, V, 口, 口 日 日The difference (b-a) between the crystal growth rates b of growth π ^ i = is controlled to be approximately the maximum. 4 · As in the semi-conductor of item 1 of the scope of patent application, in the above-mentioned crystal growth step :: ,,, °, said manufacturing method, which. ^ Λ, ^ ^ AA I ^ the reason for adjusting the above Π [ The amount of raw material supply of the group nitride halogenated a-half v-body q passes the upper command of the base substrate 4 ^ Ψ ^ ^ ^ m. ^ I Λ ΛΛ compound-based compound semiconductor crystal growth of at least a part of The speed λ '' Ϊ 2 ΐ ^ The difference (ba) 'between the crystal growth speed at the top of the head is controlled to be approximately the maximum. 5. The method for manufacturing a semiconductor crystal according to item 3 of the scope of patent application, wherein the above-mentioned raw material supply amount Q is set to 1 μmol / min or more and 100 // mol / min or less. 6 · t t: The method for manufacturing a semiconductor crystal according to item 1 of the patent, wherein the substrate material of the bottom substrate is silicon (S i) or silicon carbide (S i C). • For example, the method for manufacturing a semiconductor crystal according to item 丨 of the patent scope, wherein the above-mentioned soil base substrate material is S i (1 11), and in the step of forming the large portion, the protrusion on the base substrate is used. A protruding portion is formed in the joint portion region without exposing the S i (1 11) plane. 第25頁 575908 六、申請專利範圍 8. 如申請專利範圍第1項之半導體結晶之製造方法,其 中,在上述突起部形成步驟後,設置有: 至少在突起部表面上,形成由「AlJahNCO &lt;x $ 1)」所 構成緩衝層的步驟。 9. 如申請專利範圍第8項之半導體結晶之製造方法,其 中,將上述緩衝層厚度設定在上述突起部縱向高度以下。 1 0.如申請專利範圍第1項之半導體結晶之製造方法,其 中,在上述結晶成長步驟中,將上述基板層厚度設定在5 0 // m以上。 1 1.如申請專利範圍第1項之半導體結晶之製造方法,其 中’在上述結晶成長步驟中’在中途便將結晶成長法’從 結晶成長度較緩慢的結晶成長法,變更為結晶成長速度較 快的結晶成長法。 1 2.如申請專利範圍第1項之半導體結晶之製造方法,其 中,在上述突起部形成步驟中,使上述突起部依大致等間 隔或一定週期進行配置的方式,形成上述突起部。 1 3.如申請專利範圍第1 2項之半導體結晶之製造方法, 其中,在上述突起部形成步驟中,在以一邊為0.1/zm以上 的大致正三角形為基礎之二次元三角格子之格子點上形成 上述突起部。 1 4 ·如申請專利範圍第1項之半導體結晶之製造方法,其 中,在上述突起部形成步驟中,將上述突起部的水平截面 形狀,形成大致正三角形、大致正六角形、大致圓形、或 四角形。Page 25 575908 6. Application for Patent Scope 8. The method for manufacturing a semiconductor crystal according to item 1 of the patent application scope, wherein after the above-mentioned protrusion forming step, it is provided with: at least on the surface of the protrusion, an AlJahNCO &lt; x $ 1) ”. 9. The method for manufacturing a semiconductor crystal according to item 8 of the patent application, wherein the thickness of the buffer layer is set to be less than the longitudinal height of the protrusion. 10. The method for manufacturing a semiconductor crystal according to item 1 of the scope of the patent application, wherein in the above-mentioned crystal growth step, the thickness of the substrate layer is set to 5 0 // m or more. 1 1. The method for manufacturing a semiconductor crystal according to item 1 of the scope of patent application, wherein the crystal growth method is changed from a crystal growth method with a slower length to a crystal growth rate in the above-mentioned crystal growth step. Faster crystal growth method. 1 2. The method for manufacturing a semiconductor crystal according to item 1 of the scope of patent application, wherein in the step of forming the protrusions, the protrusions are formed by arranging the protrusions at approximately regular intervals or at a constant period. 1 3. The method for manufacturing a semiconductor crystal according to item 12 of the scope of patent application, wherein, in the step of forming the protrusions, the lattice points of the two-dimensional triangular lattice based on a substantially regular triangle with a side of 0.1 / zm or more are used. The protrusions are formed thereon. 14 · The method for manufacturing a semiconductor crystal according to item 1 of the patent application scope, wherein in the step of forming the protrusion, the horizontal cross-sectional shape of the protrusion is formed into a substantially regular triangle, a substantially regular hexagon, a substantially circular shape, or The quadrangle. 91102216.ptd 第26頁 575908 六、申請專利範圍 1 5.如申請專利範圍第1項之半導體結晶之製造方法,其 中,在上述突起部形成步驟中,將上述突起部配置間隔設 定在0.1 //m以上且10 //m以下。 1 6.如申請專利範圍第1項之半導體結晶之製造方法,其 中,在上述突起部形成步驟中,將上述突起部的縱向高度 設定在0.5 //m以上,且20 //m以下。 1 7.如申請專利範圍第1項之半導體結晶之製造方法,其 中,在上述突起部形成步驟中,將突起部的橫向粗度、寬 度或直徑設定在0.1 //m以上,且10 //m以下。 1 8.如申請專利範圍第1項之半導體結晶之製造方法,其 中,在上述結晶成長步驟之前,利用各種蝕刻處理、電子 束照射處理、雷射等光學處理、化學處理、或者切削或研 磨等物理處理,使上述基底基板突起部谷部之至少其中一 部分的露出區域之結晶性或分子構造,產生劣化或變化, 藉以降低上述露出區域中的上述第Π族氮化物系化合物半 導體之結晶成長速度a。 1 9.如申請專利範圍第1項之半導體結晶之製造方法,其 中,在上述分離步驟中,在將由上述基底基板與上述基板 層所構成的基板,殘留於成長裝置的反應室中,並在將大 致一定流量的氨(NH3)氣流通於反應室内的狀態下,依大 約「-100 °C/ min〜- 0.5 °C/ min」左右的冷卻速度,將上述 基板冷卻至大致常溫。 2 0.如申請專利範圍第1項之半導體結晶之製造方法,其 中,至少在上述分離步驟更後面,設置有將殘留於上述基91102216.ptd Page 26 575908 6. Application for patent scope 1 5. The method for manufacturing a semiconductor crystal according to item 1 of the patent application scope, wherein in the above-mentioned protrusion forming step, the above-mentioned protrusion arrangement interval is set to 0.1 // m or more and 10 // m or less. 1 6. The method for manufacturing a semiconductor crystal according to item 1 of the scope of patent application, wherein in the step of forming the protrusions, the longitudinal height of the protrusions is set to 0.5 // m or more and 20 // m or less. 1 7. The method for manufacturing a semiconductor crystal according to item 1 of the scope of patent application, wherein in the above-mentioned protrusion forming step, the lateral thickness, width, or diameter of the protrusion is set to 0.1 // m or more, and 10 // m or less. 1 8. The method for manufacturing a semiconductor crystal according to item 1 of the scope of patent application, wherein before the above crystal growth step, various etching treatments, electron beam irradiation treatments, optical treatments such as laser, chemical treatments, or cutting or grinding are used. Physical treatment causes deterioration or change in crystallinity or molecular structure of the exposed area of at least a part of the valley portion of the base substrate protrusion, thereby reducing the crystal growth rate of the group III nitride compound semiconductor in the exposed area. a. 1 9. The method for manufacturing a semiconductor crystal according to item 1 of the scope of patent application, wherein, in the separating step, a substrate composed of the base substrate and the substrate layer is left in a reaction chamber of a growth apparatus, and The ammonia (NH3) gas was passed through the reaction chamber at a substantially constant flow rate, and the substrate was cooled to approximately normal temperature at a cooling rate of approximately "-100 ° C / min to -0.5 ° C / min". 20. The method for manufacturing a semiconductor crystal according to item 1 of the scope of the patent application, wherein at least after the above separation step, a method for leaving the residue on the above base is provided. 91102216.ptd 第27頁91102216.ptd Page 27
TW91102216A 2001-02-14 2002-02-07 Method for producing semiconductor crystal and semiconductor light-emitting element TW575908B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001036604A JP4084541B2 (en) 2001-02-14 2001-02-14 Manufacturing method of semiconductor crystal and semiconductor light emitting device

Publications (1)

Publication Number Publication Date
TW575908B true TW575908B (en) 2004-02-11

Family

ID=18899862

Family Applications (1)

Application Number Title Priority Date Filing Date
TW91102216A TW575908B (en) 2001-02-14 2002-02-07 Method for producing semiconductor crystal and semiconductor light-emitting element

Country Status (3)

Country Link
JP (1) JP4084541B2 (en)
CN (1) CN100414005C (en)
TW (1) TW575908B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8216367B2 (en) 2005-06-14 2012-07-10 Showa Denko K.K. Method for production of silicon carbide layer, gallium nitride semiconductor device and silicon substrate

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4201541B2 (en) 2002-07-19 2008-12-24 豊田合成株式会社 Semiconductor crystal manufacturing method and group III nitride compound semiconductor light emitting device manufacturing method
GB0326321D0 (en) * 2003-11-12 2003-12-17 Univ Warwick Formation of lattice-tuning semiconductor substrates
KR100553366B1 (en) 2004-05-14 2006-02-20 엘지전자 주식회사 Method for manufacturing semiconductor device of Nitride chemical
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
KR100695118B1 (en) * 2005-12-27 2007-03-14 삼성코닝 주식회사 Fabrication method of multi-freestanding gan wafer
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
JP2008053602A (en) * 2006-08-28 2008-03-06 Matsushita Electric Ind Co Ltd Semiconductor element, and manufacturing method thereof
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
JP4996186B2 (en) * 2006-09-25 2012-08-08 株式会社東芝 Semiconductor device, compound semiconductor substrate and manufacturing method thereof
WO2008039534A2 (en) 2006-09-27 2008-04-03 Amberwave Systems Corporation Quantum tunneling devices and circuits with lattice- mismatched semiconductor structures
US8502263B2 (en) 2006-10-19 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Light-emitter-based devices with lattice-mismatched semiconductor structures
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
JP4915282B2 (en) * 2007-05-28 2012-04-11 三菱化学株式会社 Base substrate for group III nitride semiconductor growth and method for growing group III nitride semiconductor
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
US8344242B2 (en) 2007-09-07 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-junction solar cells
US20110127544A1 (en) * 2008-05-06 2011-06-02 Kyma Technologies Group iii nitride templates and related heterostructures, devices, and methods for making them
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
JP5416212B2 (en) 2008-09-19 2014-02-12 台湾積體電路製造股▲ふん▼有限公司 Device formation by epitaxial layer growth
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
JP5426178B2 (en) * 2009-01-13 2014-02-26 日本碍子株式会社 Method for producing group III metal nitride single crystal
KR101064068B1 (en) * 2009-02-25 2011-09-08 엘지이노텍 주식회사 Manufacturing method of light emitting device
EP2415083B1 (en) 2009-04-02 2017-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Devices formed from a non-polar plane of a crystalline material and method of making the same
US8154034B1 (en) * 2010-11-23 2012-04-10 Invenlux Limited Method for fabricating vertical light emitting devices and substrate assembly for the same
TWI458129B (en) * 2010-12-21 2014-10-21 Lextar Electronics Corp Light emitting diode chip structure and fabrication method thereof
TWI446583B (en) * 2011-06-29 2014-07-21 Univ Nat Chiao Tung Method of semiconductor manufacturing process
JP2012006830A (en) * 2011-08-12 2012-01-12 Mitsubishi Chemicals Corp Ground substrate for growing group iii nitride semiconductor, and method for growing group iii nitride semiconductor
CN103165771B (en) * 2013-03-28 2015-07-15 天津三安光电有限公司 Nitride bottom layer with embedded hole structure and preparation method of nitride bottom layer
US9558943B1 (en) * 2015-07-13 2017-01-31 Globalfoundries Inc. Stress relaxed buffer layer on textured silicon surface
CN106816509B (en) * 2017-04-07 2018-12-21 厦门乾照光电股份有限公司 Compound substrate and preparation method thereof, the preparation method of light-emitting diode chip for backlight unit
CN108598237B (en) * 2018-07-12 2023-11-10 广东省半导体产业技术研究院 Semiconductor device and method for manufacturing the same
CN111430220A (en) * 2020-03-26 2020-07-17 江苏南大光电材料股份有限公司 Preparation method of GaN self-supporting substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5919305A (en) * 1997-07-03 1999-07-06 Cbl Technologies, Inc. Elimination of thermal mismatch defects in epitaxially deposited films through the separation of the substrate from the film at the growth temperature
JP3525061B2 (en) * 1998-09-25 2004-05-10 株式会社東芝 Method for manufacturing semiconductor light emitting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8216367B2 (en) 2005-06-14 2012-07-10 Showa Denko K.K. Method for production of silicon carbide layer, gallium nitride semiconductor device and silicon substrate

Also Published As

Publication number Publication date
JP2002241192A (en) 2002-08-28
JP4084541B2 (en) 2008-04-30
CN1863944A (en) 2006-11-15
CN100414005C (en) 2008-08-27

Similar Documents

Publication Publication Date Title
TW575908B (en) Method for producing semiconductor crystal and semiconductor light-emitting element
TWI233217B (en) Method for producing semiconductor crystal
US10100425B2 (en) Method for synthesis of high quality large area bulk gallium based crystals
EP1367150B1 (en) Production method for semiconductor crystal and semiconductor luminous element
JP4084544B2 (en) Semiconductor substrate and semiconductor device manufacturing method
JP4529846B2 (en) III-V nitride semiconductor substrate and method for manufacturing the same
US7649194B2 (en) Nitride semiconductor free-standing substrate
US7163876B2 (en) Method for manufacturing group-III nitride compound semiconductor, and group-III nitride compound semiconductor device
US20030207125A1 (en) Base substrate for crystal growth and manufacturing method of substrate by using the same
TW544930B (en) Method for producing semiconductor crystal
US11466384B2 (en) Method of forming a high quality group-III metal nitride boule or wafer using a patterned substrate
US20080296626A1 (en) Nitride substrates, thin films, heterostructures and devices for enhanced performance, and methods of making the same
JP2003163370A (en) Method of manufacturing semiconductor crystal
US20210246571A1 (en) Large area group iii nitride crystals and substrates, methods of making, and methods of use
JP2004055799A (en) Method for manufacturing semiconductor crystal
JP2002249400A (en) Method for manufacturing compound semiconductor single crystal and utilization thereof
JP2002299253A (en) Production method for semiconductor wafer and semiconductor device
US20210249266A1 (en) Large area group iii nitride crystals and substrates, methods of making, and methods of use
JP4749584B2 (en) Manufacturing method of semiconductor substrate
US11661670B2 (en) High quality group-III metal nitride seed crystal and method of making
EP4104202A1 (en) Large area group iii nitride crystals and substrates, methods of making, and methods of use
JP2020200235A (en) C PLANE GaN SUBSTRATE
JP2004091278A (en) Method of manufacturing semiconductor crystal
KR101094409B1 (en) Preparation of single crystalline gallium nitride thick film
JP4747319B2 (en) Heteroepitaxial growth method

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent