JP2002299253A - Production method for semiconductor wafer and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently produce a semiconductor crystal of low transition density and high quality without cracks or polycrystalline lumps (high heat reaction part), while using silicon as a base wafer. SOLUTION: A reaction-proofing layer is provided for preventing the reaction of a semiconductor of gallium nitride (semiconductor crystal A) to be laminated layer and Si and by forming the reaction-proofing layer composed of AlN or the like, for example, having a fusion point or thermal resistance higher than the semiconductor of gallium nitride on a 'sacrificial layer' like this, even when growing the crystal of the semiconductor of gallium nitride at a high temperature for a long time, the 'reaction part' with high heat is not formed in a semiconductor wafer laminated on the reaction-proofing layer. Namely, even if the semiconductor crystal A is grown at a high temperature for a long time, because of 'opeartion for blocking dispersion of silicon' that the reaction- proofing layer has, the generation of the 'reaction part' is settled within the inside of the 'sacrificial layer' and the 'reaction part' does not appear in the upper part higher than the reaction-proofing layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to silicon (Si).
The present invention relates to a method for obtaining a semiconductor substrate by growing a crystal made of a group III nitride compound semiconductor on a base substrate formed by the method. The present invention also relates to various semiconductor devices such as a group III nitride compound semiconductor light emitting device manufactured using such a semiconductor substrate as a crystal growth substrate.

[0002]

2. Description of the Related Art FIG. 2 is a schematic cross-sectional view of a conventional semiconductor crystal grown on a Si substrate (underlying substrate). The MOCVD method was employed for this crystal growth step. As illustrated in FIG. 2, a “reaction portion”, a dislocation, a crack, and the like are generated in a semiconductor crystal (GaN crystal or the like) grown at a high temperature on a Si substrate (base substrate) by a conventional technique.

[0003]

Dislocations and cracks are generated as a result of the action of stress generated based on a difference in thermal expansion coefficient and a difference in lattice constant between dissimilar materials. When the semiconductor device is manufactured, the device characteristics are deteriorated. Further, when an independent substrate (crystal) is to be obtained by removing the underlying substrate made of, for example, silicon (Si) and leaving only the growth layer, the large area (1
cm ² ) is almost impossible.

Further, a target semiconductor substrate (semiconductor crystal A)
In the vicinity of the crystal growth temperature of 1000 ° C. to 1150 ° C., silicon (Si) and gallium nitride (GaN) may react (“reaction part” in the figure). Therefore, there is a problem that it is not easy to obtain a single-crystal GaN substrate through a high-temperature crystal growth process.

In order to obtain a single crystal GaN substrate,
Although a method of using a silicon thin film that does not easily generate the above stress as a single crystal growth substrate has been reported, these thin films are easily damaged, and it is not easy to directly handle the thin film before starting the crystal growth. Therefore, it is difficult for these conventional methods to mass-produce a large-area semiconductor substrate with high yield.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to use relatively inexpensive silicon (Si) as an undersubstrate to form cracks or polycrystalline masses (with high heat). It is to efficiently produce a high-quality semiconductor crystal without a reaction part). A further object of the present invention is to manufacture a high-quality semiconductor device by using the above-mentioned semiconductor crystal manufactured with high quality as a crystal growth substrate.

[0007]

Means for Solving the Problems, Functions and Effects of the Invention In order to solve the above-mentioned problems, the following means are effective. That is, a first means is to grow a semiconductor crystal A made of a group III nitride compound semiconductor on an underlying substrate formed of silicon (Si). A sacrifice layer growing step of crystal-growing a “sacrifice layer” made of a semiconductor substantially the same kind as the semiconductor crystal A, and a silicon (Si) made of a crystalline material B having a higher melting point or heat resistance than the semiconductor crystal A on this sacrifice layer )
A reaction preventing layer forming step of laminating a “reaction preventing layer” for preventing the diffusion of, and a crystal growing step of crystal growing a semiconductor substrate made of the semiconductor crystal A on the reaction preventing layer. is there.

However, the above-mentioned semiconductor substrate composed of the above-mentioned semiconductor crystal A may have a single-layer structure or a multi-layer structure (multi-layer structure). Also, here, "III
The group nitride compound semiconductor "Generally, binary, ternary, or quaternary" _{Al x Ga y In (1-} xy) N (0 ≦ x ≦ 1,0
≦ y ≦ 1, 0 ≦ x + y ≦ 1) ”, a semiconductor having an arbitrary mixed crystal ratio and a semiconductor further doped with p-type or n-type impurities are also included in the present specification. It falls under the category of “III-nitride compound semiconductors”. Further, a part of the group III elements (Al, Ga, In) is replaced with boron (B) or thallium (Tl), or nitrogen (N) is used.
Part of phosphorus (P), arsenic (As), antimony (S
Semiconductors substituted with b), bismuth (Bi) or the like are also included in the category of “III-nitride compound semiconductors” in the present specification.

The p-type impurities include, for example, magnesium (Mg) or calcium (C
a) and the like can be added. As the n-type impurity, for example, silicon (Si), sulfur (S), selenium (Se), tellurium (Te), germanium (Ge), or the like can be added. In addition, two or more of these impurities may be added at the same time, or both types (p-type and n-type) may be added at the same time.

FIG. 1 is a schematic cross-sectional view in a manufacturing process of a semiconductor crystal for exemplifying a basic concept of the present invention. This reaction prevention layer is formed of a gallium nitride-based semiconductor (semiconductor crystal A) laminated later than the reaction prevention layer and S.
In order to prevent the reaction with i, the reaction preventing layer (for example, SiC or AlN) having a higher melting point or heat resistance than the gallium nitride-based semiconductor is formed on the “sacrifice layer”. Even when a gallium nitride-based semiconductor (semiconductor crystal A) is grown at a high temperature for a long time by forming a crystalline material B), the semiconductor substrate (semiconductor crystal A) laminated on the reaction prevention layer can be formed. Thus, the formation of the "reaction portion" due to the high heat is eliminated. In other words, even if the semiconductor crystal A is grown for a long time at a high temperature, the generation of the "reaction portion" is not caused by the "sacrificial effect" due to the "action for preventing diffusion of silicon (Si)" provided in the reaction prevention layer. Layer, and the "reaction part" does not appear above the reaction prevention layer.

Also, the above-mentioned “reaction portion” is actively generated inside the above-mentioned “sacrifice layer”, so that polycrystalline GaN (polycrystalline lump) is formed between the silicon (Si substrate) and the reaction prevention layer. Is formed, the stress acting on the reaction preventing layer is reduced after the reaction portion is formed, and these stresses do not easily act to form cracks in the reaction preventing layer. Therefore, cracks penetrating in the vertical direction are less likely to occur in the reaction preventing layer. For this reason,
Since the base substrate (Si substrate) and the gallium nitride-based semiconductor (semiconductor crystal A) can be more reliably cut off by the reaction prevention layer without cracks penetrating in the vertical direction, the above-mentioned “reaction portion” Can be more reliably prevented in the semiconductor substrate (semiconductor crystal A).

Further, since the "stress generated between the base substrate and the semiconductor substrate" is relieved by the above-mentioned polycrystalline mass, the semiconductor substrate (desired semiconductor crystal A) grows during the crystal growth. Unnecessary stress acting on the surface is suppressed, and the density of occurrence of dislocations and cracks is reduced. That is, due to the above-described stress relaxing action, dislocations are less likely to be generated in the gallium nitride-based semiconductor (semiconductor crystal A), and the crack generation density can be significantly reduced.

[0013] Further, the above-mentioned "reaction part" is made of GaN.
Since this portion is formed from a polycrystalline mass, this portion is structurally weak, has low durability against external force and internal stress, and is brittle. Therefore, the target semiconductor substrate can be easily separated from the base substrate (Si substrate) by the “sacrifice layer” having the above-described reaction part.

By the above action and synergistic effect, it becomes possible or easy to obtain a high-quality semiconductor substrate (semiconductor crystal A) free of the above-mentioned "reaction portion" and cracks and having sufficiently suppressed dislocation density.

[0015] The second means is the first means of the composition formula of the above semiconductor crystal A is "Al _x Ga _y
In _(1-xy) N (0 ≦ x <0.9, 0.1 <y ≦ 1, x + y
.Ltoreq.1) ".

Further, the third means may be the first or the second means.
In the above method, the crystalline material B for forming the reaction preventing layer is made of silicon carbide (SiC), aluminum nitride (Al
N) or spinel (MgAl ₂ O ₄ ).

[0017] The fourth means may be the first or the second means.
Means, the crystalline material B for forming the reaction preventing layer is made of Al having an aluminum composition ratio of at least 0.30 or more.
GaN, AlInN, or AlGaInN. Further, as the crystalline material B, it is desirable to select a stable material having relatively strong bonding strength and high heat resistance (melting point).

Further, the fifth means includes the first to fourth means.
In any one of the means, the thickness of the reaction prevention layer is set to 0.1.
The thickness is formed to be not less than 2 μm and not more than 2 μm. More preferably, the thickness is 0.5 μm or more and 1.5 μm or less.

If the thickness is too small, the film thickness becomes uneven, or the crystalline material B forming the reaction preventing layer is not a sufficiently stable substance.
a) or gallium nitride (GaN) and silicon (S
i) cannot be completely shut off. Therefore, based on these reactions, the “reaction part (polycrystalline Ga
N) "cannot be sufficiently obtained.

On the other hand, if the thickness of the reaction preventing layer is too large, cracks easily occur in the reaction preventing layer, and the upper semiconductor crystal A (gallium (Ga) or gallium nitride (GaN) in the semiconductor substrate) and silicon ( Si) cannot be completely shut off. Therefore, the effect of preventing the formation of the “reaction portion” based on these reactions cannot be sufficiently obtained. As a result, the semiconductor substrate (the upper semiconductor crystal A)
A reaction part is formed therein. On the other hand, if the thickness of the reaction preventing layer is too large, the lamination time and the laminating material of the reaction preventing layer are additionally required, which is not desirable in terms of production cost and the like.

Further, the sixth means includes the first to fifth means.
In any one of the means, two or more reaction preventing layers are laminated. As described above, by stacking a plurality of reaction preventing layers, diffusion of silicon can be more reliably prevented, so that generation of a reaction portion can be more reliably prevented.

Further, the seventh means includes the first to sixth means.
In any one of the means, the “Al _x Ga ₁ -xN (0 <x ≦ 1)” is directly applied on the base substrate or the reaction prevention layer.
Is to form a buffer layer C composed of

However, the above-mentioned buffer layer C is approximately 1
A semiconductor layer such as AlN or AlGaN that grows at about 100 ° C. Aside from the buffer layer C, the semiconductor layer further has substantially the same composition as the above-mentioned buffer layer C (eg, AlN or AlGa).
An N) intermediate layer (hereinafter sometimes simply referred to as a “buffer layer”) is provided in a target semiconductor substrate (semiconductor crystal A) periodically, alternately with other layers, or in a multilayer structure. It may be laminated so as to be configured.

By laminating these buffer layers (or intermediate layers), the crystallinity can be improved by the same operation principle as that of the related art such that the stress acting on the semiconductor substrate (growth layer) due to the lattice constant difference can be reduced. It becomes possible. Also,
Such actions and effects are particularly remarkable when the crystalline material B constituting the reaction preventing layer is silicon carbide (SiC) or the like. That is, in this case, it is more desirable to form the buffer layer C on the reaction prevention layer.

An eighth means is that, in the seventh means, two or more buffer layers C are laminated.
For example, a configuration is conceivable in which two buffer layers C are provided, one on each of the upper surface of the base substrate (Si substrate) and the upper surface of the reaction prevention layer. With such a multilayer structure of the buffer layer, the operation and effect of the seventh means can be more reliably obtained.

The ninth means is the seventh or eighth means.
Means, the thickness of the buffer layer C is 0.01 μm or more,
It is formed to 1 μm or less. More preferably, 0.
The thickness is preferably not less than 02 μm and not more than 0.5 μm.

If the film thickness is too large, cracks are likely to occur in the buffer layer C, and the production time and materials are undesirably increased in cost. If the thickness is too small, it is difficult to form the buffer layer substantially uniformly. For this reason, unevenness in film formation of the buffer layer (a part where the film is not sufficiently formed) is generated, and the crystallinity tends to be uneven, which is not desirable.

A tenth means is that, in the crystal growth step of any one of the first to ninth means, the semiconductor crystal A is stacked to a thickness of 50 μm or more. As the thickness increases, the tensile stress on the semiconductor substrate (semiconductor crystal A) is relaxed, the density of dislocations and cracks in the semiconductor substrate can be reduced, and the semiconductor substrate can be made stronger. Handling at the time is also easy.

An eleventh means is that the semiconductor substrate manufactured by any one of the first to tenth means is provided as a crystal growth substrate in a group III nitride compound semiconductor device. According to this means, it is possible to easily or easily manufacture a group III nitride compound semiconductor element such as a light emitting element such as an LED or a transistor circuit such as an FET from a semiconductor having good crystallinity and a small internal stress. Become.

In a twelfth aspect, a group III nitride-based compound semiconductor device is manufactured by crystal growth using the semiconductor substrate manufactured by any one of the first to tenth means as a crystal growth substrate. It is to be. According to this means,
It becomes possible or easier to manufacture a group III nitride compound semiconductor device from a semiconductor having good crystallinity and low internal stress. By the means of the present invention described above, the above problems can be effectively or rationally solved.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In carrying out the present invention, individual manufacturing conditions may be arbitrarily selected from the following.
These manufacturing conditions may be arbitrarily combined. First, as a method for forming a group III nitride compound semiconductor layer, a metal organic chemical vapor deposition method (MOCVD or MCVD) is used.
OVPE) is preferred. However, molecular beam epitaxy (MBE), halide vapor epitaxy (Halide VPE), liquid phase epitaxy (LPE), etc. may be used, and each layer may be formed by a different growth method. .

The buffer layer is preferably formed on the surface of the underlying substrate, the surface of the reaction preventing layer, or in the semiconductor substrate (semiconductor crystal A), for the purpose of correcting lattice mismatch.

In particular, the semiconductor substrate (semiconductor crystal A)
When laminating a buffer layer (the above-mentioned intermediate layer),
For the buffer layer, a group III nitride formed at low temperature
Compound semiconductor Al_xGa_yIn_1-xyN (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y
≦ 1), more preferably Al_xGa _1-xUse N (0 ≦ x ≦ 1)
be able to. This buffer layer may be a single layer,
Of different layers. Method of forming buffer layer
May be formed at a low temperature of 380 to 420 ° C.
It may be formed by MOCVD at a temperature in the range of 00 to 1180 ° C.
In addition, using a DC magnetron sputtering device, high purity
Reacted using aluminum and nitrogen gas as raw materials
A buffer layer consisting of AlN by passive sputtering
You can also.

Similarly, the general formula Al _x Ga _y In _1-xy N (0 ≦ x ≦ 1, 0
≦ y ≦ 1, 0 ≦ x + y ≦ 1, the composition ratio is arbitrary). Further, a vapor deposition method, an ion plating method, a laser ablation method, and an ECR method can be used. Buffer layer by physical vapor deposition, 200-600
It is desirable to carry out at ℃. The temperature is more preferably from 300 to 600 ° C, and even more preferably from 350 to 450 ° C. When a physical vapor deposition method such as the sputtering method is used, the thickness of the buffer layer is desirably 100 to 3000 mm. More preferably, 100-400〜, most preferably 100
~ 300Å.

As the multilayer, for example, Al _x Ga ₁ -xN (0 ≦ x
≦ 1) and a GaN layer are alternately formed, and layers having the same composition are alternately formed at a formation temperature of, for example, 600 ° C. or lower and 1000 ° C. or higher. Of course, these may be combined, and the multilayer is composed of three or more group III nitride-based compound semiconductors Al _x Ga _y In _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y
≦ 1) may be laminated. Generally, the buffer layer is amorphous and the intermediate layer is single crystal. A plurality of cycles may be formed with the buffer layer and the intermediate layer as one cycle, and the repetition may be an arbitrary cycle. The more repetitions, the better the crystallinity.

In the group III nitride compound semiconductor of the buffer layer and the upper layer, part of the group III element composition may be replaced with boron (B) or thallium (Tl), or the composition of nitrogen (N) may be reduced. Parts are phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi)
The present invention can be substantially applied even if it is replaced by. Further, these elements may be doped to such an extent that they cannot be displayed in composition. For example, a group III nitride-based compound semiconductor having no indium (In) or arsenic (As) in the composition of Al _x Ga _1-x N (0
≦ x ≦ 1), by doping aluminum (Al), indium (In) having a larger atomic radius than gallium (Ga), or arsenic (As) having a larger atomic radius than nitrogen (N), a nitrogen atom The crystal distortion may be improved by compensating for the expansion strain of the crystal due to the loss of the crystal with the compression strain.

In this case, since the acceptor impurity easily enters the position of the group III atom, a p-type crystal can also be obtained by as-grown. By improving the crystallinity in this way, threading dislocations can be further increased by 100 to 100 in accordance with the present invention.
It can be reduced to about 1/0. Buffer layer and
In the case of a base layer in which the group III nitride compound semiconductor layer is formed in two or more periods, it is more preferable to dope an element having a larger atomic radius than the main constituent element in each group III nitride compound semiconductor layer. When a light-emitting element is used, it is preferable to use a binary or ternary group III nitride-based compound semiconductor.

When an n-type group III nitride compound semiconductor layer is formed, Si, Ge, Se, Te,
A group IV element or a group VI element such as C can be added. Examples of p-type impurities include Zn, Mg, Be, Ca, Sr, and Ba.
A Group IV element or a Group IV element can be added. These may be doped with plural or n-type impurities and p-type impurities in the same layer.

It is optional to reduce dislocations in the group III nitride compound semiconductor layer by using lateral epitaxial growth. At this time, any method using a mask or filling the step by etching can be used.

The etching mask is made of polycrystalline silicon or polycrystalline silicon.
Polycrystalline semiconductors such as crystalline nitride semiconductors, silicon oxide (SiO_x),
Silicon nitride (SiN_x), Titanium oxide (TiO_X), Zirconium oxide
(ZrO _X), Oxides, nitrides, titanium (Ti), tungsten
High melting point metal such as (W)
Can be. These film forming methods include vapor deposition, sputtering, CV
Any method other than the vapor phase growth method such as D can be used.

When etching, reactive ion beam etching (RIBE) is desirable, but any etching method can be used. Instead of forming a step having a side surface perpendicular to the substrate surface, an anisotropic etching may be used to form, for example, a V-shaped section having no bottom surface at the bottom of the step.

Semiconductor elements such as FETs and light emitting elements can be formed on group III nitride compound semiconductors. In the case of a light-emitting element, the light-emitting layer may have a homo-structure, a hetero-structure, or a double-hetero structure in addition to a multiple quantum well structure (MQW) and a single quantum well structure (SQW). May be formed.

Hereinafter, the present invention will be described with reference to specific examples. However, the present invention is not limited to the embodiments described below. (First Embodiment) An outline of a procedure for manufacturing a semiconductor crystal (crystal growth substrate) in an embodiment of the present invention will be described below.

[1] Buffer Layer Forming Step First, "Al _x " was deposited on a Si (111) substrate surface at about 1100 ° C. by metal organic compound vapor phase epitaxy (MOVPE).
Ga _1-x N (x ≒ 0.20) ”
A film is formed in a thickness of about 0.2 μm to 0.3 μm.

[2] Step of Growing Sacrificial Layer Next, as the above-mentioned sacrificial layer, GaN is grown by vapor phase growth (MO).
VPE) to form a film of about 1 μm at about 1100 ° C.

[3] Step of Forming Reaction Prevention Layer This step of forming a reaction prevention layer is a manufacturing step of laminating a reaction prevention layer on the sacrificial layer. In the present reaction preventing layer forming step, a reaction preventing layer B made of aluminum nitride (AlN) is formed on the sacrificial layer at about 1100 ° C. by about 1 μm by vapor phase epitaxy (MOVPE).

[4] Crystal Growth Step Thereafter, in the present crystal growth step, the growth step until the semiconductor crystal A (GaN) grows on the reaction preventing layer B into a thick film of about 200 μm is performed in a halide vapor phase. Growth method (HVP
(Method E).

That is, a GaN layer (semiconductor crystal A) was grown on the reaction preventing layer B by about 200 μm according to the halide vapor phase epitaxy (HVPE). This H
The crystal growth rate of the GaN layer in the VPE method is about 4
It is about 5 μm / Hr.

[5] Separation Step (a) After the above-described crystal growth step, while the ammonia (NH ₃ ) gas is flowing into the reaction chamber of the crystal growth apparatus, the base substrate (Si
The wafer having the substrate is cooled to approximately room temperature. The cooling rate at this time is generally “-50 ° C./min to −5 ° C./mi
n ”.

(B) Thereafter, when these were taken out of the reaction chamber of the crystal growth apparatus, a GaN crystal (semiconductor crystal A) separated from the underlying substrate (Si substrate) was obtained. However, this crystal is one in which debris such as a sacrificial layer having a reaction part and a reaction prevention layer remain on the back surface of the GaN layer (semiconductor substrate).

[6] Debris Removal Step After the above separation step, debris such as a sacrificial layer having a reaction portion and a reaction prevention layer remaining on the back surface of the GaN crystal are removed by lapping.

However, this debris removal step may be performed by an etching process using a mixed solution obtained by adding nitric acid to hydrofluoric acid. When the reaction prevention layer B has sufficient conductivity, the reaction prevention layer B does not need to be removed. Also,
Alternatively, this step does not have to be particularly performed. For example,
Whether or not the debris removal step is required can be selected according to the electrode connection configuration of the semiconductor light emitting element and the like.

By the above manufacturing method, the film thickness is about 200 μm
Quality GaN crystal (GaN
Layer), that is, a desired semiconductor substrate (semiconductor crystal A) independent of the underlying substrate can be obtained. That is, a single crystal of gallium nitride (GaN), which has no GaN polycrystal (reaction portion) or cracks and is more excellent in crystallinity than before, can be obtained by the above-described method for producing a semiconductor crystal.

Therefore, when such a high-quality single crystal is used as a part of a semiconductor light emitting device such as a crystal growth substrate, a high-quality single crystal having a high luminous efficiency or a suppressed driving voltage as compared with the conventional one is obtained. It becomes possible or easy to manufacture semiconductor products such as semiconductor light emitting elements and semiconductor light receiving elements. The use of such a high-quality single crystal makes it possible or easy to manufacture not only an optical element but also a so-called semiconductor electronic element such as a semiconductor power element having a high withstand voltage or a semiconductor high-frequency element operating up to a high frequency. be able to.

In order to correct the lattice constant mismatch between the reaction preventing layer forming step and the crystal growth step, an additional 10
A buffer layer forming step of performing crystal growth at a high temperature of about 00C to 1180C may be provided.

In the above embodiment, the reaction preventing layer was
As the crystalline material B to be formed, Al _xGa_1-xN (0 <
x <1) may be used. Even in these crystalline materials B,
Functions and effects substantially similar to those of the above embodiment can be obtained. Furthermore,
More generally, the crystalline material B that forms the reaction prevention layer is
Silicon carbide (SiC), aluminum nitride (Al
N), spinel (MgAl_TwoO_Four) Or aluminum
AlGaN and Al having a composition ratio of at least 0.30 or more
InN or AlGaInN can be used.

The semiconductor crystal A forming the target semiconductor substrate is not limited to gallium nitride (GaN), but may be any of the above-mentioned general “III-nitride compound semiconductors”.
Can be arbitrarily selected. The target semiconductor substrate (semiconductor crystal A) may have a multilayer structure. For example, the growth temperature of the semiconductor crystal A constituting the target semiconductor substrate is increased in the middle of the growth process, and a semiconductor layer grown at a higher temperature is formed on the upper (upper) layer to form a multilayer structure, a buffer layer, Even if the intermediate layer is provided in the middle of the multilayer structure, the function and effect of the present invention can be sufficiently obtained.

Further, the material of the "sacrifice layer" does not necessarily have to be the same as the semiconductor substrate (semiconductor crystal A) for these purposes, and the material of the "sacrifice layer" is also the same as that of the general "I".
It can be arbitrarily selected from “Group II nitride-based compound semiconductors”. That is, the present invention is not particularly limited in the type (material) of the sacrificial layer and the target semiconductor crystal, and can be applied to known or arbitrary types of heteroepitaxial growth relating to the above-described base substrate (Si substrate).

In the above embodiment, the metalorganic compound vapor phase epitaxy (MOVPE) was used. However, the crystal growth of the present invention can also be carried out by the halide vapor phase epitaxy (HVPE). is there.

Furthermore, in the above embodiment, the method of using the semiconductor crystal A as the crystal growth substrate of the semiconductor element after separating the undersubstrate and removing the debris has been described, but these separation and debris removal are performed. The process may be performed after laminating the semiconductor layers of the semiconductor element itself, or may be used as a semiconductor element without performing a separation step or the like.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view in a manufacturing step of a semiconductor crystal for exemplifying a basic concept of the present invention.

FIG. 2 is a schematic cross-sectional view illustrating a conventional semiconductor crystal grown on a Si substrate (base substrate).

[Explanation of symbols]

 A: Semiconductor crystal (target semiconductor substrate) B: Reaction prevention layer (crystalline material) C: Buffer layer D: Silicon substrate (base substrate)

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Seiji Nagai 1 Ochiai Nagahata, Kasuga-cho, Nishi-Kasugai-gun, Aichi Prefecture Inside Toyoda Gosei Co., Ltd. Ground 1 Toyota Central R & D Co., Ltd. F term (reference) 4G077 AA03 BE11 BE15 DB05 EE01 EE06 EF03 FJ03 TK04 TK08 TK10 TK11 5F045 AA04 AA05 AA10 AA18 AA19 AB06 AB09 AB14 AB17 AB18 AB38 AD14 AD15 AF03 BB12 CA09 DA53

Claims (12)

[Claims] 1. A method for obtaining a semiconductor substrate by growing a semiconductor crystal A comprising a group III nitride compound semiconductor on an underlying substrate formed of silicon (Si), comprising: A sacrifice layer growing step of crystal-growing a “sacrifice layer” made of a semiconductor of substantially the same kind as the semiconductor crystal A, comprising a crystalline material B having a higher melting point or heat resistance than the semiconductor crystal A on the sacrifice layer; A reaction prevention layer forming step of laminating an “reaction prevention layer” for preventing diffusion of silicon (Si); and a crystal growth step of crystal growing the semiconductor substrate made of the semiconductor crystal A on the reaction prevention layer. And a method for manufacturing a semiconductor substrate. 2. The semiconductor crystal A has a composition formula of “Al _x Ga _y In _(1-xy) N (0 ≦ x <0.
9. The method according to claim 1, wherein the semiconductor substrate is made of a group III nitride-based compound semiconductor that satisfies "9, 0.1 <y≤1, x + y≤1)". 3. The crystalline material B for forming the reaction preventing layer includes silicon carbide (SiC), aluminum nitride (Al
3. The method according to claim 1, wherein the substrate is made of N) or spinel (MgAl ₂ O ₄ ). 4. The crystalline material B for forming the reaction preventing layer, wherein the AlGa having an aluminum composition ratio of at least 0.30 or more.
3. The method according to claim 1, wherein the semiconductor substrate is made of N, AlInN, or AlGaInN. 5. The method according to claim 1, wherein the thickness of the reaction preventing layer is 0.1 μm or more.
The method according to claim 1, wherein the semiconductor substrate is formed to have a thickness of 2 μm or less. 6. The method for manufacturing a semiconductor substrate according to claim 1, wherein two or more reaction preventing layers are laminated. 7. A step of forming a buffer layer C made of “Al _x Ga ₁ -xN (0 <x ≦ 1)” directly on the base substrate or the reaction preventing layer. The method of manufacturing a semiconductor substrate according to claim 1, wherein: 8. The method according to claim 7, wherein two or more buffer layers C are stacked. 9. The method of manufacturing a semiconductor substrate according to claim 7, wherein said buffer layer C is formed to a thickness of 0.01 μm or more and 1 μm or less. 10. The method of manufacturing a semiconductor substrate according to claim 1, wherein in the crystal growth step, the semiconductor crystal A is stacked at a thickness of 50 μm or more. 11. A group III nitride manufactured by using the method for manufacturing a semiconductor substrate according to claim 1, wherein the group III nitride includes the semiconductor substrate as a crystal growth substrate. -Based compound semiconductor devices. 12. A semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor substrate is manufactured by crystal growth using the semiconductor substrate as a crystal growth substrate. Group III nitride compound semiconductor device.