JP4749584B2 - Manufacturing method of semiconductor substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a method for obtaining a semiconductor substrate by growing a crystal made of a group III nitride compound semiconductor on a base substrate formed of silicon (Si).Related.
[0002]
[Prior art]
  FIG. 4 illustrates a schematic cross-sectional view of a conventional semiconductor crystal grown on a Si substrate (underlying substrate). The MOCVD method was adopted for this crystal growth process. As illustrated in FIG. 4, a “reaction portion”, dislocations, cracks, and the like are generated in a semiconductor crystal (GaN crystal or the like) grown on a Si substrate (underlying substrate) at a high temperature by a conventional technique.
[0003]
[Problems to be solved by the invention]
  Dislocations and cracks are the result of stress generated based on differences in thermal expansion coefficients and lattice constants between dissimilar materials, and when various semiconductor devices are manufactured on such crystal growth substrates, Causes deterioration of characteristics.
  In addition, when an independent substrate (crystal) is obtained by removing the base substrate made of, for example, silicon (Si) and leaving only the growth layer, a large area (1 cm) is obtained due to the above-described dislocations and cracks.²It is almost impossible to obtain the above).
[0004]
  Also, in the vicinity of 1000 ° C. to 1150 ° C., which is the crystal growth temperature of the target semiconductor substrate (semiconductor crystal A), silicon (Si) and gallium nitride (GaN) react with each other to produce polycrystalline GaN (“Reaction” in the figure). Part ") may be formed. For this reason, there is a problem that it is not easy to obtain a single-crystal GaN substrate through a high-temperature crystal growth process.
[0005]
  In addition, in order to obtain a single-crystal GaN substrate, it has been reported that the above-described silicon thin film, which hardly generates stress, is used alone as a crystal growth substrate. However, since these thin films are easily damaged, crystal growth starts. It is not easy to handle the thin film directly before, so it is difficult to mass-produce a large area semiconductor substrate with a high yield by these conventional methods.
[0006]
  The present invention has been made in order to solve the above-mentioned problems, and its purpose is to use a relatively inexpensive silicon (Si) as a base substrate, and to prevent the occurrence of cracks and polycrystalline ingots (reaction parts). It is to produce quality semiconductor crystals efficiently. Another object of the present invention is to manufacture a high-quality semiconductor device by using the above-described semiconductor crystal manufactured with high quality as a crystal growth substrate.
[0007]
[Means for Solving the Problem, Action, and Effect of the Invention]
  In order to solve the above problems, the following means are effective.
  That is, the first means of the present invention is a semiconductor substrate manufacturing process in which a semiconductor crystal A made of a group III nitride compound semiconductor is grown on a base substrate formed of silicon (Si). A thin film portion forming step for forming a crystal growth surface of the base substrate with a thin film portion made of silicon (Si) by providing a cavity immediately below the crystal growth surface, and a melting point or heat resistance higher than that of the semiconductor crystal A on the thin film portion. It is to provide a reaction preventing layer forming step of laminating a reaction preventing layer made of a high crystalline material B and a crystal growth step of growing the semiconductor crystal A on the reaction preventing layer.
[0008]
  However, the semiconductor substrate composed of the semiconductor crystal A may have a single layer structure or a multilayer structure (multilayer structure).
  In addition, “Group III nitride compound semiconductor” as used herein is generally a binary, ternary, or quaternary “Al”._xGa_yIn_(1-xy)N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) ”is included, and semiconductors having an arbitrary mixed crystal ratio represented by the general formula“ N ”are added, and p-type or n-type impurities are added. These semiconductors are also included in the category of “Group III nitride compound semiconductor” in this specification.
  Further, a part of the above group III elements (Al, Ga, In) is replaced with boron (B), thallium (Tl), or the like, or a part of nitrogen (N) is phosphorus (P), Semiconductors substituted with arsenic (As), antimony (Sb), bismuth (Bi), and the like are also included in the category of “Group III nitride compound semiconductor” in this specification.
[0009]
  Moreover, as said p-type impurity, magnesium (Mg), calcium (Ca), etc. can be added, for example.
  As the n-type impurity, for example, silicon (Si), sulfur (S), selenium (Se), tellurium (Te), germanium (Ge), or the like can be added.
  Further, two or more elements of these impurities may be added simultaneously, or both types (p-type and n-type) may be added simultaneously.
[0010]
  FIG. 1 is a schematic cross-sectional view in a semiconductor crystal manufacturing process for exemplifying the basic concept of the present invention. This reaction prevention layer is for preventing the reaction between Si and the gallium nitride semiconductor (semiconductor crystal A), and thus has a melting point higher than that of the gallium nitride semiconductor on the base substrate (Si substrate). Alternatively, even when a gallium nitride semiconductor (semiconductor crystal A) is grown at a high temperature for a long time by depositing a reaction prevention layer (crystalline material B) made of, for example, SiC or AlN having high heat resistance, The “reaction part” is not formed near the silicon interface.
[0011]
  Moreover, since a thin film is formed on the crystal growth surface side of silicon (Si substrate) by forming the cavity, stress acting on the reaction preventing layer is relieved, and these stresses form a crack in the reaction preventing layer. Therefore, it is difficult to cause cracks penetrating in the vertical direction in the reaction preventing layer. For this reason, since the base layer (Si substrate) and the gallium nitride based semiconductor (semiconductor crystal A) can be more reliably cut off by the reaction-preventing layer without cracks penetrating in the vertical direction, The occurrence of “reaction part” can be prevented more reliably.
[0012]
  In addition, since the “stress based on the difference in lattice constant between the base substrate and the semiconductor substrate” is relieved by the thin film portion or the cavity, when the semiconductor substrate (desired semiconductor crystal A) is grown, the growing semiconductor Unnecessary stress acting on the substrate is suppressed, and the generation density of dislocations and cracks is reduced.
  That is, the above stress relaxation action makes it difficult for dislocations to occur in the gallium nitride semiconductor (semiconductor crystal A), and the generation density of cracks can be significantly reduced.
[0013]
  Due to the above-described action and synergistic effect, it is possible or easy to obtain a high-quality semiconductor substrate (semiconductor crystal A) free from the above “reaction part” and cracks and having a sufficiently low dislocation density.
[0014]
  The second means is the same as the first means, wherein the semiconductor crystal A is composed of the composition formula “Al_xGa_yIn_(1-xy)N (0 ≦ x <1, 0 <y ≦ 1, x + y ≦ 1) ”is formed of a group III nitride compound semiconductor.
[0015]
  A third means is the same as the first or second means described above, wherein the crystalline material B forming the reaction preventing layer is made of silicon carbide (SiC), aluminum nitride (AlN), or spinel (MgAl₂O_Four).
[0016]
  The fourth means is that in the first or second means, the crystalline material B forming the reaction preventing layer is made of AlGaN, AlInN, or AlGaInN having an aluminum composition ratio of at least 0.30 or more. Is to configure.
  Furthermore, as the crystalline material B, it is desirable to select a stable material having a relatively strong bonding force and a high heat resistance (melting point).
[0017]
  The fifth means is that, in any one of the first to fourth means, the film thickness of the reaction preventing layer is 0.1 μm or more and 2 μm or less.
  If this thickness is too thin, the film thickness is uneven, or the crystalline material B for forming the reaction preventing layer is not a sufficiently stable substance, so that gallium (Ga) or gallium nitride ( GaN) and silicon (Si) cannot be completely blocked. Therefore, the effect of preventing the formation of “reaction part (polycrystalline GaN)” based on these reactions cannot be sufficiently obtained.
[0018]
  On the other hand, if the thickness of the reaction preventing layer is too large, the reaction preventing layer is likely to crack, and gallium (Ga) or gallium nitride (GaN) and silicon (Si) cannot be completely blocked. Therefore, the effect of preventing the formation of the “reaction part” based on these reactions cannot be sufficiently obtained.
  In addition, if the thickness of the reaction preventing layer is too thick, it is not desirable in terms of production cost and the like because an extra layer of the reaction preventing layer and a laminate material are required.
[0019]
  Further, the sixth means is the step of forming “Al” on the surface of the reaction preventing layer after the reaction preventing layer forming step of any one of the first to fifth means._xGa_1-xN (0 <x ≦ 1) ”is a step for forming a buffer layer C.
[0020]
  However, the buffer layer C is a semiconductor layer such as AlN or AlGaN grown at about 1100 ° C. In addition to the buffer layer C, the buffer layer C further has substantially the same composition (example) : A layer of AlN or AlGaN (hereinafter sometimes simply referred to as “buffer layer”) in the target semiconductor substrate (semiconductor crystal A) periodically or alternately with other layers, or The layers may be laminated so as to form a multilayer structure.
[0021]
  Crystallinity can be improved by the same action principle as before, such as the relaxation of the stress acting on the semiconductor substrate (growth layer) caused by the difference in lattice constant by laminating these buffer layers (or intermediate layers). It becomes.
  Such actions and effects are particularly remarkable when the crystalline material B constituting the reaction preventing layer is silicon carbide (SiC) or the like. That is, in this case, it is more desirable to form the buffer layer C on the reaction preventing layer.
[0022]
  The seventh means is that the film thickness of the buffer layer C is 0.01 μm or more and 1 μm or less in the sixth means. More desirably, the thickness is 0.02 μm or more and 0.5 μm or less.
[0023]
  If the film thickness is too thick, cracks are likely to occur, and the manufacturing time and materials are increased in cost, which is undesirable. If the film thickness is too thin, it is difficult to form the buffer layer substantially uniformly. For this reason, film formation unevenness (part where the film is not sufficiently formed) of the buffer layer is likely to occur, and crystallinity is likely to be uneven, which is not desirable.
[0024]
  Further, an eighth means is that in any one of the first to seventh means, the difference between the thermal expansion coefficients of the semiconductor crystal A and the base substrate is obtained by cooling or heating the semiconductor crystal A and the base substrate. It is to provide a separation step of separating the semiconductor crystal A and the base substrate by generating a stress based on this and breaking the side wall of the cavity using this stress.
[0025]
  For example, if the semiconductor substrate (semiconductor crystal A) is made sufficiently thick, internal stress or external stress tends to concentrate on the side wall of the cavity. As a result, these stresses in particular act as shear stresses on the side wall of the cavity, and when this stress becomes large, the thin film portion peels off.
  Therefore, if this stress is used, the base substrate and the semiconductor substrate can be easily separated. In addition, the larger the “cavity” is, the more easily stress (shear stress) is concentrated on the side wall of the cavity.
  That is, according to the ninth means, since the stress can be easily generated, the semiconductor crystal A and the base substrate can be easily separated.
[0026]
  When the base substrate and the semiconductor substrate are separated (separated), a part of the base substrate (such as a thin film portion or a broken debris on the side wall of the cavity) may remain on the semiconductor substrate side. In other words, the above separation step does not assume (necessary conditions) the complete separation of each material such that some of these materials are eliminated.
  Such removal of fracture debris and the like can be carried out using known means such as lapping and etching as necessary.
[0027]
  The ninth means is to stack the semiconductor crystal A by 50 μm or more in the crystal growth step of any one of the first to eighth means.
  As this thickness increases, the tensile stress on the semiconductor substrate (semiconductor crystal A) is relaxed, the dislocation density and crack generation density of the semiconductor substrate can be reduced, and at the same time the semiconductor substrate can be strengthened. It becomes easy to concentrate on the side wall.
[0028]
  The thickness of the thin film portion is desirably 20 μm or less. As this thickness is reduced, the tensile stress on the semiconductor substrate (semiconductor crystal A) is relaxed, and the dislocation density and crack generation density of the semiconductor substrate are reduced. However, if the thickness of the thin film portion is less than 0.02 μm, a problem occurs in the strength of the thin film portion, and it becomes difficult to maintain high productivity. Therefore, in order to ensure the quality and productivity of the crystal growth substrate to be manufactured, the thickness of the thin film portion is preferably 0.02 μm or more and 20 μm or less.
[0029]
  In comparison, it is desirable that the thickness of the semiconductor crystal for crystal growth is approximately equal to or greater than the thickness of the thin film portion. With such a setting, the stress on the desired semiconductor crystal is easily relaxed, and the generation of dislocations and cracks can be significantly suppressed as compared with the conventional case. This stress relaxation effect increases as the target semiconductor crystal becomes relatively thick. The stress relaxation effect depends on the thickness of the thin film portion and the like, but when the thickness of the thin film portion is 20 μm or less, it is substantially saturated at about 50 to 200 μm.
[0030]
  Further, the tenth means is a physical or chemical etching treatment of a cavity opened upward in a silicon crystal constituting the base substrate in the thin film portion forming step of any one of the first to ninth means. And forming a cavity and a thin film portion by a migration action in the vicinity of the surface of the base substrate based on a heat treatment at 1000 ° C. to 1350 ° C.
[0031]
  The eleventh means includes an ion implantation step of implanting ions into a silicon crystal providing the thin film portion, and a thin film portion of the base substrate in the thin film portion forming step of any one of the first to ninth means. Separates the ion-implanted portion from the recess forming step in which the upper part of the silicon crystal constituting the other part is opened by physical or chemical etching, the bonding step of bonding the thin film portion to the recess by heat treatment And a peeling step of peeling the thin film portion as the boundary surface.
[0032]
  The “thin film portion forming step” of the present invention can be carried out sufficiently or easily by at least the tenth or eleventh means. However, the “thin film portion forming step” of the present invention is not limited to these means, and may be performed by any other appropriate method. Even in such a case, the action / effect of the present invention can be obtained to a certain level or more.
[0033]
  The twelfth means is that the height of the cavity formed in the thin film portion forming step of any one of the first to eleventh means is 0.1 μm or more and 10 μm or less. More preferably, the height of the cavity is about 0.5 to 5 μm.
  If this value is too large, the formation of holes, grooves, or pillars that support the cavity becomes unstable in strength, or processing becomes gradually difficult or inefficient, which is not desirable. In addition, the processing time becomes long and productivity is not improved.
  On the other hand, if this value is too small, the thin film portion is likely to be bonded to the bottom surface of the cavity, and the cavity cannot be reliably formed.
[0034]
  Also,In the group II nitride compound semiconductor device, the semiconductor substrate manufactured by any one of the first to twelfth means is provided as a crystal growth substrate.May be.
  to thisTherefore, it is possible or easy to manufacture a group III nitride compound semiconductor element from a semiconductor having good crystallinity and low internal stress.
[0035]
  Also,A group III nitride compound semiconductor device is manufactured by crystal growth using the semiconductor substrate manufactured by any one of the first to twelfth means as a crystal growth substrate.You may do it.  According to this, it is possible or easy to manufacture a group III nitride compound semiconductor element from a semiconductor having good crystallinity and low internal stress.
  By the above means of the present invention, the above-mentioned problem can be effectively or rationally solved.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
  In carrying out the present invention, each manufacturing condition may be arbitrarily selected from the following. These manufacturing conditions may be arbitrarily combined.
  First, as a method of forming a group III nitride compound semiconductor layer, metal organic vapor phase epitaxy (MOCVD or MOVPE) is preferable. However, molecular beam vapor phase epitaxy (MBE), halide vapor phase epitaxy (Halide VPE), liquid phase epitaxy (LPE), etc. may be used, and each layer may be formed by different growth methods. .
[0037]
  The buffer layer is preferably formed in the crystal growth substrate or the base substrate for the purpose of correcting the lattice mismatch.
  In particular, when a buffer layer (the above intermediate layer) is stacked in a semiconductor substrate (semiconductor crystal A), these buffer layers include a group III nitride compound semiconductor Al formed at a low temperature._xGa_yIn_1-xyN (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), more preferably Al_xGa_1-xN (0 ≦ x ≦ 1) can be used. This buffer layer may be a single layer or multiple layers having different compositions. The buffer layer may be formed at a low temperature of 380 to 420 ° C., and conversely, may be formed by the MOCVD method in the range of 1000 to 1180 ° C. In addition, a buffer layer made of AlN can be formed by reactive sputtering using a DC magnetron sputtering apparatus using high-purity metallic aluminum and nitrogen gas as raw materials.
[0038]
  Similarly general formula Al_xGa_yIn_1-xyN (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1, composition ratio is arbitrary) buffer layers can be formed. Furthermore, vapor deposition, ion plating, laser ablation, and ECR can be used. The buffer layer by physical vapor deposition is preferably performed at 200 to 600 ° C. More preferably, it is 300-600 degreeC, More preferably, it is 350-450 degreeC. When these physical vapor deposition methods such as sputtering are used, the thickness of the buffer layer is preferably 100 to 3000 mm. More desirably, the thickness is 100 to 400 mm, and most desirably 100 to 300 mm.
[0039]
  For example, Al_xGa_1-xThere are methods such as alternately forming layers composed of N (0 ≦ x ≦ 1) and GaN layers, and alternately forming layers having the same composition at a forming temperature of, for example, 600 ° C. or lower and 1000 ° C. or higher. Of course, these may be combined, and the multilayer is composed of three or more group III nitride compound semiconductors Al._xGa_yIn_1-xyN (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) may be stacked. In general, the buffer layer is amorphous, and the intermediate layer is single crystal. A plurality of periods may be formed with the buffer layer and the intermediate layer as one period, and the repetition may be any period. The more repeats, the better the crystallinity.
[0040]
  In the group III nitride compound semiconductor of the buffer layer and the upper layer, a part of the composition of the group III element may be replaced by boron (B) and thallium (Tl), and a part of the composition of nitrogen (N) may be phosphorous. The present invention can be substantially applied even if it is replaced with (P), arsenic (As), antimony (Sb), or bismuth (Bi). Moreover, what doped such an extent that these elements cannot be displayed on a composition may be used. For example, Al is a group III nitride compound semiconductor that does not contain indium (In) or arsenic (As) in the composition._xGa_1-xDoping N (0 ≦ x ≦ 1) with aluminum (Al), indium (In) with a larger atomic radius than gallium (Ga), or arsenic (As) with a larger atomic radius than nitrogen (N) The crystal expansion may be improved by compensating the expansion strain of the crystal due to the loss of nitrogen atoms with the compressive strain.
[0041]
  In this case, since the acceptor impurity easily enters the position of the group III atom, a p-type crystal can be obtained as-grown. By improving the crystallinity in this manner, the threading dislocation can be further reduced to about 100 to 1/1000 in combination with the present invention. In the case of a base layer in which the buffer layer and the group III nitride compound semiconductor layer are formed in two cycles or more, if each group III nitride compound semiconductor layer is doped with an element having an atomic radius larger than the main constituent element, good. In the case of constituting a light emitting element, it is desirable to use a binary or ternary group III-nitride compound semiconductor.
[0042]
  When an n-type group III nitride compound semiconductor layer is formed, a group IV element such as Si, Ge, Se, Te, C, or a group VI element can be added as an n-type impurity. Further, as a p-type impurity, a group II element or group IV element such as Zn, Mg, Be, Ca, Sr, or Ba can be added. A plurality of these or n-type impurities and p-type impurities may be doped in the same layer.
[0043]
  It is also optional to reduce the dislocations in the group III nitride compound semiconductor layer using lateral epitaxial growth. At this time, any method using a mask or filling a step by etching can be used.
[0044]
  Etching masks include polycrystalline semiconductors such as polycrystalline silicon and polycrystalline nitride semiconductor, silicon oxide (SiO_x), Silicon nitride (SiN_x), Titanium oxide (TiO_X), Zirconium oxide (ZrO_X) And other oxides, nitrides, refractory metals such as titanium (Ti) and tungsten (W), and multilayer films of these. These film forming methods are arbitrary in addition to vapor phase growth methods such as vapor deposition, sputtering, and CVD.
[0045]
  In etching, reactive ion beam etching (RIBE) is desirable, but any etching method can be used. As an example of not forming a step having a side surface perpendicular to the substrate surface, for example, a step having no bottom at the bottom of the step and having a V-shaped cross section may be formed by anisotropic etching.
[0046]
  Semiconductor elements such as FETs and light emitting elements can be formed on the group III nitride compound semiconductor. In the case of a light emitting device, the light emitting layer may be a multi-quantum well structure (MQW), a single quantum well structure (SQW), a homo structure, a hetero structure, or a double hetero structure, but a pin junction or a pn junction, etc. You may form by.
[0047]
  Hereinafter, the present invention will be described based on specific examples. However, the present invention is not limited to the following examples.
(First embodiment)
  Hereinafter, the outline of the manufacturing procedure of the semiconductor crystal (crystal growth substrate) in the embodiment of the present invention will be exemplified.
[0048]
[1] Thin film part formation process
  In this manufacturing process, the silicon crystal constituting the base substrate is provided with a recess forming step in which a cavity opened upward is formed by a physical or chemical etching process, and then the base substrate based on a heat treatment at 1000 ° C. to 1200 ° C. A cavity and a thin film portion are formed by a migration action near the surface.
[0049]
(A) Concave formation on silicon substrate
  Using a plasma CVD apparatus on a Si (111) substrate, SiO₂A film of about 1 μm is formed and SiO₂A part of the film and the Si substrate are patterned and etched by photolithography and RIE, and a number of holes having a diameter of about 0.8 μm and a depth of about 3 μm are formed on the surface of the Si (111) substrate at a period of 1.2 μm (interval). Make it.
  Then, the above SiO₂The membrane is removed with B-HF.
[0050]
(B) Migration
  Next, the Si substrate on which the recesses are formed is made H₂By performing heat treatment at 1100 ° C. in an atmosphere, Si atoms migrate on the substrate surface, and a thin film portion (membrane) having a thickness of about 1 μm is formed above the recess. That is, by closing the upper portion of the concave portion with the thin film portion D1, a large number of cavities as illustrated in FIG. 1 are formed. Thereafter, the obtained substrate is wet oxidized at 1150 ° C. to make the surface SiO 2.₂The film thickness of the remaining Si thin film portion is changed to about 0.1 μm.
[0051]
(C) Cleaning
  Then, the above SiO₂The membrane is removed with buffered hydrofluoric acid.
  Through the above steps (a) to (c), a Si substrate D having a cavity and a thin film portion D1 as illustrated in FIG. 1 was manufactured.
[0052]
[2] Reaction prevention layer formation process
  This reaction preventing layer forming step is a manufacturing step of laminating a reaction preventing layer on the base substrate (Si substrate D) having the thin film portion D1.
  In this reaction prevention layer forming step, first, reaction prevention comprising aluminum nitride (AlN) at about 1100 ° C. is performed on the crystal growth surface (thin film portion D1) of the Si (111) substrate by vapor phase growth (MOVPE). Layer B is formed to a thickness of about 1 μm.
[0053]
[3] Crystal growth process
  Thereafter, in this crystal growth step, the growth step until the semiconductor crystal A (GaN) grows to a thick film of about 200 μm on the reaction prevention layer B is performed according to the metal organic compound vapor phase growth method (MOVPE method). carry out.
  In this crystal growth process, ammonia (NH_Three) Gas, carrier gas (H₂, N₂), Trimethylgallium (Ga (CH_Three)_Three) Gas (hereinafter referred to as “TMG”), and trimethylaluminum (Al (CH_Three)_Three) Gas (hereinafter referred to as “TMA”) is used.
[0054]
  On the reaction prevention layer B, a GaN layer (semiconductor crystal A) was grown by about 200 μm according to the MOVPE method. The crystal growth rate of the GaN layer in this MOVPE method is about 30 μm / Hr.
[0055]
[4] Separation process
(A) After the above crystal growth step, ammonia (NH_ThreeThe wafer having the base substrate (Si substrate) is cooled to approximately room temperature while the gas is allowed to flow into the reaction chamber of the crystal growth apparatus. The cooling rate at this time may be about “−50 ° C./min to −5 ° C./min”.
[0056]
(B) Then, when these were taken out from the reaction chamber of the crystal growth apparatus, the GaN crystal (semiconductor crystal A) exfoliated from the base substrate (Si substrate) was obtained. However, this crystal is such that the thin film portion D1 and the broken debris on the side wall of the cavity remain on the back surface of the GaN layer (semiconductor substrate).
[0057]
[5] Debris removal process
  After the separation step, the thin film portion D1 made of Si remaining on the back surface of the GaN crystal and the broken debris on the side wall of the cavity are removed by lapping.
  However, this debris removal step may be performed by an etching process using a mixed solution of nitric acid and hydrofluoric acid. Further, the layers up to the reaction preventing layer B may be removed.
[0058]
  By the above manufacturing method, it is possible to obtain a high-quality GaN crystal (GaN layer) having a film thickness of about 200 μm, that is, a desired semiconductor substrate (semiconductor crystal A) independent from the base substrate.
  That is, by the above semiconductor crystal manufacturing method, it is possible to obtain a GaN polycrystal (reaction part) and a crack-free gallium nitride (GaN) single crystal, which are superior in crystallinity compared to the prior art.
[0059]
  Therefore, if such a high-quality single crystal is used as a part of a semiconductor light-emitting element such as a crystal growth substrate, a high-quality semiconductor light-emitting element with high light emission efficiency or a reduced driving voltage than before. It is possible or easy to manufacture semiconductor products such as semiconductor light receiving elements.
  Further, by using such a high-quality single crystal, it is possible or easy to manufacture not only an optical element but also a so-called semiconductor electronic element such as a semiconductor power element having a high withstand voltage and a semiconductor high-frequency element that operates up to a high frequency. be able to.
[0060]
  A buffer layer forming step for crystal growth at a high temperature of about 1000 ° C. to 1180 ° C. may be provided between the reaction preventing layer forming step and the crystal growth step for the purpose of correcting lattice constant mismatch.
[0061]
  In the above embodiment, as illustrated in FIG. 1, the thin film portion of the base substrate is formed by providing a large number of cavities in the vicinity of the crystal growth surface of the base substrate. You may form from. Therefore, for example, the hollow of the present invention may be formed by forming a single tubular tunnel-type cavity in an elongated and spiral shape. FIG. 1 described above can also be interpreted as a cross-sectional view of a base substrate having such a cavity.
  That is, the form, size, spacing, arrangement, orientation, etc. of the cavity are generally arbitrary for the formation form of the cavity for the purpose of forming the thin film portion of the base substrate.
[0062]
(Second embodiment)
  In the second embodiment, the thin film portion forming step of the first embodiment is replaced with the following “thin film portion forming step”, and the other steps do not need to be changed particularly.
  Hereinafter, in the present embodiment, only the “thin film portion forming step” which is different from the first embodiment will be described.
[0063]
[1] Thin film part formation process
  This manufacturing process consists of an ion implantation process for implanting ions into a silicon crystal that provides a thin film portion, and a physical or chemical etching process for the open cavity in the silicon crystal that constitutes the portion other than the thin film portion of the underlying substrate. The cavity and the thin film portion are formed by a concave portion forming step provided by the above, a bonding step in which the thin film portion is bonded to the concave portion by heat treatment, and a peeling step in which the thin film portion is peeled off using the ion implantation portion as the separation boundary surface.
[0064]
(A) Ion implantation process
  The silicon crystal (Si (111) substrate) that provides the thin film portion D1 is irradiated with hydrogen ions with an incident energy of 4 keV and a dose of 2 × 10.¹⁶~ 1x10¹⁷〔cm^-2] To inject.
  FIG. 2 is a graph illustrating the number of ions implanted (density) with respect to the depth at which ions are implanted in the second embodiment. As can be seen from this figure, an ion implantation layer having a locally high ion density is formed in the vicinity of the ion implantation surface of the silicon crystal.
[0065]
(B) Concave forming step
  On the other hand, using another plasma (CVD) apparatus on another Si (111) substrate (corresponding to symbol D in FIG. 1), SiO₂A film of about 1 μm is formed and SiO₂A part of the film and the Si substrate are patterned and etched by photolithography and RIE, and a large number of pillars having a diameter of about 0.6 μm and a height of about 3 μm are formed on the surface of the Si substrate at a period (interval) of about 2 μm.
[0066]
(C) Joining process
  Next, the ion-implanted surface of the silicon crystal that provides the thin film portion D1 is bonded perpendicularly to many columns on the surface of the Si substrate.
[0067]
(D) Peeling process
  By performing heat treatment at 500 ° C., the silicon crystal providing the thin film portion D1 is separated at the ion implantation portion, and a cavity closed by the thin film portion D1 is formed above.
[0068]
  Through the above steps (a) to (d), a Si substrate D having a cavity and a thin film portion D1 as illustrated in FIG. 1 was manufactured.
[0069]
  Hereinafter, examples of the deformable range of the second embodiment will be described.
  For example, hydrogen ion (H⁺) Instead of (He⁺) Can be used to obtain substantially the same operations and effects as in the second embodiment.
[0070]
  The dose amount of hydrogen ions depends on the material of the base substrate and the like, but is approximately 1 × 10.¹⁵〔/cm²] ~ 1 × 10²⁰〔/cm²In this condition, substantially the same actions and effects as described above can be obtained. More preferably, the dose amount of hydrogen ions is 3 × 10.¹⁵~ 1x10¹⁷〔/cm²The degree is good, more preferably 8 × 10¹⁵~ 2x10¹⁶〔/cm²] The degree is good.
[0071]
  If this value is too small, it is difficult to reliably separate the thin film portion D1 from the silicon crystal that provides the thin film portion D1. If this value is too large, damage to the thin film portion D1 will increase, and it will be difficult to separate the thin film portion D1 from the base substrate into a cleanly connected shape with a substantially uniform thickness.
[0072]
  It is also possible to control the thickness of the thin film portion separated from the base substrate by changing the incident energy. FIG. 3 illustrates the measurement result of the depth at which ions are implanted relative to the ion implantation energy (depth h of maximum density). For example, the depth at which ions are implanted (maximum density depth h) is substantially proportional to the ion implantation energy, and thus the thickness of the thin film portion can be adjusted by adjusting the incident energy (acceleration voltage). Can be controlled appropriately.
[0073]
  In addition, by performing heat treatment after ion implantation, a partial fracture portion (void) in the ion implantation layer is formed in advance, and at the same time, the crystallinity of the ion implantation portion of the base substrate damaged by ion irradiation can be recovered. it can.
  Further, the crystallinity of the semiconductor grown thereon can be improved by the heat treatment on the thin film portion D1 during the cavity formation.
[0074]
  Further, the thickness of the thin film portion D1 is desirably 20 μm or less. The thinner the thickness is, the more the tensile stress on the target semiconductor crystal is relaxed and the density of dislocations and cracks is reduced. Therefore, more desirably, the thickness of the thin film portion is 2 μm or less, and more desirably 200 nm or less. In order to realize these values, the ion implantation energy (acceleration voltage) may be adjusted so that the peak of the number of implanted ions has such a depth according to FIG.
  However, if the ion implantation layer becomes thick, it becomes difficult to control the thickness of the thin film portion, so attention should be paid to the thickness of the ion implantation layer.
[0075]
  Although the thickness of the ion implantation layer cannot be strictly defined, for example, the half width with respect to the peak value of the number of implanted ions in FIG. The thickness of the thin film portion becomes easier to control as the thickness of the ion implantation layer is reduced.
  Therefore, means for maintaining the ion implantation energy (acceleration voltage) at a constant value as much as possible is effective in accurately controlling the thickness of the thin film portion.
[0076]
  In each of the first and subsequent examples, the crystalline material B for forming the reaction preventing layer is Al._xGa_1-xN (0 <x <1) or the like may be used. Even with these crystalline materials B, substantially the same operations and effects as in the above-described embodiment can be obtained. More generally, as the crystalline material B for forming the reaction preventing layer, silicon carbide (SiC), aluminum nitride (AlN), spinel (MgAl₂O_FourAlternatively, AlGaN, AlInN, or AlGaInN having an aluminum composition ratio of at least 0.30 or more can be used.
[0077]
  Further, the semiconductor crystal A forming the target semiconductor substrate is not limited to gallium nitride (GaN), and the above-mentioned general “Group III nitride compound semiconductor” can be arbitrarily selected.
  The target semiconductor substrate (semiconductor crystal A) may have a multilayer structure.
[0078]
  That is, the present invention has no particular limitation on the type (material) of the base substrate or the target semiconductor crystal, and includes any combination of the materials of the base substrate and the semiconductor crystal as described above. It can be applied to epitaxial growth.
[0079]
  In the above embodiment, the metal organic compound vapor phase growth method (MOVPE method) is used. However, the crystal growth of the present invention can also be performed by a halide vapor phase growth method (HVPE method) or the like.
[0080]
  Further, in the above embodiment, the method of using the semiconductor crystal A as the crystal growth substrate of the semiconductor element after separating the base substrate and removing the debris was exemplified. It may be performed after the semiconductor layers of the semiconductor element itself are stacked, or may be used as a semiconductor element without performing a separation step or the like.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view in a semiconductor crystal manufacturing process for exemplifying the basic concept of the present invention.
FIG. 2 is a graph illustrating the number (density) of implanted ions with respect to the depth at which ions are implanted.
FIG. 3 is a graph illustrating an ion implantation depth (maximum density depth h) with respect to ion implantation energy;
FIG. 4 is a schematic cross-sectional view illustrating a conventional semiconductor crystal grown on a Si substrate (underlying substrate).
[Explanation of symbols]
    A ... Semiconductor crystal (target semiconductor substrate)
    B ... Reaction prevention layer (crystalline material)
    D ... Silicon substrate (underlying substrate)
    D1 ... Thin film portion of silicon substrate D

Claims (12)

A method of obtaining a semiconductor substrate by growing a semiconductor crystal A made of a group III nitride compound semiconductor on a base substrate formed of silicon (Si),
A thin film portion forming step of forming a cavity directly below the crystal growth surface of the base substrate to form the crystal growth surface of the base substrate with a thin film portion made of silicon (Si);
A reaction preventing layer forming step of laminating a reaction preventing layer made of a crystalline material B having a melting point or heat resistance higher than that of the semiconductor crystal A on the thin film portion;
And a crystal growth step for growing the semiconductor crystal A on the reaction preventing layer. The semiconductor crystal A is
3. A group III nitride compound semiconductor satisfying the composition formula “Al _x Ga _y In _(1-xy) N (0 ≦ x <1, 0 <y ≦ 1, x + y ≦ 1)” Item 12. A method for manufacturing a semiconductor substrate according to Item 1. The crystalline material B forming the reaction preventing layer is:
3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor substrate is made of silicon carbide (SiC), aluminum nitride (AlN), or spinel (MgAl ₂ O ₄ ). The crystalline material B forming the reaction preventing layer is:
3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor composition is made of AlGaN, AlInN, or AlGaInN having an aluminum composition ratio of at least 0.30 or more. The film thickness of the reaction preventing layer
5. The method of manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor substrate is formed to have a thickness of 0.1 μm or more and 2 μm or less. After the reaction preventing layer forming step,
6. The method according to claim 1, further comprising: forming a buffer layer C made of “Al _x Ga _1-x N (0 <x ≦ 1)” on the surface of the reaction preventing layer. The manufacturing method of the semiconductor substrate as described in a term. The film thickness of the buffer layer C is
The method for manufacturing a semiconductor substrate according to claim 6, wherein the semiconductor substrate is formed to have a thickness of 0.01 μm or more and 1 μm or less. By cooling or heating the semiconductor crystal A and the base substrate, a stress based on a difference in thermal expansion coefficient between the semiconductor crystal A and the base substrate is generated, and the side wall of the cavity is broken using this stress. 8. The method of manufacturing a semiconductor substrate according to claim 1, further comprising a separation step of separating the semiconductor crystal A and the base substrate. In the crystal growth step,
The method for manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor crystal A is stacked by 50 μm or more. The thin film portion forming step includes
A step of forming a recess in the silicon crystal constituting the base substrate by providing the cavity opened upward by physical or chemical etching;
10. The semiconductor according to claim 1, wherein the cavity and the thin film portion are formed by a migration action near the surface of the base substrate based on a heat treatment at 1000 ° C. to 1350 ° C. 10. A method for manufacturing a substrate. The thin film portion forming step includes
An ion implantation step of implanting ions into the silicon crystal providing the thin film portion;
A recess forming step of providing the cavity opened upward in a silicon crystal constituting a portion other than the thin film portion of the base substrate by a physical or chemical etching process,
A bonding step of bonding the thin film portion to the recess by heat treatment;
10. The method of manufacturing a semiconductor substrate according to claim 1, further comprising a peeling step of peeling the thin film portion using the ion implanted portion as a separation boundary surface. 11. The height of the cavity formed in the thin film portion forming step
12. The method of manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor substrate has a thickness of 0.1 μm or more and 10 μm or less.

Images