KR102556712B1 - Method of manufacturing AlxGa1-xN (0.5≤x≤1) piezoelectric thin films with high purity and their apparatus using the thin film - Google Patents

Abstract

The present disclosure includes forming a stress control layer of a group III nitride on a silicon film substrate by chemical vapor deposition (CVD); And, forming an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the stress control layer by physical vapor deposition at a temperature of 0.3 Tm (Tm; melting point of the piezoelectric thin film material) or higher. A method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film element comprising the piezoelectric thin film It's about how.

Description

Method of manufacturing AlxGa1-xN (0.5≤x≤1) piezoelectric thin films with high purity and their apparatus using the thin film }

The present disclosure generally relates to a high-purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, a method for manufacturing a device using the thin film, and a device using the thin film, particularly with excellent crystallinity. ) and polarity, a high purity Al _x Ga _1-x N (0.5≤x<1) piezoelectric thin film, more preferably a high purity AlN piezoelectric thin film and a method for manufacturing a device using the thin film, and this It relates to a device using a thin film. High-purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin films are used for high-quality high-frequency filters, energy harvesters, ultrasonic transducers, bio and IoT applications It is used for various resonator applications including sensors for bio & IoT. Recently, these thin films have been used as acoustic resonators (e.g., surface acoustic wave resonator, BAW resonator) in filters used in portable electronic devices such as smart phones. It is attracting attention in high-sensitivity sensors for role and bio and IoT applications. Although the use of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film has been exemplified above, the use of this thin film is not limited thereto.

Here, background art related to the present disclosure is provided, and they do not necessarily mean prior art (This section provides background information related to the present disclosure which is not necessarily prior art).

According to the document Nano Energy 51 (2018) 146-161, “AlN piezoelectric thin films for energy harvesting and acoustic devices”, AlN piezoelectric thin films have high longitudinal acoustic wave velocity (approximately 11,000 m/s), high High thermal stability (melting point; 2100℃, piezoelectric property retention temperature; 1150℃), wide energy bandgap (6.2eV), and excellent piezoelectric and dielectric properties With unique physical properties, high-quality high-frequency filters, energy harvesters, ultrasonic transducers, sensors for bio & IoT, etc. It is currently explosively used as a variety of resonator application products including resonators, and at the same time, it is the most popular material in the field where ultra-miniature and high-efficiency products through enhanced functionality and versatility of high quality are absolutely needed in the future. In general, methods for thin film synthesis of AlN piezoelectric thin film materials include PVD (physical vapor deposition; typically sputtering), which is poly-crystal deposition at a temperature of around 400 ° C, and single crystal at a temperature of around 1000 ° C Growth (epitaxial single crystal growth) is known as CVD (chemical vapor deposition; typically MOCVD, HVPE). Currently, due to the film formation (deposition, growth) process of AlN piezoelectric thin film and device design considering this film formation process, a single layer _or After forming a multi-layer thin film (typically Mo, Ti, Pt, W, Al), design and manufacture a device through polycrystalline AlN deposition at a temperature around 400 ° C, or manufacture a designed device by adding a subsequent heat treatment process if necessary. is currently doing. However, as described later in FIG. 15, due to physical process limitations, the AlN piezoelectric thin film deposited by the optimized process on the insulating layer and / or metal thin film at a temperature of around 400 ° C. has a textured poly-crystal microstructure ( Compared to AlN piezoelectric thin films with high-purity epitaxial single crystal microstructure deposited at high temperatures around 1000℃ as a microstructure), physical properties including piezoelectric properties are not superior, and various AlN piezoelectric thin film elements designed and manufactured for this reason They have limitations in terms of performance and application extension. In other words, in the prior art, the crystal quality (crystallinity and polarity) of an AlN piezoelectric thin film and a device using the same can be deposited on a single or multi-layered thin film of an insulating layer and/or a metal layer formed before AlN film formation, and the deposition film formation temperature and surface material state However, it has been difficult to construct an AlN piezoelectric thin film with a high-purity single crystal material. Several methods have been proposed to overcome these limitations and obtain high-purity single-crystal AlN piezoelectric thin films and fabricate devices. For example, single crystals having the same/similar crystal structure as AlN materials at high temperatures around 1000 ° C with MOCVD devices After directly growing a film on a film formation substrate (epitaxial synthesis substrate, Sapphire, SiC) or directly depositing a film on a silicon (Si) single crystal film formation substrate at the highest possible temperature with a sputtering device, wafer bonding ( Methods of completing a device through an AlN piezoelectric thin film transfer technology to a device substrate through wafer-bonding and lift off have been proposed.

1 is a view showing elements using a piezoelectric thin film proposed in US Patent Publication No. US2015-0033520, FIG. 1 (a) shows an example of FBAR (20; Film Bulk Acoustic Resonator), and FIG. 1 (b) SMR (20'; Solidly Mounted Resonator) is presented. FBAR and SMR belong to BAW resonators. The FBAR 20 includes a pair of electrodes 22 and 24, a piezoelectric thin film 26 disposed between the pair of electrodes 22 and 24, and an element substrate 30. The pair of electrodes 22 and 24 and the piezoelectric thin film 26 are suspended over the cavity 28 formed in the device substrate 30 . The SMR 20' includes a pair of electrodes 22' and 24', a piezoelectric thin film 26' disposed between the pair of electrodes 22' and 24', and an element substrate 30'. Unlike the FBAR 20, a multi-layered Bragg reflector 27' is provided instead of the reflector of the cavity 28.

2 to 4 are diagrams illustrating an AlN piezoelectric thin film and a method for manufacturing a device using the AlN piezoelectric thin film proposed in US Patent Publication No. US2015-0033520. First, a single crystal AlN piezoelectric thin film is grown on a sapphire (Al ₂ O ₃ ) film substrate. (Fig. 2(a)). At this time, unlike the conventional SiO ₂ film and Mo electrode formed on the Si film substrate and then forming the AlN piezoelectric thin film through PVD (Phisical Vapor Deposition) sputtering, HVPE or CVD (Chemical Vapor Deposition) MOVCD is used. to form a high-quality, high-purity single-crystal AlN piezoelectric thin film. Next, a contact electrode is formed (FIG. 2(b). In the case of manufacturing SMR, a Bragg reflector (SiO ₂ /W) reflector is first formed on a separately prepared semiconductor device substrate (FIG. 3(c)). Next The AlN piezoelectric thin film structure 40 and the Bragg reflector reflector structure 42 are wafer bonded (FIG. 3(d)). Next, a sapphire film is formed from the bonded structure 44 through Laser Lift Off (LLO). The substrate is separated (FIG. 3(e)). Finally, an upper electrode is formed on the structure 46 from which the sapphire film formation substrate is separated (FIG. 3(f)). In the case of manufacturing an FBAR, first, a separately prepared semiconductor device An air cavity is formed on the substrate (FIG. 4(c)). Next, the AlN piezoelectric thin film structure 40 and the cavity structure 52 are bonded (FIG. 4(d)). Next, the laser from the bonded structure 54 The sapphire deposition substrate is separated through lift-off (LLO) (FIG. 4(e)). Finally, an upper electrode is formed on the structure 56 from which the sapphire deposition substrate is separated (FIG. 4(f)).

Compared to polycrystalline AlN piezoelectric thin films conventionally deposited through a sputtering device on silicon oxide (SiO ₂ ) and/or metal (electrode) materials on top of Si film substrates, MOCVD-grown piezoelectric films on sapphire film substrates The single crystal (crytalline) AlN piezoelectric thin film can greatly improve the performance and quality of resonators. However, after directly growing an AlN piezoelectric thin film having an optical property of 6.2eV energy bandgap, that is, a short wavelength of 200nm when converted to a wavelength, on a sapphire film substrate, and then using the currently commercially available ArF (193nm) & KrF (248nm), etc. Separation using an excimer laser light energy source is not an easy task. This is because, in order to separate the two material layers using a laser light energy source, a thermo-chemical decomposition reaction process through which the laser light energy source is strongly absorbed and converted into thermal energy at the interface is performed. However, a process of separating a specific film formed with a function from a film formation substrate through this mechanism is referred to as “laser lift off (LLO)”. The starting point of the laser lift-off (LLO) mechanism is that a sacrificial layer composed of an appropriate material capable of absorbing a laser light energy source and converting it into a heat energy source must exist between an optically transparent film formation substrate and a specific film film. . An appropriate condition for the material of this sacrificial layer is an optically transparent semiconductor having an energy bandgap of a sufficiently larger wavelength than the wavelength of the laser irradiated through the rear surface of the optically transparent sapphire film deposition substrate, and at the same time, a light energy source. A material region having an amorphous, polycrystalline, or multi-layer microstructure capable of absorbing as much as possible is absolutely required. In the method, these points were overlooked and described.

5 is a view showing an example of a method of manufacturing an AlN piezoelectric thin film proposed in US Patent Publication No. US2006-0145785, a sapphire film formation substrate 200, a buffer layer 210 grown on the sapphire film formation substrate 200; example: GaN), an AlN piezoelectric thin film 220 formed on the buffer layer 210, and a bonding metal 230 (eg, Au) formed on the AlN piezoelectric thin film 220 are presented.

Gallium nitride (GaN) constituting the buffer layer 210 is a material having an energy band gap of 3.4 eV (at the time of wavelength conversion, 364 nm) and at the same time has an amorphous microstucture grown at a low temperature, compared to AlN. The GaN buffer layer 210 can sufficiently serve as a sacrificial layer and has the advantage of facilitating separation of the optically transparent sapphire film deposition substrate 200 and the AlN piezoelectric thin film 220, but the GaN buffer layer ( 210) and the AlN piezoelectric thin film 220, there is a significant difference in physical properties of lattice constant and thermal expansion coefficient, so a high-purity single crystal grown by MOCVD over a certain critical thickness (approximately 100 nm) that can be used as a functional piezoelectric thin film such as a resonator Securing the AlN piezoelectric thin film 220 is not easy with currently known processes and techniques.

15 is a view showing an example of a method for manufacturing an AlN piezoelectric thin film presented in Solid-State Electronics 54 (2010) 1041-1046, in which, as shown in FIG. 15 (a), (001) silicon film is formed. Forming an AlN piezoelectric thin film 62 directly sputter-deposited on the substrate 61, forming a lower electrode 63 on the AlN piezoelectric thin film 62 as shown in FIG. 15(b), and As shown in 15(c), forming an acoustic mirror 64 formed on the lower electrode 63, as shown in FIG. 15(d), a wafer over the acoustic wave mirror 64 Forming a bonded carrier wafer (65), as shown in FIG. 15 (e), (100) removing the silicon film substrate 61 by wet etching, and FIG. 15 (f) As shown in , finally, a step of forming an upper electrode 66 on the AlN piezoelectric thin film 62 from which the (100) silicon film substrate 61 is removed, through which an SMR BAW structural resonator is manufactured. According to this method, a structure in which SiO ₂ and/or metal (electrode) is formed on a silicon film substrate and then an AlN piezoelectric thin film is formed (eg, literature (“Optimization of sputter deposition Process for piezoelectric AlN ultra-thin Films”, Semester Project, Advanced NEMS group, Autumn Semester 2017, Roman Welz, January 23, 2018, SECTION MICROTECHNIQUE), a separate additional process (CMP; chemical-mechanical polishing) for quality improvement has unnecessary advantages and uniform thickness. It is possible to obtain a piezoelectric thin film and at the same time has the advantage of excluding the native oxide formed on the surface of the electrode (metal), which has a great influence on the quality of the piezoelectric thin film. It has been pointed out that it can.

In addition, there is a method of growing a high-purity AlN piezoelectric thin film on a SiC film-forming substrate, but the SiC film-forming substrate is expensive, and after growing a high-purity AlN thin film on a SiC film-forming substrate, SiC film formation through chemical wet etching in the already known AlN piezoelectric thin film resonator manufacturing process Because the substrate is removed, reuse is not possible, so it is not considered because it cannot fundamentally solve the high cost problem of AlN piezoelectric thin film resonators.

In general, in order to form (deposit, grow) a high-purity AlN piezoelectric thin film having a melting point (Tm) of 2200 ° C, “Thornton's Theory for the Adatom Surface Mobility” Accordingly, during film formation, the surface temperature of the film formation substrate must be carried out at least 0.3Tm (660°C in the case of AlN) or higher so that material diffusion of adsorbed atoms starts on the surface of the film formation substrate and the close packing ratio of the film formation material layer is reduced to single crystal. By reaching the single crystal bulk level, it is possible to form c-oriented textured polycrystals arranged in a vertical direction on the surface of the film formation substrate, and by further increasing the surface temperature of the film formation substrate to 0.5 Tm (in the case of AlN). 1100° C.) or higher, it is possible to obtain a high purity thin film by forming a pseudomorphic mosaic structured single crystal. More preferably, when the surface temperature of the film formation substrate is raised, the surface formed through the acceleration of plasma particles (protons, electrons, neutrons) rather than heating with a heater on the back plane of the film formation substrate. It is advantageous to obtain a high-purity thin film by directly applying a bombardment to increase the surface temperature. In addition, in order to form (deposit, grow) a high-purity AlN piezoelectric thin film having a hexagonal (HCP) crystal structure, Group III Nitrides (AlN, GaN, AlGaN, AlInN, InGaN) and Group 2 oxides having the same crystal structure (Group II Oxidex; ZnO, MgO, MgZnO), or sapphire and silicon carbide (SiC) material surfaces having a similar crystal structure are preferred, and at the same time, metals with large surface roughness ( Electrodes; Ceramic (SiO ₂ , SiN _x ) or semiconductor (Si) materials having relatively small surface roughness rather than Mo, W, Ti, Al) materials are advantageous in securing a much higher purity AlN piezoelectric thin film in terms of surface mobility of adsorbed atoms. do. In addition to the above conditions, favorable conditions for film formation (deposition, growth) of high-purity AlN piezoelectric thin films include minimization of the inflow of oxygen (O ₂ ) from the surroundings, including the film-formation substrate, and perfect removal of hydrogen, hydrogen compounds, and other contaminants on the surface of the film-formation substrate. Removal is the best condition.

In Physics Letter A 375 (2011) 1000-1004, “Single-crystalline AlN growth on sapphire using physical vapor deposition”, Andres M. Cardenas-Valencia, Shinzo Onishi, Benjamin Rossie, a magnetron sputtering gun (a magnetron sputtering gun) was introduced, and the temperature of the sapphire film formation substrate was set to 860° C., and a film was directly deposited to secure a 4 μm-thick single-crystal AlN piezoelectric thin film. Usually, when evaluating the quality of an AlN piezoelectric thin film, crystallinity and polarity are evaluated at the same time, and the crystalline quality measurement evaluation index is the full width at half maximum (FWHM) in the non-destructive X-ray rocking curve. Compared to the half-width value of 1.2-2.5° of the current commercial structure (Si film formation substrate / SiO ₂ /metal electrode / AlN), in the case of the cited document, the half-width is 0.32°, indicating that the crystalline quality is significantly improved. show In other words, according to the theory of surface mobility of adsorbed atoms established by Thornton, prior to the importance of the film formation (deposition, growth) method (CVD or PVD), the film formation substrate temperature and material crystal structure during specific thin film formation (deposition, growth) , and surface conditions were found to be significant influencing factors. However, the polar quality cannot be determined by the half-width value of the X-ray rocking curve. For reference, polar quality was not evaluated in the cited literature, but polar quality evaluation can usually be confirmed through surface wet etching. The main factor affecting polar quality is film formation ( deposition, growth) methods, film formation substrate materials, and surface conditions are known.

This will be described at the end of 'Specific Contents for Implementation of the Invention'.

This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features).

According to one aspect of the present disclosure (According to one aspect of the present disclosure), in a method for manufacturing a high-purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, a sacrificial layer is formed on a sapphire film deposition substrate. forming; And, growing a single-crystal Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the sacrificial layer; including, growing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film Forming a first semiconductor layer of Al _y Ga _1-y N (0.5≤y≤1) prior to the step; high purity Al _x Ga _1-x N (0.5≤x≤1) characterized in that it further comprises ) A method for manufacturing a piezoelectric thin film is provided.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in a structure having an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film; Al _x Ga _1-x N (0.5≤x≤1) A first electrode provided on one side of the piezoelectric thin film; Al _x Ga _1-x N (0.5≤x≤1) A second electrode and a reflector provided on the opposite side of the first electrode based on the piezoelectric thin film; Al _x Ga _1-x N including the first electrode (0.5≤x≤1) Al _x Ga _1-x N (0.5≤x≤1), characterized in that the surface of the piezoelectric thin film is a metallic polarity (Al-polarity or Al-polarity & Ga-polarity mixed) surface ) A structure having a piezoelectric thin film is provided.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, a sacrificial layer is formed on a sapphire film deposition substrate. Forming step; as, the sacrificial layer is made of one of the oxides including a group 3 nitride formed by chemical vapor deposition (CVD) and a group 2 or group 3 oxide formed by physical vapor deposition (PVD) , forming a sacrificial layer; And, depositing an Al _{x Ga 1-x N} (0.5≤x≤1) piezoelectric thin film on the sacrificial layer; A method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film comprising: depositing a piezoelectric thin film deposited by a physical vapor deposition method at a temperature equal to or higher than the melting point of the thin film material). is provided.

According to another aspect of the present disclosure (According to another aspect of the present disclosure), in a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, a chemical vapor deposition method on a silicon film substrate Forming a stress control layer made of a group III nitride by (CVD; Chemical Vapor Deposition); And, forming an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the stress control layer by physical vapor deposition at a temperature of 0.3 Tm (Tm; melting point of the piezoelectric thin film material) or higher. A method for manufacturing a characterized Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film is provided.

According to another aspect of the present disclosure (According to another aspect of the present disclosure), in a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film device, Al _x Ga _1-x bonding the element substrate to the N (0.5≤x≤1) piezoelectric thin film; removing the film formation substrate; And forming an electrode on the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the side from which the film formation substrate is removed; including, the Al _x Ga _1-x N (0.5≤x≤1) electrode formed 1) A method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film element is provided, wherein the surface of the piezoelectric thin film has a metallic polarity.

This will be described at the end of 'Specific Contents for Implementation of the Invention'.

1 is a view showing elements using a piezoelectric thin film presented in US Patent Publication No. US2015-0033520;
2 to 4 are views showing an AlN piezoelectric thin film and a method of manufacturing a device using the same presented in US Patent Publication No. US2015-0033520;
5 is a view showing an example of a method for manufacturing an AlN piezoelectric thin film presented in US Patent Publication No. US2006-0145785;
6 is a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. A drawing showing an example,
7 is a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. A drawing showing another example,
8 shows a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. A drawing showing another example,
9 shows a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. A drawing showing another example,
10 to 12 are diagrams showing an example of a method of manufacturing a resonator using an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure;
13 and 14 are views showing another example of a method of manufacturing a resonator using the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure;
15 is a view showing an example of a method for manufacturing an AlN piezoelectric thin film presented in Solid-State Electronics 54 (2010) 1041-1046;
16 shows a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. A drawing showing another example,
17 shows a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. A drawing showing another example,
18 shows a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. A drawing showing another example,
19 shows a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. A drawing showing another example,
20 is a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. A drawing showing another example,
21 shows a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. A drawing showing another example,
22 and 23 are diagrams showing another example of a method of manufacturing a resonator using the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure.

Hereinafter, the present disclosure will now be described in detail with reference to the accompanying drawing(s).

6 is a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. As a diagram showing an example, the structure includes a sapphire film-forming substrate 1, a first semiconductor layer 2, a sacrificial layer 3 and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4. include

7 is a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. As a diagram showing another example, the structure includes a sapphire film-forming substrate 1, a first semiconductor layer 2, a sacrificial layer 3, and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 and, additionally, a second semiconductor layer 5 between the sacrificial layer 3 and the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4.

8 shows a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. As a diagram showing another example, the structure includes a sapphire film-forming substrate 1, a first semiconductor layer 2, a sacrificial layer 3, and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 , but the formation order of the first semiconductor layer 2 and the sacrificial layer 3 is changed from the structure shown in FIG. 6 .

9 shows a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. As a diagram showing another example, the structure is a sapphire film substrate 1, a first semiconductor layer 2, a sacrificial layer 3, Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 And it includes the second semiconductor layer 5, but the formation order of the first semiconductor layer 2 and the sacrificial layer 3 is changed from the structure shown in FIG.

For example, a C-plane (0002) sapphire film-forming substrate may be used, and the group III nitride formed thereon may have a polarity (metallic or gas) surface or semi-polarity (metallic) depending on growth pretreatment conditions. If it is possible to have a surface (mixed polarity and nitrogen gas polarity), it is possible to consider using a sapphire film deposition substrate that is off the C-plane or non-C-plane. In addition to the flat film formation substrate, the use of a nano-sized Patterned Sapphire Substrate (PSS) can be considered.

In the example shown in FIGS. 6 and 7, the first semiconductor layer 2 is formed of Al _y Ga _1-y N (0.5≤y≤1) grown at a high temperature (1000 ° C or more) rather than at a low temperature, and subsequently It serves to ensure the crystal quality (crystallinity and polarity) of the grown Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4. Therefore, it is distinguished from a layer called a conventional buffer layer grown and formed at a temperature lower than the proper growth temperature. The first semiconductor layer 2 may be grown and deposited by CVD (eg, MOCVD, HVPE, ALD). The upper and lower limits of the thickness of the first semiconductor layer 2 formed of Al _y Ga _1-y N (0.5≤y≤1) are not particularly limited, but preferably Al _x Ga _1-x N (0.5≤x≤1 ) 100 nm-20 μm to be advantageous in performing a stress control function to maintain the thickness uniformity of the piezoelectric thin film 4. For example, it can be grown and formed at a temperature of 1000-1400 ° C. and a pressure of 100-200 torr, in an atmosphere composed of ammonia (NH ₃ ) and nitrogen (N ₂ ) containing a large amount of hydrogen (H ₂ ) (relatively NH ₃ content is greater than N ₂ ) or in an atmosphere composed of ammonia (NH ₃ ) and nitrogen (N ₂ ), in case of AlN, 100% Al composition, in case of Al-rich AlGaN, Al/(Al+Ga) When the value is 50% or more, growth film formation can be performed. Preferably, as a pretreatment, before the growth of the first semiconductor layer 2 made of Al _y Ga _1-y N (0.5≤y≤1) at the appropriate growth temperature, Al MOCVD source gas at 900-1000 ° C for 10 sec (eg : After pre-treatment inside the chamber with TMAl) and forming an AlN buffer layer with a thickness of 20 nm or less, it is then grown and formed under appropriate growth conditions of 1000-1400 ° C and 100-200 torr, securing high quality crystallinity and reducing dislocation density (reduction in A first semiconductor layer made of Al _y Ga _1-y N (0.5≤y≤1) and an adjacent region of the sapphire film deposition substrate 1 intentionally for suppression of dislocation density, crack generation and propagation (2) It is advantageous to form a number of air-voids inside.

In the example shown in FIGS. 8 and 9, the first semiconductor layer 2 is preferably made of Al _y Ga _1-y N (0.5≤y≤1) of 100 nm or less, and Al _x Ga ₁ subsequently grown into a film _-x N (0.5≤x≤1) serves to ensure the crystallinity and polarity of the piezoelectric thin film 4. The first semiconductor layer 2 may be deposited by PVD (eg, sputtering, PLD), and at this time, supplying a certain amount of oxygen (eg, O ₂ /(N ₂ +O ₂ ) value of 3% or less) is important, , serving as nanoscale AlN or Al-rich AlGaN seeds. The sputter deposition deposition of Al _y Ga _1-y N (0.5≤y≤1) in an atmosphere containing a small amount of O ₂ is relatively small island-shaped Al _y Ga _1-y N (0.5≤y≤1 ) Improvement of surface flatness and inside of thin film of Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 grown by CVD (eg MOCVD, HVPE, ALD) at the appropriate growth temperature by forming crystals It plays a critical role in securing high-quality crystallinity and polarity through the reduction of dislocation density. The thickness of the first semiconductor layer 2 is preferably 100 nm or less, more preferably 1 nm-, which is more advantageous for generating cracks and suppressing propagation of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4. 30 nm. For example, a film may be deposited at a temperature and pressure of 300-500° C. at a pressure of 5*10 ^-3 mbar, and an atmosphere composed of nitrogen (N ₂ ) and oxygen (O ₂ ) including a large amount of argon (Ar). (relatively much higher N ₂ content than O ₂ ; Ar 40 sccm, N2 110 sccm, O2 4 sccm) can be used. The quality of the grown Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4) was examined through the X-ray (0002) rocking curve, which is one of the measurement indicators representing the quality, and the 0.04- It showed a value of 0.06°. This shows that the quality of the thin film is greatly improved compared to the value of 1.2-2.5° of the current commercial structure (Si film formation substrate/SiO ₂ /metal electrode/AlN).

The first semiconductor layer 2 shown in FIGS. 6 and 7 and the first semiconductor layer 2 shown in FIGS. 8 and 9 are composed of Al _y Ga _1-y N (0.5≤y≤1), and subsequently grown It is common in that it serves to ensure the crystallinity and polarity of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 to be formed.

The sacrificial layer 3 is sapphire prior to forming the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 to facilitate separation of the sapphire film substrate 1 during laser lift-off (LLO). It is an optically transparent semiconductor having an energy bandgap of a sufficiently larger wavelength than the wavelength of the laser irradiated through the rear surface of the film formation substrate 1, and at the same time, an amorphous, polycrystalline, or polycrystalline), or regions of material having a multi-layer microstructure, for example multi-layer Al _x1 Ga _1-x1 N/Al _x2 Ga _1-x2 N (x ₂ < x ₁ ≤1, 0≤x ₂ <0.5), single-layer Ga-rich AlGaN (Ga/(Ga+Al) value is 50% or more) and GaN. The sacrificial layer 3 may be grown and formed by CVD (eg, MOCVD, HVPE, ALD), and absorbs laser energy during laser lift-off to form a layer on the sapphire film substrate 1 side and Al _x Ga _1-x N ( 0.5≤x≤1) serves to separate the side of the piezoelectric thin film 4. Al _z Ga _1-z N energy band gap, E(z)=3.43+1.44z+1.33z ² (eV), which is generally derived from theory and experiment and confirmed, if Al _0.5 Ga _0.5 N with 50% Al composition is It has an energy bandgap of 4.48eV. λ(nm) = 1240/E(z), an equation that converts the energy bandgap (eV) value of a semiconductor (including insulator) into a wavelength, which is an optical characteristic. By converting the wavelength through this equation, a value of 277 nm can be obtained. Therefore, a single layer of Al _z Ga _1-z N and GaN material having an Al composition of less than 50% or a sacrificial layer 3 having a multilayer microstructure composed of these materials is formed through a relatively generalized high-power short-wavelength laser light source (248 nm or more). easy to remove The thickness of the sacrificial layer 3 may be, for example, 100 nm or less, preferably 1 nm-30 nm, which is more advantageous for crack generation and propagation suppression of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4. do it with In the case of Al _z Ga _1-z N having an Al composition of less than 50%, it is possible to grow at 900-1200 ° C and 100-200 torr, and in the case of GaN, it is possible to grow at 600-1100 ° C and 100-200 torr. After the growth of the sacrificial layer (3) on the sapphire film substrate (1), the Al _x Ga _1-x N (0.5≤x≤1) sputtering AlN thin film serving as a seed prior to the growth and deposition of the piezoelectric thin film (4) To deposit a film, as a pre-sputtering treatment, stabilize the surface of the sacrificial layer 3 through a small amount of Ar (flattening and cleaning through surface etching) and a large amount of nitrogen (N ₂ ) gas containing a small amount of oxygen (O ₂ ) in the chamber It includes steps to Al _x Ga _1-x N (0.5≤x≤1) The piezoelectric thin film 4 can be grown and deposited by CVD (eg, MOCVD, HVPE, ALD), and is grown and deposited as a single crystal thin film. The thickness may vary depending on the final device, and, for example, when used in the FBAR shown in FIG. thickness is determined. Al _x Ga _1-x N (0.5≤x≤1) A case in which the piezoelectric thin film 4 includes Ga may be considered, and accordingly, the first semiconductor layer 2, the sacrificial layer 3, and the second semiconductor layer The composition of Ga in (5) may vary.

The second semiconductor layer 5 shown in FIG. 7 is formed before forming the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 by, for example, CVD (eg, MOCVD, HVPE, ALD). It can be grown and formed in a step-by-step process, and a single layer of Al _a Ga _1-a N (0.5<a≤1) or Al _b1 Ga _1-b1 N/Al _b2 Ga _1-b2 N (b ₁ ≠b ₂ ) It is composed of a multilayer structure (preferably, the Al content is 50% or more as a whole), but the Al content is higher than that of the sacrificial layer (3) as a whole, so that Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film It serves to resolve the stress difference between (4) and the sacrificial layer (3) having a high Ga content. The second semiconductor layer 5 may have an upward gradation structure in which the Al content increases from the sacrificial layer 3 toward the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4. Of course there is. In the case of the example shown in FIG. 9, the first semiconductor layer 2 is located between the second semiconductor layer 5 and the sacrificial layer 3, but the thickness of the first semiconductor layer 2 is not thick, so shown in FIG. As in the example, by providing the second semiconductor layer 5, the stress between the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 and the sacrificial layer 3 having a high Ga content ) plays a role in dissolving the difference. In addition, since the second semiconductor layer 5 plays an important role in determining the thickness uniformity of the entire wafer when the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is grown and deposited. It can be used to control wafer strain by adding a process of adding Si or/and Mg dopants. The thickness of the second semiconductor layer 5 may be, for example, 100 nm or less, and is preferably more advantageous for suppressing crack generation and propagation of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4. 1nm-30nm.

10 to 12 are diagrams illustrating an example of a method of manufacturing a resonator using an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure. Here, the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film presented in this disclosure is applied to a resonator, but the sapphire film deposition substrate from the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film. After removing the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, any element or device can be expanded and applied without limitation. Of course, the methods presented in FIGS. 3 and 4 can be used, and can also be applied to SAW resonators in addition to BAW resonators. Hereinafter, the structure presented in FIG. 6 will be described. As shown in FIG. 10, first, an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4 ), a first electrode (6; for example: Mo, W, Ta, Pt, Ir, Ru, Rh, Re, Au, Cu, Al, Invar, or an alloy thereof) is formed. Next, on the first electrode 6, a first protective film 7 (eg: Mo, W, Ta, Pt, Ti, TiW, TaN, TiN, SiO ₂ , Al ₂ O ₃ , SiC, SiCN, SiN _x , AlN , Polyimide, BCB, SU-8, SOG, etc.). Next, a first bonding layer 8 (eg, SnIn, AuSn, AgIn, PdIn, NiSn, CuSn, Cu to Cu, Au to Au, Epoxy, SU-8, BCB) is formed on the first protective film 7. . A temporary substrate 9 (eg: sapphire, AlN, glass) is wafer bonded to the first bonding layer 8 . Next, the sapphire film deposition substrate 1 is separated through laser lift-off (LLO). In this process, a metal droplet removal process, a trimming process for accurate thickness adjustment, and the like may be accompanied. The surface of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4) after the separation of the sapphire film formation substrate (1), the removal of metal droplets, and the trimming process has a nitrogen gas polarity (N-polarity) (face). Subsequently, as shown in FIG _. 11, the second electrode 14 ₍ eg: Mo, W, Ta, Pt, Ir, Ru, Rh, Re, Au, Cu, Al, Invar, these alloys) and a multi-layered Bragg reflector (10; eg SiO ₂ /W) reflector is formed. Preferably, after the deposition process of the second electrode 14 and the Bragg reflector 10 reflector, then the second protective film 11 on the reflector of the Bragg reflector 10; eg Mo, W, Ta, Pt, Ti, TiW, TaN, TiN, SiO ₂ , Al ₂ O ₃ , SiC, SiCN, SiN _x , AlN, Polyimide, BCB, SU-8, SOG, etc.) are formed. Next, a second bonding layer 12 (eg, SnIn, AuSn, AgIn, PdIn, NiSn, CuSn, Cu to Cu, Au to Au, Epoxy, SU-8, BCB, etc.) is formed on the second protective film 11. . Subsequently, as shown in FIG. 12, the device substrate 13 (eg: Si, GaAs, AlN, Mo, Cu, W, MoCu, CuW, Invar, Laminate) is eutectic bonding with the second bonding layer 12, Wafer bonding is performed by brazing or the like. Although not shown, an electrical insulator material layer (protective layer) and a wafer bonding layer are sequentially formed on the device substrate 13 prior to wafer bonding. Finally, the temporary substrate 9 is separated and removed through thermal processing, laser irradiation, and chemical and physical energy source supply, and then the first bonding layer 8 and the first protective film 7 are removed. The same can be applied to the examples presented in FIGS. 7 to 9 . At this time, the second semiconductor layer 5 is also removed. By using two wafer bonding processes, the metallic polarity (Al-polarity or Al-polarity & Ga-polarity mixed) surface of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is formed. It can be used as the upper surface of the device, and through this, it has an advantage in terms of post-processing and quality of the final device by having a chemically and structurally stable surface such as corrosion resistance.

13 and 14 are diagrams showing another example of a method of manufacturing a resonator using an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure, and FIGS. Unlike the method presented in 12, a temporary substrate 9 is not used. First, as shown in FIG. 13, the second electrode 14 (eg: Mo, W, Ta, Pt, Ir, Ru, Rh, Re, Au, Cu, Al, Invar, or an alloy thereof) and a multilayer structure After forming the reflector, the second protective film 11, and the second bonding layer 12 of the Bragg reflector 10, the device substrate 13 is wafer bonded, and then the sapphire film deposition substrate 1 is removed. Finally, as shown in FIG. 14, the first electrode 6 is formed.

The difference between the resonator element manufactured by the method shown in FIGS. 10 to 12 and the method shown in FIGS. 13 and 14 depends on the location where the second electrode 14 including the reflector of the Bragg reflector 10 is formed and placed and the number of wafer bonding. Al _x Ga _1-x N (0.5≤x≤1) The surface polarity of the piezoelectric thin film 4 is determined. The method shown in FIGS. 10 to 12 is manufactured through two wafer bonding processes, and the second electrode 14 including the Bragg reflector 10 reflector is Al _x Ga _1-x N (0.5≤x≤1) piezoelectric. While placed on the N-polarity face of the thin film 4, the second electrode 14 including the Bragg reflector 10 and the reflector in the case of the method shown in FIGS. 13 and 14 undergoing a single wafer bonding process This Al _x Ga _1-x N (0.5≤x≤1) is located on the metallic polarity surface (Al-polarity or Al-polarity & Ga-polarity mixed face) of the piezoelectric thin film 4. For reference, in the case of a resonator element made of a polycrystalline AlN piezoelectric thin film formed by sputtering on a conventional Si film substrate, there is a limit in adjusting the surface polarity and polarity ratio, so the Bragg reflector 10 includes a reflector. The position of the polarity of the two electrodes 14 cannot be defined.

16 shows a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. As a diagram showing another example, the structure includes a sapphire film-forming substrate 1, a sacrificial layer 23a, and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4. The sacrificial layer 23a is a single-layer Al _c Ga _1-c N (0≤c≤0.5) or multi-layer Al _c1 Ga _1-c1 N/Al _c2 Ga ₁ grown by CVD (MOCVD, ALD, MBE, etc.). _-c2 N (c ₂ < c ₁ ≤ 1, 0 ≤ c ₂ < 0.5) of group 3 nitride. The Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is deposited on the sacrificial layer 23a by PVD (eg sputtering, PLD) at a temperature of 0.3Tm (melting point of the piezoelectric thin film material) or higher. and high quality is ensured.

17 shows a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. As a diagram showing another example, the structure is a sacrificial layer 23a, a second semiconductor layer 5, and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film sequentially on a sapphire film formation substrate 1. (4) is included. It is distinguished from the structure shown in FIG. 16 in that a second semiconductor layer 5 is added, and the second semiconductor layer 5 functions similarly to the second semiconductor layer 5 shown in FIG. 7, and the sacrificial layer 23a ), but formed by CVD, but composed of group 3 nitrides having a different composition (Al _a Ga _1-a N (0.5<a≤1)), Al _x Ga _1-x N having a uniform thickness by controlling stress (0.5≤x≤1) serves to facilitate securing the piezoelectric thin film 4.

18 shows a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. As a diagram showing another example, the structure includes a sapphire film-forming substrate 1, a sacrificial layer 23b, and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4. The sacrificial layer 23b is a single layer of ZnO, ITO, or a multi-layer oxide structure including at least one of these (ZnO/ITO, ZnO/SiO ₂ , ITO/SiO ₂ ) It is distinguished from the structure shown in FIG. 16 in that it is made of an oxide. The Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is deposited on the sacrificial layer 23b by PVD (eg sputtering, PLD, etc.) at a temperature of 0.3Tm or higher (the melting point of the piezoelectric thin film material). A film is formed and high quality is ensured.

19 shows a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. As a diagram showing another example, the structure is sequentially formed on the sapphire film-forming substrate 1 by sequentially forming a sacrificial layer 23b, an oxygen (O ₂ ) inflow prevention layer (O), and Al _x Ga _1-x N (0.5≤x≤1 ) piezoelectric thin film (4). It is distinguished from the structure shown in FIG. 18 in that an oxygen (O ₂ ) inflow prevention layer (O) is added, and the oxygen (O ₂ ) inflow prevention layer (O) is an AlN or AlNO material containing a minute amount of oxygen on the sacrificial layer (23b). It is deposited and formed with the same PVD (eg L sputtering, PLD) as the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 to be subsequently deposited to prevent oxygen inflow from the sacrificial layer 23b. It serves to promote the securing of the high-purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4.

In the examples shown in FIGS. 16 and 17, the sacrificial layer 23a is a single-layer Al _c Ga _1-c N formed by single crystal growth by CVD (MOCVD, HVPE, ALD, MBE) at a high temperature (900 ° C. or more) rather than a low temperature. (0≤c≤0.5) or multi-layered Al _c1 Ga _1-c1 N / Al _c2 Ga _1-c2 N (c ₂ <c ₁ ≤ 1, 0≤c ₂ <0.5) of group 3 nitrides, , Crystal quality (crystallinity and polarity) of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 subsequently deposited by PVD (eg sputtering, PLD) at a temperature of 0.3Tm (660 ° C) or higher. ) serves to ensure that Therefore, the sacrificial layer 23a is distinguished from a layer called a conventional buffer layer grown at a temperature lower than the proper growth temperature, and plays the role of the first semiconductor layer 2 and the sacrificial layer 3 shown in FIGS. 6 to 9. The difference is that they are performed simultaneously. The upper and lower limits of the thickness of the sacrificial layer 23a are not particularly limited, but preferably Al _x Ga _1-x N (0.5≤x≤1) Stress for maintaining thickness uniformity of the piezoelectric thin film 4 It is set to 50 nm-3 μm to be advantageous for the stress control function. For example, it can be grown at a temperature of 900-1100 ° C. and a pressure of 100-600 torr. More preferably, as in the example shown in FIG. 17, Al _x Ga 1 positioned between the sacrificial layer 23a and the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film ₄ and subsequently deposited into a film. _-x N (0.5≤x≤1) A second semiconductor layer 5 is provided to improve crystallinity and thickness uniformity of the piezoelectric thin film 4. The second semiconductor layer 5 is formed by single crystal growth with the same CVD (MOCVD, HVPE, ALD, MBE, etc.) as the sacrificial layer 23a, and at this time, an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film ( 4) is preferably composed of a group 3 nitride having the same or similar composition. In addition, the sacrificial layer 23a and the second semiconductor layer 5 have high quality (crystallinity and polarity) and uniform thickness during deposition of the Al _y Ga _1-y N (0.5≤y≤1) piezoelectric thin film 4. It is preferable to control the film formation substrate curvature to maintain a zero (flat) state as much as possible.

In the examples shown in FIGS. 18 and 19, the sacrificial layer 23b is a single layer of ZnO deposited with crystallinity (polycrystal or single crystal) by PVD (eg, sputtering, PLD) at a high temperature (400° C. or more) rather than at a low temperature. and ITO, or a multi-layered oxide structure including at least one of these (ZnO/ITO, ZnO/SiO ₂ , ITO/SiO ₂ ). The upper and lower limits of the thickness of the single layer sacrificial layer 23b are not particularly limited, but preferably Al _x Ga _1-x N (0.5≤x≤1) to maintain the thickness uniformity of the piezoelectric thin film 4. It is set to 50 nm-3 μm to be advantageous for the stress control function. The sacrificial layer 23b may be deposited by PVD (eg, sputtering, PLD), and during film formation, the temperature of the film formation substrate is 750 ° C, the process pressure consisting of argon (Ar) and oxygen (O ₂ ) gas is 10-20 mTorr, , the amount of oxygen is relatively small compared to argon, and it is desirable to configure it within at least 50%. More preferably, as in the example shown in FIG. 19, Al _x Ga 1 positioned between the sacrificial layer 23b and the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film ₄ , and subsequently deposited into a film. _-x N (0.5≤x≤1) In order to improve crystallinity and thickness uniformity of the piezoelectric thin film 4, an oxygen (O ₂ ) inflow prevention layer (O) is provided. The oxygen (O ₂ ) inflow prevention layer (O) is deposited on the sacrificial layer (23b) of AlN or AlNO material containing a small amount of oxygen, and subsequently deposited Al _x Ga _1-x N (0.5≤x≤1) piezoelectric. A high-purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is formed by depositing a film with the same PVD (eg, sputtering, PLD) as the thin film 4 to prevent oxygen inflow from the sacrificial layer 23b. It serves as a facilitator for obtaining In particular, when AlNO (Al _y Ga _1-y N (0.5≤y≤1) sputtering deposition in an atmosphere containing a small amount of O ₂ ) is applied as an oxygen (O ₂ ) inflow prevention layer (O), a certain amount (eg, O ₂ / Supply of oxygen (N ₂ +O ₂ ) value of 3% or less is important, and serves as a seed to secure the high-purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4) . The sputtering deposition of Al _y Ga _1-y N (0.5≤y≤1) in an atmosphere containing a small amount of O ₂ produces relatively small island-shaped Al _y Ga _1-y N (0.5≤y≤1) Surface flatness improvement of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4) deposited by PVD (eg sputtering, PLD) at the appropriate deposition film formation temperature by forming crystals and It plays an important seed role in securing high-quality crystallinity and polarity through the reduction of dislocation density. It is preferable that the thickness of the oxygen inflow prevention layer (O) composed of AlN or AlNO is 100 nm or less, more preferably for crack generation and propagation suppression of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4). It is set to 1 nm-30 nm, which is more advantageous. For example, a temperature and pressure of 300-500° C. can be deposited at a pressure of 5*10 ^-3 mbar.

The crystalline quality of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4) structure manufactured according to the method presented in FIGS. 16 to 19 is commonly the half width of the X-ray rocking curve. It aims to have this small value (target value: 0.1° or less), and in relation to the polar quality, in the case of FIGS. 16 and 17, the sacrificial layer 23a and the second semiconductor layer 5, FIG. In the case of 18 and 19, there is an advantage that can be freely adjusted according to the surface state of the sacrificial layer (23b) and the oxygen inflow prevention layer (O).

Of course, the method of manufacturing the resonator shown in FIGS. 10 to 14 can be applied to the structures shown in FIGS. 16 to 19 as it is.

16 to 19, the sacrificial layers 23a and 23b are Al _x Ga _1-x N (0.5≤x≤1) formed on the optically transparent film substrate 1 through a laser lift-off (LLO) process. ) It is located between the film formation substrate 1 and the high-purity piezoelectric thin film 4 so that the piezoelectric thin film 4 can be separated, ② has an energy band gap (generally 200 nm or more) to function as a sacrificial layer for the laser, ③ It can be composed of Group 3 nitride formed by CVD, Group 2 or Group 3 oxide formed by PVD (eg ZnO, In ₂ O ₃ , Ga ₂ O ₃ , ITO), ④ Al _x Ga _1-x N (0.5≤ x≤1) To enable high-temperature film formation of piezoelectric thin films, the material must have thermal stability at 0.3Tm (660℃) or higher, ⑤ Al _x Ga _1-x N (0.5≤ x≤1) A material having the same or similar crystal structure as the piezoelectric thin film 4, ⑥ Al _x Ga _1-x N (0.5≤x≤1) surface roughness to enable film formation of the piezoelectric thin film 4 ) is a ceramic (nitride, oxide) material that can be 10 nm or less, and ⑦ Al _x Ga _1-x N (0.5≤x≤1) A surface state in which various contaminants are removed to enable film formation of the piezoelectric thin film (4) It is preferable that the material of

The sacrificial layer 23a may be grown as a high-temperature single-crystal layer (single-layer or multi-layer structure) having a structure including a conventional buffer layer grown at a low temperature.

If necessary, a sacrificial layer (23a, 23b) to secure a single crystal piezoelectric thin film having a tilted c-axis crystal plane before forming the Al _x Ga _1-x N (0.5≤x≤1) pressure welded thin film (4). It is also possible to perform photo-lithographic etch patterning on the surface of

After deposition of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4, crystallinity and polarity may be improved through post-annealing, which is an additional post-on heat treatment process.

As described above, when the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 having a uniform thickness is particularly required, Al _x Ga _1-x N (0.5≤x≤1) The structure shown in FIG. 16 (sapphire deposition substrate 1-sacrificial layer 23a) placed under the piezoelectric thin film 4, the structure shown in FIG. 17 (sapphire deposition substrate 1-sacrificial layer 23a-second semiconductor layer 5), the structure shown in FIG. 18 (sapphire deposition substrate 1-sacrificial layer 23b) and the structure shown in FIG. 19 (sapphire deposition substrate 1-sacrificial layer 23b-oxygen (O ₂ ) It is important to keep the inflow prevention layer (O)) as flatness as possible at the deposition temperature of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4, and the present disclosure It provides a foundation to sustain. For example, the sapphire film formation substrate 1 having the sacrificial layer 23a grown by CVD has a convex shape upward at room temperature, but when the temperature is raised again for PVD deposition film formation, it becomes flat with the temperature rise. After going through the state, it has a downward concave shape. This behavior is affected by the difference in thermal expansion coefficient between the sapphire film-forming substrate 1 and the sacrificial layer 23a, and therefore Al _x Ga _1-x N ( 0.5≤x≤1) Deposition of the piezoelectric thin film 4 becomes possible. This principle can also be applied to the design of the second semiconductor layer 5, the design of the sacrificial layer 23b, and the design of the oxygen (O ₂ ) inflow prevention layer (O).

20 is a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. As a diagram showing another example, the structure includes a silicon film substrate 1, a stress control layer 23c, and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4.

Compared to the structure shown in FIG. 16, the stress control layer 23c is grown and deposited by CVD like the sacrificial layer 23a, and the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is formed by PVD It is the same in that a film is deposited by deposition, but silicon is used as the film formation substrate 1 instead of sapphire, and the stress control layer 23c is formed on the silicon film formation substrate 1 instead of by laser lift off (LLO). ) has a difference in that it is removed together in the process of being removed through etching. Since the silicon film substrate 1 has a different lattice constant and thermal expansion coefficient from the sapphire film film substrate 1, the stress control layer 23c formed thereon and Al _x Ga _1-x N (0.5≤x≤1) piezoelectric The film formation conditions of the thin film 4 are Al _x Ga _1-x N (0.5≤x≤1) so that no cracks occur in the piezoelectric thin film 4 and Al _x Ga _1-x N (0.5≤x≤1) piezoelectric It is important to control the thin film 4 so that it is formed with a uniform thickness. As the silicon film substrate 1, for example, an 8-inch Si (111) substrate may be used. Therefore, the stress control layer 23c does not have the constraints that the sacrificial layer 23a must have for Laser Lift Off (LLO), and is made of high-quality Al _x Ga _1-x N (0.5≤x≤1) piezoelectric. It is possible to concentrate only on the formation of the thin film 4.

The stress control layer 23c is a single-layer Al _g Ga _1-g N (0≤g≤1) or multi-layer Al _h1 Ga _1-h1 N/ Al _h2 Ga _1-h2 N (h ₂ <h ₁ ≤ 1, 0 ≤ _{h 2} ≤ 1) of a group III nitride. The stress control layer 23c prevents and alleviates wafer curvature and cracks caused by differences in physical properties (lattice constant and thermal expansion coefficient) at the growth temperature with the silicon film substrate 1. It plays a major role in stress control. Above all, in the initial stage of forming the stress control layer 23c, silicon (Si), group 3 (Al, Ga), and group 5 (N) elements and chemical It is important to minimize the formation of intermetallic compounds (Si-Al-(Ga)) and/or silicon nitride (Si(Al,Ga)Nx) through the reaction. The Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is deposited on the sacrificial layer 23c by PVD (eg sputtering, PLD) at a temperature of 0.3Tm (melting point of the piezoelectric thin film material) or higher. and can ensure high quality.

The stress control layer 23c may be formed at a temperature of 500° C. or higher, and the upper and lower limits of the thickness are not particularly limited, but are preferably Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 It is set to 50 nm-3 μm to be advantageous in performing a stress control function to maintain the thickness uniformity of . For example, the growth film may be formed at a temperature of 500-1100°C and a pressure of 100-600 torr.

21 shows a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film structure according to the present disclosure. As a diagram showing another example, the structure is sequentially formed on a silicon film substrate 1, a stress control layer 23c, a surface polarity control layer C, and Al _x Ga _1-x N (0.5≤x≤1) piezoelectric It includes a thin film (4). 20 in that a surface polarity control layer (C) is added, and the surface polarity control layer (C), like the stress control layer 23c, is formed by CVD (eg, MOCVD, HVPE, ALD, MBE) Single or multi-layer Al _m1 Ga _{1- m1} N/Al _m2 Ga _1-m2 N (m _{2 <} m ₁ ≤1, 0≤m ₂ ≤1), Al _x Ga _1-x N (0.5≤x≤1) The surface of the piezoelectric thin film 4 has a single polarity (metallic polarity or nitrogen gas polarity) in addition to minimizing crystal defects and controlling stress to promote Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4) having a uniform thickness. . An Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is deposited on the stress control layer 23c by PVD (eg sputtering, PLD) at a temperature of 0.3Tm (melting point of the piezoelectric thin film material) or higher. A film can be formed to ensure high quality. Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film having a metallic polar surface through the surface polarity control layer (C) is PVD (eg sputtering, PLD) to Al _x Ga _1-x N ( 0.5≤x≤1) Prior to depositing the piezoelectric thin film 4, the surface polarity control layer (C) is grown and formed by CVD (eg MOCVD, HVPE, ALD, MBE), and then with a predetermined amount (rate) of oxygen. It can be obtained by plasma treatment of the surface of the surface polarity control layer (C). On the other hand, as a method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film having a nitrogen gas polar surface through the surface polarity control layer (C), a piezoelectric thin film (4 Al having a nitrogen gas polar surface by excessively adding (doping) magnesium (Mg) during the growth film formation of the surface polarity control layer (C) by CVD (MOCVD, HVPE, ALD, MBE) prior to deposition of ). _x Ga _1-x N (0.5≤x≤1) piezoelectric thin films can be obtained (SCIENTIFIC REPORT, Intentional polarity conversion of AlN epitaxial layers by oxygen, published online: 20 September 2018). Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film ( It is also possible to adjust the polarity of 4).

The surface polarity control layer (C) can be grown at the same constant temperature (500 ° C. or more) as the stress control layer (23c), and is Al _x Ga _1-x N at a pressure of 100-600 torr with a thickness of 0.5 μm or less. (0.5≤x≤1) It is preferable to be composed of a group III nitride having the same or similar composition as that of the piezoelectric thin film 4. In addition, the stress control layer 23c and the surface polarity control layer C have high quality (crystallinity and polarity) and uniform thickness when the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is deposited. It is preferable to control the curvature of the film formation substrate to maintain a zero (flat) state so as to have .

The bending state of the film formation substrate 1 depends on the film formation conditions (temperature, pressure) of the thin films 23c, C, 4 to be formed (deposited and grown) thereon, and the silicon film formation substrate 1 and the films 23c, C, 4 to be formed. ) is affected by the thermal expansion coefficient (the thermal expansion coefficient is a function of temperature) and the lattice constant, and preferably maintains a zero state, but it is good to have at least an upward convex state, and after completion of film formation, a downward convex ( It is important to prevent concave state, and the silicon film formation substrate 1 Since the degree of warpage can be measured during film formation, the film formation conditions (temperature, pressure) and the composition of AlGaN to be filmed during film formation are determined in a state where the warpage of the silicon film substrate 1 is zero or convex and after the final film formation. It will be important to adjust the condition so that it is. Considering the thermal expansion coefficient of the silicon film substrate 1 and the thermal expansion coefficient of AlGaN, it is not easy to perform such adjustment only by CVD, and by only PVD, a high-quality stress control layer 23c is formed, and a high temperature (0.3Tm (660 ℃)), it is not easy to form the Al _x Ga _1-x N (0.5≤y≤1) piezoelectric thin film 4. In the present disclosure, the stress control layer 23c and the surface polarity control layer C are grown and formed by CVD, and the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is deposited and deposited by PVD, Provides an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4) with excellent crystallinity and polarity despite using a silicon film formation substrate (1) having a large difference in lattice constant and thermal expansion coefficient You can do it.

For example, 1) Al _x Ga _1-x N (0.5≤x≤1) When the piezoelectric thin film 4 is deposited with AlN at a temperature of 800 ° C by PVD (eg sputtering, PLD), the stress control layer (23c) may be formed of Al _0.9 Ga _0.1 N with a thickness of 500 nm at a temperature of 500-900° C. and a pressure of 100-600 Torr by CVD (eg, MOCVD). 2) In addition, when the surface polarity control layer (C) is formed of 100 nm thick Al _0.9 Ga _0.1 N at a temperature of 500-1100 ° C. and a pressure of 100-600 Torr by CVD (eg MOCVD), Al _x Ga _{1- x} N (0.5≤x≤1) The piezoelectric thin film 4 is formed of AlN at a temperature of 800° C. by PVD (e.g. sputtering, PLD), and the stress control layer 23c is formed by CVD (e.g. MOCVD) at 500 It can be formed of Al _0.8 Ga _0.2 N with a thickness of 500 nm at a temperature of -900 ° C and a pressure of 100-600 Torr. At this time, the minimum (zero) film formation under the process conditions (temperature, pressure) for growing the stress control layer 23c and/or the surface polarity control layer C on the silicon film substrate 1 by CVD (eg MOCVD) While maintaining the warpage of the substrate 1 is of the utmost importance, a silicon film deposition substrate at room temperature (25 ° C.) after completion of the growth deposition of the stress control layer 23c and / or the surface polarity control layer (C) by CVD (eg MOCVD) (1) It is important to adjust the warp to maintain zero or convex state. In order to have the crystal quality and uniform thickness of the AlN piezoelectric thin film 4 deposited on the stress control layer 23c and/or the surface polarity control layer C by PVD (eg, sputtering) subsequently, the film formation described above This may be possible by controlling the conditions and the corresponding behavior of the silicon film substrate 1 in a state of being recognized.

The crystalline quality of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4) structure manufactured according to the method presented in FIGS. 20 to 21 is commonly X-ray Rocking Curve (XRC ) has a half width value of 0.1° or less, and the polar quality can be freely adjusted according to the surface state of the stress control layer 23c and/or the surface polarity control layer C.

The stress control layer 23c and the surface polarity control layer C are composed of a group 3 nitride formed by ① CVD (MOCVD, HVPE, ALD, MBE), ② Al _x Ga _1-x N (0.5≤x≤1) To enable high-temperature deposition of the piezoelectric thin film 4, it must be a material with thermal stability at 0.3Tm (660 ° C) or higher, ③ Al _x Ga _1-x N (0.5≤ x≤1) It is a material having the same or similar crystal structure as that of the piezoelectric thin film (4), ④ Al _x Ga _1-x N (0.5≤x≤1) The surface roughness (surface roughness) It is a ceramic (nitride) material with a roughness of 10 nm or less, and ⑤ Al _x Ga _1-x N (0.5≤x≤1) A surface state in which various contaminants are removed to enable deposition of the piezoelectric thin film (4). It is preferable that the material of

If necessary, an Al _x Ga _1-x N (0.5≤x≤1) stress control layer (23c) to secure a single-crystal piezoelectric thin film having a tilted c-axis crystal plane before depositing the pressure-contact thin film (4) And/or it is also possible to perform photo-lithographic etch patterning on the surface of the surface polarity control layer (C).

The Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 deposited subsequently on the stress control layer 23c and/or the surface polarity control layer (C) on the silicon deposition substrate 1 Unlike the conventional piezoelectric thin film deposited by PVD (e.g., sputtering, PLD) at a low temperature (around 400 ° C), the high-temperature single-crystal crystal structure deposited at 0.3 Tm (660 ° C) or higher provides higher quality. have

After deposition of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4, it is possible to further improve crystallinity and polarity through post-annealing, which is an additional high-temperature post-annealing process. .

It is preferable to preferentially grow and form an AlGaN thin film in which the gallium (Ga) component is minimized while controlling the temperature of the stress control layer 23c from a temperature of 500 ° C or higher to a low / medium / high temperature. This is to prevent a melt-back phenomenon by suppressing a reaction between silicon (Si) and gallium (Ga), which forms an intermetallic compound relatively easily.

An intermediate layer of a superlattice structure may be introduced between the stress control layer 23c and the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4, which is to suppress crystal defects.

Al _x Ga _1-x N (0.5≤x≤1) While increasing the Al content during the deposition of the piezoelectric thin film 4, the deposition temperature of PVD can also be increased, which suppresses tensile stress This is to prevent micro-cracks of the piezoelectric thin film 4.

As the method of manufacturing the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 structure using the silicon film substrate 1, the methods presented in FIGS. 10 to 14 can be used as they are. However, the silicon (Si) film formation substrate 1, the stress control layer 23c, and the surface polarity control layer C are not Laser Lift Off (LLO), but a known wet etch and It has a difference in that it is removed through parallel dry etching. In this process, a trimming process or the like for accurate thickness adjustment may be accompanied.

22 and 23 are views showing another example of a method of manufacturing a resonator using an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure, a silicon film substrate ( 1), a stress control layer 23c and a surface polarity control layer 3 are provided, and magnesium (Mg) is added (doped) to the surface polarity control layer 3 to form Al _x Ga _1-x N (0.5 ≤x≤1) After the piezoelectric thin film 4 is formed to have a nitrogen gas polar surface, the second electrode 14, the Bragg reflector 10 reflector, the second protective film 11, the second bonding layer 12 and An element substrate 13 is formed, and the silicon film substrate 1, the stress control layer 23c, and the surface polarity control layer 3 are formed of Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 After removal from the Al _x Ga _1-x N (0.5 ≤ x ≤ 1) piezoelectric thin film 4 structure in which the first electrode 6 is formed is presented. Through this, as shown in FIGS. 10 to 12, without using two wafer bonding processes, that is, through one wafer bonding process, a metallic polarity (Al-polarity or Al-polarity & Ga-polarity mixed) surface can be formed. It is possible to provide an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 structure used as the upper surface of the device.

In the resonator-based device manufactured according to the present disclosure, the position where the second electrode 14 including the Bragg reflector 10 reflector is formed and placed is Al _x formed on a silicon (Si) film deposition substrate 1 Ga _1-x N (0.5≤x≤1) Al _x Ga _1-x N (0.5≤x≤1) according to the number of wafer bonding in the process of polarity control of the piezoelectric thin film and the subsequent device process On the piezoelectric thin film 4, the surface polarity can be freely selected. The method shown in FIGS. 10 to 12 is manufactured through two wafer bonding processes, and the second electrode 14 including the Bragg reflector 10 reflector is Al _x Ga _1-x N (0.5≤x≤1) piezoelectric. It is placed on the N-polarity face of the thin film 4, and also in the case of the method shown in FIGS. 22 and 23 in which a single wafer bonding process is performed, the second electrode 14 including the Bragg reflector 10 reflector ) is equally located on the N-polarity face of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4. For reference, in the case of a resonator element made of a polycrystalline AlN piezoelectric thin film formed through PVD (e.g., sputtering, PLD) directly on a conventional Si film substrate at a low temperature, there is a limit to adjusting the surface polarity and polarity ratio. , the position of the polarity of the second electrode 14 including the reflector of the Bragg reflector 10 cannot be defined. As a result, it is difficult to manufacture mixed polarity and polarity-adjusted devices regardless of the crystallinity positive/negative, so it is necessary to improve the performance of Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4) resonators. has a limit.

Hereinafter, various embodiments of the present disclosure will be described.

(1) A method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, comprising: forming a sacrificial layer on a sapphire film deposition substrate; And, growing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the sacrificial layer; including, growing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film. Prior to the step of forming a first semiconductor layer of Al _y Ga _1-y N (0.5≤y≤1); Al _x Ga _1-x N (0.5≤x≤1) piezoelectric, characterized in that it further comprises How to make a thin film.

(2) A method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, characterized in that the first semiconductor layer is formed at a temperature of 1000 °C or higher prior to formation of the sacrificial layer.

(3) A method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, characterized in that the first semiconductor layer is formed by PVD in a state in which oxygen is supplied after formation of the sacrificial layer.

(4) Between the sacrificial layer and the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, the Al content is greater than that of the sacrificial layer, and Al _x Ga _1-x N (0.5≤x≤1) Al is greater than that of the piezoelectric thin film. A method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, further comprising: forming a second semiconductor layer having a small content.

(5) In a structure having an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film; Al _x Ga _1-x N (0.5≤x≤1) A first electrode provided on one side of the piezoelectric thin film; Al _x Ga _1-x N (0.5≤x≤1) A second electrode and a reflector provided on the opposite side of the first electrode based on the piezoelectric thin film; Al _x Ga _1-x N including the first electrode (0.5≤x≤1) Al _x Ga _1-x N (0.5≤x≤1), characterized in that the surface of the piezoelectric thin film is a metallic polarity (Al-polarity or Al-polarity & Ga-polarity mixed) surface ) structure comprising a piezoelectric thin film.

(6) A structure having an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, wherein the reflector is one of an air cavity and a Bragg reflector.

(7) When the first semiconductor layer 2 is grown at a high temperature by MOCVD, it is preferable to insert a plurality of air-voids to relieve stress, and when formed by PVD, Sc, Mg, It is possible to add Zr as a doping or alloying component. The reason for inserting Sc, Mg, or Zr as a doping or alloy component is to maximize the electro-mechanical coupling efficiency of a device structure using a piezoelectric thin film.

(8) Second semiconductor layer (5) Al _x Ga _1-x N (0.5≤x≤1) Al _x Ga _1-x N (0.5≤x≤1) 1) It is possible to add Si or/and Mg into the second semiconductor layer 5 to play a role of uniforming the thickness of the piezoelectric thin film.

(9) In the method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, forming a sacrificial layer on a sapphire film deposition substrate; as, the sacrificial layer is chemical vapor deposition (CVD; Chemical Vapor Forming a sacrificial layer made of one of oxides including a group 3 nitride formed by deposition and a group 2 or group 3 oxide formed by physical vapor deposition (PVD); And, depositing an Al _{x Ga 1-x N} (0.5≤x≤1) piezoelectric thin film on the sacrificial layer; Depositing a piezoelectric thin film deposited by a physical vapor deposition method at a temperature equal to or higher than the melting point of the piezoelectric thin film material; Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, characterized in that it comprises.

(10) The sacrificial layer is a single-layer Al _c Ga _1-c N (0≤c≤0.5) formed by CVD or a multi-layer Al _c1 Ga _1-c1 N / Al _c2 Ga _1-c2 N (c ₂ <c ₁ ≤1, 0≤c ₂ <0.5) A method for producing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, characterized in that it is a group III nitride.

(11) It is formed by CVD between the sacrificial layer and the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, and has a different composition from the sacrificial layer (Al _a Ga _1-a N (0.5<a≤1)) A method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, further comprising: forming a second semiconductor layer made of a group III nitride.

(12) The sacrificial layer is Al _x Ga _1-x N (0.5 ≤x≤1) A method for producing a piezoelectric thin film.

(13) It is formed by PVD between the sacrificial layer and the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, and oxygen in the oxide sacrificial layer is Al _x Ga _1-x N (0.5≤x≤1 ) forming an oxygen (O ₂ ) inflow prevention layer to prevent inflow into the piezoelectric thin film; a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, characterized in that it further comprises.

(14) In a method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, a stress control layer made of a group III nitride is formed on a silicon film substrate by chemical vapor deposition (CVD). forming; And, forming an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the stress control layer by physical vapor deposition at a temperature of 0.3 Tm (Tm; melting point of the piezoelectric thin film material) or higher. A method for producing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film characterized by

(15) Prior to the deposition step, performing a pretreatment for adjusting the surface polarity of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film; Al _x Ga _1- , characterized in that it further comprises Method for producing _x N (0.5≤x≤1) piezoelectric thin film. Here, the pretreatment refers to intentional conversion of the surface polarity of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, and the aforementioned plasma treatment or excessive addition of magnesium (Mg) (doping).

(16) prior to the deposition step, forming a surface polarity control layer; further comprising, pretreatment is performed on the surface polarity control layer, and Al _x Ga _1-x N (0.5≤x ≤1) A method for producing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, characterized in that the piezoelectric thin film is formed.

(17) In the method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film element, bonding the element substrate to the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film element ; removing the film formation substrate; And forming an electrode on the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the side from which the film formation substrate is removed; including, the Al _x Ga _1-x N (0.5≤x≤1) electrode formed 1) A method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film element, characterized in that the surface of the piezoelectric thin film has a metallic polarity. The method presented in FIGS. 20 to 23 is not only for forming an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on a silicon film substrate, but also for forming an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film. It can be extended to a general method of manufacturing a device having a piezoelectric thin film. A typical example of an element having an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film is an RF resonator.

(18) Prior to the bonding step, a step of pre-treating the surface polarity of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the side where the device substrate is bonded to have a nitrogen gas polarity; A method for manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film element.

According to the present disclosure, it is possible to manufacture a high-purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, manufacture a resonator, and apply the resonator to various devices.

Deposition substrate (1), first semiconductor layer (2), sacrificial layer (3), Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4), second semiconductor layer (5), first electrode 6, second electrode 14

Claims (3)

In the method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film used in resonators,
Single-layer Al _g Ga _1-g N (0≤g≤1) and multi-layer Al _h1 Ga _1-h1 N/Al _h2 Ga _1-h2 N ( h ₂ <h ₁ ≤ 1, 0≤h ₂ ≤ 1), forming a stress control layer having a single crystal (single crystalline) crystal structure;
A single-layer Al _k Ga _1-k N (0≤k≤1) and a multi-layer Al _m1 Ga _1-m1 N/Al _m2 Ga _1-m2 N ( m ₂ <m ₁ ≤1, 0≤m ₂ ≤1), forming a surface polarity control layer having a single crystal crystal structure;
Al _x Ga _1-x N (0.5≤x≤1) performing a pretreatment on the surface polarity control layer to adjust the surface polarity of the piezoelectric thin film; and,
By forming an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the pretreated surface polarity control layer by physical vapor deposition at a temperature of 0.3Tm (Tm; melting point of the piezoelectric thin film material) or higher, thickness uniformity (thickness) uniformity) and forming an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film having a single crystal crystal structure;
The chemical vapor deposition method is one of MOCVD, HVPE, ALD, and MBE,
The physical vapor deposition method is one of sputtering and PLD,
The stress control layer is formed to a thickness of 50 nm to 3 μm,
The surface polarity control layer is characterized in that formed to a thickness of 0.5㎛ or less, a method for producing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film. delete delete