KR20210005989A - Method of manufacturing AlxGa1-xN (0.5≤x≤1) piezoelectric thin films with high purity and their apparatus using the thin film - Google Patents

Abstract

The present invention relates to a method of manufacturing an Al_xGa_(1-x)N (0.5<=x<=1) piezoelectric thin film and a method of manufacturing an Al_xGa_(1-x)N (0.5<=x<=1) piezoelectric thin film element including the piezoelectric thin film. The method of manufacturing an Al_xGa_(1-x)N (0.5<=x<=1) piezoelectric thin film comprises: a step of forming a stress control layer made of a group III-nitride on a silicon film formation substrate by chemical vapor deposition (CVD); and a step of forming an Al_xGa_(1-x)N (0.5<=x<=1) piezoelectric thin film over the stress control layer at a temperature of 0.3Tm (Tm is the melting point of a piezoelectric thin film material) or higher by physical vapor deposition.

Description

TECHNICAL FIELD The method of manufacturing AlxGa1-xN (0.5≤x≤1) piezoelectric thin films with high purity and their apparatus using the thin film is a high purity AlxGa1-xN (0.5≤x≤1) piezoelectric thin film and a method of manufacturing a device using the thin film. }

The present disclosure (Disclosure) as a whole relates to a high purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, a method for manufacturing a device using the thin film, and an apparatus using the thin film, and particularly, to excellent crystallinity ) And a high purity Al _x Ga _1-x N (0.5≤x<1) piezoelectric thin film, more preferably a high purity AlN piezoelectric thin film, and a method of manufacturing a device using the thin film and the same It relates to a device using a thin film. High-purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin films are used for high-frequency filters, energy harvesters, ultrasonic transducers, bio and IoT applications. It is used in various resonator applications including sensors for bio & IoT. Recently, these thin films have been used as acoustic resonators (e.g., surface acoustic wave resonators, BAW resonators) in filters used in portable electronic devices such as smart phones. It is attracting attention in its role and high-sensitivity sensors for bio and IoT applications. Although the use of the Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film has been exemplified above, the use of this thin film is not limited thereto.

Here, a background technology related to the present disclosure is provided, and these do not necessarily mean a known technology (This section provides background information related to the present disclosure which is not necessarily prior art).

According to the literature Nano Energy 51 (2018) 146-161, “AlN piezoelectric thin films for energy harvesting and acoustic devices”, AlN piezoelectric thin films have high longitudinal acoustic wave velocity (approximately 11,000 m/s), high Thermal stability (high thermal satbility, melting point; 2100℃, piezoelectric property maintenance temperature; 1150℃), wide energy bandgap (6.2eV), and excellent piezoelectric and dielectric properties. It has unique properties, so it can provide high-quality high-frequency filters, energy harvesters, ultrasonic transducers, and sensors for bio & IoT. It is currently explosively used as a variety of resonator applications including, and is the most popular material in the field where ultra-miniature and high-efficiency products are absolutely required through enhanced functionality and versatility in the future. In general, AlN piezoelectric thin film material is formed by thin film synthesis: PVD (physical vapor deposition; typically sputtering) in which poly-crystal deposition is performed at temperatures around 400℃ and single crystals at temperatures around 1000℃. It is known as epitaxial single crystal growth (CVD) (chemical vapor deposition; typically MOCVD, HVPE). Currently, due to the deposition (deposition, growth) process of the AlN piezoelectric thin film and the device design in consideration of such a deposition process, a single layer of a metal layer including an insulating layer (typically SiO ₂ ) and/or an electrode function on a high-resistivity Si deposition substrate sequentially or After forming a multi-layered thin film (typically Mo, Ti, Pt, W, Al), designing a device by forming a polycrystalline AlN deposition film at a temperature around 400℃, or by adding a subsequent heat treatment process if necessary to fabricate a designed device It is a situation. However, as will be described later in detail in FIG. 15, due to physical process limitations, the AlN piezoelectric thin film deposited by an optimized process on the insulating layer and/or the metal thin film at a temperature of around 400° C. is a textured poly-crystal microstructure ( Microstucture) is not superior in physical properties, including piezoelectric properties, compared to the high-purity epitaxial single crystal microstructured AlN piezoelectric thin film deposited at a high temperature of around 1000℃. They have limitations in terms of performance and application expansion. In other words, the crystal quality (crystallinity and polarity) of an AlN piezoelectric thin film and a device using the same in the prior art can be formed on a single or multilayer thin film of an insulating layer and/or a metal layer formed before AlN film formation, and the deposition film temperature and surface material state It is difficult to construct an AlN piezoelectric thin film from a high-purity single crystal material because it is limited to such physical factors. Several methods have been proposed to overcome these limitations and obtain a high-purity single crystal AlN piezoelectric thin film, and as an example, a single crystal having the same/similar crystal structure as an AlN material at a high temperature around 1000°C with a MOCVD device. Direct growth (growth) deposition on the epitaxial synthesis substrate (Sapphire, SiC) or directly on the silicon (Si) single crystal deposition substrate at the highest possible high temperature by a sputtering device, and then wafer bonding ( Methods of completing a device through an AlN piezoelectric thin film transfer technology to a device substrate through wafer-bonding and film-forming substrate lift-off have been proposed.

FIG. 1 is a diagram showing devices using a piezoelectric thin film presented in U.S. Patent Publication No. US2015-0033520, and FIG. 1(a) shows an example of an FBAR (Film Bulk Acoustic Resonator) 20, and FIG. 1(b) SMR (20'; Solidly Mounted Resonator) is shown. FBAR and SMR belong to BAW resonators. The FBAR 20 includes a pair of electrodes 22 and 24, a piezoelectric thin film 26 interposed between the pair of electrodes 22 and 24, and an element substrate 30. The pair of electrodes 22 and 24 and the piezoelectric thin film 26 are suspended on the cavity 28 formed in the device substrate 30. The SMR 20 ′ includes a pair of electrodes 22 ′ and 24 ′, a piezoelectric thin film 26 ′ disposed between the pair of electrodes 22 ′ and 24 ′, and an element substrate 30 ′. Unlike the FBAR 20, a Bragg reflector 27' having a multilayer structure is provided in place of the reflector of the cavity 28.

2 to 4 are diagrams showing an AlN piezoelectric thin film disclosed in US 2015-0033520 and a method of manufacturing a device using the same. First, a single crystal AlN piezoelectric thin film is grown on a sapphire (Al ₂ O ₃ ) deposition substrate. (Fig. 2(a)). At this time, unlike the conventional SiO ₂ film and Mo electrode formed on the Si deposition substrate, and then formed an AlN piezoelectric thin film through sputtering, which is PVD (Phisical Vapor Deposition), HVPE or CVD (Chemical Vapor Depostion) MOVCD is used. Thus, a high-quality, high-purity single crystal AlN piezoelectric thin film is formed. Next, a contact electrode is formed (Fig. 2(b). In the case of manufacturing SMR, a Bragg reflector (SiO ₂ /W) reflector is first formed on a separately provided semiconductor device substrate (Fig. 3(c))). The AlN piezoelectric thin film structure 40 and the Bragg reflector reflector structure 42 are wafer-bonded (Fig. 3(d). Next, the sapphire film is formed from the bonded structure 44 through a laser lift off (LLO)). Separate the substrate (Fig. 3(e)) Finally, an upper electrode is formed on the structure 46 from which the sapphire film-forming substrate is separated (Fig. 3(f)) In the case of manufacturing the FBAR, a semiconductor device provided separately first An air cavity is formed in the substrate (Fig. 4(c)) Next, the AlN piezoelectric thin film structure 40 and the cavity structure 52 are combined (Fig. 4(d). Next, the laser from the bonded structure 54) The sapphire deposition substrate is separated through lift-off (LLO) (Fig. 4(e)) Finally, an upper electrode is formed on the structure 56 from which the sapphire deposition substrate is separated (Fig. 4(f)).

Compared with the conventional polycrystalline AlN piezoelectric thin film deposited on a silicon oxide (SiO ₂ ) and/or metal (electrode) material through a sputtering device on top of a Si deposition substrate, MOCVD growth was deposited on a sapphire deposition substrate. The single crytalline AlN piezoelectric thin film significantly improves the performance and quality of the resonator. However, on the sapphire deposition substrate, a 6.2eV energy bandgap, that is, an AlN piezoelectric thin film having an optical property of a short wavelength of 200 nm when converted to a wavelength is directly grown, and then it is commercially available such as ArF (193 nm) & KrF (248 nm). Separation using the excimer laser light energy source is no easy task. The reason for this is that in order to separate the two material layers using a laser light energy source, it is achieved through a thermo-chemical decomposition reaction process through strong absorption of the laser light energy source at the interface and conversion to thermal energy. However, the process of separating a specific deposited thin film having a function from the deposition substrate through this mechanism is referred to as “laser lift off (LLO)”. The starting point of the laser lift-off (LLO) mechanism is that a sacrificial ayer made of an appropriate material capable of absorbing the laser light energy source and converting it into a thermal energy source must be present between the optically transparent deposition substrate and a specific deposited thin film. . The appropriate conditions for this sacrificial ayer material are optically transparent semiconductors having an energy band gap sufficiently larger than the wavelength of the laser incident upon irradiation through the rear surface of the optically transparent sapphire deposition substrate. It is absolutely necessary to have a material region having an amorphous or polycrystalline, or multi-layered microstructure capable of absorbing as much as possible, which is presented in US 2015-0033520. In the method, this point was overlooked and described.

5 is a view showing an example of a method of manufacturing an AlN piezoelectric thin film disclosed in US 2006-0145785 A, a sapphire deposition substrate 200, a buffer layer 210 grown on the sapphire deposition substrate 200; Example: GaN), an AlN piezoelectric thin film 220 formed on the buffer layer 210, and a bonding metal 230 (eg, Au) formed on the AlN piezoelectric thin film 220 are presented.

Gallium nitride (GaN) constituting the buffer layer 210 is a material having an energy band gap of 3.4 eV (364 nm at the time of wavelength conversion) and at the same time has an amorphous microstucture formed by low temperature growth, compared to AlN. The GaN buffer layer 210 can sufficiently serve as a sacrificial layer and thus has the advantage of facilitating separation of the optically transparent sapphire deposition substrate 200 from the AlN piezoelectric thin film 220, but the GaN buffer layer ( 210) and AlN piezoelectric thin film 220, there is a significant difference in physical properties of lattice constant and thermal expansion coefficient, so high purity single crystal grown by MOCVD with a certain critical thickness (about 100 nm) or more that can be used as a functional piezoelectric thin film such as a resonator Securing the AlN piezoelectric thin film 220 is by no means easy with known processes and techniques.

15 is a view showing an example of a method of manufacturing an AlN piezoelectric thin film presented in Solid-State Electronics 54 (2010) 1041-1046, the manufacturing method as shown in FIG. 15 (a), (001) silicon film formation Forming an AlN piezoelectric thin film 62 directly sputtered on the substrate 61, forming a lower electrode 63 on the AlN piezoelectric thin film 62, as shown in FIG. 15(b), and As shown in 15(c), forming an acoustic wave mirror 64 formed on the lower electrode 63, as shown in FIG. 15(d), the wafer on the acoustic wave mirror 64 Forming a bonded carrier wafer 65, as shown in FIG. 15(e), removing the (100) silicon film-forming substrate 61 by wet etching, and FIG. 15(f) As shown in FIG. 6, the method includes forming an upper electrode 66 on the AlN piezoelectric thin film 62 from which the (100) silicon deposition substrate 61 has been removed, and the SMR BAW structure resonator is manufactured through this. According to this method, SiO ₂ and/or a metal (electrode) is formed on a silicon deposition substrate, and then an AlN piezoelectric thin film is formed (eg, “Optimization of sputter deposition Process for piezoelectric AlN ultra-thin Films”, Semester Project, Advanced NEMS group, Autumn Semester 2017, Roman Welz, January 23, 2018, SECTION MICROTECHNIQUE), a separate additional process (CMP; chemical-mechanical polishing) for quality improvement is unnecessary and has a uniform thickness. It is possible to obtain a piezoelectric thin film and at the same time, it has the advantage of excluding the native oxide formed on the surface of the electrode (metal), which has a great influence on the quality of the piezoelectric thin film, thus securing an advantage in terms of quality and cost compared to the conventional manufacturing process. It is pointed out that you can.

In addition, there is a method of growing a high-purity AlN piezoelectric thin film on a SiC film-forming substrate, but the SiC film-forming substrate is expensive, and after growing a high-purity AlN thin film on the SiC film-forming substrate, the SiC film is formed through chemical wet etching in the known AlN piezoelectric thin film resonator manufacturing process. Since the substrate is removed, it is not possible to reuse the AlN piezoelectric thin film resonator because it cannot solve the high cost and cost problem.

In order to form (deposition, grow) a high-purity AlN piezoelectric thin film having a melting point (Tm) of 2200℃ in general, “Thornton's Theory for the Adatom Surface Mobility” established by Thornton Therefore, the process must be carried out at the surface temperature of the film formation substrate at least 0.3Tm (660℃ in case of AlN) during film formation, so that the material diffusion of adsorption atoms starts from the surface of the film formation substrate, and the close packing ratio of the film formation material layer is single crystal. By reaching the single crystal bulk level, it is possible to form c-oriented textured polycrystals arranged in a vertical direction on the surface of the film-forming substrate, and by further increasing the surface temperature of the film-forming substrate, 0.5Tm (for AlN) 1100℃) or higher, a pseudomorphic mosaic structured single crystal can be formed to obtain a high purity thin film. More preferably, when the surface temperature of the deposition substrate is increased, the surface formed through acceleration of plasma particles (protons, electrons, neutrons) than a method of heating with a heater at the back plane of the deposition substrate It is advantageous to obtain a high-purity thin film to increase the surface temperature by directly applying a bombardment to it. In addition, to form (deposit, grow) a high-purity AlN piezoelectric thin film having a hexagonal (HCP) crystal structure, Group III Nitrides (AlN, GaN, AlGaN, AlInN, InGaN) and Group 2 oxides having the same crystal structure (Group II Oxidex; ZnO, MgO, MgZnO), or a sapphire and silicon carbide (SiC) material surface having a similar crystal structure is preferred to be selected first, and at the same time, a metal having a large surface roughness ( Electrodes; Ceramic (SiO ₂ , SiN _x ) or semiconductor (Si) materials with relatively smaller surface roughness than Mo, W, Ti, Al) materials are advantageous in securing a much higher purity AlN piezoelectric thin film from the viewpoint of adsorption atom surface mobility Do. In addition to the above conditions, favorable conditions for depositing (depositing, growing) a high-purity AlN piezoelectric thin film include minimizing the amount of oxygen (O ₂ ) inflow from the surroundings including the deposition substrate, and completely eliminating hydrogen, hydrogen compounds, and other contaminants on the surface of the deposition substrate Removal is the best condition.

In the literature (Physics Letter A 375 (2011) 1000-1004, “Single-crystalline AlN growth on sapphire using physical vapor deposition”, Andres M. Cardenas-Valencia, Shinzo Onishi, Benjamin Rossie), a magnetron sputtering gun on a sapphire deposition substrate (a magnetron sputtering gun), the temperature of the sapphire film-forming substrate was set to 860°C and deposited directly to obtain a single crystal AlN piezoelectric thin film having a thickness of 4 μm. Typically, when evaluating the quality of an AlN piezoelectric thin film, both crystallinity and polarity are evaluated at the same time, and the crystalline quality measurement evaluation index is the half width (FWHM) in the non-destructive X-ray rocking curve. Compared to the current commercial structure (Si film-forming substrate/SiO ₂ /metal electrode/AlN), the half-width value of 1.2-2.5°, the cited document has a half-value width of 0.32°, indicating that the crystallinity quality has improved considerably. Show. In other words, according to the theory of adsorption atom surface mobility established by Thornton, the deposition substrate temperature and material crystal structure during specific thin film deposition (deposition, growth) prior to the importance of the deposition (deposition, growth) method (CVD or PVD). , And it was found that the surface condition was a significant influence factor. However, the polar quality cannot be determined from the half-width value of the X-ray rocking curve. For reference, although the polarity quality was not evaluated in the cited literature, the polar quality evaluation can be confirmed through surface wet etching. The main factor affecting the polar quality is film formation ( Evaporation, growth) method, film formation substrate material, and surface state.

This will be described later in the'Specific Contents for the Implementation of the Invention'.

Here, a summary of the present disclosure is provided, and this section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features).

According to one aspect of the present disclosure, in a method of manufacturing a high _- purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, a sacrificial layer is formed on a sapphire deposition substrate. Forming; And, growing a single crystal Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the sacrificial layer; Including, and growing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film Prior to the step, forming a first semiconductor layer of Al _y Ga _1-y N (0.5≤y≤1); high purity Al _x Ga _1-x N (0.5≤x≤1), characterized in that it further comprises ) A method of manufacturing a piezoelectric thin film is provided.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in the structure including the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film, Al _x Ga _1-x N (0.5≦x≦1) piezoelectric thin film; A first electrode provided on one side of the Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film; Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) A second electrode and a reflector provided on opposite sides of the first electrode based on the piezoelectric thin film; including, Al _x Ga _1-x N having the first electrode (0.5≤x≤1) Al _x Ga _1-x N (0.5≤x≤1), characterized in that the surface of the piezoelectric thin film is a metallic polarity (Al-polarity or Al-polarity & Ga-polarity mixed) surface. ) A structure including a piezoelectric thin film is provided.

According to another aspect of the present disclosure, in the method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, a sacrificial layer is formed on a sapphire deposition substrate. Forming; As, the sacrificial layer is made of one of oxides including a group 3 nitride formed by a chemical vapor deposition method (CVD; Chemical Vapor Deposition) and a group 2 or 3 oxide formed by a physical vapor deposition method (PVD; , Forming a sacrificial layer; And, depositing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the sacrificial layer; As Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film is 0.3Tm (Tm; piezoelectric A method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film comprising; depositing a piezoelectric thin film deposited by physical vapor deposition at a temperature equal to or higher than the melting point of the thin film material) Is provided.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in the method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, a chemical vapor deposition method on a silicon film forming substrate Forming a stress control layer made of a group III nitride by (CVD; Chemical Vapor Deposition); And, forming an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the stress control layer by a physical vapor deposition method at a temperature of 0.3Tm (Tm; melting point of the piezoelectric thin film material) or higher; A method of manufacturing an Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film is provided.

According to another aspect according to the present disclosure (According to another aspect of the present disclosure), in the method of manufacturing a piezoelectric thin film device Al _x Ga _1-x N (0.5≤x≤1), Al _x Ga _1-x Bonding the device substrate to the N (0.5≦x≦1) piezoelectric thin film; Removing the film-forming substrate; And forming an electrode on the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film from the side from which the film-forming substrate is removed; including, the Al _x Ga _1-x N (0.5 ≤ _x ≤ 1) A method of manufacturing an Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film device, characterized in that the surface of the piezoelectric thin film has a metallic polarity, is provided.

This will be described later in the'Specific Contents for the Implementation of the Invention'.

1 is a diagram showing devices using a piezoelectric thin film disclosed in US 2015-0033520,
2 to 4 are diagrams showing an AlN piezoelectric thin film disclosed in U.S. Patent Publication No. US2015-0033520 and a method of manufacturing a device using the same,
5 is a view showing an example of a method of manufacturing an AlN piezoelectric thin film disclosed in US 2006-0145785 A,
Figure 6 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure A drawing showing an example,
7 is of _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure A drawing showing another example,
Figure 8 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure A drawing showing another example,
9 is of _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the teachings of this A drawing showing another example,
10 to 12 are diagrams illustrating an example of a method of manufacturing a resonator using the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure;
13 and 14 are views showing another example of a method of manufacturing a resonator using the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure;
15 is a view showing an example of a method of manufacturing an AlN piezoelectric thin film presented in Solid-State Electronics 54 (2010) 1041-1046,
Figure 16 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure A drawing showing another example,
Figure 17 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure A drawing showing another example,
Figure 18 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure A drawing showing another example,
19 is of _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the teachings of this A drawing showing another example,
Figure 20 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure A drawing showing another example,
Figure 21 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure A drawing showing another example,
22 and 23 are views showing another example of a method of manufacturing a resonator using the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure.

Hereinafter, the present disclosure will now be described in detail with reference to the accompanying drawing(s)).

Figure 6 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure As a diagram showing an example, the structure includes a sapphire deposition substrate 1, a first semiconductor layer 2, a sacrificial layer 3, and an Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 Include.

7 is of _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure As a diagram showing another example, the structure is a sapphire film formation substrate 1, a first semiconductor layer 2, a sacrificial layer 3, and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4) And a second semiconductor layer 5 between the sacrificial layer 3 and the Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4.

Figure 8 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure As a diagram showing another example, the structure is a sapphire film formation substrate 1, a first semiconductor layer 2, a sacrificial layer 3, and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4) However, the order of formation of the first semiconductor layer 2 and the sacrificial layer 3 is changed from that of the structure shown in FIG. 6.

9 is of _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the teachings of this As a diagram showing another example, the structure is a sapphire film formation substrate 1, a first semiconductor layer 2, a sacrificial layer 3, Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4) In addition, although the second semiconductor layer 5 is included, the order of formation of the first semiconductor layer 2 and the sacrificial layer 3 is changed from that of the structure shown in FIG. 7.

For example, a C-plane (0002) sapphire deposition substrate may be used, and a group III nitride formed thereon may be polarity (metallic or gas) surface or semi-polarity (metallic) depending on the growth pretreatment conditions. If it is possible to have a surface (mixed of polarity and nitrogen gas polarity), it is possible to consider using a sapphire deposition substrate that is off the C-plane or is not the C-plane. In addition to the flat substrate, it is possible to consider the use of a nano-sized PSS (Patterned Sapphire Substrate).

In the examples shown in FIGS. 6 and 7, the first semiconductor layer 2 is made of Al _y Ga _1-y N (0.5 ≤ _y ≤ ₁ ) grown and deposited at a high temperature (1000° C. or higher) rather than a low temperature, and subsequently It serves to ensure the crystal quality (crystallinity and polarity) of the grown Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4. Therefore, it is distinguished from a layer called a conventional buffer layer that is grown and deposited at a temperature lower than the appropriate growth temperature. The first semiconductor layer 2 may be grown by CVD (eg, MOCVD, HVPE, ALD). _{Al y Ga 1-y N (} 0.5≤y≤1) a first upper and lower limits of the semiconductor layer 2 in the thickness is not particularly limited, and preferably _{Al x Ga 1-x N (} 0.5≤x≤1 ) The piezoelectric thin film 4 is set to 100 nm-20 μm to be advantageous in functioning a stress control function for maintaining the thickness uniformity of the piezoelectric thin film 4. For example, it can be grown and deposited at a temperature of 1000-1400℃ and a pressure of 100-200torr, and an atmosphere consisting of ammonia (NH ₃ ) and nitrogen (N ₂ ) containing a large amount of hydrogen (H ₂ ) (relatively N ₂ NH ₃ content is greater than) or ammonia (NH ₃₎ and nitrogen (in N ₂₎ consisting of an atmosphere, in the case of AlN, if the 100% Al configuration, Al-rich AlGaN, Al / (Al + Ga) When the value is 50% or more, growth film formation can be performed. Preferably, as a pretreatment, before the growth of the first semiconductor layer 2 of Al _y Ga _1-y N (0.5≤y≤1) at the appropriate growth temperature, Al MOCVD source gas (e.g. : Pretreatment inside the chamber with TMAl) and forming an AlN buffer layer with a thickness of 20 nm or less, and then, growth is formed under appropriate growth conditions of 1000-1400°C and 100-200 torr, securing high quality crystallinity and reducing dislocation density (reduction in A first semiconductor layer made of Al _y Ga _1-y N (0.5≤y≤1) with the adjacent region of the sapphire deposition substrate 1 intentionally for dislocation density), crack generation & propagation suppression (suppression of generation & propagation) (2) It is advantageous to form a number of air-voids inside.

In the examples shown in FIGS. 8 and 9, the first semiconductor layer 2 is preferably made of 100 nm or less of Al _y Ga _1-y N (0.5 ≤ _y ≤ ₁ ), and is subsequently grown and formed with Al _x Ga _{1 -x} N (0.5≤x≤1) serves to ensure the crystallinity and polarity of the piezoelectric thin film 4. The first semiconductor layer 2 may be deposited by PVD (eg, sputtering, PLD), and at this time, supply of oxygen in a certain amount (eg, O ₂ /(N ₂ +O ₂ ) is 3% or less) is important. , Serves as a nano-scale AlN or Al-rich AlGaN seed. In an atmosphere containing a small amount of _{O 2 Al y Ga 1-y} N (0.5≤y≤1) sputtering deposition is a relatively small island (smaller islands) the shape of the _{Al y Ga 1-y N (} 0.5≤y≤1 of ) to form a crystalline CVD (at the appropriate growth temperature for example: MOCVD, HVPE, ALD) to improve the surface flatness of the grown _{Al x Ga 1-x N (} 0.5≤x≤1 deposition), the piezoelectric thin film 4 and also the thin film inside It plays an important role in securing high quality crystallinity and polarity by reducing the dislocation density of. The thickness of the first semiconductor layer 2 is preferably 100 nm or less, and more preferably ₁ nm, which is more advantageous in suppressing crack generation and propagation of the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4- It is set to 30 nm. For example, a temperature and pressure of 300-500℃ can be deposited at a pressure of 5*10 ^-3 mbar, and an atmosphere consisting of nitrogen (N ₂ ) and oxygen (O ₂ ) containing a large amount of argon (Ar) (Relatively, the content of N ₂ is much higher than that of O ₂ ; Ar 40 sccm, N2 110 sccm, O2 4 sccm) can be used. The quality of the grown Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 was examined through the X-ray (0002) rocking curve, which is one of the measurement indicators of quality, and 0.04- It showed a value of 0.06°. This shows that the quality of the thin film is considerably improved compared to the value of 1.2-2.5°, which is the value of the current commercial structure (Si film formation substrate/SiO ₂ /metal electrode/AlN).

The first semiconductor layer 2 shown in FIGS. 6 and 7 and the first semiconductor layer 2 shown in FIGS. 8 and 9 are made of Al _y Ga _1-y N (0.5≦ _y ≦ ₁ ), and subsequently grown It is common in that it serves to ensure the crystallinity and polarity of the Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4 to be formed.

The sacrificial layer 3 is formed of a sapphire layer prior to forming the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 to facilitate separation of the sapphire deposition substrate 1 during laser lift off (LLO). It is an optically transparent semiconductor having an energy band gap of sufficiently larger than the wavelength of the laser irradiated through the back side of the film forming substrate 1, and can absorb as much light energy source as possible, amorphous or polycrystalline. polycrystalline), or a material region having a multi-layered microstructure is preferred, for example, a multi-layered Al _x1 Ga _1-x1 N/Al _x2 Ga _1-x2 N (x ₂ <x ₁ ≤1, 0≤x ₂ <0.5), a single layer of Ga-rich AlGaN (Ga/(Ga+Al) value of 50% or more) and GaN. The sacrificial layer 3 can be grown and deposited by CVD (e.g., MOCVD, HVPE, ALD), and absorbs the energy of the laser when the laser is lifted off, so that the sapphire deposition substrate 1 side and Al _x Ga _1-x N ( 0.5≤x≤1) serves to separate the piezoelectric thin film (4) side. In general, the Al _z Ga _1-z N energy bandgap, E(z)=3.43+1.44z+1.33z ² (eV) derived from theory and experimentation, if Al _0.5 Ga _0.5 N with 50% Al composition It has an energy bandgap of 4.48eV. An equation for converting the energy bandgap (eV) value of a semiconductor (including an insulator) into a wavelength, which is an optical characteristic, is λ(nm) = 1240/E(z), and wavelength conversion through this equation yields a 277nm value. Therefore, a single layer of Al _z Ga _1-z N and GaN material having an Al composition of less than 50%, or a sacrificial layer 3 made of a multi-layered microstructure composed of these, is formed through a relatively generalized high-power short-wavelength laser light source (more than 248 nm). It is easy to remove. The thickness of the sacrificial layer 3 may be, for example, 100 nm or less, preferably ₁ nm-30 nm, which is more advantageous in suppressing crack generation and propagation of the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 To In the case of Al _z Ga _1-z N having an Al composition of less than 50%, it is possible to grow in 900-1200°C and 100-200 torr conditions, and in the case of GaN, it is possible to grow in 600-1100°C and 100-200 torr conditions. A sputtered AlN thin film that serves as a seed before growing the Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4 after the sacrificial layer 3 is grown on the sapphire deposition substrate 1 As a pretreatment for sputtering, the surface of the sacrificial layer (3) is stabilized through a small amount of Ar (planarization and cleaning through surface etching) and a large amount of nitrogen (N ₂ ) gas containing a trace amount of oxygen (O ₂ ). It includes the step of making. The Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4 may be grown by CVD (eg, MOCVD, HVPE, ALD), and grown into a single crystal thin film. The thickness may vary depending on the final device. For example, when used for the FBAR shown in Fig. 1(b), the thickness of the electrodes 22'24' formed on both sides and the resonance frequency The thickness is determined. Al _x Ga _1-x N (0.5≤x≤1) The case where the piezoelectric thin film 4 contains Ga can be considered, and accordingly, the first semiconductor layer 2, the sacrificial layer 3, and the second semiconductor layer The Ga composition of (5) may vary.

The second semiconductor layer 5 shown in FIG. 7 is, for example, by CVD (for example, MOCVD, HVPE, ALD) before the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is formed. A single layer of Al _a Ga _1-a N (0.5 <a ≤ 1) or Al _b1 Ga _1-b1 N/Al _b2 Ga _1-b2 N (b ₁ ≠ b ₂ ) It consists of a multi-layer structure (preferably 50% or more of Al as the whole multi-layer structure), but the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film as the whole has a higher Al content than the sacrificial layer 3 It serves to resolve the stress difference between (4) and the sacrificial layer 3 having a high Ga content. The second semiconductor layer 5 may have an upward gradation structure in which the Al content increases from the sacrificial layer 3 toward the Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4. Yes, of course. In the case of the example shown in FIG. 9, the first semiconductor layer 2 is located between the second semiconductor layer 5 and the sacrificial layer 3, but the thickness of the first semiconductor layer 2 is not thick, As in the example, by providing the second semiconductor layer 5, the stress between the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 and the sacrificial layer 3 having a high Ga content ) It serves to dissolve the car. In addition, the second semiconductor layer 5 plays an important role in determining the overall thickness uniformity of the wafer when the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 is grown and formed. A process of adding Si or/and Mg dopants can be added to control wafer strain. The thickness of the second semiconductor layer 5 may be, for example, 100 nm or less, preferably Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ), which is more advantageous in suppressing crack generation and propagation of the piezoelectric thin film 4 1nm-30nm.

10 to 12 are diagrams showing an example of a method of manufacturing a resonator using the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film presented in the present disclosure. Here, the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film presented in the present disclosure is applied to the resonator, but the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film is applied to the sapphire film formation substrate. It goes without saying that any device or device that can use the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film after removal of is not limited. Of course, the method shown in FIGS. 3 and 4 may be used, and of course, it may also be applied to a SAW resonator other than a BAW resonator. Hereinafter, it will be described with the structure shown in FIG. 6. As shown in FIG. 10, first, an Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 having a metallic polarity (Al-polarity or Al-polarity & Ga-polarity mixed) surface. ) On the first electrode 6 (eg: Mo, W, Ta, Pt, Ir, Ru, Rh, Re, Au, Cu, Al, Invar, or alloys thereof). Next, the first protective film 7 on the first electrode 6; e.g., Mo, W, Ta, Pt, Ti, TiW, TaN, TiN, SiO ₂ , Al ₂ O ₃ , SiC, SiCN, SiN _x , AlN , Polyimide, BCB, SU-8, SOG, etc.). Next, a first bonding layer 8 (eg: SnIn, AuSn, AgIn, PdIn, NiSn, CuSn, Cu to Cu, Au to Au, Epoxy, SU-8, BCB) is formed on the first passivation layer 7 . A temporary substrate 9 (eg, sapphire, AlN, Glass) is wafer-bonded to the first bonding layer 8. Next, the sapphire film-forming substrate 1 is separated through laser lift-off (LLO). In this process, a process of removing metallic droplets, a trimming process for accurate thickness adjustment, etc. may be involved. Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4) after separation of the sapphire film formation substrate (1), removal of metal droplets, and trimming processes is a surface with nitrogen gas polarity (N-polarity) (face). Next, as shown in Fig. 11, the second electrode 14 on the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4; e.g., Mo, W, Ta, Pt, Ir, Ru, Rh, Re, Au, Cu, Al, Invar, these alloys) and a multilayered Bragg reflector 10 (eg, SiO ₂ /W) reflector is formed. Preferably, after the second electrode 14 and the Bragg reflector 10 reflector deposition process, a second protective film 11 on the reflector of the Bragg reflector 10; e.g.: Mo, W, Ta, Pt, Ti, TiW, TaN, TiN, SiO ₂ , Al ₂ O ₃ , SiC, SiCN, SiN _x , AlN, Polyimide, BCB, SU-8, SOG, etc.) are formed. Next, a second bonding layer 12 (e.g., SnIn, AuSn, AgIn, PdIn, NiSn, CuSn, Cu to Cu, Au to Au, Epoxy, SU-8, BCB, etc.) is formed on the second passivation layer 11 . Subsequently, as shown in FIG. 12, the device substrate 13 (e.g., Si, GaAs, AlN, Mo, Cu, W, MoCu, CuW, Invar, Laminate) is bonded to the second bonding layer 12 and uthetic bonding, Wafer bonding is performed by a method such as brazing. Although not shown, prior to wafer bonding, an electrical insulator material layer (protective layer) and a wafer bonding layer are sequentially formed on the device substrate 13. Finally, the temporary substrate 9 is separated and removed through thermal processing, laser irradiation, and supply of a chemical and physical energy source, and then the first bonding layer 8 and the first protective film 7 are removed. The same can be applied to the examples shown in FIGS. 7 to 9. At this time, the second semiconductor layer 5 is also removed. By using two wafer bonding processes, the metallic polarity (Al-polarity or Al-polarity & Ga-polarity mixed) surface of the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 It can be used as an upper surface of a device, and through this, it has an advantage in terms of post-processing and quality of the final device by having a surface chemically and structurally stable surface such as corrosion resistance.

13 and 14 are views showing another example of a method of manufacturing a resonator using the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film presented in the present disclosure, and FIGS. 10 to 14 Unlike the method presented in 12, a temporary substrate 9 is not used. First, as shown in FIG. 13, a second electrode 14 (eg: Mo, W, Ta, Pt, Ir, Ru, Rh, Re, Au, Cu, Al, Invar, or an alloy thereof) and a multilayer structure The Bragg reflector 10 of the reflector, the second protective film 11, and the second bonding layer 12 are formed, and then the device substrate 13 is wafer-bonded, and then the sapphire deposition substrate 1 is removed. Finally, as shown in FIG. 14, the first electrode 6 is formed.

The difference between the method shown in FIGS. 10 to 12 and the resonator element manufactured by the method shown in FIGS. 13 and 14 depends on the position where the second electrode 14 including the Bragg reflector 10 and the reflector is formed and the number of wafer bonding. Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) The surface polarity of the piezoelectric thin film 4 is determined. The method shown in FIGS. 10 to 12 is fabricated through two wafer bonding processes, and the Bragg reflector 10 and the second electrode 14 including the reflector are Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric In the case of the method shown in Figs. 13 to 14, which is placed on the N-polarity face of the thin film 4, while undergoing a single wafer bonding process, a Bragg reflector 10 and a second electrode 14 including a reflector It is located on the metallic polarity surface (Al-polarity or Al-polarity & Ga-polarity mixed face) of the Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4. For reference, in the case of a resonator device made of a polycrystalline AlN piezoelectric thin film formed through sputtering on a conventional Si deposition substrate, there is a limit to controlling the surface polarity and polarity ratio. 2 The polarity position of the electrode 14 cannot be defined.

Figure 16 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure As a figure showing another example, the structure includes a sapphire film formation substrate 1, a sacrificial layer 23a, and an Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4. The sacrificial layer 23a is a single layer of Al _c Ga _1-c N (0 ≤ _c ≤ 0.5) grown by CVD (MOCVD, ALD, MBE, etc.) or a multilayer Al _c1 Ga _1-c1 N/Al _c2 Ga _{1 -c2} N (c ₂ <c ₁ ≤1, 0≤c ₂ <0.5) may be made of a group III nitride. Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is deposited on the sacrificial layer 23a with PVD (eg, sputtering, PLD) at a temperature of 0.3Tm or more (melting point of the piezoelectric thin film material) And high quality is ensured.

Figure 17 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure As a diagram showing another example, the structure is a sacrificial layer 23a, a second semiconductor layer 5, and an Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film sequentially on the sapphire deposition substrate 1 It includes (4). It is distinguished from the structure shown in FIG. 16 in that a second semiconductor layer 5 is added, and the second semiconductor layer 5 functions like the second semiconductor layer 5 shown in FIG. 7, and the sacrificial layer 23a ), it is grown by CVD, but is made of group III nitride having _a different composition (Al _a Ga _1-a N (0.5<a≤1)), and has a uniform thickness by controlling the stress Al _x Ga _1-x N (0.5≤x≤1) It serves to promote to secure the piezoelectric thin film (4).

Figure 18 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure As a view showing another example, the structure includes a sapphire film formation substrate 1, a sacrificial layer 23b, and an Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4. The sacrificial layer 23b is a single layer of ZnO, ITO, or a multi-layered oxide structure including at least one of them (ZnO/ITO, ZnO/SiO ₂ , ITO/SiO ₂ ) deposited by PVD (e.g., L sputtering, PLD) ) It is distinguished from the structure shown in Fig. 16 in that it is made of oxide. Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is deposited on the sacrificial layer 23b with PVD (eg sputtering, PLD, etc.) at a temperature of 0.3Tm or more (melting point of the piezoelectric thin film material) The film is formed to ensure high quality.

19 is of _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the teachings of this As a view showing another example, the structure is a sacrificial layer 23b, an oxygen (O ₂ ) inflow prevention layer (O), and Al _x Ga _1-x N (0.5 ≤ _x ≤ 1) sequentially on the sapphire deposition substrate 1 ) Includes a piezoelectric thin film (4). It is distinguished from the structure shown in FIG. 18 in that an oxygen (O ₂ ) inflow prevention layer (O) is added, and the oxygen (O ₂ ) inflow prevention layer (O) is made of AlN or an AlNO material containing a small amount of oxygen on the sacrificial layer 23b. The Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 that is deposited by deposition and subsequently deposited is formed of the same PVD (e.g. L sputtering, PLD) to prevent oxygen inflow from the sacrificial layer 23b. It serves to promote the high purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 to be secured.

In the examples shown in FIGS. 16 and 17, the sacrificial layer 23a is a single layer of Al _c Ga _1-c N formed by single crystal growth by CVD (MOCVD, HVPE, ALD, MBE) at a high temperature (900°C or higher) rather than a low temperature. (0≤c≤0.5) or multi-layer Al _c1 Ga _1-c1 N/Al _c2 Ga _1-c2 N (c ₂ <c ₁ ≤1, 0≤c ₂ <0.5), , The crystal quality (crystallinity and polarity of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4) subsequently deposited by PVD (e.g., sputtering, PLD) at a temperature of 0.3Tm (660℃) or higher. ) To guarantee. Therefore, the sacrificial layer 23a is distinguished from a layer called a conventional buffer layer grown at a temperature lower than an appropriate growth temperature, and serves as the first semiconductor layer 2 and the sacrificial layer 3 shown in FIGS. 6 to 9. It differs in that it performs at the same time. The upper and lower limits of the thickness of the sacrificial layer 23a are not particularly limited, but preferably, stress for maintaining the thickness uniformity of the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 It is set to 50nm-3㎛ to be advantageous for stress control function. For example, it can be grown at a temperature of 900-1100°C and a pressure of 100-600torr. More preferably, as in the example shown in FIG. 17, the sacrificial layer 23a and the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 are positioned between the Al _x Ga _{1 -x} N (0.5≦ _x ≦1) A second semiconductor layer 5 is provided to improve crystallinity and thickness uniformity of the piezoelectric thin film 4. The second semiconductor layer 5 is formed by single crystal growth by the same CVD (MOCVD, HVPE, ALD, MBE, etc.) as the sacrificial layer 23a, in which case Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film ( It is preferable to consist of a group III nitride having the same or similar composition as 4). In addition, the sacrificial layer 23a and the second semiconductor layer 5 have high quality (crystallinity and polarity) and uniform thickness when forming an Al _y Ga _1-y N (0.5 ≤ _y ≤ ₁ ) piezoelectric thin film 4 It is preferable to control the film-forming substrate to maintain a zero (flat) state as possible.

In the examples shown in FIGS. 18 and 19, the sacrificial layer 23b is a single layer of ZnO formed by a deposition film having crystalline (polycrystalline or single crystal) with PVD (eg, sputtering, PLD) at a high temperature (400°C or higher) rather than a low temperature. And ITO, or a multilayer oxide structure including at least one of them (ZnO/ITO, ZnO/SiO ₂ , ITO/SiO ₂ ). The upper and lower limits of the thickness of the monolayer sacrificial layer 23b are not particularly limited, but preferably Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) to maintain the thickness uniformity of the piezoelectric thin film 4 It is set to 50nm-3㎛ to be advantageous for the stress control function. The sacrificial layer 23b may be deposited by PVD (e.g., sputtering, PLD), the deposition substrate temperature at the time of deposition is 750°C, the process pressure consisting of argon (Ar) and oxygen (O ₂ ) gas is 10-20 mTorr, and , It is preferable that the amount of oxygen is relatively small compared to argon and is composed of at least 50%. More preferably, as in the example shown in FIG. 19, the sacrificial layer 23b and the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 are positioned between the Al _x Ga _{1 -x} N (0.5≤x≤1) In order to improve the crystallinity and thickness uniformity of the piezoelectric thin film 4, an oxygen (O ₂ ) inflow prevention layer (O) is provided. The oxygen (O ₂ ) inflow prevention layer (O) is formed by deposition on the sacrificial layer 23b of AlN or AlNO material containing a minute amount of oxygen, and is subsequently deposited by Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric. High purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is formed by depositing and forming the same PVD (e.g., sputtering, PLD) as the thin film 4 to prevent oxygen inflow from the sacrificial layer 23b. It plays a role in facilitating the acquisition. In particular, when AlNO (Al _y Ga _1-y N (0.5≤y≤1) sputter deposition in an atmosphere containing a small amount of O ₂ ) is applied as the oxygen (O ₂ ) inflow prevention layer (O), a certain amount (e.g. O ₂ / (N ₂ +O ₂ ) value is less than 3%) oxygen supply is important, and serves as a seed to secure the high purity Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 . The sputter deposition of Al _y Ga _1-y N (0.5≤y≤1) in an atmosphere containing a small amount of O ₂ is relatively small islands of Al _y Ga _1-y N (0.5≤y≤1). Forming crystals and improving the surface flatness of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 deposited by PVD (e.g., sputtering, PLD) at the appropriate deposition temperature It plays an important role in securing high quality crystallinity and polarity through reduction of dislocation density. The thickness of the oxygen inflow prevention layer (O) composed of AlN or AlNO is preferably 100 nm or less, more preferably Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) to suppress the crack generation and propagation of the piezoelectric thin film 4 The more advantageous 1nm-30nm. For example, a temperature and pressure of 300-500° C. can be deposited at a pressure of 5*10 ^-3 mbar.

The crystalline quality of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 structure manufactured according to the method shown in FIGS. 16 to 19 is the half width of the X-ray rocking curve in common It aims to have this small value (target value: 0.1° or less), and with respect to polar quality, in the case of FIGS. 16 and 17, the sacrificial layer 23a and the second semiconductor layer 5, FIG. In the cases 18 and 19, there is an advantage that the sacrificial layer 23b and the oxygen inflow prevention layer O can be freely adjusted according to the surface conditions.

It goes without saying that the method of manufacturing the resonator in FIGS. 10 to 14 may be applied as it is to the structures shown in FIGS. 16 to 19.

16 to 19, the sacrificial layers 23a and 23b are formed on the optically transparent film-forming substrate 1 through the ① Laser Lift-Off (LLO) process. Al _x Ga _1-x N (0.5≤x≤1) ) It is located between the film-forming substrate 1 and the high-purity piezoelectric thin film 4 to separate the piezoelectric thin film 4, ② has an energy band gap (generally 200 nm or more) to function as a sacrificial layer for the laser, ③ It can be composed of Group 3 nitride formed by CVD, Group 2 or Group 3 oxide formed by PVD (eg ZnO, In ₂ O ₃ , Ga ₂ O ₃ , ITO), and ④ Al _x Ga _1-x N (0.5≤ x≤1) In order to be able to form a piezoelectric thin film at high temperature, it should be a material that has thermal stability above 0.3Tm (660℃), and ⑤ Al _x Ga _1-x N (0.5≤) having a hexagonal (HCP) crystal structure. x≤1) It is a material having the same or similar crystal structure as the piezoelectric thin film 4, and ⑥ Al _x Ga _1-x N (0.5≤x≤1) surface roughness so that the piezoelectric thin film 4 can be formed. ) Is a ceramic (nitride, oxide) material capable of 10 nm or less, and ⑦ Al _x Ga _1-x N (0.5≤x≤1) The surface state in which various contaminants are removed so that the piezoelectric thin film 4 can be formed It is preferably a material of.

The sacrificial layer 23a may be grown as a high-temperature single crystal layer (single layer or multi-layer structure) having a structure including a buffer layer grown at a conventional low temperature.

If necessary, sacrificial layers (23a, 23b) to secure a single crystal piezoelectric thin film having a tilted c-axis crystal plane before the Al _x Ga _1-x N (0.5≤x≤1) pressure-welded thin film (4) It is also possible to perform photo-lithographic etch patterning on the surface.

After deposition of the Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4, crystallinity and polarity may be improved through post-annealing, which is an additional ON-follow-up heat treatment process.

As described above, when an Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 having a uniform thickness is particularly required, Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) The structure shown in Fig. 16 (sapphire deposition substrate 1)-sacrificial layer 23a) placed under the piezoelectric thin film 4, and the structure shown in Fig. 17 (sapphire deposition substrate 1)-sacrificial layer 23a-second semiconductor Layer 5), the structure shown in FIG. 18 (sapphire deposition substrate 1-sacrificial layer 23b) and the structure shown in FIG. 19 (sapphire deposition substrate 1)-sacrificial layer 23b-oxygen (O ₂ ) It is important that the inflow prevention layer O) maintains the flatness as possible at the deposition temperature of the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4, and the present disclosure demonstrates such flatness. It provides a sustainable foundation. For example, the sapphire film-forming substrate 1 having the sacrificial layer 23a grown by CVD has a convex shape at room temperature, but when the temperature is raised again for PVD deposition film formation, It has a concave shape down through the state. This behavior is affected by the difference in the coefficient of thermal expansion between the sapphire deposition substrate 1 and the sacrificial layer 23a, and therefore, Al _x Ga _1-x N ( 0.5≦x≦1) The piezoelectric thin film 4 can be deposited. This principle can be applied as it is to the design of the second semiconductor layer 5, the design of the sacrificial layer 23b, and the design of the oxygen (O ₂ ) inflow prevention layer (O).

Figure 20 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure As a view showing another example, the structure includes a silicon film forming substrate 1, a stress control layer 23c, and an Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4.

Compared with the structure shown in FIG. 16, the stress control layer 23c is grown by CVD like the sacrificial layer 23a, and the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 is PVD. It is the same in that it is deposited by evaporation, but silicon is used as the deposition substrate 1, not sapphire, and the stress control layer 23c is not by laser lift off (LLO) but the silicon deposition substrate 1 The difference is that) are removed together in a process that is removed through etching. Since the silicon deposition substrate 1 has a different lattice constant and thermal expansion coefficient than the sapphire deposition substrate 1, the stress control layer 23c formed thereon and Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric The film formation conditions of the thin film 4 are set to Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric so that no cracks are generated in the thin film 4 and Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric. It is important to control the thin film 4 to have a uniform thickness. As the silicon deposition substrate 1, for example, an 8 inch Si (111) substrate may be used. Therefore, the stress control layer 23c does not have the constraints that the sacrificial layer 23a must have in order to be laser lifted off (LLO), and high quality Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric It is possible to focus only on the formation of the thin film 4.

The stress control layer 23c is a single layer of Al _g Ga _1-g N (0 ≤ _g ≤ ₁ ) or a multilayer of Al _h1 Ga _1-h1 N/ grown by CVD (e.g., MOCVD, HVPE, ALD, MBE). Al _h2 Ga _1-h2 N (h ₂ <h ₁ ≤ 1, ₀ ≤ h ₂ ≤ 1) may be made of a group III nitride. The stress control layer 23c prevents and mitigates wafer curvature and cracks caused by differences in physical properties (lattice constant and thermal expansion coefficient) at the growth temperature with the silicon film-forming substrate 1. The main role is the stress control function. Above all, in the initial stage of depositing the stress control layer 23c, the silicon (Si), group 3 (Al, Ga), and group 5 (N) elements and chemicals are applied on the surface of the silicon (Si) material of the silicon deposition substrate 1 It is important to minimize the formation of intermetallic compounds (Si-Al-(Ga)) and/or silicon nitride (Si(Al,Ga)Nx) through the reaction. Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is deposited on the sacrificial layer 23c with PVD (e.g., sputtering, PLD) at a temperature of 0.3Tm or more (melting point of the piezoelectric thin film material) And can secure high quality.

The stress control layer 23c may be formed at a temperature of 500°C or higher, and the upper and lower limits of the thickness are not particularly limited, but preferably Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 It is set to 50nm-3㎛ to benefit from the stress control function to maintain the thickness uniformity of the. For example, the film may be grown at a temperature of 500-1100°C and a pressure of 100-600torr.

Figure 21 is a _{Al x Ga 1-x N (} 0.5≤x≤1) method for producing a piezoelectric thin film _{and, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin-film structure (structure) in accordance with the present disclosure As a diagram showing another example, the structure is a stress control layer 23c, a surface polarity control layer (C), and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric sequentially on a silicon film formation substrate (1). It includes a thin film (4). It is distinguished from the structure shown in Fig. 20 in that the surface polarity control layer (C) is added, and the surface polarity control layer (C) is CVD (e.g., MOCVD, HVPE, ALD, MBE) like the stress control layer 23c. _Single- layer or multi-layered Al _m1 Ga _1-m1 N/Al _m2 Ga _1-m2 N (m ₂ <m ₁ ) is grown but has the same or different composition (Al _k Ga _1-k N (0≤k≤1)) ≤1, 0≤m ₂ ≤1) can be made of a group III nitride, and the surface of the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 has a single polarity (metallic polarity or nitrogen gas) In addition to the main function of having a polarity), it plays a role of promoting the securing of a piezoelectric thin film 4 of Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) having a uniform thickness by minimizing crystal defects and controlling stress. . Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is deposited at a temperature of 0.3Tm (melting point of piezoelectric thin film material) or higher with PVD (e.g., sputtering, PLD) on the stress control layer 23c It is formed into a film, and high quality can be ensured. Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film fabrication method having a metallic polarity surface through the surface polarity control layer (C) is PVD (e.g., sputtering, PLD) and Al _x Ga _1-x N ( 0.5≤x≤1) Before depositing the piezoelectric thin film 4, the surface polarity control layer C is grown by CVD (e.g., MOCVD, HVPE, ALD, MBE), and then formed with a predetermined amount of oxygen (ratio). It can be obtained by plasma treatment of the surface of the surface polarity control layer (C). On the other hand, an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film having a nitrogen gas polarity surface through the surface polarity control layer (C) is PVD (e.g., sputtering, PLD). ) Before deposition and deposition, the surface polarity control layer (C) is grown by CVD (MOCVD, HVPE, ALD, MBE), and magnesium (Mg) is excessively added (doped) during deposition to form Al with nitrogen gas polarity surface. _A piezoelectric thin film of _x Ga _1-x N (0.5≤x≤1) can be obtained (SCIENTIFIC REPORT, Intentional polarity conversion of AlN epitaxial layers by oxygen, published online: 20 September 2018). Plasma treatment on the surface of the stress control layer 23c or excessive addition (doping) of magnesium (Mg) in the process of growth film formation Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film ( It is also possible to adjust the polarity of 4).

The surface polarity control layer (C) can be grown and formed at the same temperature (500°C or higher) as the stress control layer (23c), and has a thickness of 0.5 μm or less, and Al _x Ga _1-x N at a pressure of 100-600 torr. (0.5≦x≦1) It is preferable to use a group III nitride having the same or similar composition as the piezoelectric thin film 4. In addition, the stress control layer 23c and the surface polarity control layer C are of high quality (crystallinity and polarity) and uniform thickness when the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 is deposited. It is preferable to control the film-forming substrate to have a curvature of as much as possible to maintain a zero (flat) state.

The bending state of the film-forming substrate 1 is the film-forming conditions (temperature, pressure) of the thin films 23c, C, and 4 to be deposited (deposited, grown) thereon, and the silicon film-forming substrate 1 and the films 23c, C, and 4 to be deposited. ) Of the thermal expansion coefficient (the thermal expansion coefficient is a function of temperature) and the lattice constant, preferably to maintain a zero state, but at least to be convex upward (convex), and convex downward ( It is important not to become concave), and the silicon film-forming substrate 1 Since the degree of warpage can be measured during film formation, the film formation conditions (temperature, pressure) and the composition of the film formed AlGaN during film formation are determined in a state in which the warpage of the silicon film formation substrate 1 is zero or convex, and even after the final film formation. It is important to control it so that it is in a state. Considering the thermal expansion coefficient of the silicon film-forming substrate 1 and the thermal expansion coefficient of AlGaN, it is not easy to perform such control only by CVD, and a high-quality stress control layer 23c is formed only with PVD, and a high temperature (0.3Tm (660)) is formed on it. ℃)), it is not easy to form the piezoelectric thin film 4 of Al _x Ga _1-x N (0.5≤y≤1). The present disclosure is formed by growing a stress control layer 23c and a surface polarity control layer (C) by CVD, and depositing an Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 by PVD, Provides an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 with excellent crystallinity and polarity despite the use of a silicon substrate 1 having a large difference in lattice constant and thermal expansion coefficient You can do it.

For example, when 1) Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4 is deposited with AlN at a temperature of 800°C with PVD (eg sputtering, PLD), the stress control layer (23c) may be formed of _0.9 Ga _0.1 N of 500 nm thick Al at a temperature of 500-900°C and a pressure of 100-600 Torr by CVD (eg, MOCVD). 2) In addition, when the surface polarity control layer (C) is formed by CVD (e.g. MOCVD) at a temperature of 500-1100°C and a pressure of 100-600 Torr, 100 nm thick Al _0.9 Ga _0.1 N, Al _x Ga _{1- x} N (0.5≤x≤1) piezoelectric thin film 4 is formed of AlN with PVD (e.g., sputtering, PLD) at a temperature of 800°C, and the stress control layer 23c is 500 by CVD (e.g., MOCVD) At a temperature of -900°C and a pressure of 100-600 Torr, it can be formed of _0.8 Ga _0.2 N of Al having a thickness of 500 nm. At this time, the minimum (zero) film formation under the process conditions (temperature, pressure) of growing and forming the stress control layer 23c and/or the surface polarity control layer C by CVD (for example, MOCVD) on the silicon film deposition substrate 1 At the same time, maintaining the warpage of the substrate 1 is of paramount importance, and at the same time, a silicon film-forming substrate at room temperature (25°C) after growth of the stress control layer 23c and/or the surface polarity control layer (C) by CVD (eg MOCVD) is completed. (1) It is important to control so that the warpage remains zero or convex. In order to have the crystal quality and uniform thickness of the AlN piezoelectric thin film 4, which is subsequently deposited on the stress control layer 23c and/or the surface polarity control layer C, by PVD (e.g. sputtering) It may be possible by adjusting the conditions and the corresponding behavior of the silicon film-forming substrate 1 in a state of being recognized.

The crystalline quality of the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 structure manufactured according to the method shown in FIGS. 20 to 21 is commonly X-ray Rocking Curve (XRC ) Has an advantage of being less than or equal to 0.1°, and the polar quality can be freely adjusted according to the surface conditions of the stress control layer 23c and/or the surface polarity control layer C.

The stress control layer (23c) and the surface polarity control layer (C) are composed of ① Group III nitride formed by CVD (MOCVD, HVPE, ALD, MBE), ② Al _x Ga _1-x N (0.5≤x≤1) In order to enable high-temperature deposition of the piezoelectric thin film 4, it must be a material that has thermal stability above 0.3Tm (660°C), and ③ Al _x Ga _1-x N (0.5≤) having a hexagonal (HCP) crystal structure. x≤1) is a material having the same or similar crystal structure as the piezoelectric thin film 4, and ④ Al _x Ga _1-x N (0.5≤x≤1) The surface roughness of the piezoelectric thin film 4 can be deposited. It is a ceramic (nitride) material with a roughness) of 10 nm or less, and ⑤ Al _x Ga _1-x N (0.5≤x≤1) The surface state where various contaminants are removed to enable the deposition of the piezoelectric thin film 4 It is preferably a material of.

If necessary, the Al _x Ga _1-x N (0.5≤x≤1) pressure-welded thin film 4, a stress control layer 23c to secure a single crystal piezoelectric thin film having a tilted c-axis crystal plane before deposition. And/or it is possible to perform photo-lithographic etch patterning processing on the surface of the surface polarity control layer (C).

The Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 deposited on the silicon deposition substrate 1 and subsequently deposited on the stress control layer 23c and/or the surface polarity control layer C Unlike piezoelectric thin films deposited by PVD (e.g., sputtering, PLD) at low temperatures (around 400℃), high-temperature single crystal structures deposited at 0.3Tm (660℃) or higher provide higher quality. Have.

After deposition of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4, it is possible to further improve crystallinity and polarity through post-annealing, which is an additional high-temperature post-heat treatment process. .

It is preferable to preferentially grow and deposit an AlGaN thin film with a minimum gallium (Ga) component while controlling the temperature of the stress control layer 23c at a temperature of 500°C or higher at low/medium/high temperature, which is the material of the film-forming substrate (1). This is to prevent a melt-back phenomenon by suppressing the reaction between silicon (Si) and gallium (Ga), which relatively easily forms an intermetallic compound.

An intermediate layer having a superlattice structure may be introduced between the stress control layer 23c and the Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4, in order to suppress crystal defects.

Al _x Ga _1-x N (0.5≤x≤1) When the piezoelectric thin film 4 is deposited, the Al content can be increased while the PVD deposition temperature can be increased, which suppresses tensile stress. This is to prevent minute cracks in the piezoelectric thin film 4.

The method of manufacturing the Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4 structure using the silicon film-forming substrate 1 may be the method shown in FIGS. 10 to 14 as it is. However, the silicon (Si) film-forming substrate 1, the stress control layer 23c, and the surface polarity control layer C are not laser lift off (LLO), but a known wet etch and The difference is that it is removed through a combination of dry etch. In this process, a trimming process for accurate thickness adjustment may be involved.

22 and 23 are views showing another example of a method of manufacturing a resonator using the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film proposed in the present disclosure, 1), a stress control layer 23c and a surface polarity control layer 3 are provided, but by adding (doped) magnesium (Mg) to the surface polarity control layer 3, Al _x Ga _1-x N (0.5 ≤x≤1) After forming the piezoelectric thin film 4 to have a nitrogen gas polarity surface, the second electrode 14, the Bragg reflector 10, the reflector, the second protective film 11, the second bonding layer 12, and The element substrate 13 is formed, and the silicon film forming substrate 1, the stress control layer 23c, and the surface polarity control layer 3 are formed into Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film 4 After removal from, an Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4 structure on which the first electrode 6 is formed is presented. Through this, the metallic polarity (Al-polarity or Al-polarity & Ga-polarity mixed) surface is formed through a single wafer bonding process without using two wafer bonding processes as in FIGS. 10 to 12. It is possible to provide an Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film 4 structure used as a top surface of a device.

A resonator produced in accordance with this disclosure based device (resonator-based device) is a Bragg reflector 10 of Al _x film forming the first laid position the second electrode 14 is formed, including a reflector on a silicon (Si) film-forming substrate (1) Ga _1-x N (0.5≤x≤1) Al _x Ga _1-x N (0.5≤x≤1) depending on the number of wafer bonding in the process of controlling the polarity of the piezoelectric thin film and subsequent device processing The surface polarity can be freely selected on the piezoelectric thin film 4. The method shown in FIGS. 10 to 12 is fabricated through two wafer bonding processes, and the Bragg reflector 10 and the second electrode 14 including the reflector are Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric The second electrode 14 including the Bragg reflector 10 and the reflector is placed on the N-polarity face of the thin film 4, and also in the case of the method shown in FIGS. 22 and 23 that undergoes a single wafer bonding process. ) Is equally located on the nitrogen gas polarity face of the piezoelectric thin film 4 (0.5≦ _x ≦ ₁ ) Al _x Ga _1-x N. For reference, in the case of a resonator element made of a polycrystalline AlN piezoelectric thin film formed through PVD (e.g., sputtering, PLD) directly at low temperature on a conventional Si deposition substrate, it is limited to control the surface polarity and polarity ratio. Because there is a Bragg reflector 10, the polarity position of the second electrode 14 including the reflector cannot be defined. For this reason, it is difficult to fabricate a device with mixed polarity and polarity controlled regardless of the amount of crystallinity or negative, so that the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film (4) is used to improve the performance of the resonator. It has limitations.

Hereinafter, various embodiments of the present disclosure will be described.

(1) A method of manufacturing an Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film, the method comprising: forming a sacrificial layer on a sapphire deposition substrate; And, growing an Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film on the sacrificial layer; including, growing an Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film Prior to forming a first semiconductor layer of Al _y Ga _1-y N (0.5≤y≤1); Al _x Ga _1-x N (0.5≤x≤1) piezoelectric, characterized in that it further comprises How to make a thin film.

(2) A method of manufacturing an Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film, wherein the first semiconductor layer is formed at a temperature of 1000° C. or higher prior to formation of the sacrificial layer.

(3) A method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, wherein the first semiconductor layer is formed of PVD while oxygen is supplied after the sacrificial layer is formed.

(4) Between the sacrificial layer and the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, the Al content is higher than that of the sacrificial layer, and the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film Forming a second semiconductor layer having a small content; Al _x Ga _1-x N (0.5≤x≤1) method for manufacturing a piezoelectric thin film further comprising a.

_{(5) Al x Ga 1-} x N (0.5≤x≤1) in the structure including a piezoelectric thin _{film, Al x Ga 1-x N} (0.5≤x≤1) the piezoelectric thin film; A first electrode provided on one side of the Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film; Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) A second electrode and a reflector provided on opposite sides of the first electrode based on the piezoelectric thin film; including, Al _x Ga _1-x N having the first electrode (0.5≤x≤1) Al _x Ga _1-x N (0.5≤x≤1), characterized in that the surface of the piezoelectric thin film is a metallic polarity (Al-polarity or Al-polarity & Ga-polarity mixed) surface. ) Structure having a piezoelectric thin film.

(6) A structure having an Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film, wherein the reflector is one of an air cavity and a Bragg reflector.

(7) When the first semiconductor layer 2 is grown at a high temperature by MOCVD, it is preferable to insert a number of air-voids to relieve stress.When forming a film by PVD, in addition to a small amount of oxygen, Sc, Mg, It is possible to add Zr doping or alloying components. The reason for inserting Sc, Mg, Zr doping or alloying is to maximize the electro-mechanical coupling efficiency of the device structure using the piezoelectric thin film.

(8) The second semiconductor layer 5 Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) The wafer stress is relieved before the piezoelectric thin film is grown to maintain the horizontal Al _x Ga _1-x N (0.5 ≤ _x ≤ 1) Si or/and Mg can be added in the second semiconductor layer 5 to serve to uniformize the thickness of the piezoelectric thin film.

(9) A method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, comprising: forming a sacrificial layer on a sapphire film formation substrate; wherein the sacrificial layer is a chemical vapor deposition method (CVD; Chemical Vapor) Forming a sacrificial layer consisting of one of oxides including Group 3 nitride formed by Deposition) and Group 2 or Group 3 oxide formed by Physical Vapor Deposition (PVD); And, depositing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the sacrificial layer; As, the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film is 0.3Tm (Tm; Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film comprising; depositing a piezoelectric thin film deposited by physical vapor deposition at a temperature equal to or higher than the melting point of the piezoelectric thin film material.

(10) The sacrificial layer is a single layer of Al _c Ga _1-c N (0≤c≤0.5) formed by CVD or a multilayer of Al _c1 Ga _1-c1 N/Al _c2 Ga _1-c2 N (c ₂ <c ₁ A method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, characterized in that it is a Group III nitride of ≤1, 0≤c ₂ <0.5).

(11) A sacrificial layer and an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film formed by CVD, and a composition different from the sacrificial layer (Al _a Ga _1-a N (0.5<a≤1)) Forming a second semiconductor layer made of a group III nitride having a; Al _x Ga _1-x N (0.5≤x≤1) method for manufacturing a piezoelectric thin film further comprising a.

(12) The sacrificial layer is Al _x Ga _1-x N (0.5), characterized in that the sacrificial layer is made of a single-layered group 2 oxide formed of PVD, a single-layered group 3 oxide, or an oxide having a multilayered oxide structure including at least one of them. ≤x≤1) A method of manufacturing a piezoelectric thin film.

(13) PVD is formed between the sacrificial layer and the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, and the oxygen in the sacrificial layer of oxide is Al _x Ga _1-x N (0.5≤x≤1) ) Forming an oxygen (O ₂ ) inflow prevention layer to prevent the inflow of the piezoelectric thin film; Al _x Ga _1-x N (0.5≤x≤1) method of manufacturing a piezoelectric thin film, characterized in that it further comprises.

(14) A method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, wherein a stress control layer made of a group III nitride is formed on a silicon film-forming substrate by chemical vapor deposition (CVD). Forming; And, forming an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film on the stress control layer by a physical vapor deposition method at a temperature of 0.3Tm (Tm; melting point of the piezoelectric thin film material) or higher; A method of manufacturing a piezoelectric thin film of Al _x Ga _1-x N (0.5≤x≤1), characterized in that.

(15) Prior to the deposition step, performing a pretreatment for adjusting the surface polarity of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film; Al _x Ga _{1- x} N (0.5≤x≤1) A method of manufacturing a piezoelectric thin film. Here, the pretreatment refers to the action of intentional conversion of the surface polarity of the Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film, and the above-described plasma treatment or excessive addition of magnesium (Mg) Refers to actions such as (doping).

(16) prior to the deposition step, forming a surface polarity control layer; further comprising, the pretreatment is performed on the surface polarity control layer, and Al _x Ga _1-x N (0.5≦ _x) on the pretreated surface polarity control layer ≤ 1) A method of manufacturing an Al _x Ga _1-x N (0.5 ≤ _x ≤ 1) piezoelectric thin film, characterized in that a piezoelectric thin film is formed.

_{(17) Al x Ga 1-} x N (0.5≤x≤1) a process for producing a piezoelectric thin film device, comprising: bonding the element substrate to the _{Al x Ga 1-x N (} 0.5≤x≤1) piezoelectric thin film ; Removing the film-forming substrate; And forming an electrode on the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film from the side from which the film-forming substrate is removed; including, the Al _x Ga _1-x N (0.5 ≤ _x ≤ 1) A method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film device, wherein the surface of the piezoelectric thin film has metallic polarity. The method shown in FIGS. 20 to 23 is not only when an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film is formed on a silicon deposition substrate, but also Al _x Ga _1- xN (0.5≤x≤1). A method of manufacturing a device having a piezoelectric thin film can be generally extended. A device including an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film is a representative example of an RF resonator.

(18) prior to the bonding step, pre-treating the surface polarity of the Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film on the side to which the device substrate is bonded to have a nitrogen gas polarity; Al _x Ga _1-x N (0.5≤x≤1) method of manufacturing a piezoelectric thin film device.

According to the present disclosure, a high _- purity Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film is manufactured, a resonator is manufactured for it, and the resonator can be applied to various devices.

Film-forming substrate 1, first semiconductor layer 2, sacrificial layer 3, Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film 4, second semiconductor layer 5, first Electrode 6, second electrode 14

Claims (3)

In the method of manufacturing an Al _x Ga _1-x N (0.5≤x≤1) piezoelectric thin film,
Forming a stress control layer made of a group III nitride on the silicon film formation substrate by chemical vapor deposition (CVD); And,
And forming an Al _x Ga _1-x N (0.5≦ _x ≦ ₁ ) piezoelectric thin film on the stress control layer by a physical vapor deposition method at a temperature of 0.3 Tm (Tm; melting point of the piezoelectric thin film material) or higher. Al _x Ga _1-x N (0.5≤x≤1) method of manufacturing a piezoelectric thin film. The method according to claim 1,
Prior to the deposition step, performing a pretreatment for controlling the surface polarity of the Al _x Ga _1-x N (0.5 ≤ _x ≤ ₁ ) piezoelectric thin film; Al _x Ga _1-x N ( 0.5≤x≤1) A method of manufacturing a piezoelectric thin film. The method according to claim 2,
Prior to the step of depositing, forming a surface polarity control layer; further comprises,
Pretreatment is performed on the surface polarity control layer,
Process for preparing a _{Al x Ga 1-x N (} 0.5≤x≤1) piezoelectric thin film characterized in that the _{Al x Ga 1-x N (} 0.5≤x≤1) piezoelectric thin film on the pretreated surface polarity control layer formed .

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