JP4059387B2 - 集積回路のノードにおけるディジタル信号の遷移エッジのスルー・レートを変化させる装置 - Google Patents

集積回路のノードにおけるディジタル信号の遷移エッジのスルー・レートを変化させる装置 Download PDF

Info

Publication number
JP4059387B2
JP4059387B2 JP2002206776A JP2002206776A JP4059387B2 JP 4059387 B2 JP4059387 B2 JP 4059387B2 JP 2002206776 A JP2002206776 A JP 2002206776A JP 2002206776 A JP2002206776 A JP 2002206776A JP 4059387 B2 JP4059387 B2 JP 4059387B2
Authority
JP
Japan
Prior art keywords
transistor
coupled
drive
source
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002206776A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003069415A5 (enExample
JP2003069415A (ja
Inventor
ガイ・ハーラン・ハンフリー
Original Assignee
アバゴ・テクノロジーズ・ジェネラル・アイピー（シンガポール）プライベート・リミテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by アバゴ・テクノロジーズ・ジェネラル・アイピー（シンガポール）プライベート・リミテッド filed Critical アバゴ・テクノロジーズ・ジェネラル・アイピー（シンガポール）プライベート・リミテッド
Publication of JP2003069415A publication Critical patent/JP2003069415A/ja
Publication of JP2003069415A5 publication Critical patent/JP2003069415A5/ja
Application granted granted Critical
Publication of JP4059387B2 publication Critical patent/JP4059387B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/12—Shaping pulses by steepening leading or trailing edges
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163—Soft switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00032—DC control of switching transistors
    • H03K2005/00039—DC control of switching transistors having four transistors serially

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
JP2002206776A 2001-08-02 2002-07-16 集積回路のノードにおけるディジタル信号の遷移エッジのスルー・レートを変化させる装置 Expired - Fee Related JP4059387B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/920,889 US6683482B2 (en) 2001-08-02 2001-08-02 Slew rate control of output drivers using PVT controlled edge rates and delays
US09/920,889 2001-08-02

Publications (3)

Publication Number Publication Date
JP2003069415A JP2003069415A (ja) 2003-03-07
JP2003069415A5 JP2003069415A5 (enExample) 2005-10-20
JP4059387B2 true JP4059387B2 (ja) 2008-03-12

Family

ID=25444571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002206776A Expired - Fee Related JP4059387B2 (ja) 2001-08-02 2002-07-16 集積回路のノードにおけるディジタル信号の遷移エッジのスルー・レートを変化させる装置

Country Status (3)

Country Link
US (1) US6683482B2 (enExample)
JP (1) JP4059387B2 (enExample)
SG (1) SG123533A1 (enExample)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6798237B1 (en) 2001-08-29 2004-09-28 Altera Corporation On-chip impedance matching circuit
US20030095000A1 (en) * 2001-11-16 2003-05-22 Acoustic Technology, Inc. Apparatus with ultra high output power class D audio amplifier
US6836144B1 (en) * 2001-12-10 2004-12-28 Altera Corporation Programmable series on-chip termination impedance and impedance matching
US7109744B1 (en) 2001-12-11 2006-09-19 Altera Corporation Programmable termination with DC voltage level control
JP3808060B2 (ja) * 2003-06-23 2006-08-09 ローム株式会社 半導体集積回路装置
EP1492233A1 (en) * 2003-06-27 2004-12-29 Dialog Semiconductor GmbH Circuit and method for slew rate sensing and control of a high-voltage output driver for a variable voltage range and variable output load
US6888370B1 (en) 2003-08-20 2005-05-03 Altera Corporation Dynamically adjustable termination impedance control techniques
US7202702B2 (en) * 2003-12-10 2007-04-10 Hewlett-Packard Development Company, L.P. Output buffer slew rate control using clock signal
KR100598168B1 (ko) * 2004-04-12 2006-07-10 주식회사 하이닉스반도체 출력 드라이버 회로
KR100579045B1 (ko) * 2004-04-14 2006-05-12 삼성전자주식회사 슬루율 제어가 가능한 전송선 드라이버 및 전송선 구동방법
US7005886B2 (en) * 2004-04-30 2006-02-28 Agilent Technologies, Inc. Tristateable CMOS driver with controlled slew rate for integrated circuit I/O pads
US7088129B2 (en) * 2004-04-30 2006-08-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers
US7157932B2 (en) * 2004-11-30 2007-01-02 Agere Systems Inc. Adjusting settings of an I/O circuit for process, voltage, and/or temperature variations
WO2006064822A1 (en) * 2004-12-13 2006-06-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance using the same
US7425849B2 (en) * 2004-12-31 2008-09-16 Stmicroelectronics Pvt. Ltd. Low noise output buffer capable of operating at high speeds
US20070024317A1 (en) * 2005-07-29 2007-02-01 Hansen James E Apparatus for obtaining precision integrated resistors
US7679397B1 (en) 2005-08-05 2010-03-16 Altera Corporation Techniques for precision biasing output driver for a calibrated on-chip termination circuit
US7863946B2 (en) * 2005-12-01 2011-01-04 Ricoh Company, Ltd. Electric signal outputting apparatus with a switching part, an impedance matching part, and an auxiliary switching part
US7843235B2 (en) * 2006-12-05 2010-11-30 Integrated Device Technology, Inc. Output slew rate control in low voltage differential signal (LVDS) driver
US8063613B2 (en) * 2006-12-11 2011-11-22 International Rectifier Corporation Power converter driver with split power supply
US7812647B2 (en) * 2007-05-21 2010-10-12 Advanced Analogic Technologies, Inc. MOSFET gate drive with reduced power loss
KR20090074427A (ko) * 2008-01-02 2009-07-07 삼성전자주식회사 데이터 출력 버퍼 회로 및 그것을 포함하는 반도체 메모리장치
US7911262B2 (en) * 2009-03-29 2011-03-22 Nanya Technology Corp. External compensation for input current source
JP5499635B2 (ja) * 2009-10-29 2014-05-21 日本電気株式会社 多相クロック発生回路
TWI452833B (zh) * 2009-12-30 2014-09-11 Ind Tech Res Inst 輸出元件、信號迴轉率的校正與控制方法以及信號振幅的控制方法
US8633736B2 (en) 2010-05-27 2014-01-21 Standard Microsystems Corporation Driver with accurately controlled slew rate and limited current
JP2012119883A (ja) * 2010-11-30 2012-06-21 Toshiba Corp 半導体装置
JP5938852B2 (ja) 2011-05-25 2016-06-22 富士電機株式会社 電圧制御型スイッチング素子のゲート駆動回路
US9711189B1 (en) * 2011-08-12 2017-07-18 Altera Corporation On-die input reference voltage with self-calibrating duty cycle correction
US8754695B2 (en) * 2011-08-30 2014-06-17 Micron Technology, Inc. Methods, integrated circuits, apparatuses and buffers with adjustable drive strength
US8643419B2 (en) * 2011-11-04 2014-02-04 Silicon Laboratories Inc. Flexible low power slew-rate controlled output buffer
JP6169928B2 (ja) * 2013-09-12 2017-07-26 東芝シュネデール・インバータ株式会社 ゲート駆動回路および電力変換装置
US9614506B1 (en) * 2015-12-03 2017-04-04 Texas Instruments Incorporated Digital pre-compensation for voltage slewing in a power converter
US10277380B2 (en) * 2016-04-06 2019-04-30 Maxim Integrated Products, Inc. Configurable bidirectional transceiver for full-duplex serial link communication system
DE102017107416A1 (de) * 2016-04-06 2017-10-12 Maxim Integrated Products, Inc. Konfigurierbarer bidirektionaler Transceiver für Kommunikationssystem mit serieller Vollduplex-Verbindung
US11349456B2 (en) 2017-07-21 2022-05-31 Texas Instruments Incorporated Ultra-low energy per cycle oscillator topology
US10574222B1 (en) * 2019-05-08 2020-02-25 PsiQuantum Corp. High speed high voltage drivers

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62220026A (ja) * 1986-03-20 1987-09-28 Toshiba Corp 出力バツフア回路
JPH01161916A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 半導体集積回路
US4975598A (en) * 1988-12-21 1990-12-04 Intel Corporation Temperature, voltage, and process compensated output driver
US5214320A (en) * 1992-06-12 1993-05-25 Smos Systems, Inc. System and method for reducing ground bounce in integrated circuit output buffers
US5581197A (en) 1995-05-31 1996-12-03 Hewlett-Packard Co. Method of programming a desired source resistance for a driver stage
US5986489A (en) * 1996-04-03 1999-11-16 Cypress Semiconductor Corp. Slew rate control circuit for an integrated circuit

Also Published As

Publication number Publication date
US6683482B2 (en) 2004-01-27
US20030025541A1 (en) 2003-02-06
SG123533A1 (en) 2006-07-26
JP2003069415A (ja) 2003-03-07

Similar Documents

Publication Publication Date Title
JP4059387B2 (ja) 集積回路のノードにおけるディジタル信号の遷移エッジのスルー・レートを変化させる装置
KR100491382B1 (ko) 버퍼 회로를 보상하는 슬루 레이트와 임피던스에 대한 방법 및 장치
US6900663B1 (en) Low voltage differential signal driver circuit and method
US4877980A (en) Time variant drive circuit for high speed bus driver to limit oscillations or ringing on a bus
EP0717334B1 (en) Circuit for providing a compensated bias voltage
US9325305B1 (en) Active biasing in metal oxide semiconductor (MOS) differential pairs
US7843235B2 (en) Output slew rate control in low voltage differential signal (LVDS) driver
KR100236058B1 (ko) 트리거 전압 조정이 가능한 슈미트 트리거 회로
US6087899A (en) Optical transmitter module, and semiconductor integrated circuit capable of increasing gain and band of amplifier constructed from FET
US7902885B2 (en) Compensated output buffer for improving slew control rate
US6975141B2 (en) LVDS driver for small supply voltages
KR100706576B1 (ko) 슬루율이 제어된 출력 구동회로
US20050122146A1 (en) Precise slew rate control line driver
US20100264957A1 (en) Output circuit
US20060125521A1 (en) Level shifter and level shifting method
US6958626B2 (en) Off chip driver
US20020011881A1 (en) Output buffer circuit
US6542004B1 (en) Output buffer method and apparatus with on resistance and skew control
US7501873B2 (en) Digitally controlled threshold adjustment circuit
US6236255B1 (en) Output impedance adjustment circuit
US6130569A (en) Method and apparatus for a controlled transition rate driver
US6348814B1 (en) Constant edge output buffer circuit and method
US6292037B1 (en) Output circuit of semiconductor integrated circuit
JP2004242240A (ja) 出力ｄｃ電圧調整高周波用バッファアンプ回路
JP2001203568A (ja) バッファ装置

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050627

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050627

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20060629

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20060913

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061129

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070727

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070808

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20071015

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071108

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071130

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20071213

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101228

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101228

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111228

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111228

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121228

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121228

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131228

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees