JP4057990B2 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
JP4057990B2
JP4057990B2 JP2003363461A JP2003363461A JP4057990B2 JP 4057990 B2 JP4057990 B2 JP 4057990B2 JP 2003363461 A JP2003363461 A JP 2003363461A JP 2003363461 A JP2003363461 A JP 2003363461A JP 4057990 B2 JP4057990 B2 JP 4057990B2
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JP
Japan
Prior art keywords
output
circuit
node
delay
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003363461A
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English (en)
Japanese (ja)
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JP2005130185A5 (enExample
JP2005130185A (ja
Inventor
浩一 大川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2003363461A priority Critical patent/JP4057990B2/ja
Priority to US10/865,923 priority patent/US7193430B2/en
Publication of JP2005130185A publication Critical patent/JP2005130185A/ja
Publication of JP2005130185A5 publication Critical patent/JP2005130185A5/ja
Application granted granted Critical
Publication of JP4057990B2 publication Critical patent/JP4057990B2/ja
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Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP2003363461A 2003-10-23 2003-10-23 半導体集積回路装置 Expired - Fee Related JP4057990B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003363461A JP4057990B2 (ja) 2003-10-23 2003-10-23 半導体集積回路装置
US10/865,923 US7193430B2 (en) 2003-10-23 2004-06-14 Semiconductor integrated circuit device with filter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003363461A JP4057990B2 (ja) 2003-10-23 2003-10-23 半導体集積回路装置

Publications (3)

Publication Number Publication Date
JP2005130185A JP2005130185A (ja) 2005-05-19
JP2005130185A5 JP2005130185A5 (enExample) 2005-11-24
JP4057990B2 true JP4057990B2 (ja) 2008-03-05

Family

ID=34510042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003363461A Expired - Fee Related JP4057990B2 (ja) 2003-10-23 2003-10-23 半導体集積回路装置

Country Status (2)

Country Link
US (1) US7193430B2 (enExample)
JP (1) JP4057990B2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7409659B2 (en) * 2004-11-12 2008-08-05 Agere Systems Inc. System and method for suppressing crosstalk glitch in digital circuits
JP4670675B2 (ja) * 2006-02-16 2011-04-13 ソニー株式会社 電荷転送部の駆動回路及び電荷転送部の駆動方法
US8997255B2 (en) * 2006-07-31 2015-03-31 Inside Secure Verifying data integrity in a data storage device
US8352752B2 (en) * 2006-09-01 2013-01-08 Inside Secure Detecting radiation-based attacks
US20080061843A1 (en) * 2006-09-11 2008-03-13 Asier Goikoetxea Yanci Detecting voltage glitches
US7616926B2 (en) * 2006-12-27 2009-11-10 Sun Microsystems, Inc. Conductive DC biasing for capacitively coupled on-chip drivers
JP4412507B2 (ja) 2007-10-03 2010-02-10 Ｎｅｃエレクトロニクス株式会社 半導体回路
US9342089B2 (en) * 2014-04-25 2016-05-17 Texas Instruments Deutschland Gmbh Verification of bandgap reference startup
US10044362B2 (en) * 2014-06-19 2018-08-07 Texas Instruments Incorporated Complementary current reusing preamp for operational amplifier
CN116827330B (zh) * 2022-12-12 2024-03-12 南京微盟电子有限公司 强抗干扰通讯端口电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3321306B2 (ja) 1994-06-23 2002-09-03 株式会社東芝 遅延回路
US5910730A (en) * 1996-12-13 1999-06-08 International Business Machines Corporation Digital circuit noise margin improvement
KR100252476B1 (ko) * 1997-05-19 2000-04-15 윤종용 플레이트 셀 구조의 전기적으로 소거 및 프로그램 가능한 셀들을 구비한 불 휘발성 반도체 메모리 장치및 그것의 프로그램 방법
US6812726B1 (en) * 2002-11-27 2004-11-02 Inapac Technology, Inc. Entering test mode and accessing of a packaged semiconductor device
US6366115B1 (en) * 2001-02-21 2002-04-02 Analog Devices, Inc. Buffer circuit with rising and falling edge propagation delay correction and method
KR100383262B1 (ko) * 2001-03-19 2003-05-09 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 데이터 출력방법
US6750677B2 (en) * 2001-06-04 2004-06-15 Matsushita Electric Industrial Co., Ltd. Dynamic semiconductor integrated circuit
JP3950704B2 (ja) * 2002-02-21 2007-08-01 キヤノン株式会社 画像処理装置、画像処理方法、印刷制御装置、印刷制御方法、プログラム
JP2004104681A (ja) * 2002-09-12 2004-04-02 Renesas Technology Corp 入力バッファ回路

Also Published As

Publication number Publication date
JP2005130185A (ja) 2005-05-19
US7193430B2 (en) 2007-03-20
US20050088224A1 (en) 2005-04-28

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