JP4040388B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP4040388B2
JP4040388B2 JP2002237124A JP2002237124A JP4040388B2 JP 4040388 B2 JP4040388 B2 JP 4040388B2 JP 2002237124 A JP2002237124 A JP 2002237124A JP 2002237124 A JP2002237124 A JP 2002237124A JP 4040388 B2 JP4040388 B2 JP 4040388B2
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semiconductor device
device unit
bump
mounting
laminated
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JP2003152161A (en
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浩之 平井
義孝 福岡
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置とその製造方法に係り、更に詳細には、半導体素子内蔵型の半導体装置とその製造方法に関する。
【０００２】
【従来の技術】
従来より、複数の半導体装置ユニットを三次元的に多段に配置した、いわゆるＴＣＰ（Tape Carrier Package）型の半導体装置が知られている。図９は代表的なＴＣＰ型半導体装置１００の断面図である。図９に示したように、この半導体装置１００では、半導体素子をＴＣＰパッケージに組み上げた二つのＴＣＰパッケージ１１０，１２０を用意し、これらのＴＣＰパッケージのアウターリード１１１，１２１を実装に適した所定の長さにトリミングし、リフォーミングすることにより図９に示したようなＴＣＰ型半導体装置１００を製造している。
【０００３】
ところで、図９に示したようなＴＣＰ型半導体装置１００を製造するには、長尺のアウターリードを配設するために高価な金型を必要とする。そのため、製造コストが増大するという問題がある。
【０００４】
また、図９に示したように、アウターリード１１１，１２１が長尺であるため、ＴＣＰ型半導体装置１００の体積が嵩張り、スペースを必要とするので集積度を向上する上で支障となるという問題がある。
【０００５】
【発明が解決しようとする課題】
上記したように、従来の方法では、製造コストが増大したり集積度を向上させる上で支障があるという問題があった。
【０００６】
本発明は上記従来の問題を解消するためになされた発明である。即ち、本発明は、高価な製造設備を必要とせず、しかも多層板表面全体に配線パターンを形成して集積度を向上させることのできる半導体装置及びその製造方法を提供することを目的とする。
【０００７】
【課題を解決するための手段】
本発明の半導体装置の製造方法は、少なくとも上面側には電極パッドが形成された、配線パターンを絶縁基板の両面に有し、これらの配線パターンが層間接続導体により接続されてなる第１の２層基板の、前記電極パッド上に半導体素子実装用の実装バンプを、前記電極パッド以外の上面側の配線パターン上には積層用の積層バンプを、それぞれ導電ペーストによって形成する工程と、第１の２層基板の実装バンプ上に異方性導電性接着剤を介して半導体素子を載置し、加圧、接着により実装バンプと半導体素子を電気的に接合させて第１の半導体装置ユニットを形成する工程と、少なくとも上面側には電極パッドが形成された、配線パターンを絶縁基板の両面に有し、これらの配線パターンが層間接続導体により接続されてなる第２の２層基板の、前記電極パッド上に半導体素子実装用の実装バンプを、導電ペーストによって形成する工程と、第２の２層基板の実装バンプ上に異方性導電性接着剤を介して半導体素子を載置し、加圧、接着により実装バンプと半導体素子を接合せて第２の半導体装置ユニットを形成する工程と、第１の半導体装置ユニットの積層バンプ上に異方性導電性接着剤を介して第２の半導体装置ユニットの下面側の配線パターンを載置し、加熱下での加圧、接着により積層バンプと前記配線パターンを接合させる工程とを具備することを特徴とする。
【０００９】
また、本発明の半導体装置の製造方法は、前記第２の半導体装置ユニットを形成する工程を用いて、第２の半導体装置ユニットに対応する第３及び第４の半導体装置ユニットを形成する工程と、第３の半導体装置ユニットの下面側の配線パターン上に積層用の積層バンプを導電ペーストによって形成する工程と、第４の半導体装置ユニットの上面側の、第３の半導体装置ユニットの積層バンプを接続すべき配線パターン上に、異方性導電性接着剤を介して第３の半導体装置ユニットの積層バンプを載置し、加熱下での加圧、接着により前記配線パターンと積層バンプを接合させる工程とを具備することを特徴とする。
【００１０】
さらに、本発明の半導体装置の製造方法は、少なくとも上面側には電極パッドが形成された、配線パターンを絶縁基板の両面に有し、これらの配線パターンが層間接続導体により接続されてなる第５の２層基板の、前記電極パッド以外の上面側の配線パターン上に積層用の積層バンプを導電ペーストによって形成するとともに、前記電極パッド上には、半導体素子をワイヤボンディングにより実装して第５の半導体装置ユニットを形成する工程と、少なくとも上面側には電極パッドが形成された、配線パターンを絶縁基板の両面に有し、これらの配線パターンが層間接続導体により接続されてなる第６の２層基板の、前記電極パッド上に半導体素子をワイヤボンディングにより実装して第６の半導体装置ユニットを形成する工程と、第５の半導体装置ユニットの積層バンプ上に異方性導電性接着剤を介して第６の半導体装置ユニットの下面側の配線パターンを載置し、加熱下での加圧、接着により積層バンプと前記配線パターンを接合させる工程とを具備する。
【００１１】
本発明により製造される半導体装置は、配線パターンを両面に有し、これらの配線パターンが層間接続導体により接続された２層基板上に半導体素子が実装された一の半導体装置ユニットと、前記一の半導体装置ユニットの上部に配設された他の半導体装置ユニットと、前記一の半導体装置ユニットと前記他の半導体装置ユニットとの間に介挿され、前記一の半導体装置ユニットの上面側の配線パターンと前記他の半導体装置ユニットの下面側の配線パターンとを電気的に接続する導電ペーストによって形成された積層用の導体バンプと、前記導体バンプの周囲を包囲する異方性導電性接着剤とを具備することを特徴とする。
【００１２】
上記半導体装置において、前記半導体素子は導電ペーストバンプを介して実装されていてもよい。
【００１３】
上記半導体装置において、前記導電ペーストバンプが、表面にＮｉ層及びその上のＡｕ層を備えていてもよい。また、上記半導体装置において、前記半導体素子が金属バンプを介して実装されていてもよい。更に、上記半導体装置において、前記半導体素子が金線を介して実装されていてもよい。
【００１４】
本発明では、半導体装置ユニットを積層バンプを介して多段に積層するので、高価な製造設備を必要としない。また、積層バンプ自体が小型であるので、積層するのに大きなスペースを必要とせず、集積度の高い半導体装置を得ることができる。
【００１５】
【発明の実施の形態】
（第１の実施の形態）
以下、本発明の第１の実施の形態に係る半導体装置の製造について説明する。図１及び図２は本実施形態に係る半導体装置の製造方法のフローチャートであり、図３、図４及び図５は製造途中の本実施形態に係る半導体装置の断面図である。
【００１６】
本実施形態に係る半導体装置を製造するには、まず絶縁基板の両面に配線パターンを形成した、いわゆる２層板を用意する。この２層板の製造方法のフローチャートを示したのが図１であり、製造途中の２層板の断面図を示したのが図３である。この２層板を製造するには、最初に図３（ａ）に示したように銅箔などの導体板１０を用意する。この導体板１０の上に印刷技法を用いて導体バンプ２０，２０…を形成する。
【００１７】
この導体バンプ２０，２０，…の形成方法としては、例えば、バンプ形成部分に貫通孔を設けたマスキングを施し（ステップ１）、この貫通孔内に導電性ペースト、例えば銀などの金属微粒子をエポキシ樹脂のような液状樹脂中に分散させたペースト状組成物を充填し（ステップ２）、マスキング上面からスキージ（ステップ３）し、前記マスキングを剥離する（ステップ４）ことからなる方法が挙げられる。このようにして、図３（ｂ）に示したような、略円錐形の導体バンプ２０，２０，…を形成した後、この導体バンプ２０，２０，…を乾燥させ、硬化する（ステップ５）。
【００１８】
次に図３（ｃ）に示したように、導体バンプ２０，２０，…の上にプリプレグ（絶縁基板前駆体）３０、すなわちガラス繊維マットのような補強材料中にエポキシ樹脂などの絶縁性樹脂を含浸させたものを重ね、更にこのプリプレグ３０の上にもう１枚の銅箔などの導体板４０を重ね合わせ（ステップ６）、この状態でヒートプレス、すなわち加熱下に加圧する（ステップ７）。
【００１９】
このヒートプレスすることにより導体バンプ２０，２０，…はプリプレグ３０を貫通して導体板１０と導体板４０との間が電気的に接続されると同時にプリプレグ３０が硬化して、図３（ｄ）に示したような、２層型プリント配線基板５０が得られる。この２層型配線基板５０表面の導体板１０，４０に例えばエッチング処理等によるパターニング（ステップ８）を施すことにより配線パターン１１，４１ａが形成された２層板５２が形成される。
【００２０】
次いで２層板５２上の配線パターン４１ａのうち、図４（ｆ）に示すように、半導体素子の電極に対応する位置に形成した電極パッド４１ｂ，４１ｂ，…上に導電ペーストバンプとして、銀ペーストバンプのような実装バンプ６０，６０，…を形成する。この実装バンプ６０，６０，…の形成方法は上記導体バンプ２０，２０，…の形成方法と実質的に同じである。
【００２１】
すなわち、バンプ形成部分に貫通孔を設けたマスキングを施し（ステップ１ａ）、この貫通孔内に導電性ペースト、例えば銀などの金属微粒子をエポキシ樹脂のような液状樹脂中に分散させたペースト状組成物を充填し（ステップ２ａ）、マスキング上面からスキージ（ステップ３ａ）し、前記マスキングを剥離する（ステップ４ａ）ことからなる方法である。
【００２２】
但し、ここで形成する実装バンプ６０，６０，…の大きさは、高さが１５〜３０μｍ、底面直径が５０〜８０μｍである。これは後述する半導体素子７０の大きさに対応させるためである。実装バンプ６０，６０，…の大きさの更に好ましい範囲は、高さが１８〜２２μｍ、底面直径が６５〜７５μｍである。
【００２３】
マスキングを剥離して実装バンプ６０，６０，…を形成した後、配線パターン４１ａ，４１ａ，…上に積層バンプとして銀ペーストバンプのような積層バンプ８０，８０，…を形成する。この積層バンプ８０，８０，…の形成方法は上記実装バンプ６０，６０，…の形成方法と同じである。
【００２４】
即ち、バンプ形成部分に貫通孔を設けたマスキングを施し（ステップ５ａ）、この貫通孔内に導電性ペースト、例えば銀などの金属微粒子をエポキシ樹脂のような液状樹脂中に分散させたペースト状組成物を充填し（ステップ６ａ）、マスキング上面からスキージ（ステップ７ａ）し、前記マスキングを剥離する（ステップ８ａ）ことからなる方法である。
【００２５】
但し、ここで形成する積層バンプ８０，８０，…の大きさは、高さが３５０〜５００μｍ、底面直径が３００〜４００μｍである。これは層間接続の信頼性を向上させるためと作業上の必要性に対応させるためである。積層バンプ８０，８０，…の大きさの更に好ましい範囲は、高さが４００〜４６０μｍ、底面直径が３３０〜３７０μｍである。
【００２６】
次にマスキング剥離後、実装バンプ６０，６０，…及び積層バンプ８０，８０，…を硬化させ（ステップ９ａ）、然る後に、例えば電解メッキや無電解メッキなどのＮｉメッキ処理を施すことにより、実装バンプ６０，６０，…、その底部の電極パッド４１ｂ、積層バンプ８０，８０，…、及びその底部の配線パターン４１ａ表面に図４（ｈ）に示したようなバリアメタル層としてのＮｉ層６１，８１を形成する（ステップ１０ａ）。次いでＮｉ層６１，８１の上からＡｕメッキ処理（ステップ１１ａ）を施すことによりＡｕ層６２，８２を形成する。こうして図４（ｉ）に示したようなバンプ付基板５２Ａが得られる。
【００２７】
次にこうして得られたバンプ付基板５２Ａの実装バンプ６０，６０，…形成面上に図４（ｊ）に示したように、ＡＣＦ（異方性導電接着剤層）６３を形成し、電極パッド４１ｂ，４１ｂ，…に対して電極板７１，７１，…が対向するように半導体素子７０を位置合わせする（ステップ１２ａ）。
【００２８】
次いでこの状態で半導体素子７０とバンプ付基板５２Ａとを加圧すると図５（ｋ）に示したように実装バンプ６０，６０，…がＡＣＦ（異方性導電接着剤層）６３を貫通し、電極板７１，７１，…に加圧される（ステップ１３ａ）。このとき実装バンプ６０，６０，…の表面にはＡｕ層６２，６２，…が形成されており、電極板７１，７１，…はＡｌで出来ているので、実装バンプ６０，６０，…と電極板７１，７１，…との間にはＡｌ−Ａｕ接合が形成され、電極パッド４１ｂ，４１ｂ，…と電極板７１，７１，…との間がＡｕ層６２，Ｎｉ層６１，実装バンプ６０，ＡＣＦ（異方性導電接着剤層）６３を介して電気的に接合される。こうして図５（ｋ）に示したような半導体素子７０が実装された半導体装置ユニット５３が得られる。
【００２９】
次にこうして得られた半導体装置ユニット５３の積層バンプ８０，８０，…周辺を包囲するようにＡＣＦ（異方性導電接着剤層）６４を形成し、このＡＣＦ（異方性導電接着剤層）６４を形成した半導体装置ユニット５３の上に他の半導体装置ユニット５４を図５（ｌ）のようにマウンタ９０を用いて位置合わせする（ステップ１６ａ）。
すなわち、他の半導体装置ユニット５４の下面側の配線パターンの所定の位置に積層バンプ８０の先端を一致させる。
【００３０】
ここで他の半導体装置ユニット５４は、積層バンプ８０，８０，…を形成しないこと以外は上記半導体装置ユニット５３と同様の工程により形成した同一構造の基板である。
【００３１】
次いで、この状態で半導体装置ユニット５３、及び他の半導体装置ユニット５４をヒートプレスにかけて加熱下に加圧すると（ステップ１７ａ）、図５（ｍ）に示したように、半導体装置ユニット５３の積層バンプ８０，８０，…がＡＣＦ６４を貫通して他の半導体装置ユニット５４の下面側の配線パターンに当接し、層間接続導体の導体バンプを介して上側の配線パターンに接続された半導体素子との間を電気的に接続して、半導体装置ユニット５３と半導体装置ユニット５４との間を電気的に接合する。このようにして、いわゆる４層配線型の立体配置型半導体装置１が得られる。
【００３２】
以上説明したように、本実施形態に係る半導体装置１では、半導体素子７０が実装された半導体装置ユニット５３，５４が積層バンプ８０とＡＣＦ６４とにより多段に積層されているので、高価な製造設備を用いることなく多段積層型の半導体装置を安価に製造することができる。
【００３３】
また、半導体装置ユニット間を接合する積層バンプ８０，８０，…は非常にコンパクトなものであるので、半導体装置１を小型化することができ、集積度の高い半導体装置を得ることができる。
【００３４】
（第２の実施の形態）
以下、本発明の第２の実施の形態に係る半導体装置の製造について説明する。図６は製造途中の本実施形態に係る半導体装置の断面図である。
【００３５】
本実施形態に係る半導体装置では、上記第１の実施形態において、積層バンプを半導体素子とは反対側の面に配設した構造とした。すなわち本実施形態では、図６（ｋ）に示したように、半導体装置ユニット５３ａ上において半導体素子７０と反対側（下面側）に積層バンプ８０ａ，８０ａ，…を形成する。この半導体装置ユニット５３ａを用いて半導体装置を形成するには、図６（ｌ）に示したような他の半導体装置ユニット５４ａ上面の配線パターン上にＡＣＦ６４を形成し、マウンタ９０で半導体装置ユニット５３ａを位置決めし、図６（ｌ）に示した状態で半導体装置ユニット５３ａと半導体装置ユニット５４ａとをヒートプレスすることにより、図６（ｍ）に示したような二段積層型の半導体装置１ａが得られる。
【００３６】
（第３の実施の形態）
以下、本発明の第３の実施の形態に係る半導体装置の製造について説明する。図７は製造途中の本実施形態に係る半導体装置の断面図である。
【００３７】
本実施形態に係る半導体装置では、上記第１の実施形態において、半導体素子としてフェイスダウン型のフリップチップ半導体素子７０を用いる代わりに、フェイスアップ型のワイヤボンディング半導体素子７２を実装した半導体装置ユニット５３ｂを用いて半導体装置を作成した。
【００３８】
すなわち本実施形態では、図７（ｋ）に示したように、基板上にワイヤボンディング型の半導体素子７２がフェイスアップで配設されており、基板上の電極パッド４１ｂと半導体素子７２の電極７３との間は金線７４を介して接続されている。
【００３９】
この半導体装置ユニット５３ｂを用いて半導体装置を形成するには、図７（ｌ）に示したようにこの半導体装置ユニット５３ｂの積層バンプ８０ｂ周辺を包囲するようにＡＣＦ６４を形成し、マウンタ９０で他の半導体装置ユニット５４ｂを位置決めし、図７（ｌ）に示した状態で半導体装置ユニット５３ｂと半導体装置ユニット５４ｂとをヒートプレスすることにより、図７（ｍ）に示したような二段積層型の半導体装置１ｂが得られる。
【００４０】
（第４の実施の形態）
以下、本発明の第４の実施の形態に係る半導体装置について説明する。図８は本実施形態に係る半導体装置１ｃの断面図である。
【００４１】
図８に示したように、本実施形態に係る半導体装置１ｃでは、前記第１の実施の形態の半導体装置ユニット５４と同様の半導体装置ユニット５４ｃ，５４ｄ，５４ｅを三段に積み上げ、積層バンプ８０，８０ｄ及びＡＣＦ６４，６４ｄを介して半導体装置ユニット５４ｃ，５４ｄ，５４ｅの間を電気的に接続した構成とした。このように多段に積み上げても、積層バンプ８０，８０ｄ自体がコンパクトであるので、半導体装置そのものが嵩高くなることがなく、集積度の高い半導体装置を得ることができる。
【００４２】
【発明の効果】
本発明によれば、半導体装置ユニットを積層バンプを介して多段に積層するので、高価な製造設備を必要としない。また、積層バンプ自体が小型であるので、積層するのに大きなスペースを必要とせず、集積度の高い半導体装置を得ることができる。
【図面の簡単な説明】
【図１】第１の実施形態に係る半導体装置の製造方法のフローチャートである。
【図２】第１の実施形態に係る半導体装置の製造方法のフローチャートである。
【図３】第１の実施形態に係る半導体装置の製造途中のものの断面図である。
【図４】第１の実施形態に係る半導体装置の製造途中のものの断面図である。
【図５】第１の実施形態に係る半導体装置の製造途中のものの断面図である。
【図６】第２の実施形態に係る半導体装置の製造途中のものの断面図である。
【図７】第３の実施形態に係る半導体装置の製造途中のものの断面図である。
【図８】第４の実施形態に係る半導体装置の製造途中のものの断面図である。
【図９】従来の半導体装置の断面図である。
【符号の説明】
１…半導体装置、５２…２層板、４１ａ…配線パターン、４１ｂ…電極パッド、６０…実装バンプ、６１…Ｎｉ層（バリアメタル層）、６２…Ａｕ層、６３…ＡＣＦ、６４…ＡＣＦ、７０…半導体素子、７１…電極板、８０…積層バンプ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device incorporating a semiconductor element and a manufacturing method thereof.
[0002]
[Prior art]
Conventionally, a so-called TCP (Tape Carrier Package) type semiconductor device in which a plurality of semiconductor device units are arranged three-dimensionally in multiple stages is known. FIG. 9 is a cross-sectional view of a typical TCP type semiconductor device 100. As shown in FIG. 9, in this semiconductor device 100, two TCP packages 110 and 120 in which semiconductor elements are assembled in a TCP package are prepared, and outer leads 111 and 121 of these TCP packages are provided in a predetermined manner suitable for mounting. The TCP type semiconductor device 100 as shown in FIG. 9 is manufactured by trimming to a length and performing reforming.
[0003]
By the way, in order to manufacture the TCP type semiconductor device 100 as shown in FIG. 9, an expensive metal mold is required for disposing the long outer leads. Therefore, there is a problem that the manufacturing cost increases.
[0004]
Further, as shown in FIG. 9, since the outer leads 111 and 121 are long, the volume of the TCP-type semiconductor device 100 is bulky and requires a space, which is an obstacle to improving the degree of integration. There's a problem.
[0005]
[Problems to be solved by the invention]
As described above, the conventional method has a problem in that the manufacturing cost increases and there is a problem in improving the degree of integration.
[0006]
The present invention has been made to solve the above conventional problems. That is, an object of the present invention is to provide a semiconductor device that does not require expensive manufacturing equipment and that can improve the degree of integration by forming a wiring pattern on the entire surface of the multilayer board and a method for manufacturing the same.
[0007]
[Means for Solving the Problems]
The method for manufacturing a semiconductor device according to the present invention is a first method in which electrode pads are formed on at least the upper surface side, wiring patterns are provided on both surfaces of the insulating substrate , and these wiring patterns are connected by an interlayer connection conductor. A step of forming a mounting bump for mounting a semiconductor element on the electrode pad of the layer substrate and a stacking bump for stacking on the wiring pattern on the upper surface side other than the electrode pad by a conductive paste, respectively, A semiconductor element is mounted on a mounting bump of a two-layer substrate via an anisotropic conductive adhesive, and the mounting bump and the semiconductor element are electrically joined by pressure and adhesion to form a first semiconductor device unit. a step of, at least the upper surface side electrode pad is formed, has a wiring pattern on both surfaces of the insulating substrate, the second two layers of the wiring patterns, which are connected by an interlayer connection conductor A step of forming a mounting bump for mounting a semiconductor element on the electrode pad of the plate by a conductive paste, and mounting the semiconductor element on the mounting bump of the second two-layer substrate via an anisotropic conductive adhesive Placing the mounting bump and the semiconductor element by pressurization and bonding to form a second semiconductor device unit, and an anisotropic conductive adhesive on the laminated bump of the first semiconductor device unit And placing a wiring pattern on the lower surface side of the second semiconductor device unit, and bonding the laminated bump and the wiring pattern by pressurization and adhesion under heating .
[0009]
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the step of forming third and fourth semiconductor device units corresponding to the second semiconductor device unit using the step of forming the second semiconductor device unit. Forming a laminated bump for lamination on the wiring pattern on the lower surface side of the third semiconductor device unit by a conductive paste, and forming the laminated bump of the third semiconductor device unit on the upper surface side of the fourth semiconductor device unit. A laminated bump of the third semiconductor device unit is placed on the wiring pattern to be connected via an anisotropic conductive adhesive, and the wiring pattern and the laminated bump are bonded by pressure and adhesion under heating . And a process.
[0010]
Furthermore, in the method for manufacturing a semiconductor device of the present invention, there is provided a fifth method in which electrode pads are formed on at least the upper surface side, wiring patterns are provided on both surfaces of the insulating substrate , and these wiring patterns are connected by interlayer connection conductors. A multilayer bump for stacking is formed by conductive paste on a wiring pattern on the upper surface side of the two-layer substrate other than the electrode pad, and a semiconductor element is mounted on the electrode pad by wire bonding. A step of forming a semiconductor device unit, and a sixth two-layer structure in which electrode pads are formed on at least the upper surface side, wiring patterns are provided on both surfaces of the insulating substrate , and these wiring patterns are connected by interlayer connection conductors. Mounting a semiconductor element on the electrode pad of the substrate by wire bonding to form a sixth semiconductor device unit; and a fifth half Via an anisotropic conductive adhesive on the laminated bump body apparatus unit by placing the lower surface side of the wiring pattern of the sixth semiconductor device unit, pressurizing under heating, the the stacked bump by bonding a wiring pattern A step of bonding.
[0011]
The semiconductor device produced by the present invention has a wiring pattern on both surfaces, and one semiconductor device unit in which a semiconductor element connected to the 2-layer base board is mounted by these wiring patterns interlayer connection conductor, the Another semiconductor device unit disposed above the one semiconductor device unit, and interposed between the one semiconductor device unit and the other semiconductor device unit , on the upper surface side of the one semiconductor device unit Conductive bumps for lamination formed by a conductive paste that electrically connects a wiring pattern and a wiring pattern on the lower surface side of the other semiconductor device unit , and an anisotropic conductive adhesive that surrounds the periphery of the conductive bump It is characterized by comprising.
[0012]
In the semiconductor device, the semiconductor element may be mounted via a conductive paste bump.
[0013]
In the semiconductor device, the conductive paste bump may include a Ni layer and an Au layer thereon on the surface. In the semiconductor device, the semiconductor element may be mounted via a metal bump. Furthermore, in the semiconductor device, the semiconductor element may be mounted via a gold wire.
[0014]
In the present invention, since the semiconductor device units are stacked in multiple stages via the stacked bumps, expensive manufacturing equipment is not required. In addition, since the laminated bump itself is small, a large space is not required for lamination, and a highly integrated semiconductor device can be obtained.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, the manufacture of the semiconductor device according to the first embodiment of the present invention will be described. 1 and 2 are flowcharts of a method for manufacturing a semiconductor device according to the present embodiment, and FIGS. 3, 4, and 5 are cross-sectional views of the semiconductor device according to the present embodiment during manufacturing.
[0016]
In order to manufacture the semiconductor device according to this embodiment, first, a so-called two-layer board in which wiring patterns are formed on both surfaces of an insulating substrate is prepared. FIG. 1 shows a flowchart of the manufacturing method of the two-layer board, and FIG. 3 shows a cross-sectional view of the two-layer board in the middle of manufacturing. In order to manufacture this two-layer plate, first, a conductor plate 10 such as a copper foil is prepared as shown in FIG. .. Are formed on the conductor plate 10 by using a printing technique.
[0017]
As a method of forming the conductor bumps 20, 20,..., For example, masking with through holes provided in the bump forming portion is performed (step 1), and conductive paste, for example, metal fine particles such as silver is epoxy-bonded in the through holes. A method comprising filling a paste-like composition dispersed in a liquid resin such as a resin (step 2), squeegeeing from the upper surface of the mask (step 3), and peeling the masking (step 4). In this way, after forming the substantially conical conductor bumps 20, 20,... As shown in FIG. 3B, the conductor bumps 20, 20,... Are dried and cured (step 5). .
[0018]
Next, as shown in FIG. 3C, an insulating resin such as an epoxy resin in a prepreg (insulating substrate precursor) 30, that is, a reinforcing material such as a glass fiber mat, on the conductor bumps 20, 20,. Then, another conductor plate 40 such as a copper foil is overlaid on the prepreg 30 (step 6), and in this state, pressure is applied under heat press, that is, heating (step 7). .
[0019]
By this heat pressing, the conductor bumps 20, 20,... Penetrate the prepreg 30 and the conductor plate 10 and the conductor plate 40 are electrically connected, and at the same time, the prepreg 30 is cured, and FIG. The two-layer printed wiring board 50 as shown in FIG. The conductor plates 10 and 40 on the surface of the two-layer wiring board 50 are subjected to patterning (step 8) by, for example, an etching process to form the two-layer plate 52 on which the wiring patterns 11 and 41a are formed.
[0020]
Next, among the wiring patterns 41a on the two-layer board 52, as shown in FIG. 4 (f), silver paste is used as conductive paste bumps on electrode pads 41b, 41b,... Formed at positions corresponding to the electrodes of the semiconductor element. Mounting bumps 60, 60,... Like bumps are formed. The method for forming the mounting bumps 60, 60,... Is substantially the same as the method for forming the conductor bumps 20, 20,.
[0021]
In other words, the bump forming portion is masked with a through hole (step 1a), and a conductive paste, for example, a metal paste such as silver is dispersed in a liquid resin such as an epoxy resin in the through hole. It is a method comprising filling an object (Step 2a), squeegeeing from the upper surface of the masking (Step 3a), and peeling off the masking (Step 4a).
[0022]
However, the mounting bumps 60, 60,... Formed here have a height of 15 to 30 μm and a bottom diameter of 50 to 80 μm. This is to correspond to the size of the semiconductor element 70 described later. A more preferable range of the size of the mounting bumps 60, 60,... Is 18 to 22 μm in height and 65 to 75 μm in bottom diameter.
[0023]
After forming the mounting bumps 60, 60,... By peeling off the masking, stacked bumps 80, 80,... Such as silver paste bumps are formed on the wiring patterns 41a, 41a,. The method for forming the laminated bumps 80, 80,... Is the same as the method for forming the mounting bumps 60, 60,.
[0024]
That is, the bump formation portion is masked with through holes (step 5a), and a paste-like composition in which conductive fine particles, for example, metal fine particles such as silver are dispersed in a liquid resin such as an epoxy resin in the through holes. It is a method comprising filling an object (step 6a), squeegeeing from the upper surface of the masking (step 7a), and peeling off the masking (step 8a).
[0025]
However, the stacked bumps 80, 80,... Formed here have a height of 350 to 500 μm and a bottom surface diameter of 300 to 400 μm. This is to improve the reliability of the interlayer connection and to meet the work needs. More preferable ranges of the size of the laminated bumps 80, 80,... Are 400 to 460 μm in height and 330 to 370 μm in bottom diameter.
[0026]
Next, after removing the masking, the mounting bumps 60, 60,... And the laminated bumps 80, 80,... Are cured (step 9a), and thereafter, Ni plating treatment such as electrolytic plating or electroless plating is performed. The mounting bumps 60, 60,..., The bottom electrode pads 41b, the laminated bumps 80, 80,..., And the Ni wiring layer 61 as a barrier metal layer as shown in FIG. , 81 are formed (step 10a). Next, Au layers 62 and 82 are formed by performing Au plating processing (step 11a) on the Ni layers 61 and 81, respectively. In this way, a bumped substrate 52A as shown in FIG. 4I is obtained.
[0027]
Next, as shown in FIG. 4 (j), an ACF (anisotropic conductive adhesive layer) 63 is formed on the formation surface of the mounting bumps 60, 60,... The semiconductor element 70 is aligned so that the electrode plates 71, 71,... Are opposed to 41b, 41b,.
[0028]
Then, when the semiconductor element 70 and the bumped substrate 52A are pressurized in this state, the mounting bumps 60, 60,... Penetrate the ACF (anisotropic conductive adhesive layer) 63 as shown in FIG. Pressure is applied to the electrode plates 71, 71,... (Step 13a). At this time, Au layers 62, 62,... Are formed on the surface of the mounting bumps 60, 60,... And the electrode plates 71, 71,. An Al—Au bond is formed between the plates 71, 71,..., And an Au layer 62, an Ni layer 61, a mounting bump 60, between the electrode pads 41b, 41b,. Electrically bonded through an ACF (anisotropic conductive adhesive layer) 63. Thus, the semiconductor device unit 53 on which the semiconductor element 70 as shown in FIG.
[0029]
Next, an ACF (anisotropic conductive adhesive layer) 64 is formed so as to surround the periphery of the laminated bumps 80, 80,... Of the semiconductor device unit 53 thus obtained, and this ACF (anisotropic conductive adhesive layer). The other semiconductor device unit 54 is aligned on the semiconductor device unit 53 in which 64 is formed by using the mounter 90 as shown in FIG. 5L (step 16a).
That is, the tips of the laminated bumps 80 are made to coincide with predetermined positions of the wiring pattern on the lower surface side of the other semiconductor device unit 54.
[0030]
Here, the other semiconductor device unit 54 is a substrate having the same structure formed by the same process as the semiconductor device unit 53 except that the laminated bumps 80, 80,... Are not formed.
[0031]
Next, in this state, when the semiconductor device unit 53 and the other semiconductor device unit 54 are heated and pressed under pressure (step 17a), as shown in FIG. 80, 80,... Pass through the ACF 64 and come into contact with the wiring pattern on the lower surface side of the other semiconductor device unit 54 , and between the semiconductor elements connected to the upper wiring pattern via the conductor bumps of the interlayer connection conductors. Electrical connection is made, and the semiconductor device unit 53 and the semiconductor device unit 54 are electrically joined. In this way, a so-called four-layer wiring type three-dimensionally arranged semiconductor device 1 is obtained.
[0032]
As described above, in the semiconductor device 1 according to the present embodiment, since the semiconductor device units 53 and 54 on which the semiconductor element 70 is mounted are laminated in multiple stages by the laminated bump 80 and the ACF 64, an expensive manufacturing facility is provided. A multi-stage stacked semiconductor device can be manufactured at low cost without using it.
[0033]
Further, since the laminated bumps 80, 80,... For joining the semiconductor device units are very compact, the semiconductor device 1 can be reduced in size and a highly integrated semiconductor device can be obtained.
[0034]
(Second Embodiment)
The manufacture of the semiconductor device according to the second embodiment of the present invention will be described below. FIG. 6 is a cross-sectional view of the semiconductor device according to the present embodiment during manufacture.
[0035]
The semiconductor device according to the present embodiment has a structure in which the laminated bumps are disposed on the surface opposite to the semiconductor element in the first embodiment. That is, in this embodiment, as shown in FIG. 6K, the stacked bumps 80a, 80a,... Are formed on the semiconductor device unit 53a on the opposite side (lower surface side) from the semiconductor element 70. In order to form a semiconductor device using the semiconductor device unit 53a, an ACF 64 is formed on a wiring pattern on the upper surface of another semiconductor device unit 54a as shown in FIG. And the semiconductor device unit 53a and the semiconductor device unit 54a are heat-pressed in the state shown in FIG. 6L, whereby the two-stage stacked semiconductor device 1a as shown in FIG. can get.
[0036]
(Third embodiment)
The manufacture of the semiconductor device according to the third embodiment of the present invention will be described below. FIG. 7 is a cross-sectional view of the semiconductor device according to the present embodiment during manufacture.
[0037]
In the semiconductor device according to this embodiment, instead of using the face-down flip-chip semiconductor element 70 as the semiconductor element in the first embodiment, the semiconductor device unit 53b in which the face-up wire bonding semiconductor element 72 is mounted. A semiconductor device was created using
[0038]
That is, in this embodiment, as shown in FIG. 7 (k), the wire bonding type semiconductor element 72 is arranged face up on the substrate, and the electrode pad 41b on the substrate and the electrode 73 of the semiconductor element 72 are arranged. Are connected via a gold wire 74.
[0039]
In order to form a semiconductor device using the semiconductor device unit 53b, an ACF 64 is formed so as to surround the periphery of the laminated bump 80b of the semiconductor device unit 53b as shown in FIG. The semiconductor device unit 54b is positioned, and the semiconductor device unit 53b and the semiconductor device unit 54b are heat-pressed in the state shown in FIG. 7L, so that the two-stage stacked type as shown in FIG. The semiconductor device 1b is obtained.
[0040]
(Fourth embodiment)
The semiconductor device according to the fourth embodiment of the present invention will be described below. FIG. 8 is a cross-sectional view of the semiconductor device 1c according to the present embodiment.
[0041]
As shown in FIG. 8, in the semiconductor device 1c according to the present embodiment, the semiconductor device units 54c, 54d, and 54e similar to the semiconductor device unit 54 of the first embodiment are stacked in three stages to obtain a laminated bump 80. , 80d and ACFs 64, 64d, the semiconductor device units 54c, 54d, 54e are electrically connected. Even when stacked in this manner, the stacked bumps 80 and 80d themselves are compact, so that the semiconductor device itself does not become bulky and a highly integrated semiconductor device can be obtained.
[0042]
【The invention's effect】
According to the present invention, since semiconductor device units are stacked in multiple stages via stacked bumps, expensive manufacturing equipment is not required. In addition, since the laminated bump itself is small, a large space is not required for lamination, and a highly integrated semiconductor device can be obtained.
[Brief description of the drawings]
FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to a first embodiment.
FIG. 2 is a flowchart of a manufacturing method of the semiconductor device according to the first embodiment.
FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment that is being manufactured;
FIG. 4 is a cross-sectional view of the semiconductor device according to the first embodiment that is being manufactured;
FIG. 5 is a cross-sectional view of the semiconductor device according to the first embodiment that is being manufactured;
FIG. 6 is a cross-sectional view of the semiconductor device according to the second embodiment which is being manufactured.
FIG. 7 is a cross-sectional view of a semiconductor device according to a third embodiment that is being manufactured;
FIG. 8 is a cross-sectional view of a semiconductor device in the middle of manufacture according to a fourth embodiment.
FIG. 9 is a cross-sectional view of a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 52 ... Double layer board, 41a ... Wiring pattern, 41b ... Electrode pad, 60 ... Mounting bump, 61 ... Ni layer (barrier metal layer), 62 ... Au layer, 63 ... ACF, 64 ... ACF, 70 ... Semiconductor element, 71 ... Electrode plate, 80 ... Laminated bump.

Claims (5)

少なくとも上面側には電極パッドが形成された、配線パターンを絶縁基板の両面に有し、これらの配線パターンが層間接続導体により接続されてなる第１の２層基板の、前記電極パッド上に半導体素子実装用の実装バンプを、前記電極パッド以外の上面側の配線パターン上には積層用の積層バンプを、それぞれ導電ペーストによって形成する工程と、
第１の２層基板の実装バンプ上に異方性導電性接着剤を介して半導体素子を載置し、加圧、接着により実装バンプと半導体素子を電気的に接合させて第1の半導体装置ユニットを形成する工程と、
少なくとも上面側には電極パッドが形成された、配線パターンを絶縁基板の両面に有し、これらの配線パターンが層間接続導体により接続されてなる第２の２層基板の、前記電極パッド上に半導体素子実装用の実装バンプを、導電ペーストによって形成する工程と、
第２の２層基板の実装バンプ上に異方性導電性接着剤を介して半導体素子を載置し、加圧、接着により実装バンプと半導体素子を接合せて第２の半導体装置ユニットを形成する工程と、
第１の半導体装置ユニットの積層バンプ上に異方性導電性接着剤を介して第２の半導体装置ユニットの下面側の配線パターンを載置し、加熱下での加圧、接着により積層バンプと前記配線パターンを接合させる工程と
を具備することを特徴とする半導体装置の製造方法。A semiconductor on the electrode pad of a first two-layer substrate having electrode patterns on at least both surfaces of an insulating substrate having electrode pads formed on at least the upper surface side, and these wiring patterns connected by interlayer connection conductors A step of forming a mounting bump for element mounting on the wiring pattern on the upper surface side other than the electrode pads, respectively, with a conductive paste,
A semiconductor element is mounted on a mounting bump of a first two-layer substrate via an anisotropic conductive adhesive, and the mounting bump and the semiconductor element are electrically joined by pressure and adhesion to form a first semiconductor device Forming a unit;
A semiconductor on the electrode pad of a second two-layer substrate having electrode pads formed on at least both sides of the insulating substrate and having these wiring patterns connected to each other by an interlayer connection conductor. Forming a mounting bump for element mounting with a conductive paste;
A semiconductor element is mounted on the mounting bump of the second two-layer substrate through an anisotropic conductive adhesive, and the mounting bump and the semiconductor element are joined by pressure and adhesion to form a second semiconductor device unit. And a process of
A wiring pattern on the lower surface side of the second semiconductor device unit is placed on the laminated bumps of the first semiconductor device unit via an anisotropic conductive adhesive, and the laminated bumps are formed by pressing and bonding under heating. And a step of bonding the wiring patterns. 請求項１の第２の半導体装置ユニットを形成する工程を用いて、第２の半導体装置ユニットに対応する第３及び第４の半導体装置ユニットを形成する工程と、
第３の半導体装置ユニットの下面側の配線パターン上に積層用の積層バンプを導電ペーストによって形成する工程と、
第４の半導体装置ユニットの上面側の、第３の半導体装置ユニットの積層バンプを接続すべき配線パターン上に、異方性導電性接着剤を介して第３の半導体装置ユニットの積層バンプを載置し、加熱下での加圧、接着により前記配線パターンと積層バンプを接合させる工程とを具備することを特徴とする半導体装置の製造方法。Forming the third and fourth semiconductor device units corresponding to the second semiconductor device unit using the step of forming the second semiconductor device unit of claim 1;
Forming a lamination bump for lamination on the wiring pattern on the lower surface side of the third semiconductor device unit with a conductive paste;
On the upper surface side of the fourth semiconductor device unit, on the wiring pattern to which the laminated bump of the third semiconductor device unit is to be connected, the laminated bump of the third semiconductor device unit is placed via an anisotropic conductive adhesive. And a step of bonding the wiring pattern and the laminated bump by pressurization and adhesion under heating . 半導体装置ユニットを形成する工程に先立って、実装バンプ上に、Ａｕ層を形成する工程を具備することを特徴とする請求項１又は２記載の半導体装置の製造方法。  3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming an Au layer on the mounting bump prior to the step of forming the semiconductor device unit. 少なくとも上面側には電極パッドが形成された、配線パターンを絶縁基板の両面に有し、これらの配線パターンが層間接続導体により接続されてなる第５の２層基板の、前記電極パッド以外の上面側の配線パターン上に積層用の積層バンプを導電ペーストによって形成するとともに、前記電極パッド上には、半導体素子をワイヤボンディングにより実装して第５の半導体装置ユニットを形成する工程と、
少なくとも上面側には電極パッドが形成された、配線パターンを絶縁基板の両面に有し、これらの配線パターンが層間接続導体により接続されてなる第６の２層基板の、前記電極パッド上に半導体素子をワイヤボンディングにより実装して第６の半導体装置ユニットを形成する工程と、
第５の半導体装置ユニットの積層バンプ上に異方性導電性接着剤を介して第６の半導体装置ユニットの下面側の配線パターンを載置し、加熱下での加圧、接着により積層バンプと前記配線パターンを接合させる工程と
を具備することを特徴とする半導体装置の製造方法。An upper surface other than the electrode pads of a fifth two-layer substrate having electrode patterns formed on at least both surfaces of the insulating substrate and having these wiring patterns connected to each other by an interlayer connection conductor. Forming a laminated bump on the wiring pattern on the side with a conductive paste, and mounting a semiconductor element on the electrode pad by wire bonding to form a fifth semiconductor device unit;
A semiconductor on the electrode pad of a sixth two-layer board having electrode pads formed on at least the upper surface side, having wiring patterns on both surfaces of the insulating substrate, and connecting these wiring patterns with interlayer connection conductors Mounting the element by wire bonding to form a sixth semiconductor device unit;
A wiring pattern on the lower surface side of the sixth semiconductor device unit is placed on the laminated bumps of the fifth semiconductor device unit via an anisotropic conductive adhesive, and the laminated bumps are bonded by pressing and bonding under heating. And a step of bonding the wiring patterns. 積層バンプと配線パターンの接合に先立って、積層バンプ上に、Ａｕ層を形成する工程を具備することを特徴とする請求項１乃至４のいずれか1項記載の半導体装置の製造方法。  5. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming an Au layer on the laminated bump prior to joining of the laminated bump and the wiring pattern.
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