JP2003152161A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2003152161A JP2003152161A JP2002237124A JP2002237124A JP2003152161A JP 2003152161 A JP2003152161 A JP 2003152161A JP 2002237124 A JP2002237124 A JP 2002237124A JP 2002237124 A JP2002237124 A JP 2002237124A JP 2003152161 A JP2003152161 A JP 2003152161A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- device unit
- bump
- wiring pattern
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置とその製
造方法に係り、更に詳細には、半導体素子内蔵型の半導
体装置とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device with a built-in semiconductor element and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来より、複数の半導体装置ユニットを
三次元的に多段に配置した、いわゆるＴＣＰ（Tape Car
rier Package）型の半導体装置が知られている。図９は
代表的なＴＣＰ型半導体装置１００の断面図である。図
９に示したように、この半導体装置１００では、半導体
素子をＴＣＰパッケージに組み上げた二つのＴＣＰパッ
ケージ１１０，１２０を用意し、これらのＴＣＰパッケ
ージのアウターリード１１１，１２１を実装に適した所
定の長さにトリミングし、リフォーミングすることによ
り図９に示したようなＴＣＰ型半導体装置１００を製造
している。2. Description of the Related Art Conventionally, a so-called TCP (Tape Car) in which a plurality of semiconductor device units are three-dimensionally arranged in multiple stages
A carrier package) type semiconductor device is known. FIG. 9 is a sectional view of a typical TCP type semiconductor device 100. As shown in FIG. 9, in this semiconductor device 100, two TCP packages 110 and 120 in which semiconductor elements are assembled in a TCP package are prepared, and outer leads 111 and 121 of these TCP packages are provided in a predetermined manner suitable for mounting. A TCP type semiconductor device 100 as shown in FIG. 9 is manufactured by trimming to a length and reforming.
【０００３】ところで、図９に示したようなＴＣＰ型半
導体装置１００を製造するには、長尺のアウターリード
を配設するために高価な金型を必要とする。そのため、
製造コストが増大するという問題がある。By the way, in order to manufacture the TCP type semiconductor device 100 as shown in FIG. 9, an expensive mold is required to dispose a long outer lead. for that reason,
There is a problem that the manufacturing cost increases.
【０００４】また、図９に示したように、アウターリー
ド１１１，１２１が長尺であるため、ＴＣＰ型半導体装
置１００の体積が嵩張り、スペースを必要とするので集
積度を向上する上で支障となるという問題がある。Further, as shown in FIG. 9, since the outer leads 111 and 121 are long, the TCP type semiconductor device 100 has a large volume and requires a space, which is an obstacle to improving the degree of integration. There is a problem that becomes.
【０００５】[0005]
【発明が解決しようとする課題】上記したように、従来
の方法では、製造コストが増大したり集積度を向上させ
る上で支障があるという問題があった。As described above, the conventional methods have a problem in that the manufacturing cost increases and there is a problem in improving the degree of integration.
【０００６】本発明は上記従来の問題を解消するために
なされた発明である。即ち、本発明は、高価な製造設備
を必要とせず、しかも多層板表面全体に配線パターンを
形成して集積度を向上させることのできる半導体装置及
びその製造方法を提供することを目的とする。The present invention is an invention made to solve the above conventional problems. That is, an object of the present invention is to provide a semiconductor device which does not require expensive manufacturing equipment and can improve the degree of integration by forming a wiring pattern on the entire surface of the multilayer board, and a manufacturing method thereof.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、絶縁基板上に配線パターンを形成する工程
と、前記配線パターン上に素子実装用の実装バンプと、
積層用の積層バンプとを形成する工程と、前記実装バン
プを介して半導体素子を実装する工程と、前記積層バン
プ上に異方導電樹脂層を形成して第1の半導体装置ユニ
ットを形成する工程と、前記異方導電樹脂層上に、絶縁
基板の両面に配線パターンを備え一方の配線パターン上
に半導体素子が実装された第2の半導体装置ユニットを
重ね合わせる工程と、前記第1の半導体装置ユニットと
前記第2の半導体装置ユニットとを加熱下に加圧して前
記第1の半導体装置ユニットと前記第2の半導体装置ユニ
ットとを電気的に接続する工程とを具備することを特徴
とする。A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a wiring pattern on an insulating substrate, a mounting bump for mounting an element on the wiring pattern,
A step of forming a laminated bump for lamination, a step of mounting a semiconductor element via the mounting bump, and a step of forming an anisotropic conductive resin layer on the laminated bump to form a first semiconductor device unit. And a step of stacking a second semiconductor device unit having wiring patterns on both surfaces of an insulating substrate on the anisotropic conductive resin layer and having a semiconductor element mounted on one wiring pattern, the first semiconductor device A step of pressurizing the unit and the second semiconductor device unit under heating to electrically connect the first semiconductor device unit and the second semiconductor device unit.
【０００８】上記半導体装置の製造方法において、前記
実装バンプと積層バンプとを、前記絶縁基板の同じ側に
形成してもよい。In the above method of manufacturing a semiconductor device, the mounting bump and the laminated bump may be formed on the same side of the insulating substrate.
【０００９】上記半導体装置の製造方法において、前記
実装バンプと積層バンプとを、前記絶縁基板の反対側に
形成してもよい。In the above method of manufacturing a semiconductor device, the mounting bump and the laminated bump may be formed on the opposite side of the insulating substrate.
【００１０】本発明の他の半導体装置の製造方法は、絶
縁基板上に配線パターンを形成する工程と、前記配線パ
ターンと半導体素子とをワイヤボンディングにより実装
する工程と、前記配線パターン上に積層用の積層バンプ
を形成する工程と、前記積層バンプ上に異方導電樹脂層
を形成して第1の半導体装置ユニットを形成する工程
と、前記異方導電樹脂層上に、絶縁基板の両面に配線パ
ターンを備え一方の配線パターン上に半導体素子が実装
された第2の半導体装置ユニットを重ね合わせる工程
と、前記第1の半導体装置ユニットと前記第2の半導体装
置ユニットとを加熱下に加圧して前記第1の半導体装置
ユニットと前記第2の半導体装置ユニットとを電気的に
接続する工程とを具備することを特徴とする。Another method of manufacturing a semiconductor device according to the present invention is a step of forming a wiring pattern on an insulating substrate, a step of mounting the wiring pattern and a semiconductor element by wire bonding, and a step of stacking on the wiring pattern. Forming a laminated bump, a step of forming an anisotropic conductive resin layer on the laminated bump to form a first semiconductor device unit, and wiring on both sides of an insulating substrate on the anisotropic conductive resin layer. A step of stacking a second semiconductor device unit in which a semiconductor element is mounted on one wiring pattern having a pattern, and pressing the first semiconductor device unit and the second semiconductor device unit under heating. And a step of electrically connecting the first semiconductor device unit and the second semiconductor device unit.
【００１１】本発明の半導体装置は、２層板上に半導体
素子が実装された一の半導体装置ユニットと、前記一の
半導体装置ユニットの上部に配設された他の半導体装置
ユニットと、前記一の半導体装置ユニットと前記他の半
導体装置ユニットとの間に介挿され、前記一の半導体装
置ユニット上面の配線パターンと前記他の半導体装置ユ
ニット下面の配線パターンとを電気的に接続する導体バ
ンプと、前記導体バンプの周囲を包囲する樹脂部とを具
備することを特徴とする。According to another aspect of the present invention, there is provided a semiconductor device including one semiconductor device unit in which a semiconductor element is mounted on a two-layer plate, another semiconductor device unit disposed above the one semiconductor device unit, and the other semiconductor device unit. Conductor bumps that are interposed between the semiconductor device unit and the other semiconductor device unit and electrically connect the wiring pattern on the upper surface of the one semiconductor device unit and the wiring pattern on the lower surface of the other semiconductor device unit. And a resin portion that surrounds the periphery of the conductor bump.
【００１２】上記半導体装置において、前記半導体素子
は導電ペーストバンプを介して実装されていてもよい。In the above semiconductor device, the semiconductor element may be mounted via a conductive paste bump.
【００１３】上記半導体装置において、前記導電ペース
トバンプが、表面にＮｉ層及びその上のＡｕ層を備えて
いてもよい。また、上記半導体装置において、前記半導
体素子が金属バンプを介して実装されていてもよい。更
に、上記半導体装置において、前記半導体素子が金線を
介して実装されていてもよい。In the above semiconductor device, the conductive paste bump may include a Ni layer and an Au layer on the Ni layer on the surface. Further, in the above semiconductor device, the semiconductor element may be mounted via a metal bump. Further, in the above semiconductor device, the semiconductor element may be mounted via a gold wire.
【００１４】本発明では、半導体装置ユニットを積層バ
ンプを介して多段に積層するので、高価な製造設備を必
要としない。また、積層バンプ自体が小型であるので、
積層するのに大きなスペースを必要とせず、集積度の高
い半導体装置を得ることができる。According to the present invention, since the semiconductor device units are laminated in multiple stages via the laminated bumps, expensive manufacturing equipment is not required. Also, since the laminated bump itself is small,
A large space is not required for stacking, and a highly integrated semiconductor device can be obtained.
【００１５】[0015]
【発明の実施の形態】（第１の実施の形態）以下、本発
明の第１の実施の形態に係る半導体装置の製造について
説明する。図１及び図２は本実施形態に係る半導体装置
の製造方法のフローチャートであり、図３、図４及び図
５は製造途中の本実施形態に係る半導体装置の断面図で
ある。BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) Manufacturing of a semiconductor device according to a first embodiment of the present invention will be described below. 1 and 2 are flowcharts of the method for manufacturing a semiconductor device according to the present embodiment, and FIGS. 3, 4 and 5 are cross-sectional views of the semiconductor device according to the present embodiment during manufacturing.
【００１６】本実施形態に係る半導体装置を製造するに
は、まず絶縁基板の両面に配線パターンを形成した、い
わゆる２層板を用意する。この２層板の製造方法のフロ
ーチャートを示したのが図１であり、製造途中の２層板
の断面図を示したのが図３である。この２層板を製造す
るには、最初に図３（ａ）に示したように銅箔などの導
体板１０を用意する。この導体板１０の上に印刷技法を
用いて導体バンプ２０，２０…を形成する。In order to manufacture the semiconductor device according to this embodiment, first, a so-called two-layer board having wiring patterns formed on both surfaces of an insulating substrate is prepared. FIG. 1 shows a flowchart of the method for manufacturing the two-layer board, and FIG. 3 shows a cross-sectional view of the two-layer board in the process of being manufactured. To manufacture this two-layer board, first, as shown in FIG. 3A, a conductor board 10 such as a copper foil is prepared. The conductor bumps 20, 20, ... Are formed on the conductor plate 10 by using a printing technique.
【００１７】この導体バンプ２０，２０，…の形成方法
としては、例えば、バンプ形成部分に貫通孔を設けたマ
スキングを施し（ステップ１）、この貫通孔内に導電性
ペースト、例えば銀などの金属微粒子をエポキシ樹脂の
ような液状樹脂中に分散させたペースト状組成物を充填
し（ステップ２）、マスキング上面からスキージ（ステ
ップ３）し、前記マスキングを剥離する（ステップ４）
ことからなる方法が挙げられる。このようにして、図３
（ｂ）に示したような、略円錐形の導体バンプ２０，２
０，…を形成した後、この導体バンプ２０，２０，…を
乾燥させ、硬化する（ステップ５）。As a method of forming the conductor bumps 20, 20, ..., For example, masking is performed by providing a through hole in a bump forming portion (step 1), and a conductive paste, for example, a metal such as silver is provided in the through hole. A paste composition in which fine particles are dispersed in a liquid resin such as an epoxy resin is filled (step 2), a squeegee is applied from the upper surface of the masking (step 3), and the masking is removed (step 4).
A method consisting of In this way, FIG.
The substantially conical conductor bumps 20 and 2 as shown in FIG.
After forming 0, ..., The conductor bumps 20, 20, ... Are dried and cured (step 5).
【００１８】次に図３（ｃ）に示したように、導体バン
プ２０，２０，…の上にプリプレグ（絶縁基板前駆体）
３０、すなわちガラス繊維マットのような補強材料中に
エポキシ樹脂などの絶縁性樹脂を含浸させたものを重
ね、更にこのプリプレグ３０の上にもう１枚の銅箔など
の導体板４０を重ね合わせ（ステップ６）、この状態で
ヒートプレス、すなわち加熱下に加圧する（ステップ
７）。Next, as shown in FIG. 3C, a prepreg (insulating substrate precursor) is formed on the conductor bumps 20, 20, ....
30, that is, a reinforcing material such as a glass fiber mat impregnated with an insulating resin such as an epoxy resin is stacked, and another conductor plate 40 such as a copper foil is stacked on the prepreg 30 ( Step 6), in this state, heat press, that is, pressurizing under heating (step 7).
【００１９】このヒートプレスすることにより導体バン
プ２０，２０，…はプリプレグ３０を貫通して導体板１
０と導体板４０との間が電気的に接続されると同時にプ
リプレグ３０が硬化して、図３（ｄ）に示したような、
２層型プリント配線基板５０が得られる。この２層型配
線基板５０表面の導体板１０，４０に例えばエッチング
処理等によるパターニング（ステップ８）を施すことに
より配線パターン１１，４１ａが形成された２層板５２
が形成される。By this heat pressing, the conductor bumps 20, 20, ...
0 and the conductor plate 40 are electrically connected, the prepreg 30 is cured at the same time, and as shown in FIG.
A two-layer printed wiring board 50 is obtained. By patterning the conductor plates 10 and 40 on the surface of the two-layer type wiring board 50 by, for example, etching treatment (step 8), the two-layer board 52 having the wiring patterns 11 and 41a is formed.
Is formed.
【００２０】次いで２層板５２上の配線パターン４１ａ
のうち、図４（ｆ）に示すように、半導体素子の電極に
対応する位置に形成した電極パッド４１ｂ，４１ｂ，…
上に導電ペーストバンプとして、銀ペーストバンプのよ
うな実装バンプ６０，６０，…を形成する。この実装バ
ンプ６０，６０，…の形成方法は上記導体バンプ２０，
２０，…の形成方法と実質的に同じである。Next, the wiring pattern 41a on the two-layer board 52
Of these, as shown in FIG. 4F, electrode pads 41b, 41b, ... Formed at positions corresponding to the electrodes of the semiconductor element.
Mounting bumps 60, 60, ... Like silver paste bumps are formed on the top as conductive paste bumps. The method of forming the mounting bumps 60, 60, ...
This is substantially the same as the method of forming 20 ,.
【００２１】すなわち、バンプ形成部分に貫通孔を設け
たマスキングを施し（ステップ１ａ）、この貫通孔内に
導電性ペースト、例えば銀などの金属微粒子をエポキシ
樹脂のような液状樹脂中に分散させたペースト状組成物
を充填し（ステップ２ａ）、マスキング上面からスキー
ジ（ステップ３ａ）し、前記マスキングを剥離する（ス
テップ４ａ）ことからなる方法である。That is, masking was performed by forming a through hole in the bump forming portion (step 1a), and a conductive paste, for example, metal fine particles such as silver was dispersed in a liquid resin such as an epoxy resin in the through hole. It is a method comprising filling a paste composition (step 2a), squeegeeing from the upper surface of the masking (step 3a), and peeling off the masking (step 4a).
【００２２】但し、ここで形成する実装バンプ６０，６
０，…の大きさは、高さが１５〜３０μｍ、底面直径が
５０〜８０μｍである。これは後述する半導体素子７０
の大きさに対応させるためである。実装バンプ６０，６
０，…の大きさの更に好ましい範囲は、高さが１８〜２
２μｍ、底面直径が６５〜７５μｍである。However, the mounting bumps 60, 6 formed here
The size of 0, ... Has a height of 15 to 30 μm and a bottom diameter of 50 to 80 μm. This is a semiconductor device 70 described later.
This is to correspond to the size of. Mounting bumps 60, 6
The more preferable range of the size of 0, ... is 18 to 2 in height.
The diameter is 2 μm and the bottom diameter is 65 to 75 μm.
【００２３】マスキングを剥離して実装バンプ６０，６
０，…を形成した後、配線パターン４１ａ，４１ａ，…
上に積層バンプとして銀ペーストバンプのような積層バ
ンプ８０，８０，…を形成する。この積層バンプ８０，
８０，…の形成方法は上記実装バンプ６０，６０，…の
形成方法と同じである。The masking is removed to remove the mounting bumps 60, 6
After forming 0, ..., The wiring patterns 41a, 41a ,.
As the laminated bumps, laminated bumps 80, 80, ... Such as silver paste bumps are formed. This laminated bump 80,
The forming method of 80, ... Is the same as the forming method of the mounting bumps 60, 60 ,.
【００２４】即ち、バンプ形成部分に貫通孔を設けたマ
スキングを施し（ステップ５ａ）、この貫通孔内に導電
性ペースト、例えば銀などの金属微粒子をエポキシ樹脂
のような液状樹脂中に分散させたペースト状組成物を充
填し（ステップ６ａ）、マスキング上面からスキージ
（ステップ７ａ）し、前記マスキングを剥離する（ステ
ップ８ａ）ことからなる方法である。That is, masking was performed by providing a through hole in the bump forming portion (step 5a), and a conductive paste, for example, metal fine particles such as silver was dispersed in a liquid resin such as an epoxy resin in the through hole. It is a method comprising filling the paste composition (step 6a), squeegeeing from the upper surface of the masking (step 7a), and peeling off the masking (step 8a).
【００２５】但し、ここで形成する積層バンプ８０，８
０，…の大きさは、高さが３５０〜５００μｍ、底面直
径が３００〜４００μｍである。これは層間接続の信頼
性を向上させるためと作業上の必要性に対応させるため
である。積層バンプ８０，８０，…の大きさの更に好ま
しい範囲は、高さが４００〜４６０μｍ、底面直径が３
３０〜３７０μｍである。However, the laminated bumps 80, 8 formed here
The size of 0, ... Has a height of 350 to 500 μm and a bottom diameter of 300 to 400 μm. This is to improve the reliability of the interlayer connection and to meet the work need. More preferably, the size of the laminated bumps 80, 80, ... Is 400 to 460 μm in height and 3 in bottom diameter.
It is 30 to 370 μm.
【００２６】次にマスキング剥離後、実装バンプ６０，
６０，…及び積層バンプ８０，８０，…を硬化させ（ス
テップ９ａ）、然る後に、例えば電解メッキや無電解メ
ッキなどのＮｉメッキ処理を施すことにより、実装バン
プ６０，６０，…、その底部の電極パッド４１ｂ、積層
バンプ８０，８０，…、及びその底部の配線パターン４
１ａ表面に図４（ｈ）に示したようなバリアメタル層と
してのＮｉ層６１，８１を形成する（ステップ１０
ａ）。次いでＮｉ層６１，８１の上からＡｕメッキ処理
（ステップ１１ａ）を施すことによりＡｕ層６２，８２
を形成する。こうして図４（ｉ）に示したようなバンプ
付基板５２Ａが得られる。Next, after removing the masking, the mounting bumps 60,
, And the laminated bumps 80, 80, ... (Step 9a), followed by Ni plating such as electrolytic plating or electroless plating to mount the bumps 60, 60 ,. Electrode pad 41b, laminated bumps 80, 80, ..., And wiring pattern 4 on the bottom thereof.
Ni layers 61 and 81 as barrier metal layers as shown in FIG. 4H are formed on the surface of 1a (step 10).
a). Then, Au plating treatment (step 11a) is performed on the Ni layers 61 and 81 to form Au layers 62 and 82.
To form. In this way, the bumped substrate 52A as shown in FIG. 4I is obtained.
【００２７】次にこうして得られたバンプ付基板５２Ａ
の実装バンプ６０，６０，…形成面上に図４（ｊ）に示
したように、ＡＣＦ（異方性導電接着剤層）６３を形成
し、電極パッド４１ｂ，４１ｂ，…に対して電極板７
１，７１，…が対向するように半導体素子７０を位置合
わせする（ステップ１２ａ）。Next, the bumped substrate 52A thus obtained
As shown in FIG. 4 (j), ACF (anisotropic conductive adhesive layer) 63 is formed on the mounting bumps 60, 60, ... Forming surface of the mounting bumps 60, 60 ,. 7
The semiconductor element 70 is aligned so that 1, 71, ... Are opposed to each other (step 12a).
【００２８】次いでこの状態で半導体素子７０とバンプ
付基板５２Ａとを加圧すると図５（ｋ）に示したように
実装バンプ６０，６０，…がＡＣＦ（異方性導電接着剤
層）６３を貫通し、電極板７１，７１，…に加圧される
（ステップ１３ａ）。このとき実装バンプ６０，６０，
…の表面にはＡｕ層６２，６２，…が形成されており、
電極板７１，７１，…はＡｌで出来ているので、実装バ
ンプ６０，６０，…と電極板７１，７１，…との間には
Ａｌ−Ａｕ接合が形成され、電極パッド４１ｂ，４１
ｂ，…と電極板７１，７１，…との間がＡｕ層６２，Ｎ
ｉ層６１，実装バンプ６０，ＡＣＦ（異方性導電接着剤
層）６３を介して電気的に接合される。こうして図５
（ｋ）に示したような半導体素子７０が実装された半導
体装置ユニット５３が得られる。Then, when the semiconductor element 70 and the substrate with bumps 52A are pressed in this state, the mounting bumps 60, 60, ... Form an ACF (anisotropic conductive adhesive layer) 63 as shown in FIG. 5 (k). It penetrates and is pressurized by the electrode plates 71, 71, ... (Step 13a). At this time, the mounting bumps 60, 60,
Au layers 62, 62, ... Are formed on the surface of
Since the electrode plates 71, 71, ... Are made of Al, an Al-Au joint is formed between the mounting bumps 60, 60, ... And the electrode plates 71, 71 ,.
, and the electrode plates 71, 71, ... Between the Au layers 62, N
It is electrically joined via the i layer 61, the mounting bumps 60, and the ACF (anisotropic conductive adhesive layer) 63. Thus, FIG.
The semiconductor device unit 53 in which the semiconductor element 70 as shown in (k) is mounted is obtained.
【００２９】次にこうして得られた半導体装置ユニット
５３の積層バンプ８０，８０，…周辺を包囲するように
ＡＣＦ（異方性導電接着剤層）６４を形成し、このＡＣ
Ｆ（異方性導電接着剤層）６４を形成した半導体装置ユ
ニット５３の上に他の半導体装置ユニット５４を図５
（ｌ）のようにマウンタ９０を用いて位置合わせする
（ステップ１６ａ）。Next, an ACF (anisotropic conductive adhesive layer) 64 is formed so as to surround the periphery of the laminated bumps 80, 80, ... Of the semiconductor device unit 53 thus obtained.
Another semiconductor device unit 54 is formed on the semiconductor device unit 53 on which the F (anisotropic conductive adhesive layer) 64 is formed, as shown in FIG.
Positioning is performed using the mounter 90 as in (l) (step 16a).
【００３０】ここで他の半導体装置ユニット５４は、積
層バンプ８０，８０，…を形成しないこと以外は上記半
導体装置ユニット５３と同様の工程により形成した基板
である。Here, the other semiconductor device unit 54 is a substrate formed by the same process as the semiconductor device unit 53 except that the laminated bumps 80, 80, ... Are not formed.
【００３１】次いで、この状態で半導体装置ユニット５
３、及び他の半導体装置ユニット５４をヒートプレスに
かけて加熱下に加圧すると（ステップ１７ａ）、図５
（ｍ）に示したように、半導体装置ユニット５３の積層
バンプ８０，８０，…がＡＣＦ６４を貫通して他の半導
体装置ユニット５４と半導体装置ユニット５３との間を
電気的に接合する。このようにして、いわゆる４層配線
型の立体配置型半導体装置１が得られる。Next, in this state, the semiconductor device unit 5
3 and the other semiconductor device unit 54 are subjected to heat pressurization under heating (step 17a), as shown in FIG.
As shown in (m), the laminated bumps 80, 80, ... Of the semiconductor device unit 53 penetrate the ACF 64 to electrically bond the other semiconductor device unit 54 and the semiconductor device unit 53. In this way, a so-called four-layer wiring type three-dimensionally arranged semiconductor device 1 is obtained.
【００３２】以上説明したように、本実施形態に係る半
導体装置１では、半導体素子７０が実装された半導体装
置ユニット５３，５４が積層バンプ８０とＡＣＦ６４と
により多段に積層されているので、高価な製造設備を用
いることなく多段積層型の半導体装置を安価に製造する
ことができる。As described above, in the semiconductor device 1 according to this embodiment, the semiconductor device units 53 and 54 on which the semiconductor element 70 is mounted are stacked in multiple stages by the stacked bumps 80 and the ACF 64, which is expensive. A multi-stage stacked semiconductor device can be manufactured at low cost without using manufacturing equipment.
【００３３】また、半導体装置ユニット間を接合する積
層バンプ８０，８０，…は非常にコンパクトなものであ
るので、半導体装置１を小型化することができ、集積度
の高い半導体装置を得ることができる。Further, since the laminated bumps 80, 80, ... Joining the semiconductor device units are very compact, the semiconductor device 1 can be miniaturized and a highly integrated semiconductor device can be obtained. it can.
【００３４】（第２の実施の形態）以下、本発明の第２
の実施の形態に係る半導体装置の製造について説明す
る。図６は製造途中の本実施形態に係る半導体装置の断
面図である。(Second Embodiment) The second embodiment of the present invention will be described below.
Manufacturing of the semiconductor device according to the embodiment will be described. FIG. 6 is a cross-sectional view of the semiconductor device according to the present embodiment which is being manufactured.
【００３５】本実施形態に係る半導体装置では、上記第
１の実施形態において、積層バンプを半導体素子とは反
対側の面に配設した構造とした。すなわち本実施形態で
は、図６（ｋ）に示したように、半導体装置ユニット５
３ａ上において半導体素子７０と反対側（下面側）に積
層バンプ８０ａ，８０ａ，…を形成する。この半導体装
置ユニット５３ａを用いて半導体装置を形成するには、
図６（ｌ）に示したような他の半導体装置ユニット５４
ａ上面の配線パターン上にＡＣＦ６４を形成し、マウン
タ９０で半導体装置ユニット５３ａを位置決めし、図６
（ｌ）に示した状態で半導体装置ユニット５３ａと半導
体装置ユニット５４ａとをヒートプレスすることによ
り、図６（ｍ）に示したような二段積層型の半導体装置
１ａが得られる。In the semiconductor device according to the present embodiment, the laminated bump is arranged on the surface opposite to the semiconductor element in the first embodiment. That is, in this embodiment, as shown in FIG.
The laminated bumps 80a, 80a, ... Are formed on the side (lower surface side) opposite to the semiconductor element 70 on 3a. To form a semiconductor device using this semiconductor device unit 53a,
Another semiconductor device unit 54 as shown in FIG.
ACF 64 is formed on the wiring pattern on the upper surface of a, and the semiconductor device unit 53a is positioned by the mounter 90.
By heat-pressing the semiconductor device unit 53a and the semiconductor device unit 54a in the state shown in (l), the two-stage stacked semiconductor device 1a as shown in FIG. 6 (m) is obtained.
【００３６】（第３の実施の形態）以下、本発明の第３
の実施の形態に係る半導体装置の製造について説明す
る。図７は製造途中の本実施形態に係る半導体装置の断
面図である。(Third Embodiment) The third embodiment of the present invention will be described below.
Manufacturing of the semiconductor device according to the embodiment will be described. FIG. 7 is a cross-sectional view of the semiconductor device according to the present embodiment which is being manufactured.
【００３７】本実施形態に係る半導体装置では、上記第
１の実施形態において、半導体素子としてフェイスダウ
ン型のフリップチップ半導体素子７０を用いる代わり
に、フェイスアップ型のワイヤボンディング半導体素子
７２を実装した半導体装置ユニット５３ｂを用いて半導
体装置を作成した。In the semiconductor device according to the present embodiment, in the first embodiment described above, instead of using the face-down type flip-chip semiconductor element 70 as the semiconductor element, a face-up type wire bonding semiconductor element 72 is mounted on the semiconductor device. A semiconductor device was created using the device unit 53b.
【００３８】すなわち本実施形態では、図７（ｋ）に示
したように、基板上にワイヤボンディング型の半導体素
子７２がフェイスアップで配設されており、基板上の電
極パッド４１ｂと半導体素子７２の電極７３との間は金
線７４を介して接続されている。That is, in this embodiment, as shown in FIG. 7K, the wire bonding type semiconductor element 72 is arranged face up on the substrate, and the electrode pad 41b and the semiconductor element 72 on the substrate are arranged. The electrode 73 is connected via a gold wire 74.
【００３９】この半導体装置ユニット５３ｂを用いて半
導体装置を形成するには、図７（ｌ）に示したようにこ
の半導体装置ユニット５３ｂの積層バンプ８０ｂ周辺を
包囲するようにＡＣＦ６４を形成し、マウンタ９０で他
の半導体装置ユニット５４ｂを位置決めし、図７（ｌ）
に示した状態で半導体装置ユニット５３ｂと半導体装置
ユニット５４ｂとをヒートプレスすることにより、図７
（ｍ）に示したような二段積層型の半導体装置１ｂが得
られる。To form a semiconductor device using this semiconductor device unit 53b, an ACF 64 is formed so as to surround the periphery of the laminated bump 80b of this semiconductor device unit 53b as shown in FIG. The other semiconductor device unit 54b is positioned at 90, and as shown in FIG.
By heat-pressing the semiconductor device unit 53b and the semiconductor device unit 54b in the state shown in FIG.
A two-layer stacked semiconductor device 1b as shown in (m) is obtained.
【００４０】（第４の実施の形態）以下、本発明の第４
の実施の形態に係る半導体装置について説明する。図８
は本実施形態に係る半導体装置１ｃの断面図である。(Fourth Embodiment) The fourth embodiment of the present invention will be described below.
A semiconductor device according to the embodiment will be described. Figure 8
FIG. 4 is a cross-sectional view of a semiconductor device 1c according to this embodiment.
【００４１】図８に示したように、本実施形態に係る半
導体装置１ｃでは、前記第１の実施の形態の半導体装置
ユニット５４と同様の半導体装置ユニット５４ｃ，５４
ｄ，５４ｅを三段に積み上げ、積層バンプ８０，８０ｄ
及びＡＣＦ６４，６４ｄを介して半導体装置ユニット５
４ｃ，５４ｄ，５４ｅの間を電気的に接続した構成とし
た。このように多段に積み上げても、積層バンプ８０，
８０ｄ自体がコンパクトであるので、半導体装置そのも
のが嵩高くなることがなく、集積度の高い半導体装置を
得ることができる。As shown in FIG. 8, in the semiconductor device 1c according to the present embodiment, semiconductor device units 54c and 54 similar to the semiconductor device unit 54 of the first embodiment.
d, 54e are stacked in three layers to form laminated bumps 80, 80d
And the semiconductor device unit 5 via the ACFs 64 and 64d.
4c, 54d and 54e are electrically connected. Even when stacked in multiple stages like this, the laminated bumps 80,
Since 80d itself is compact, the semiconductor device itself does not become bulky and a highly integrated semiconductor device can be obtained.
【００４２】[0042]
【発明の効果】本発明によれば、半導体装置ユニットを
積層バンプを介して多段に積層するので、高価な製造設
備を必要としない。また、積層バンプ自体が小型である
ので、積層するのに大きなスペースを必要とせず、集積
度の高い半導体装置を得ることができる。According to the present invention, since the semiconductor device units are stacked in multiple stages via the stacked bumps, expensive manufacturing equipment is not required. Moreover, since the laminated bump itself is small, a large space is not required for laminating, and a semiconductor device having a high degree of integration can be obtained.
【図１】第１の実施形態に係る半導体装置の製造方法の
フローチャートである。FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to a first embodiment.
【図２】第１の実施形態に係る半導体装置の製造方法の
フローチャートである。FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to the first embodiment.
【図３】第１の実施形態に係る半導体装置の製造途中の
ものの断面図である。FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment which is being manufactured.
【図４】第１の実施形態に係る半導体装置の製造途中の
ものの断面図である。FIG. 4 is a cross-sectional view of the semiconductor device according to the first embodiment which is being manufactured.
【図５】第１の実施形態に係る半導体装置の製造途中の
ものの断面図である。FIG. 5 is a sectional view of the semiconductor device according to the first embodiment which is being manufactured.
【図６】第２の実施形態に係る半導体装置の製造途中の
ものの断面図である。FIG. 6 is a sectional view of a semiconductor device in the process of being manufactured according to a second embodiment.
【図７】第３の実施形態に係る半導体装置の製造途中の
ものの断面図である。FIG. 7 is a sectional view of a semiconductor device in the process of being manufactured according to a third embodiment.
【図８】第４の実施形態に係る半導体装置の製造途中の
ものの断面図である。FIG. 8 is a sectional view of a semiconductor device in the process of being manufactured according to a fourth embodiment.
【図９】従来の半導体装置の断面図である。FIG. 9 is a cross-sectional view of a conventional semiconductor device.
１…半導体装置、５２…２層板、４１ａ…配線パター
ン、４１ｂ…電極パッド、６０…実装バンプ、６１…Ｎ
ｉ層（バリアメタル層）、６２…Ａｕ層、６３…ＡＣ
Ｆ、６４…ＡＣＦ、７０…半導体素子、７１…電極板、
８０…積層バンプ。DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 52 ... Two-layer board, 41a ... Wiring pattern, 41b ... Electrode pad, 60 ... Mounting bump, 61 ... N
i layer (barrier metal layer), 62 ... Au layer, 63 ... AC
F, 64 ... ACF, 70 ... Semiconductor element, 71 ... Electrode plate,
80 ... Stacked bumps.
Claims (7)
程と、前記配線パターン上に素子実装用の実装バンプと
積層用の積層バンプとを形成する工程と、 前記実装バンプを介して半導体素子を実装する工程と、 前記積層バンプ上に異方導電樹脂層を形成して第1の半
導体装置ユニットを形成する工程と、 前記異方導電樹脂層上に、絶縁基板の両面に配線パター
ンを備え一方の配線パターン上に半導体素子が実装され
た第2の半導体装置ユニットを重ね合わせる工程と、 前記第1の半導体装置ユニットと前記第2の半導体装置ユ
ニットとを加熱下に加圧して前記第1の半導体装置ユニ
ットと前記第2の半導体装置ユニットとを電気的に接続
する工程とを具備することを特徴とする半導体装置の製
造方法。1. A step of forming a wiring pattern on an insulating substrate, a step of forming a mounting bump for mounting an element and a laminated bump for stacking on the wiring pattern, and a semiconductor element via the mounting bump. A step of mounting, a step of forming an anisotropic conductive resin layer on the laminated bump to form a first semiconductor device unit, and a wiring pattern provided on both surfaces of an insulating substrate on the anisotropic conductive resin layer. A step of stacking a second semiconductor device unit in which a semiconductor element is mounted on the wiring pattern, and the first semiconductor device unit and the second semiconductor device unit are heated and pressed to heat the first semiconductor device unit. A method of manufacturing a semiconductor device, comprising the step of electrically connecting a semiconductor device unit and the second semiconductor device unit.
であって、前記実装バンプと積層バンプとを、前記絶縁
基板の同じ側に形成することを特徴とする半導体装置の
製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the mounting bump and the laminated bump are formed on the same side of the insulating substrate.
であって、前記実装バンプと積層バンプとを、前記絶縁
基板の反対側に形成することを特徴とする半導体装置の
製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the mounting bump and the laminated bump are formed on the opposite side of the insulating substrate.
程と、 前記配線パターンと半導体素子とをワイヤボンディング
により実装する工程と、 前記配線パターン上に積層用の積層バンプを形成する工
程と、 前記積層バンプ上に異方導電樹脂層を形成して第1の半
導体装置ユニットを形成する工程と、 前記異方導電樹脂層上に、絶縁基板の両面に配線パター
ンを備え一方の配線パターン上に半導体素子が実装され
た第2の半導体装置ユニットを重ね合わせる工程と、 前記第1の半導体装置ユニットと前記第2の半導体装置ユ
ニットとを加熱下に加圧して前記第1の半導体装置ユニ
ットと前記第2の半導体装置ユニットとを電気的に接続
する工程とを具備することを特徴とする半導体装置の製
造方法。4. A step of forming a wiring pattern on an insulating substrate, a step of mounting the wiring pattern and a semiconductor element by wire bonding, a step of forming a laminated bump for lamination on the wiring pattern, Forming an anisotropic conductive resin layer on the laminated bumps to form a first semiconductor device unit; and providing wiring patterns on both surfaces of an insulating substrate on the anisotropic conductive resin layer and forming a semiconductor on one wiring pattern. A step of stacking a second semiconductor device unit on which an element is mounted, and pressing the first semiconductor device unit and the second semiconductor device unit under heating to heat the first semiconductor device unit and the first semiconductor device unit. And a step of electrically connecting the semiconductor device unit to the second semiconductor device unit.
半導体装置ユニットと、 前記一の半導体装置ユニットの上部に配設された他の半
導体装置ユニットと、 前記一の半導体装置ユニットと前記他の半導体装置ユニ
ットとの間に介挿され、前記一の半導体装置ユニット上
面の配線パターンと前記他の半導体装置ユニット下面の
配線パターンとを電気的に接続する導体バンプと、 前記導体バンプの周囲を包囲する樹脂部とを具備するこ
とを特徴とする半導体装置。5. A semiconductor device unit in which a semiconductor element is mounted on a two-layer board, another semiconductor device unit disposed above the one semiconductor device unit, and the one semiconductor device unit. A conductor bump that is interposed between the other semiconductor device unit and electrically connects the wiring pattern on the upper surface of the one semiconductor device unit and the wiring pattern on the lower surface of the other semiconductor device unit; A semiconductor device comprising: a resin portion surrounding the periphery.
前記半導体素子が導電ペーストバンプを介して実装され
ていることを特徴とする半導体装置。6. The semiconductor device according to claim 5, wherein:
A semiconductor device, wherein the semiconductor element is mounted via a conductive paste bump.
前記導電ペーストバンプが、表面にＮｉ層及びその上の
Ａｕ層を備えていることを特徴とする半導体装置。7. The semiconductor device according to claim 6, wherein:
A semiconductor device, wherein the conductive paste bump is provided with a Ni layer and an Au layer on the Ni layer on the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002237124A JP4040388B2 (en) | 2001-08-31 | 2002-08-15 | Manufacturing method of semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001-264473 | 2001-08-31 | ||
| JP2001264473 | 2001-08-31 | ||
| JP2002237124A JP4040388B2 (en) | 2001-08-31 | 2002-08-15 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003152161A true JP2003152161A (en) | 2003-05-23 |
| JP4040388B2 JP4040388B2 (en) | 2008-01-30 |
Family
ID=26621457
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002237124A Expired - Fee Related JP4040388B2 (en) | 2001-08-31 | 2002-08-15 | Manufacturing method of semiconductor device |
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| Country | Link |
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| JP (1) | JP4040388B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007123705A (en) * | 2005-10-31 | 2007-05-17 | Elpida Memory Inc | Laminated semiconductor device and its manufacturing method |
| JP2012119574A (en) * | 2010-12-02 | 2012-06-21 | J Devices:Kk | Semiconductor device and manufacturing method of the same |
-
2002
- 2002-08-15 JP JP2002237124A patent/JP4040388B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007123705A (en) * | 2005-10-31 | 2007-05-17 | Elpida Memory Inc | Laminated semiconductor device and its manufacturing method |
| JP2012119574A (en) * | 2010-12-02 | 2012-06-21 | J Devices:Kk | Semiconductor device and manufacturing method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4040388B2 (en) | 2008-01-30 |
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