JP4037534B2 - Printed wiring board and manufacturing method thereof - Google Patents

Description

【００２０】
このような無電解めっき液から析出する多孔質なCu−Ni−Ｐ合金は、その表面が図21に示すような外観を有するものであり、その微孔の数は、１cm² 当たり 100,000〜1,000,000 の範囲内にあり、一般には 3,000,000〜300,000,000 の範囲に含まれるものである。また、その微孔の径は、0.01〜100 μｍの範囲内、一般には 0.1〜10μｍの範囲に含まれるものである。
【００２１】
本発明では、さらにこの粗化層表面をイオン化傾向が銅より大きくチタン以下である金属層もしくは貴金属層にて被覆することが望ましい。特に、スズの場合は、ホウフッ化スズ−チオ尿素、塩化スズ−チオ尿素液を使用する。この場合、Cu−Snの置換反応により 0.1〜２μｍ程度のSn層が形成される。また貴金属の場合は、スパッタや蒸着などの方法が採用できる。
【００２２】
本発明では、上記導体回路上に形成する層間絶縁層として無電解めっき用接着剤を用いることが望ましい。この無電解めっき用接着剤は、硬化処理された酸あるいは酸化剤に可溶性の耐熱性樹脂粒子が、酸あるいは酸化剤に難溶性の未硬化の耐熱性樹脂中に分散されてなるものが最適である。酸あるいは酸化剤の溶液で処理することにより、耐熱性樹脂粒子が溶解除去されて、この接着剤層の表面に蛸つぼ状のアンカーからなる粗化面を形成できるからである。
【００２３】
上記無電解めっき用接着剤において、特に硬化処理された前記耐熱性樹脂粒子としては、▲１▼平均粒径が10μｍ以下の耐熱性樹脂粉末、▲２▼平均粒子径が相対的に大きな粒子と平均粒子径が相対的に小さな粒子を混合した粒子が望ましい。これらは、より複雑なアンカーを形成できるからである。使用できる耐熱性樹脂としては、エポキシ樹脂、ポリイミド樹脂、エポキシ樹脂と熱可塑性樹脂との複合体などが挙げられる。複合させる熱可塑性樹脂としては、ポエリエーテルスルホン（ＰＥＳ）などが挙げられる。また、酸や酸化剤の溶液に溶解する耐熱性樹脂粒子としては、エポキシ樹脂（特にアミン系硬化剤で硬化させたエポキシ樹脂がよい）、アミノ樹脂がある。
また、本発明で使用されるソルダーレジストとしては、エポキシ樹脂アクリレートおよびイミダゾール硬化剤からなるものを使用できる。
【００２４】
次に、本発明にかかるプリント配線板を製造する一方法について説明する。
(1) まず、コア基板の表面に内層銅パターンを形成した配線基板を作製する。
このコア基板への銅パターンの形成は、銅張積層板をエッチングして行うか、あるいは、ガラスエポキシ基板やポリイミド基板、セラミック基板、金属基板などの基板に無電解めっき用接着剤層を形成し、この接着剤層表面を粗化して粗化面とし、ここに無電解めっきを施して行う方法がある。
なお、コア基板には、スルーホールが形成され、このスルーホールを介して表面と裏面の配線層を電気的に接続することができる。
また、スルーホールおよびコア基板の導体回路間には樹脂が充填されて、平滑性を確保してもよい。
特に本発明では、コア基板の導体回路表面、スルーホールのランド表面には、多孔質な銅−ニッケル−リンからなる合金粗化層を形成する。
【００２５】
(2) 次に、前記(1) で作製した配線基板の上に、層間樹脂絶縁層を形成する。特に本発明では、層間樹脂絶縁材として前述した無電解めっき用接着剤を用いることが望ましい。
(3) 形成した無電解めっき用接着剤層を乾燥した後、必要に応じてバイアホール形成用開口を設ける。感光性樹脂の場合は、露光、現像してから熱硬化することにより、また、熱硬化性樹脂の場合は、熱硬化したのちレーザー加工することにより、前記接着剤層にバイアホール形成用の開口部を設ける。
(4) 次に、硬化した前記接着剤層の表面に存在する酸や酸化剤に可溶性の樹脂粒子を酸あるいは酸化剤によって溶解除去し、接着剤層表面を粗化処理する。
ここで、上記酸としては、リン酸、塩酸、硫酸、あるいは蟻酸や酢酸などの有機酸があるが、特に有機酸を用いることが望ましい。粗化処理した場合に、バイアホールから露出する金属導体層を腐食させにくいからである。
一方、上記酸化剤としては、クロム酸、過マンガン酸塩（過マンガン酸カリウムなど）の水溶液を用いることが望ましい。
(5) 次に、接着剤層表面を粗化した配線基板に触媒核を付与する。
触媒核の付与には、貴金属イオンや貴金属コロイドなどを用いることが望ましく、一般的には、塩化パラジウムやパラジウムコロイドを使用する。なお、触媒核を固定するために加熱処理を行うことが望ましい。このような触媒核としてはパラジウムがよい。
(6) 次に、無電解めっき用接着剤層の表面に無電解めっきを施し、粗化面全面に無電解めっき膜を形成する。無電解めっき膜の厚みは 0.5〜５μｍである。
つぎに、無電解めっき膜上にめっきレジストを形成する。
(7) 次に、めっきレジスト非形成部に５〜20μｍの厚みの電解めっきを施し、導体回路、ならびにバイアホールを形成する。
ここで、上記電解めっきとしては、銅めっきを用いることが望ましい。
(8) さらに、めっきレジストを除去した後、そのめっきレジスト下の無電解めっき膜を、硫酸と過酸化水素の混合液や過硫酸ナトリウム、過硫酸アンモニウムなどの水溶液からなるエッチング液で溶解除去し、独立した導体回路とする。
(9) ついで、導体回路表面に、本発明にかかる多孔質な銅−ニッケル−リンからなる合金粗化層を形成する。
(10)次に、この基板上に層間樹脂絶縁層として、無電解めっき用接着剤層を形成する。
(11)さらに、前記 (3)〜(8) の工程を繰り返して上層の導体回路を設け、片面３層の６層両面多層プリント配線板を得る。
【００２６】
なお、以上の説明は、セミアティティブ法と呼ばれる方法によりプリント配線板を製造する例であるが、無電解めっき用接着剤層を粗化した後、触媒核を付与し、めっきレジストを設けて、無電解めっきを行い導体回路を形成する、いわゆるフルアディティブ法にも適用することが可能である。
【００２７】
【実施例】
以下、本発明を実施例に基づいて説明する。
（実施例１）
Ａ．無電解めっき用接着剤の調製
▲１▼．クレゾールノボラック型エポキシ樹脂（日本化薬製、分子量2500）の25％アクリル化物を35重量部、感光性モノマー（東亜合成製、アロニックスＭ325 ） 3.15重量部、消泡剤 0.5重量部、ＮＭＰ 3.6重量部を攪拌混合した。
▲２▼．ポリエーテルスルフォン（ＰＥＳ）12重量部、エポキシ樹脂粒子（三洋化成製、ポリマーポール）の平均粒径 1.0μｍのものを 7.2重量部、平均粒径 0.5μｍのものを3.09重量部を混合した後、さらにＮＭＰ30重量部を添加し、ビーズミルで攪拌混合した。
▲３▼．イミダゾール硬化剤（四国化成製、2E4MZ-CN）２重量部、光開始剤であるベンゾフェノン２重量部、光増感剤であるミヒラーケトン 0.2重量部、ＮＭＰ1.5 重量部を攪拌混合した。
これらを混合して無電解めっき用接着剤を得た。
【００２８】
Ｂ．プリント配線板の製造方法
(1) 厚さ１mmのガラスエポキシ樹脂またはＢＴ（ビスマレイミドトリアジン）樹脂からなる基板１の両面に18μｍの銅箔８がラミネートされている銅張積層板を出発材料とした（図１参照）。まず、この銅張積層板をドリル削孔し、めっきレジストを形成した後、無電解めっき処理してスルーホール９を形成し、さらに、銅箔を常法に従いパターン状にエッチングすることにより、基板の両面に内層銅パターン４を形成した。
【００２９】
(2) 内層銅パターン４を形成した基板を、水洗いし、乾燥した後、NaOH（10ｇ／ｌ）、NaClO₂（40ｇ／ｌ）、Na₃PO₄（６ｇ／ｌ）の水溶液を酸化浴（黒化浴）とし、導体回路、スルーホール全表面に粗化層11を設けた（図２参照）。
【００３０】
(3) エポキシ樹脂を主成分とする樹脂充填剤10を、基板の両面に印刷機を用いて塗布することにより、導体回路４間あるいはスルーホール９内に充填し、加熱乾燥を行った。即ち、この工程により、樹脂充填剤10が内層銅パターン４の間あるいはスルーホール９内に充填される（図３参照）。
【００３１】
(4) 前記(3) の処理を終えた基板の片面を、ベルト研磨紙（三共理化学製）を用いたベルトサンダー研磨により、内層銅パターン４の表面やスルーホール９のランド表面に樹脂充填剤10が残らないように研磨し、次いで、前記ベルトサンダー研磨による傷を取り除くためのバフ研磨を行った。このような一連の研磨を基板の他方の面についても同様に行った。そして、充填した樹脂充填剤10を加熱硬化した（図４参照）。
このようにして、スルーホール９等に充填された樹脂充填剤10の表層部および内層導体回路４上面の粗化層11を除去して基板両面を平滑化し、樹脂充填剤10と導体回路４の側面とが粗化層11を介して強固に密着し、またスルーホール９の内壁面と樹脂充填剤10とが粗化層11を介して強固に密着した配線基板を得た。
【００３２】
(5) さらに、露出した導体回路４およびスルーホール９のランド上面に厚さ２μｍのCu−Ni−Ｐからなる多孔質な合金粗化層18を形成し、さらにこの粗化層18の表面に厚さ 0.3μｍのSn層を設けた（図５参照、但し、Sn層については図示しない）。
その粗化層の形成方法は以下のようである。即ち、基板をアルカリ脱脂してソフトエッチングし、次いで、塩化パラジウムと有機酸からなる触媒溶液で処理して、Pd触媒を付与し、この触媒を活性化した後、硫酸銅 3.2×10^-2 mol／ｌ、硫酸ニッケル 2.4×10^-3 mol／ｌ、クエン酸 5.2×10^-2 mol／ｌ、次亜リン酸ナトリウム 2.7×10^-1 mol／ｌ、ｌ、ホウ酸 5.0×10^-1 mol／ｌ、界面活性剤（日信化学工業製、サーフィノール104 ） 1.0ｇ／ｌの水溶液からなるｐＨ＝９の無電銅めっき浴に基板を浸漬し、浸漬２分後から１秒に１回の割合で縦方向に振動させて、銅導体回路４およびスル−ホ−ル９のランドの表面にCu−Ni−Ｐからなる多孔質な合金からなる厚さ２μｍ粗化層を設けた。
さらに、 100℃で30分、 120℃で30分、 150℃で２時間の加熱処理を行い、10体積％の硫酸水溶液、および0.2mol／ｌのホウフッ酸水溶液で処理した後、ホウフッ化スズ 0.1 mol／ｌ、チオ尿素 1.0 mol／ｌの水溶液を用い、温度35℃、ｐＨ＝1.2 の条件でCu−Sn置換反応させ、多孔質な粗化層18の表面に厚さ 0.3μｍのSn層を設けた（Sn層についは図示しない）。
【００３３】
(6) 基板の両面に、Ａの無電解めっき用接着剤をロールコータを用いて塗布し、水平状態で20分間放置してから、60℃で30分の乾燥を行った（図６参照）。
【００３４】
(7) 前記(6) で接着剤の層を形成した基板の両面に、85μｍφの黒円が印刷されたフォトマスクフィルムを密着させ、超高圧水銀灯により 500mJ／cm² で露光した。これをＤＭＤＧ溶液でスプレー現像することにより、その接着剤の層に85μｍφのバイアホールとなる開口を形成した。さらに、当該基板を超高圧水銀灯により3000mJ／cm² で露光し、100 ℃で１時間、その後 150℃で５時間の加熱処理をすることにより、フォトマスクフィルムに相当する寸法精度に優れた開口（バイアホール形成用開口６）を有する層間樹脂絶縁層２を形成した（図７参照）。なお、バイアホールとなる開口には、図示しないスズめっき層を部分的に露出させた。
【００３５】
(8) バイアホール形成用開口を形成した基板を、 800ｇ／ｌのクロム酸水溶液に70℃で２０分間浸漬し、層間樹脂絶縁層２の表面に存在するエポキシ樹脂粒子を溶解除去してその表面を粗化し、粗化面を得た。その後、中和溶液（シプレイ社製）に浸漬してから水洗いした（図８参照）。
さらに、粗面化処理した該基板の表面に、パラジウム触媒（アトテック製）を付与することにより、層間絶縁材層２の表面およびバイアホール用開口６の内壁面に触媒核を付けた。
【００３６】
(9) 以下の組成の無電解銅めっき水溶液中に基板を浸漬して、粗面全体に厚さ
0.6μｍの無電解銅めっき膜12を形成した（図９参照）。
〔無電解めっき水溶液〕
ＥＤＴＡ 150 ｇ／ｌ
硫酸銅 20 ｇ／ｌ
ＨＣＨＯ 30 ml／ｌ
ＮａＯＨ 40 ｇ／ｌ
α、α’−ビピリジル 80 mg／ｌ
ＰＥＧ 0.1 ｇ／ｌ
〔無電解めっき条件〕
70℃の液温度で30分
【００３７】
(10)市販の感光性ドライフィルムを無電解銅めっき膜12に張り付け、マスクを載置して、 100mJ／cm² で露光、 0.8％炭酸ナトリウム水溶液で現像処理し、めっきレジスト３を設けた（図10参照）。
【００３８】
(11)ついで、以下の条件で電解銅めっきを施し、電解銅めっき膜13を形成した（図11参照）。

【００３９】
(12)めっきレジスト３を５％ＫＯＨ水溶液で剥離除去した後、そのめっきレジスト３下の無電解めっき膜12を硫酸と過酸化水素の混合液でエッチング処理して溶解除去し、無電解銅めっき膜12と電解銅めっき膜13からなる厚さ18μｍの導体回路（バイアホール７を含む）５を形成した（図12参照）。
【００４０】
(13)導体回路５を形成した基板に対し、前記(5) と同様の処理を行い、導体回路５の表面に厚さ２μｍのCu−Ni−Ｐからなる多孔質な合金粗化層18を形成し、さらに、その表面に厚さ 0.3μｍのSn層を設けた（図13参照）。
【００４１】
(14)前記 (6)〜(13)の工程を繰り返すことにより、さらに上層の導体回路を形成し、多層配線板を得た（図14〜19参照）。但し、最上層は、Sn置換は行わなかった。
【００４２】
(15)一方、DMDGに溶解させた60wt％のクレゾールノボラック型エポキシ樹脂（日本化薬製）のエポキシ基50％をアクリル化した感光性付与のオリゴマー（分子量4000）を 60.00重量部、イミダゾール硬化剤（四国化成製、2E4MZ-CN）1.6 重量部、感光性モノマーである多価アクリルモノマー（日本化薬製、Ｒ604 ）5 重量部混合し、さらにこの混合物に対して光開始剤としてのベンゾフェノン（関東化学製）を２重量部、光増感剤としてのミヒラーケトン（関東化学製）0.2 重量部を加えて、ソルダーレジスト組成物を得た。
【００４３】
(16)前記(14)で得た多層配線基板の両面に、上記ソルダーレジスト組成物を20μｍの厚さで塗布した。次いで、70℃で20分間、70℃で30分間の乾燥処理を行った後、ソルダーレジスト開口部の円パターン（マスクパターン）が描画されたフィルムを、ソルダーレジスト層に密着させて1000mJ／cm² の紫外線で露光し、DMTG現像処理した。さらに、80℃で１時間、 100℃で１時間、 120℃で１時間、 150℃で３時間の条件で加熱処理し、はんだパッドの上面、バイアホールおよびランド部分を開口した（開口径 200μｍ）ソルダーレジストパターン層14を形成した。
【００４４】
(17)次に、ソルダーレジストパターン層14を形成した基板を、塩化ニッケル30ｇ／ｌ、次亜リン酸ナトリウム10ｇ／ｌ、クエン酸ナトリウム10ｇ／ｌの水溶液からなるｐＨ＝５の無電解ニッケルめっき液に20分間浸漬して、開口部に厚さ５μｍのニッケルめっき層15を形成した。さらに、その基板を、シアン化金カリウム２ｇ／ｌ、塩化アンモニウム75ｇ／ｌ、クエン酸ナトリウム50ｇ／ｌ、次亜リン酸ナトリウム10ｇ／ｌの水溶液からなる無電解金めっき液に93℃の条件で23秒間浸漬して、ニッケルめっき層15上に厚さ0.03μｍの金めっき層16を形成した。
【００４５】
(18)そして、ソルダーレジストパターン層14の開口部に、はんだペーストを印刷して 200℃でリフローすることによりはんだバンプ（はんだ体）17を形成し、はんだバンプ17を有する多層プリント配線板を製造した（図20参照）。
【００４６】
（比較例）
露出した導体回路およびスルーホールのランド上面に、厚さ５μｍのCu−Ni−Ｐ合金被覆層、厚さ２μｍのCu−Ni−Ｐ針状合金粗化層および粗化層表面に 0.3μｍの厚さのSn層を設けることにより、導体回路表面を粗化したこと以外は実施例１と同様にして多層プリント配線板を製造した。
その粗化方法は以下のようである。即ち、基板をアルカリ脱脂してソフトエッチングし、次いで、塩化パラジウムと有機酸からなる触媒溶液で処理して、Pd触媒を付与し、この触媒を活性化した後、硫酸銅 3.2×10^-2 mol／ｌ、硫酸ニッケル 3.9×10^-3 mol／ｌ、クエン酸 5.8×10^-2 mol／ｌ、次亜リン酸ナトリウム 3.3×10^-1 mol／ｌ、ホウ酸 5.0×10^-1 mol／ｌおよび界面活性剤（日信化学工業製、サーフィノール465 ） 0.1ｇ／ｌの水溶液からなるｐＨ＝９の無電解めっき浴に基板を浸漬し、この基板を４秒に１回の割合で縦方向に揺動させて、銅導体回路およびスルーホールのランド表面にCu−Ni−Ｐからなる針状合金の被覆層と粗化層を設けた。
さらに、 100℃で30分、 120℃で30分、 150℃で２時間の加熱処理を行い、10体積％の硫酸水溶液、および0.2mol／ｌのホウフッ酸水溶液で処理した後、ホウフッ化スズ0.1mol／ｌ、チオ尿素1.0mol／ｌの水溶液を用い、温度50℃、ｐＨ＝1.2 の条件にてCu−Sn置換反応させ、粗化層の表面に厚さ 0.3μｍのSn層を設けた。
【００４７】
このようにして実施例および比較例で製造した多層プリント配線板について、ピール強度、樹脂残りの有無、ソルダーレジスト層におけるクラックの有無、形成可能な絶縁層の厚さ、形成可能なＬ／Ｓの大きさ、Snの付きまわり性、インタープレート粗化層の厚さのばらつきを調べ、評価した。
その結果を表１に記載した。
【００４８】
【表１】

【００４９】
表１に示す結果から明らかなように、本発明のプリント配線板は、ピール強度を低下させることなく粗化層を薄くできるため、樹脂絶縁層を薄く、またＬ／Ｓを小さくすることが可能である。それ故、プリント配線板を小型軽量化でき、高密度化が可能となる。
【００５０】
また、異物や樹脂を洗浄や現像により除去しやすく、ソルダーレジスト層のクラックやバイアホール底部の樹脂残りを防止できる。
【００５１】
【発明の効果】
以上説明したように本発明によれば、導体回路と層間絶縁樹脂との密着性を低下させることなく、導通不良や絶縁不良を防止した信頼性に優れるプリント配線板を提供することができる。しかも、ビルドアップ多層配線基板の高密度化を容易に実現することができる。
【図面の簡単な説明】
【図１】本発明にかかるプリント配線板の一製造工程を示す図である。
【図２】本発明にかかるプリント配線板の一製造工程を示す図である。
【図３】本発明にかかるプリント配線板の一製造工程を示す図である。
【図４】本発明にかかるプリント配線板の一製造工程を示す図である。
【図５】本発明にかかるプリント配線板の一製造工程を示す図である。
【図６】本発明にかかるプリント配線板の一製造工程を示す図である。
【図７】本発明にかかるプリント配線板の一製造工程を示す図である。
【図８】本発明にかかるプリント配線板の一製造工程を示す図である。
【図９】本発明にかかるプリント配線板の一製造工程を示す図である。
【図１０】本発明にかかるプリント配線板の一製造工程を示す図である。
【図１１】本発明にかかるプリント配線板の一製造工程を示す図である。
【図１２】本発明にかかるプリント配線板の一製造工程を示す図である。
【図１３】本発明にかかるプリント配線板の一製造工程を示す図である。
【図１４】本発明にかかるプリント配線板の一製造工程を示す図である。
【図１５】本発明にかかるプリント配線板の一製造工程を示す図である。
【図１６】本発明にかかるプリント配線板の一製造工程を示す図である。
【図１７】本発明にかかるプリント配線板の一製造工程を示す図である。
【図１８】本発明にかかるプリント配線板の一製造工程を示す図である。
【図１９】本発明にかかるプリント配線板の一製造工程を示す図である。
【図２０】本発明にかかるプリント配線板の一製造工程を示す図である。
【図２１】本発明にかかる多孔質なCu−Ni−Ｐ合金層の表面外観写真を示す図である。
【符号の説明】
１ 基板
２ 樹脂絶縁層 (接着剤層)
３ めっきレジスト
４ 内層導体回路 (内層銅パターン)
５ 外層導体回路 (内層銅パターン)
６ バイアホール用開口
７ バイアホール
８ 銅箔
９ スルーホール
10 樹脂充填剤
11 粗化層
12 無電解めっき膜
13 電解めっき膜
14 ソルダーレジスト層
15 ニッケルめっき層
16 金めっき層
17 はんだバンプ
18 多孔質な粗化層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed wiring board and a method for manufacturing the same, and more particularly, to a printed wiring board and a method for manufacturing the same that prevent conduction failure such as disconnection and insulation failure without reducing adhesion between a conductor circuit and an interlayer insulating resin. suggest.
[0002]
[Prior art]
In recent years, so-called build-up multilayer wiring boards have attracted attention because of the demand for higher density of multilayer wiring boards. For example, as disclosed in JP-A-6-283860, this build-up multilayer wiring board is made of a needle-like alloy made of Cu-Ni-P by electroless plating on the surface of a conductor circuit on the substrate. A roughening layer is provided, then an interlayer insulating resin is applied to form an interlayer insulating layer, and then a via hole opening for interlayer conduction is provided, and then plating is performed thereon to form a via hole and a conductor layer And it manufactures by repeatedly forming these interlayer insulation layers and conductor layers.
According to the technique disclosed in this publication, the build-up multilayer wiring board can ensure excellent adhesion between the conductor circuit and the interlayer insulating resin by the needle-like alloy made of Cu-Ni-P.
[0003]
[Problems to be solved by the invention]
However, with this acicular alloy plating made of Cu-Ni-P, there are limits to making the layers and conductors smaller and thinner, and it is difficult to increase the density of the build-up wiring board. There were drawbacks. Specifically, a needle-like alloy roughened layer made of Cu-Ni-P needs to have a thickness of 7 μm or more as a whole in order to ensure adhesion with the interlayer insulating resin. Is as large as ± 3 μm, so it is necessary to increase the thickness of the interlayer insulating layer to 20 μm or more in order to ensure interlayer insulation. This build-up multilayer wiring uses a needle-like alloy roughened layer made of Cu-Ni-P. There was a limit to making the substrate thinner and lighter.
[0004]
Moreover, since the acicular alloy which consists of Cu-Ni-P is formed by electroless plating, it deposits uniformly also on the side surface of a copper conductor circuit. Therefore, in the wiring board of a copper conductor circuit with L / S = 25 μm / 25 μm or less, the deposited Cu—Ni—P needle-shaped alloys are electrically connected. In other words, with acicular alloy plating made of Cu-Ni-P, it is difficult to create a wiring board with a higher density than in the past by ensuring insulation between conductors at L / S = 25 μm / 25 μm or less. There was a problem.
[0005]
Further, when forming a via hole in the interlayer insulating layer, the interlayer insulating layer formed by applying an interlayer insulating material is exposed and developed to provide a via hole opening, and after roughening, plating is performed. It is formed and electrically connected to the inner layer conductor exposed from the via hole opening.
However, in order to ensure adhesion with the interlayer insulating resin, when the needle-like alloy made of Cu-Ni-P is formed on the surface of the inner layer conductor, after the development process or the roughening process, Resin of the interlayer insulation layer remains at the bottom of the opening for the via hole, and this resin residue insulates conduction between the layers and causes disconnection (conductivity failure) when the via hole is formed by electroless copper plating. There was a problem. As a cause of the occurrence of such resin residue, the acicular alloy roughened layer made of Cu-Ni-P has a large variation in the shape and size of the acicular shape. As a result, it is presumed that a portion of the resin having a strong adhesive force remains at the bottom of the via hole opening after the development process or the roughening process. Therefore, the resin at the bottom of the opening for the via hole needs to be surely removed by developing or roughening without reducing the adhesion with the interlayer insulating resin.
[0006]
On the other hand, in order to improve the adhesion with the solder resist layer, a needle-like alloy roughened layer made of Cu—Ni—P may be formed on the surface of the solder pad. In a wiring board provided with such an acicular alloy layer, there has been a problem that cracks occur in the solder resist layer in a reliability test (for example, a HAST test). The cause is that a foreign matter of about 0.5 μm adheres to the needle-shaped alloy, and in the needle-shaped alloy, such a foreign matter of about 0.5 μm is difficult to be physically removed. it is conceivable that.
[0007]
The present invention has been made in order to solve the above-described various problems of the prior art, and its main purpose is to reduce conduction failure and insulation failure without reducing the adhesion between the conductor circuit and the interlayer insulating resin. An object of the present invention is to provide a printed wiring board which is prevented and has excellent reliability.
Another object of the present invention is to provide a printed wiring board capable of easily realizing a high density of a build-up multilayer wiring board.
Still another object of the present invention is to propose a method capable of reliably manufacturing the printed wiring board described above.
[0008]
[Means for Solving the Problems]
  As a result of intensive research aimed at the realization of the above object, the inventors have made the following content of the invention.InI came up with it.
(1) The printed wiring board of the present invention is a printed wiring board in which an interlayer insulating layer is formed on a substrate provided with a conductor circuit, and further a conductor circuit is formed on the interlayer insulating layer to form a multilayer. On the surface of the conductor circuit formed inThe substrate was formed by immersing and vibrating in an aqueous solution of electroless copper plating having copper ions, nickel ions, complexing agents, hypophosphite compounds and acetylene-containing polyoxyethylene surfactants.A roughened layer made of a porous Cu-Ni-P alloy was formed, and the interlayer insulating layer was provided with a via hole, and was formed on the substrate via the via hole and the roughened layer. The conductor circuit and the conductor circuit on the interlayer insulating layer are electrically connected to form a multilayer.
  In this printed wiring board, the via hole is preferably filled with a plating film.
[0009]
(2) The printed wiring board of the present invention is a printed wiring board in which a solder resist layer is formed through a roughened layer on the surface of the conductor circuit on a substrate provided with a conductor circuit to be a solder pad.
  The roughening layer isThe substrate was formed by immersing and vibrating in an aqueous solution of electroless copper plating having copper ions, nickel ions, complexing agents, hypophosphite compounds and acetylene-containing polyoxyethylene surfactants.It consists of a porous Cu-Ni-P alloy.
  The solder resist layer is preferably formed with an opening that exposes at least a part of the conductor circuit serving as the solder pad.
[0010]
(3) The printed wiring board of the present invention is a printed wiring board in which an interlayer insulating layer is formed on a substrate on which a conductor circuit is provided, and further a conductor circuit is formed on the interlayer insulating layer. On the surface of the conductor circuit formed inThe substrate was formed by immersing and vibrating in an aqueous solution of electroless copper plating having copper ions, nickel ions, complexing agents, hypophosphite compounds and acetylene-containing polyoxyethylene surfactants.A roughened layer made of a porous Cu—Ni—P alloy is formed, and the roughened layer is covered with a metal layer or a noble metal layer containing one or more metals having an ionization tendency larger than copper and equal to or less than titanium. It is formed.
  In this printed wiring board, a via hole is provided in the interlayer insulating layer, and the conductor circuit formed on the substrate and the conductor circuit on the interlayer insulating layer via the via hole and the roughened layer, Are preferably electrically connected to form a multilayer.
[0011]
(4) A method for producing a printed wiring board according to the present invention includes a substrate on which a conductor circuit is formed, copper ions, nickel ions, a complexing agent, a hypophosphite compound, and an acetylene-containing polyoxyethylene surfactant. A porous roughened layer made of a Cu-Ni-P alloy is formed on the surface of the conductor circuit by immersing in an aqueous solution of electroless copper plating, and then the interlayer insulating layer and the conductor circuit on the interlayer insulating layer Are sequentially formed to be multilayered.
(5) A method for producing a printed wiring board according to the present invention includes a substrate provided with a conductor circuit serving as a solder pad, a copper ion, a nickel ion, a complexing agent, a hypophosphite compound, and an acetylene-containing polyoxyethylene system. It is immersed in an aqueous solution of electroless copper plating having a surfactant to form a porous roughened layer made of a Cu-Ni-P alloy on the surface of the conductor circuit, and then to form a solder resist layer. Features.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
The present invention is characterized in that a roughened layer of an alloy composed of porous Cu-Ni-P is formed on the surface of the inner layer of the build-up multilayer wiring board or on the surface of the solder pad of the surface layer.
Thus, by changing the shape of the alloy made of Cu-Ni-P from the needle shape to the porous shape, the alloy roughened layer made of Cu-Ni-P has a total thickness of around 2 to 3 μm. The thickness variation is as small as ± 0.3 μm, and the structure is thin and stable. As a result, interlayers and conductors can be set smaller than conventional wiring boards, and the multi-layered build-up wiring board can be increased in density and weight. In other words, by reducing the thickness of the Cu—Ni—P alloy roughening layer, the thickness of the interlayer insulating layer can be reduced to 15 μm and the space required for conductor insulation can be reduced to 15 μm. The board can be made thin and high-density wiring can be obtained.
[0013]
Further, the roughened surface made of a porous alloy made of Cu-Ni-P has a better flow of the cleaning solution and the developer than the needle-like alloy, and it is easy to remove foreign matter and resin. As a result, according to the present invention, in the reliability test, problems such as cracks in the solder resist layer generated due to foreign matters and resin residues generated at the bottom of the via hole opening can be solved.
[0014]
The conductor circuit according to the present invention is excellent in adhesion to the interlayer insulating layer because a rough alloy layer is formed by precipitating and growing a porous alloy made of Cu-Ni-P on the surface. More preferably, the conductor side of this alloy roughened layer is constituted by a coating portion having a thickness of 0.1 to 0.2 μm, and the insulating layer side is constituted by a roughened portion having a thickness of 1.5 to 2 μm. This covering portion protects the circuit surface in order to prevent local battery reaction. As a result, there is no connection failure due to peeling of the interlayer insulating layer or insulation between layers and lines. For example, the peel strength from the interlayer insulating layer is 0.8 kgf / cm, which is equivalent to that of a conventional needle-like alloy made of Cu-Ni-P. That is, this roughened alloy layer can ensure practical adhesion with the interlayer resin even if it has a porous structure, and does not impair the role of ensuring adhesion with the interlayer resin that the conventional acicular alloy bears. .
[0015]
The roughened layer of the alloy has poor adhesion to the interlayer insulating layer if the entire layer is too thin, and conversely, if the entire layer is too thick, it is difficult to maintain insulation between the layers or conductors. .
[0016]
On the surface of such a roughened alloy layer according to the present invention, a metal layer or a noble metal layer containing one or more metals having a higher ionization tendency than copper and not more than titanium is preferably formed with a thickness of 0.1 to 2 μm. It is desirable to be made. By covering with these metal layers, the contact between the electrolyte solution and the roughened layer can be prevented, or the metal layers themselves can be dissolved by the local cell reaction to dissolve the roughened layer and the conductor circuit. This is because it can be prevented.
As the metal having an ionization tendency larger than copper and not more than titanium, at least one selected from titanium, aluminum, zinc, iron, indium, thallium, cobalt, nickel, tin, lead and bismuth can be used. Moreover, as a noble metal, at least 1 sort (s) chosen from gold | metal | money, silver, platinum, and palladium can be used. Of these metals, tin is particularly preferable. This is because tin can form a thin layer by electroless displacement plating and can be deposited along the unevenness of the roughened layer.
[0017]
Next, in the present invention, a plating method for forming a rough alloy layer by depositing and growing a porous alloy made of Cu-Ni-P on the surface of the conductor circuit will be described.
In the present invention, a substrate on which a conductor circuit is formed is immersed in a plating aqueous solution comprising a complexing agent, a copper compound, a nickel compound, a hypophosphite, and an acetylene-containing polyoxyethylene surfactant, and the substrate is vibrated. Alternatively, a porous alloy composed of Cu—Ni—P is precipitated and grown by a method of imparting rocking or by supplying metal ions to form a roughened alloy layer composed of a coating layer and a roughened layer. . The plating aqueous solution has a copper ion concentration, a nickel ion concentration, a hypophosphite ion concentration, and a complexing agent concentration of 0.007 to 0.160 mol / l, 0.001 to 0.023 mol / l, 0.1 to 1.0 mol / l, and 0.01, respectively. It is desirable to adjust so that it may become -0.2 mol / l.
[0018]
As the complexing agent, citric acid, tartaric acid, malic acid, EDTA, quadrol, glycine and the like can be used.
As the acetylene-containing polyoxyethylene-based surfactant, it is optimal to use one having a structure as shown in Chemical Formula 1. For example, alkynediols such as 2,4,7,9-tetramethyl-5-decyne-4,7-diol and 3,6-dimethyl-4-octyne-3,6-diol can be used. Commercially available products include Surfinol 104 manufactured by Nissin Chemical Industry.
[0019]
[Chemical 1]

[0020]
The porous Cu—Ni—P alloy deposited from such an electroless plating solution has an appearance as shown in FIG. 21, and the number of micropores is 1 cm.²It is in the range of 100,000 to 1,000,000 per unit, and generally in the range of 3,000,000 to 300,000,000. Further, the diameter of the micropores is within the range of 0.01 to 100 μm, and generally within the range of 0.1 to 10 μm.
[0021]
In the present invention, it is further desirable to coat the surface of the roughened layer with a metal layer or a noble metal layer having an ionization tendency larger than copper and equal to or less than titanium. In particular, in the case of tin, a borofluoride tin-thiourea or tin chloride-thiourea solution is used. In this case, an Sn layer of about 0.1 to 2 μm is formed by the substitution reaction of Cu—Sn. In the case of a noble metal, a method such as sputtering or vapor deposition can be employed.
[0022]
In the present invention, it is desirable to use an electroless plating adhesive as an interlayer insulating layer formed on the conductor circuit. This electroless plating adhesive is optimally prepared by dispersing heat-resistant resin particles that are soluble in a cured acid or oxidizing agent in an uncured heat-resistant resin that is sparingly soluble in acid or oxidizing agent. is there. This is because the heat-resistant resin particles are dissolved and removed by treatment with an acid or oxidizing agent solution, and a roughened surface composed of crucible-like anchors can be formed on the surface of the adhesive layer.
[0023]
In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles that are particularly cured include (1) heat-resistant resin powder having an average particle size of 10 μm or less, and (2) particles having a relatively large average particle size. Particles in which particles having a relatively small average particle diameter are mixed are desirable. This is because more complex anchors can be formed. Examples of the heat resistant resin that can be used include an epoxy resin, a polyimide resin, and a composite of an epoxy resin and a thermoplastic resin. Examples of the thermoplastic resin to be compounded include polyether ether sulfone (PES). Examples of the heat-resistant resin particles that are dissolved in an acid or oxidizer solution include an epoxy resin (especially an epoxy resin cured with an amine curing agent) and an amino resin.
Moreover, as a soldering resist used by this invention, what consists of epoxy resin acrylate and an imidazole hardening | curing agent can be used.
[0024]
Next, one method for producing a printed wiring board according to the present invention will be described.
(1) First, a wiring substrate having an inner layer copper pattern formed on the surface of the core substrate is manufactured.
The copper pattern is formed on the core substrate by etching a copper-clad laminate, or an adhesive layer for electroless plating is formed on a substrate such as a glass epoxy substrate, a polyimide substrate, a ceramic substrate, or a metal substrate. There is a method in which the surface of the adhesive layer is roughened to obtain a roughened surface, which is subjected to electroless plating.
A through hole is formed in the core substrate, and the wiring layers on the front surface and the back surface can be electrically connected through the through hole.
Further, resin may be filled between the through hole and the conductor circuit of the core substrate to ensure smoothness.
In particular, in the present invention, a roughened alloy layer made of porous copper-nickel-phosphorus is formed on the conductor circuit surface of the core substrate and the land surface of the through hole.
[0025]
(2) Next, an interlayer resin insulating layer is formed on the wiring board produced in (1). In particular, in the present invention, it is desirable to use the above-described adhesive for electroless plating as an interlayer resin insulating material.
(3) After the formed electroless plating adhesive layer is dried, openings for forming via holes are provided as necessary. In the case of a photosensitive resin, by exposing and developing and then thermosetting, and in the case of a thermosetting resin, by thermosetting and then laser processing, via holes are formed in the adhesive layer. Provide a part.
(4) Next, the acid or oxidant-soluble resin particles present on the surface of the cured adhesive layer are dissolved and removed with an acid or oxidant, and the surface of the adhesive layer is roughened.
Here, examples of the acid include phosphoric acid, hydrochloric acid, sulfuric acid, and organic acids such as formic acid and acetic acid. It is particularly preferable to use an organic acid. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded.
On the other hand, as the oxidizing agent, it is desirable to use an aqueous solution of chromic acid or permanganate (such as potassium permanganate).
(5) Next, a catalyst nucleus is imparted to the wiring board whose surface of the adhesive layer is roughened.
For imparting the catalyst nucleus, it is desirable to use a noble metal ion or a noble metal colloid. Generally, palladium chloride or a palladium colloid is used. It is desirable to perform heat treatment to fix the catalyst core. Palladium is preferable as such a catalyst nucleus.
(6) Next, electroless plating is performed on the surface of the electroless plating adhesive layer to form an electroless plating film on the entire roughened surface. The thickness of the electroless plating film is 0.5 to 5 μm.
Next, a plating resist is formed on the electroless plating film.
(7) Next, electroplating with a thickness of 5 to 20 μm is applied to the plating resist non-forming portion to form a conductor circuit and a via hole.
Here, it is desirable to use copper plating as the electrolytic plating.
(8) Further, after removing the plating resist, the electroless plating film under the plating resist is dissolved and removed with an etching solution made of a mixed solution of sulfuric acid and hydrogen peroxide, an aqueous solution of sodium persulfate, ammonium persulfate, Independent conductor circuit.
(9) Next, an alloy roughening layer made of porous copper-nickel-phosphorous according to the present invention is formed on the surface of the conductor circuit.
(10) Next, an electroless plating adhesive layer is formed on the substrate as an interlayer resin insulation layer.
(11) Further, the steps (3) to (8) are repeated to provide an upper conductor circuit to obtain a six-layer double-sided multilayer printed wiring board having three layers on one side.
[0026]
In addition, although the above description is an example which manufactures a printed wiring board by the method called a semi-active method, after roughening the adhesive layer for electroless plating, a catalyst nucleus is provided, plating resist is provided. Also, it can be applied to a so-called full additive method in which electroless plating is performed to form a conductor circuit.
[0027]
【Example】
Hereinafter, the present invention will be described based on examples.
Example 1
A. Preparation of adhesive for electroless plating
(1). 35 parts by weight of 25% acrylate of cresol novolac type epoxy resin (Nippon Kayaku, molecular weight 2500), 3.15 parts by weight of photosensitive monomer (Aronix M325, manufactured by Toagosei Co., Ltd.) 0.5 parts by weight of antifoaming agent, 3.6 parts by weight of NMP Were mixed with stirring.
(2). After mixing 12 parts by weight of polyethersulfone (PES), 7.2 parts by weight of epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd., polymer pole) with an average particle diameter of 1.0 μm, and 3.09 parts by weight with an average particle diameter of 0.5 μm, Further, 30 parts by weight of NMP was added and stirred and mixed with a bead mill.
(3). 2 parts by weight of an imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN), 2 parts by weight of benzophenone as a photoinitiator, 0.2 part by weight of Michler's ketone as a photosensitizer, and 1.5 parts by weight of NMP were mixed with stirring.
These were mixed to obtain an electroless plating adhesive.
[0028]
B. Method for manufacturing printed wiring board
(1) The starting material was a copper clad laminate in which 18 μm copper foil 8 was laminated on both sides of a substrate 1 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm (see FIG. 1). First, after drilling this copper-clad laminate to form a plating resist, electroless plating treatment is performed to form a through hole 9, and further, the copper foil is etched into a pattern according to a conventional method, whereby a substrate is obtained. The inner layer copper pattern 4 was formed on both sides of the substrate.
[0029]
(2) The substrate on which the inner layer copper pattern 4 is formed is washed with water and dried, followed by NaOH (10 g / l), NaClO.₂(40 g / l), Na_ThreePO_FourAn aqueous solution of (6 g / l) was used as an oxidation bath (blackening bath), and a roughening layer 11 was provided on the entire surface of the conductor circuit and the through hole (see FIG. 2).
[0030]
(3) The resin filler 10 mainly composed of an epoxy resin was applied to both sides of the substrate using a printing machine so as to be filled between the conductor circuits 4 or into the through holes 9 and dried by heating. That is, in this step, the resin filler 10 is filled between the inner layer copper patterns 4 or into the through holes 9 (see FIG. 3).
[0031]
(4) Resin filler is applied to the surface of the inner layer copper pattern 4 and the land surface of the through hole 9 by belt sander polishing using belt polishing paper (manufactured by Sankyori Kagaku) on one side of the substrate after the processing of (3). Polishing was performed so that no 10 remained, and then buffing was performed to remove scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate. And the resin filler 10 with which it filled was heat-hardened (refer FIG. 4).
In this way, the surface layer portion of the resin filler 10 filled in the through-holes 9 and the like and the roughening layer 11 on the upper surface of the inner conductor circuit 4 are removed to smooth both surfaces of the substrate. A wiring board was obtained in which the side surface was in close contact with the roughened layer 11 and the inner wall surface of the through hole 9 and the resin filler 10 were in close contact with each other through the roughened layer 11.
[0032]
(5) Further, a porous alloy roughening layer 18 made of Cu—Ni—P having a thickness of 2 μm is formed on the exposed conductor circuit 4 and the land upper surface of the through hole 9, and further on the surface of the roughening layer 18. An Sn layer having a thickness of 0.3 μm was provided (see FIG. 5, but the Sn layer is not shown).
The method for forming the roughened layer is as follows. That is, the substrate was degreased and soft-etched, and then treated with a catalyst solution composed of palladium chloride and an organic acid to give a Pd catalyst. After activating this catalyst, copper sulfate 3.2 × 10^-2 mol / l, nickel sulfate 2.4 × 10^-3 mol / l, citric acid 5.2 × 10^-2 mol / l, sodium hypophosphite 2.7 × 10^-1 mol / l, l, boric acid 5.0 × 10^-1 Molten l / surfactant (manufactured by Nissin Chemical Industry Co., Ltd., Surfinol 104) Immerse the substrate in an electroless copper plating bath of pH = 9 consisting of 1.0 g / l aqueous solution, and once every second after 2 minutes of immersion. The surface of the land of the copper conductor circuit 4 and the through hole 9 was provided with a 2 μm thick roughened layer made of a porous alloy made of Cu—Ni—P.
Further, after heat treatment at 100 ° C. for 30 minutes, 120 ° C. for 30 minutes and 150 ° C. for 2 hours, treatment with 10% by volume sulfuric acid aqueous solution and 0.2 mol / l borofluoric acid aqueous solution, tin borofluoride 0.1 Using an aqueous solution of mol / l and thiourea 1.0 mol / l, a Cu-Sn substitution reaction was performed under the conditions of a temperature of 35 ° C. and a pH = 1.2, and a 0.3 μm thick Sn layer was formed on the surface of the porous roughened layer 18. (Sn layer is not shown).
[0033]
(6) The electroless plating adhesive A was applied to both sides of the substrate using a roll coater, left in a horizontal state for 20 minutes, and then dried at 60 ° C. for 30 minutes (see FIG. 6). .
[0034]
(7) Adhere a photomask film printed with 85μmφ black circle on both sides of the substrate on which the adhesive layer was formed in (6) above, and use an ultrahigh pressure mercury lamp to achieve 500mJ / cm²And exposed. This was spray-developed with a DMDG solution to form an opening serving as a via hole of 85 μmφ in the adhesive layer. Furthermore, the substrate is 3000 mJ / cm with an ultra-high pressure mercury lamp.²The interlayer resin insulation layer having an opening (via hole forming opening 6) with excellent dimensional accuracy equivalent to that of a photomask film by exposure at 100 ° C. and heat treatment at 100 ° C. for 1 hour and then at 150 ° C. for 5 hours. 2 was formed (see FIG. 7). Note that a tin plating layer (not shown) was partially exposed in the opening serving as a via hole.
[0035]
(8) The substrate on which the opening for forming the via hole is immersed in an 800 g / l chromic acid aqueous solution at 70 ° C. for 20 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer 2. Was roughened to obtain a roughened surface. Then, it was immersed in the neutralization solution (made by Shipley Co., Ltd.) and washed with water (see FIG. 8).
Furthermore, a catalyst core was attached to the surface of the interlayer insulating material layer 2 and the inner wall surface of the via hole opening 6 by applying a palladium catalyst (manufactured by Atotech) to the surface of the roughened substrate.
[0036]
(9) Immerse the substrate in an electroless copper plating aqueous solution with the following composition to obtain a thickness on the entire rough surface
An electroless copper plating film 12 having a thickness of 0.6 μm was formed (see FIG. 9).
[Electroless plating aqueous solution]
EDTA 150 g / l
Copper sulfate 20 g / l
HCHO 30 ml / l
NaOH 40 g / l
α, α'-bipyridyl 80 mg / l
PEG 0.1 g / l
[Electroless plating conditions]
30 minutes at a liquid temperature of 70 ° C
[0037]
(10) A commercially available photosensitive dry film is pasted on the electroless copper plating film 12 and a mask is placed on it.²And developed with 0.8% aqueous sodium carbonate solution to provide a plating resist 3 (see FIG. 10).
[0038]
(11) Next, electrolytic copper plating was performed under the following conditions to form an electrolytic copper plating film 13 (see FIG. 11).

[0039]
(12) After stripping and removing the plating resist 3 with a 5% KOH aqueous solution, the electroless plating film 12 under the plating resist 3 is etched and removed with a mixed solution of sulfuric acid and hydrogen peroxide, and electroless copper plating is performed. A conductor circuit (including via hole 7) 5 having a thickness of 18 μm composed of film 12 and electrolytic copper plating film 13 was formed (see FIG. 12).
[0040]
(13) The substrate on which the conductor circuit 5 is formed is subjected to the same treatment as (5) above, and a porous alloy roughening layer 18 made of Cu-Ni-P having a thickness of 2 μm is formed on the surface of the conductor circuit 5. Further, an Sn layer having a thickness of 0.3 μm was provided on the surface (see FIG. 13).
[0041]
(14) By repeating the steps (6) to (13), an upper conductor circuit was formed to obtain a multilayer wiring board (see FIGS. 14 to 19). However, Sn substitution was not performed on the uppermost layer.
[0042]
(15) On the other hand, 600.00% cresol novolak type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG, photosensitized oligomer (molecular weight 4000) acrylated with 50% epoxy group, 60.00 parts by weight, imidazole curing agent (Shikoku Chemicals, 2E4MZ-CN) 1.6 parts by weight, 5 parts by weight of a polyacrylic monomer (Nippon Kayaku, R604), which is a photosensitive monomer, and benzophenone as a photoinitiator (Kanto) 2 parts by weight of Chemical) and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Chemical) as a photosensitizer were added to obtain a solder resist composition.
[0043]
(16) The solder resist composition was applied to both sides of the multilayer wiring board obtained in (14) to a thickness of 20 μm. Next, after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the film on which the solder resist opening circular pattern (mask pattern) was drawn was brought into close contact with the solder resist layer and 1000 mJ / cm²Were exposed to UV light and DMTG developed. Furthermore, heat treatment was performed at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours to open the upper surface of the solder pad, via hole, and land (opening diameter 200 μm). A solder resist pattern layer 14 was formed.
[0044]
(17) Next, the substrate on which the solder resist pattern layer 14 is formed is electroless nickel-plated with a pH of 5 comprising an aqueous solution of nickel chloride 30 g / l, sodium hypophosphite 10 g / l and sodium citrate 10 g / l. It was immersed in the liquid for 20 minutes to form a nickel plating layer 15 having a thickness of 5 μm in the opening. Further, the substrate was applied to an electroless gold plating solution composed of an aqueous solution of potassium gold cyanide 2 g / l, ammonium chloride 75 g / l, sodium citrate 50 g / l and sodium hypophosphite 10 g / l at 93 ° C. A gold plating layer 16 having a thickness of 0.03 μm was formed on the nickel plating layer 15 by dipping for 23 seconds.
[0045]
(18) And solder bumps (solder bodies) 17 are formed by printing solder paste on the openings of the solder resist pattern layer 14 and reflowing at 200 ° C. to manufacture a multilayer printed wiring board having the solder bumps 17. (See Fig. 20).
[0046]
(Comparative example)
5 μm thick Cu—Ni—P alloy coating layer, 2 μm thick Cu—Ni—P acicular alloy roughened layer and 0.3 μm thick on the surface of the roughened layer on the exposed conductor circuit and through hole land top surface A multilayer printed wiring board was manufactured in the same manner as in Example 1 except that the surface of the conductor circuit was roughened by providing the Sn layer.
The roughening method is as follows. That is, the substrate was degreased and soft-etched, and then treated with a catalyst solution composed of palladium chloride and an organic acid to give a Pd catalyst. After activating this catalyst, copper sulfate 3.2 × 10^-2 mol / l, nickel sulfate 3.9 × 10^-3 mol / l, citric acid 5.8 × 10^-2 mol / l, sodium hypophosphite 3.3 × 10^-1 mol / l, boric acid 5.0 × 10^-1 Mol / l and surfactant (manufactured by Nissin Chemical Industry Co., Ltd., Surfinol 465) The substrate is immersed in an electroless plating bath having a pH of 9 consisting of an aqueous solution of 0.1 g / l, and the substrate is immersed once every 4 seconds. The acicular alloy coating layer and roughening layer made of Cu-Ni-P were provided on the surface of the copper conductor circuit and the land of the through hole.
Further, heat treatment was performed at 100 ° C. for 30 minutes, 120 ° C. for 30 minutes, and 150 ° C. for 2 hours. After treatment with 10% by volume sulfuric acid aqueous solution and 0.2 mol / l borofluoric acid aqueous solution, tin borofluoride 0.1 Using an aqueous solution of mol / l and thiourea 1.0 mol / l, a Cu—Sn substitution reaction was performed under the conditions of a temperature of 50 ° C. and a pH = 1.2 to provide a 0.3 μm thick Sn layer on the surface of the roughened layer.
[0047]
Thus, about the multilayer printed wiring board manufactured by the Example and the comparative example, peel strength, the presence or absence of a resin residue, the presence or absence of a crack in a soldering resist layer, the thickness of a formable insulating layer, the L / S of formable Variations in size, throwing power of Sn, and thickness of the interplate roughened layer were investigated and evaluated.
The results are shown in Table 1.
[0048]
[Table 1]

[0049]
As is clear from the results shown in Table 1, the printed wiring board of the present invention can thin the roughened layer without lowering the peel strength, so the resin insulating layer can be made thin and the L / S can be reduced. It is. Therefore, the printed wiring board can be reduced in size and weight, and the density can be increased.
[0050]
Further, foreign substances and resins can be easily removed by washing and development, and cracks in the solder resist layer and resin residues at the bottom of the via holes can be prevented.
[0051]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a printed wiring board excellent in reliability that prevents conduction failure and insulation failure without reducing the adhesion between the conductor circuit and the interlayer insulating resin. In addition, the high density of the build-up multilayer wiring board can be easily realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a manufacturing process of a printed wiring board according to the present invention.
FIG. 2 is a diagram showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 3 is a diagram showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 4 is a view showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 5 is a diagram showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 6 is a view showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 7 is a diagram showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 8 is a diagram showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 9 is a diagram showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 10 is a diagram showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 11 is a diagram showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 12 is a diagram showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 13 is a view showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 14 is a view showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 15 is a diagram showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 16 is a view showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 17 is a diagram showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 18 is a diagram showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 19 is a view showing one manufacturing process of the printed wiring board according to the present invention.
FIG. 20 is a diagram showing a manufacturing process of the printed wiring board according to the present invention.
FIG. 21 is a view showing a surface appearance photograph of a porous Cu—Ni—P alloy layer according to the present invention.
[Explanation of symbols]
1 Substrate
2 Resin insulation layer (adhesive layer)
3 Plating resist
4 Inner layer conductor circuit (Inner layer copper pattern)
5 Outer layer conductor circuit (inner layer copper pattern)
6 Via-hole opening
7 Bahia Hall
8 Copper foil
9 Through hole
10 Resin filler
11 Roughening layer
12 Electroless plating film
13 Electrolytic plating film
14 Solder resist layer
15 Nickel plating layer
16 Gold plating layer
17 Solder bump
18 Porous roughened layer

Claims (9)

In a printed wiring board in which an interlayer insulating layer is formed on a substrate provided with a conductor circuit, and further a conductor circuit is formed on the interlayer insulating layer to form a multilayer,
On the surface of the conductor circuit formed on the substrate, the substrate is made of electroless copper plating having copper ions, nickel ions, a complexing agent, a hypophosphite compound and an acetylene-containing polyoxyethylene surfactant. A roughened layer made of a porous Cu-Ni-P alloy formed by immersing in an aqueous solution and vibrating is formed, and a via hole is provided in the interlayer insulating layer,
A printed wiring board, wherein the conductor circuit formed on the substrate and the conductor circuit on the interlayer insulating layer are electrically connected through the via hole and the roughened layer to form a multilayer.  The printed wiring board according to claim 1, wherein the via hole is filled with a plating film. In a printed wiring board in which a solder resist layer is formed on a substrate provided with a conductor circuit serving as a solder pad via a roughened layer on the surface of the conductor circuit,
The roughening layer immerses the substrate in an aqueous solution of electroless copper plating having copper ions, nickel ions, a complexing agent, a hypophosphite compound and an acetylene-containing polyoxyethylene surfactant, and vibrates. A printed wiring board comprising a porous Cu—Ni—P alloy formed by  The printed wiring board according to claim 3, wherein an opening is formed in the solder resist layer so as to expose at least a part of a conductor circuit serving as the solder pad. In a printed wiring board in which an interlayer insulating layer is formed on a substrate provided with a conductor circuit, and further a conductor circuit is formed on the interlayer insulating layer to form a multilayer,
On the surface of the conductor circuit formed on the substrate, the substrate is made of electroless copper plating having copper ions, nickel ions, a complexing agent, a hypophosphite compound and an acetylene-containing polyoxyethylene surfactant. A roughened layer made of a porous Cu-Ni-P alloy formed by immersing in an aqueous solution and vibrating is formed, and in the roughened layer, a metal whose ionization tendency is larger than copper and equal to or less than titanium is formed. A printed wiring board, wherein a metal layer or a noble metal layer containing one or more kinds is coated.  A via hole is provided in the interlayer insulating layer, and the conductor circuit formed on the substrate and the conductor circuit on the interlayer insulating layer are electrically connected via the via hole and the roughened layer. The printed wiring board according to claim 5, wherein the printed wiring board is multilayered.  The printed wiring board according to claim 6, wherein the via hole is filled with a plating film. By immersing the substrate on which the conductor circuit is formed in an aqueous solution of electroless copper plating having copper ions, nickel ions, a complexing agent, a hypophosphite compound and an acetylene-containing polyoxyethylene surfactant , and vibrating the substrate . A porous roughened layer made of a Cu-Ni-P alloy is formed on the surface of the conductor circuit, and then an interlayer insulating layer and a conductor circuit on the interlayer insulating layer are sequentially formed to be multilayered. A method for manufacturing a printed wiring board. A substrate provided with a conductor circuit to be a solder pad is immersed in an aqueous solution of electroless copper plating having copper ions, nickel ions, a complexing agent, a hypophosphite compound and an acetylene-containing polyoxyethylene surfactant , A method for producing a printed wiring board, wherein a porous roughened layer made of a Cu-Ni-P alloy is formed on the surface of the conductor circuit by vibrating , and then a solder resist layer is formed.

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