JP3971033B2 - レイアウトデータ作成方法、レイアウトデータ作成装置、及び、記録媒体 - Google Patents

レイアウトデータ作成方法、レイアウトデータ作成装置、及び、記録媒体 Download PDF

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Publication number
JP3971033B2
JP3971033B2 JP21315698A JP21315698A JP3971033B2 JP 3971033 B2 JP3971033 B2 JP 3971033B2 JP 21315698 A JP21315698 A JP 21315698A JP 21315698 A JP21315698 A JP 21315698A JP 3971033 B2 JP3971033 B2 JP 3971033B2
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Japan
Prior art keywords
module
power supply
data creation
layout data
layout
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Expired - Fee Related
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JP21315698A
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Japanese (ja)
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JP2000048057A5 (enExample
JP2000048057A (ja
Inventor
和茂 板津
孝行 松澤
孝倫 名和
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to JP21315698A priority Critical patent/JP3971033B2/ja
Priority to US09/215,239 priority patent/US6405354B1/en
Publication of JP2000048057A publication Critical patent/JP2000048057A/ja
Publication of JP2000048057A5 publication Critical patent/JP2000048057A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP21315698A 1998-07-28 1998-07-28 レイアウトデータ作成方法、レイアウトデータ作成装置、及び、記録媒体 Expired - Fee Related JP3971033B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP21315698A JP3971033B2 (ja) 1998-07-28 1998-07-28 レイアウトデータ作成方法、レイアウトデータ作成装置、及び、記録媒体
US09/215,239 US6405354B1 (en) 1998-07-28 1998-12-18 Method and apparatus to optimize power wiring layout and generate wiring layout data for a semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21315698A JP3971033B2 (ja) 1998-07-28 1998-07-28 レイアウトデータ作成方法、レイアウトデータ作成装置、及び、記録媒体

Publications (3)

Publication Number Publication Date
JP2000048057A JP2000048057A (ja) 2000-02-18
JP2000048057A5 JP2000048057A5 (enExample) 2005-02-17
JP3971033B2 true JP3971033B2 (ja) 2007-09-05

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JP21315698A Expired - Fee Related JP3971033B2 (ja) 1998-07-28 1998-07-28 レイアウトデータ作成方法、レイアウトデータ作成装置、及び、記録媒体

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US (1) US6405354B1 (enExample)
JP (1) JP3971033B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4491113B2 (ja) * 1999-06-14 2010-06-30 セイコーエプソン株式会社 半導体集積回路の設計方法
JP2001351979A (ja) * 2000-06-05 2001-12-21 Fujitsu Ltd 半導体装置設計支援装置
US6523154B2 (en) * 2000-12-14 2003-02-18 International Business Machines Corporation Method for supply voltage drop analysis during placement phase of chip design
JP3654190B2 (ja) * 2001-01-17 2005-06-02 日本電気株式会社 配線設計方法および配線設計装置
JP4582962B2 (ja) 2001-06-08 2010-11-17 富士通セミコンダクター株式会社 電源網解析方法、電源網解析方法を実行するコンピュータプログラム、記録媒体、及び電源網解析装置
JP2003197750A (ja) * 2001-12-21 2003-07-11 Mitsubishi Electric Corp 半導体装置
US7603641B2 (en) * 2003-11-02 2009-10-13 Mentor Graphics Corporation Power/ground wire routing correction and optimization
JP4287294B2 (ja) * 2004-01-21 2009-07-01 株式会社東芝 自動設計方法、自動設計装置、及び半導体集積回路
US7315992B2 (en) * 2004-07-29 2008-01-01 Texas Instruments Incorporated Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs
KR100593803B1 (ko) * 2004-12-06 2006-06-28 주식회사 엔타시스 반도체 집적회로의 블록배치 및 전력배선 설계방법
JP2007258215A (ja) * 2006-03-20 2007-10-04 Fujitsu Ltd セル配置プログラム、セル配置装置、及びセル配置方法
US7703059B2 (en) * 2006-05-22 2010-04-20 Lsi Corporation Method and apparatus for automatic creation and placement of a floor-plan region

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2580301B2 (ja) * 1988-12-27 1997-02-12 株式会社日立製作所 半導体集積回路装置
JP3052519B2 (ja) * 1992-01-14 2000-06-12 日本電気株式会社 集積回路の電源配線設計方法
JP3299842B2 (ja) * 1994-05-19 2002-07-08 富士通株式会社 半導体集積回路の配置配線方法および装置
US5598348A (en) * 1994-09-22 1997-01-28 Sun Microsystems, Inc. Method and apparatus for analyzing the power network of a VLSI circuit
JPH08316331A (ja) * 1995-03-15 1996-11-29 Toshiba Corp 半導体集積回路及びその設計方法
US5878053A (en) * 1997-06-09 1999-03-02 Synopsys, Inc. Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs
JP4153095B2 (ja) * 1998-08-07 2008-09-17 富士通株式会社 レイアウトデータ作成方法、レイアウトデータ作成装置、及び記録媒体

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US6405354B1 (en) 2002-06-11
JP2000048057A (ja) 2000-02-18

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