JP3964608B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP3964608B2
JP3964608B2 JP2000247702A JP2000247702A JP3964608B2 JP 3964608 B2 JP3964608 B2 JP 3964608B2 JP 2000247702 A JP2000247702 A JP 2000247702A JP 2000247702 A JP2000247702 A JP 2000247702A JP 3964608 B2 JP3964608 B2 JP 3964608B2
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JP
Japan
Prior art keywords
pattern
line
region
mask
line pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000247702A
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English (en)
Japanese (ja)
Other versions
JP2002064043A5 (enExample
JP2002064043A (ja
Inventor
祐司 竹内
史隆 荒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000247702A priority Critical patent/JP3964608B2/ja
Priority to US09/920,859 priority patent/US6531357B2/en
Priority to KR10-2001-0049228A priority patent/KR100434835B1/ko
Priority to CNB011255900A priority patent/CN1203547C/zh
Publication of JP2002064043A publication Critical patent/JP2002064043A/ja
Priority to US10/216,732 priority patent/US6596578B2/en
Publication of JP2002064043A5 publication Critical patent/JP2002064043A5/ja
Application granted granted Critical
Publication of JP3964608B2 publication Critical patent/JP3964608B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2000247702A 2000-08-17 2000-08-17 半導体装置 Expired - Fee Related JP3964608B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2000247702A JP3964608B2 (ja) 2000-08-17 2000-08-17 半導体装置
US09/920,859 US6531357B2 (en) 2000-08-17 2001-08-03 Method of manufacturing a semiconductor device
KR10-2001-0049228A KR100434835B1 (ko) 2000-08-17 2001-08-16 반도체 장치 및 그 제조 방법
CNB011255900A CN1203547C (zh) 2000-08-17 2001-08-16 半导体器件及其制造方法
US10/216,732 US6596578B2 (en) 2000-08-17 2002-08-13 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000247702A JP3964608B2 (ja) 2000-08-17 2000-08-17 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007112330A Division JP4791999B2 (ja) 2007-04-20 2007-04-20 半導体装置

Publications (3)

Publication Number Publication Date
JP2002064043A JP2002064043A (ja) 2002-02-28
JP2002064043A5 JP2002064043A5 (enExample) 2005-07-21
JP3964608B2 true JP3964608B2 (ja) 2007-08-22

Family

ID=18737739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000247702A Expired - Fee Related JP3964608B2 (ja) 2000-08-17 2000-08-17 半導体装置

Country Status (1)

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JP (1) JP3964608B2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100454131B1 (ko) * 2002-06-05 2004-10-26 삼성전자주식회사 라인형 패턴을 갖는 반도체 소자 및 그 레이아웃 방법
KR100519795B1 (ko) 2003-02-07 2005-10-10 삼성전자주식회사 다층배선 형성을 위한 포토마스크 세트 및 이를 사용하여제조된 반도체장치
JP5106747B2 (ja) 2004-10-27 2012-12-26 ルネサスエレクトロニクス株式会社 パターン形成方法、半導体装置の製造方法及び露光用マスクセット
KR100718216B1 (ko) 2004-12-13 2007-05-15 가부시끼가이샤 도시바 반도체 장치, 패턴 레이아웃 작성 방법, 노광 마스크
JP2006173186A (ja) * 2004-12-13 2006-06-29 Toshiba Corp 半導体装置、パターンレイアウト作成方法および露光マスク
JP4801986B2 (ja) 2005-02-03 2011-10-26 株式会社東芝 半導体記憶装置
JP2007129018A (ja) * 2005-11-02 2007-05-24 Nec Electronics Corp 半導体装置
KR100817089B1 (ko) 2007-02-28 2008-03-26 삼성전자주식회사 이중 패터닝 기술을 이용한 반도체 소자의 미세 패턴 형성방법
KR100886353B1 (ko) 2007-04-02 2009-03-03 삼성전자주식회사 이중 패터닝 기술을 사용한 반도체 메모리 장치 및 그레이아웃 방법
JP2009271261A (ja) * 2008-05-02 2009-11-19 Powerchip Semiconductor Corp 回路構造とそれを定義するためのフォトマスク
US8247904B2 (en) * 2009-08-13 2012-08-21 International Business Machines Corporation Interconnection between sublithographic-pitched structures and lithographic-pitched structures
CN106463352B (zh) * 2014-06-13 2020-06-19 英特尔公司 借助于电子束的层上单向金属
US10497566B1 (en) * 2018-06-19 2019-12-03 Macronix International Co., Ltd. Layout design for fanout patterns in self-aligned double patterning process
US11335569B2 (en) 2020-06-17 2022-05-17 Winbond Electronics Corp. Conductive wire structure and manufacturing method thereof
CN113808999B (zh) * 2020-06-17 2024-02-27 华邦电子股份有限公司 导线结构及其制造方法

Also Published As

Publication number Publication date
JP2002064043A (ja) 2002-02-28

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