JP3949443B2 - ディセーブルオプションを有する変換スイッチ回路 - Google Patents

ディセーブルオプションを有する変換スイッチ回路 Download PDF

Info

Publication number
JP3949443B2
JP3949443B2 JP2001383546A JP2001383546A JP3949443B2 JP 3949443 B2 JP3949443 B2 JP 3949443B2 JP 2001383546 A JP2001383546 A JP 2001383546A JP 2001383546 A JP2001383546 A JP 2001383546A JP 3949443 B2 JP3949443 B2 JP 3949443B2
Authority
JP
Japan
Prior art keywords
coupled
node
circuit
potential
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001383546A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002252556A5 (enExample
JP2002252556A (ja
Inventor
トレノー・エフ・クッデル
ジェイムス・ブーマー
ブレント・ローウェ
Original Assignee
フェアチャイルド セミコンダクター コーポレイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by フェアチャイルド セミコンダクター コーポレイション filed Critical フェアチャイルド セミコンダクター コーポレイション
Publication of JP2002252556A publication Critical patent/JP2002252556A/ja
Publication of JP2002252556A5 publication Critical patent/JP2002252556A5/ja
Application granted granted Critical
Publication of JP3949443B2 publication Critical patent/JP3949443B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Landscapes

  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
JP2001383546A 2000-12-15 2001-12-17 ディセーブルオプションを有する変換スイッチ回路 Expired - Fee Related JP3949443B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/737,977 US6433613B1 (en) 2000-12-15 2000-12-15 Translating switch circuit with disabling option
US09/737977 2000-12-15

Publications (3)

Publication Number Publication Date
JP2002252556A JP2002252556A (ja) 2002-09-06
JP2002252556A5 JP2002252556A5 (enExample) 2005-07-28
JP3949443B2 true JP3949443B2 (ja) 2007-07-25

Family

ID=24966055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001383546A Expired - Fee Related JP3949443B2 (ja) 2000-12-15 2001-12-17 ディセーブルオプションを有する変換スイッチ回路

Country Status (4)

Country Link
US (1) US6433613B1 (enExample)
JP (1) JP3949443B2 (enExample)
DE (1) DE10161052A1 (enExample)
TW (1) TW518823B (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7145378B2 (en) * 2001-07-16 2006-12-05 Fairchild Semiconductor Corporation Configurable switch with selectable level shifting
WO2003079566A2 (en) * 2002-03-11 2003-09-25 Fairchild Semiconductor Corporation Drain activated/deactivated ac coupled bandpass rf switch
US8289066B2 (en) * 2009-12-30 2012-10-16 Stmicroelectronics Asia Pacific Pte Ltd. Gate control circuit for high bandwidth switch design
JP5431992B2 (ja) * 2010-02-09 2014-03-05 セイコーインスツル株式会社 トランスミッションゲート及び半導体装置
FR2979173B1 (fr) * 2011-08-19 2013-08-16 St Microelectronics Grenoble 2 Commutateur analogique basse tension
CN102437843B (zh) * 2011-11-30 2013-10-16 中国科学院微电子研究所 高电压开关电路
US8729951B1 (en) 2012-11-27 2014-05-20 Freescale Semiconductor, Inc. Voltage ramp-up protection
US9929730B2 (en) * 2014-12-03 2018-03-27 Cisco Technology, Inc. Efficiently managing multiple power supplies
CN113300701B (zh) * 2021-06-21 2024-05-28 深圳市誉娇诚科技有限公司 一种可防止高压继电器误动作的硬件防抖自锁电路
CN117406847B (zh) * 2023-12-14 2024-04-09 浙江地芯引力科技有限公司 芯片及其供电电路和电子设备

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3272298B2 (ja) * 1998-04-27 2002-04-08 インターナショナル・ビジネス・マシーンズ・コーポレーション 放電回路を備えたスイッチ回路および電子機器
US6052019A (en) * 1998-10-29 2000-04-18 Pericom Semiconductor Corp. Undershoot-isolating MOS bus switch
US5963080A (en) * 1998-12-23 1999-10-05 Fairchild Semiconductor Corporation Undershoot hardened FET switch

Also Published As

Publication number Publication date
TW518823B (en) 2003-01-21
DE10161052A1 (de) 2002-10-10
US6433613B1 (en) 2002-08-13
JP2002252556A (ja) 2002-09-06
US20020075060A1 (en) 2002-06-20

Similar Documents

Publication Publication Date Title
US5623216A (en) Output buffer current slew rate control integrated circuit
US7034573B1 (en) Level shifter without DC current flow
US6856190B2 (en) Leak current compensating device and leak current compensating method
US6040729A (en) Digital output buffer for multiple voltage system
US5469080A (en) Low-power, logic signal level converter
KR20010049227A (ko) 레벨조정회로 및 이를 포함하는 데이터 출력회로
JPH02290327A (ja) デジタル・インタフェース回路、デジタル入力回路及びデジタル変換回路
US6970024B1 (en) Over-voltage protection of integrated circuit I/O pins
JP3949443B2 (ja) ディセーブルオプションを有する変換スイッチ回路
JPH04229714A (ja) バッファを有する集積回路
JPH09502325A (ja) Ｖｃｃ変換器回路
US5214317A (en) CMOS to ECL translator with incorporated latch
US6538867B1 (en) FET switch with overvoltage protection
JP3256664B2 (ja) レベル変換回路
US6577163B1 (en) Configurable PCI clamp or high voltage tolerant I/O circuit
EP0642226A2 (en) Translator circuits with symmetrical switching delays
EP1895656A2 (en) High gain, high speed comparator operable at low current
EP0320582A2 (en) Bicmos driver circuit including submicron on-chip voltage source
JP5314533B2 (ja) ドライバ回路およびそれを用いた試験装置
US5903175A (en) D-type latch circuit and device using the same
US7667519B2 (en) Biasing circuit for pass transistor for voltage level translator circuit
US6522199B2 (en) Reconfigurable dual-mode multiple stage operational amplifiers
US4958132A (en) Complementary metal-oxide-semiconductor translator
JPH04227326A (ja) 高速反転用ヒステリシスｔｔｌバッファ回路
US5999017A (en) CMOS implemented output buffer circuit for providing ECL level signals

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041217

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041217

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060728

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060829

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20061129

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20061204

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070227

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070320

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070418

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees