JP3901105B2 - Pixel circuit, display device, and driving method of pixel circuit - Google Patents

Description

【００２３】
ここで、μはキャリアの移動度、Ｃｏｘは単位面積当たりのゲート容量、Ｗはゲート幅、Ｌはゲート長をそれぞれ示している。
【００２４】
（３）式によれば、ＩoledはＴＦＴ２１のしきい値Ｖｔｈによらず、外部から与えられるΔＶdataによって制御される。言い換えれば、図３の画素回路２０を用いれば、画素毎にばらつくしきい値Ｖｔｈの影響を受けず、電流の均一性、ひいては輝度の均一性が比較的高い表示装置を実現することができる。
【００２５】
【特許文献１】
ＵＳＰ５，６８４，３６５
【特許文献２】
特開平８−２３４６８３号公報
【特許文献３】
ＵＳＰ６，２２９，５０６
【特許文献４】
特表２００２−５１４３２０号公報のＦＩＧ．３
【００２６】
【発明が解決しようとする課題】
上述のように、図１のような画素回路１０を用いた場合、トランジスタのしきい値Ｖｔｈのばらつきのため、画素間の輝度の均一性が損なわれ、高品位の表示装置を構成することは困難である。
【００２７】
一方、図３の画素回路を用いれば、輝度の均一性が比較的高い表示装置を実現することが可能であるが、これには次のような問題がある。
【００２８】
第１の問題は、外部から駆動するデータ振幅ΔＶdataに対し、駆動トランジスタのゲート振幅ΔVgは（１）式に従って減少する。逆に言えば、同じΔVgを得るために大きなΔＶdataを与える必要があり、これは消費電力やノイズの点から望ましくない。
【００２９】
第２の問題は、図３の画素回路２０に関する上記動作説明は理想的なものであって、実際には、発光素子（OLED）２５を駆動するＴＦＴ２１のＶｔｈのばらつきの影響が無くなるわけではない。
これは、オートゼロ線ＡＺＬとＴＦＴ２１のゲートノードがＴＦＴ２３のゲート容量によって結合されており、オートゼロ線ＡＺＬが高レベルへ遷移してＴＦＴ２３が非導通状態となる過程において、ＴＦＴ２３のチャネル電荷がＴＦＴ２１のゲートノードに流入するためである。この理由を次に説明する。
【００３０】
すなわち、オートゼロ動作終了後、ＴＦＴ２１のゲート電位は理想的にはVDD-|Vth| であるべきであるが、上記電荷の流入によって実際にはそれよりやや高い電位となり、なおかつこの電荷の流入量はＶｔｈの値によって変動する。なぜなら、オートゼロ動作終了直前におけるＴＦＴ２１のゲート電位はほぼVDD-|Vth|である。したがって、この電位は|Vth| がたとえば小さい程高い。
一方、オートゼロ動作終了時、オートゼロ線ＡＺＬの電位が上昇してＴＦＴ２３が非導通に転ずる際、そのソース電位、すなわちＴＦＴ２１のゲート電位が高い程、ＴＦＴ２３が非導通になるタイミングが遅れるため、より多くの電荷がＴＦＴ２１のゲートに流入することになる。結果としてオートゼロ動作終了後のＴＦＴ２１のゲート電位が|Vth| の影響を受けるため、前述の（２）式や（３）式が厳密には成立せず、画素毎にばらつくＶｔｈの影響を受けることになる。
【００３１】
本発明は、かかる事情に鑑みてなされたものであり、その目的は、画素内部の能動素子のしきい値のばらつきによらず、安定かつ正確に各画素の発光素子に所望の値の電流を供給でき、その結果として高品位な画像を表示することが可能な画素回路、表示装置、および画素回路の駆動方法を提供することにある。
【００３２】
【課題を解決するための手段】
上記目的を達成するため、本発明の第１の観点は、流れる電流によって輝度が変化する電気光学素子を駆動する画素回路であって、少なくとも輝度情報に応じたデータ信号が供給されるデータ線と、少なくとも第１の制御線と、ノードと、第１および第２の基準電位と、所定のプリチャージ電位と、第１端子と第２端子間で電流供給ラインを形成し、制御端子の電位に応じて上記電流供給ラインを流れる電流を制御する駆動トランジスタと、上記駆動トランジスタの第１端子に接続された第１のスイッチと、上記駆動トランジスタの第１端子と上記ノードとの間に接続された第２のスイッチと、上記駆動トランジスタの制御端子と上記所定のプリチャージ電位との間に接続された第３のスイッチと、上記データ線と上記ノードとの間に接続され、上記第１の制御線によって導通制御される第４のスイッチと、上記ノードと上記駆動トランジスタの制御端子との間に接続された結合キャパシタと、を有し、上記第１の基準電位と第２の基準電位との間に、上記駆動トランジスタの電流供給ライン、上記第１のスイッチ、および上記電気光学素子が直列に接続されている。
【００３３】
本発明の第２の観点は、流れる電流によって輝度が変化する電気光学素子を駆動する画素回路であって、少なくとも輝度情報に応じた信号が供給されるデータ線と、少なくとも第１の制御線と、第１および第２の基準電位と、所定のプリチャージ電位と、電界効果トランジスタと、ノードと、上記電界効果トランジスタのソースと第１の基準電位との間に接続された第１のスイッチと、上記電界効果トランジスタのソースと上記ノードとの間に接続された第２のスイッチと、上記電界効果トランジスタのゲートと上記プリチャージ電位との間に接続された第３のスイッチと、上記データ線と上記ノードとの間に接続され、上記第１の制御線により導通制御される第４のスイッチと、上記ノードと上記電界効果トランジスタのゲートとの間に接続された結合キャパシタと、を有し、上記電気光学素子は上記電界効果トランジスタのドレインと第２の基準電位との間に接続されている。
【００３４】
本発明の第３の観点は、流れる電流によって輝度が変化する電気光学素子を駆動する画素回路であって、少なくとも輝度情報に応じた信号が供給されるデータ線と、少なくとも第１の制御線と、第１および第２の基準電位と、所定のプリチャージ電位と、電界効果トランジスタと、ノードと、上記電界効果トランジスタのソースと上記電気光学素子との間に接続された第１のスイッチと、上記電界効果トランジスタのソースと上記ノードとの間に接続された第２のスイッチと、上記電界効果トランジスタのゲートと上記プリチャージ電位との間に接続された第３のスイッチと、上記データ線と上記ノードとの間に接続され、上記第１の制御線により導通制御される第４のスイッチと、上記ノードと上記電界効果トランジスタのゲートとの間に接続された結合キャパシタと、を有し、上記電気光学素子は上記第１のスイッチと第２の基準電位との間に接続されている。
【００３５】
好適には、上記ノードに保持容量が接続されている
【００３６】
好適には、上記所定のプリチャージ電位は上記データ線を通して供給される。
【００３７】
また、好適には、上記第１のスイッチが第２の制御線により導通制御され、上記第２のスイッチおよび上記第３のスイッチが第３の制御線により導通制御される。
【００３８】
また、好適には、上記第１のスイッチが第２の制御線により導通制御され、上記第２のスイッチが第３の制御線により導通制御され、上記第３のスイッチが第４の制御線により導通制御される。
【００３９】
好適には、上記電気光学素子を駆動する場合、第１ステージとして、上記第２の制御線および上記第３の制御線により上記第１のスイッチ、上記第２のスイッチ、および上記第３のスイッチが所定時間導通させられ、第２ステージとして、第２の制御線により上記第１のスイッチが非導通状態に保持され、所定時間経過後に上記第３の制御線により上記第２のスイッチおよび上記第３のスイッチが非導通状態に保持され、第３ステージとして、上記第１の制御線により上記第４のスイッチが導通させられ、上記データ線を伝播されるデータが上記ノードに書き込まれた後、上記第４のスイッチが非導通状態に保持され、第４ステージとして、上記第２の制御線により上記第１のスイッチが導通させられて、上記電気光学素子に上記データ信号に応じた電流を供給する。
【００４０】
また、好適には、上記電気光学素子を駆動する場合、第１ステージとして、上記第２の制御線、上記第３の制御線、および上記第４の制御線により上記第１のスイッチ、上記第２のスイッチ、および上記第３のスイッチが所定時間導通させられ、第２ステージとして、第２の制御線により上記第１のスイッチが非導通状態に保持され、所定時間経過後に上記第３の制御線により上記第２のスイッチが非導通状態に保持された後、上記第４の制御線により上記第３のスイッチが非導通状態に保持され、第３ステージとして、上記第１の制御線により上記第４のスイッチが導通させられ、上記データ線を伝播されるデータが上記ノードに書き込まれた後、上記第４のスイッチが非導通状態に保持され、第４ステージとして、上記第２の制御線により上記第１のスイッチが導通させられて、上記電気光学素子に上記データ信号に応じた電流を供給する。
【００４１】
また、第２の観点において、好適には、上記プリチャージ電位は、上記第１の基準電位から上記電界効果トランジスタのしきい値の絶対値を減じた値より小さい値に設定されている。
【００４２】
また、第３の観点において、好適には、上記プリチャージ電位は、上記電気光学素子のしきい値と上記電界効果トランジスタのしきい値とを足し合わせた値より大きい値に設定されている。
【００４３】
本発明の第４の観点に係る表示装置は、マトリクス状に複数配列された画素回路と、上記画素回路のマトリクス配列に対して列毎に配線され、少なくとも輝度情報に応じたデータ信号が供給されるデータ線と、上記画素回路のマトリクス配列に対して行毎に配線された少なくとも第１の制御線と、第１および第２の基準電位と、所定のプリチャージ電位と、を有し、上記各画素回路は、ノードと、第１端子と第２端子間で電流供給ラインを形成し、制御端子の電位に応じて上記電流供給ラインを流れる電流を制御する駆動トランジスタと、上記駆動トランジスタの第１端子に接続された第１のスイッチと、上記駆動トランジスタの第１端子と上記ノードとの間に接続された第２のスイッチと、上記駆動トランジスタの制御端子と上記所定のプリチャージ電位との間に接続された第３のスイッチと、上記データ線と上記ノードとの間に接続され、上記第１の制御線によって導通制御される第４のスイッチと、上記ノードと上記駆動トランジスタの制御端子との間に接続された結合キャパシタと、を有し、上記第１の基準電位と第２の基準電位との間に、上記駆動トランジスタの電流供給ライン、上記第１のスイッチ、および上記電気光学素子が直列に接続されている。
【００４４】
本発明の第５の観点に係る表示装置は、マトリクス状に複数配列された画素回路と、上記画素回路のマトリクス配列に対して列毎に配線され、少なくとも輝度情報に応じたデータ信号が供給されるデータ線と、上記画素回路のマトリクス配列に対して行毎に配線された少なくとも第１の制御線と、第１および第２の基準電位と、所定のプリチャージ電位と、を有し、上記各画素回路は、電界効果トランジスタと、ノードと、上記電界効果トランジスタのソースと第１の基準電位との間に接続され、上記第１の制御線により導通制御される第１のスイッチと、上記電界効果トランジスタのソースと上記ノードとの間に接続された第２のスイッチと、上記電界効果トランジスタのゲートと上記プリチャージ電位との間に接続された第３のスイッチと、上記データ線と上記ノードとの間に接続され、上記第１の制御線により導通制御される第４のスイッチと、上記ノードと上記電界効果トランジスタのゲートとの間に接続された結合キャパシタと、を有し、上記電気光学素子は上記電界効果トランジスタのドレインと第２の基準電位との間に接続されている。
【００４５】
本発明の第６の観点に係る表示装置は、マトリクス状に複数配列された画素回路と、上記画素回路のマトリクス配列に対して列毎に配線され、少なくとも輝度情報に応じたデータ信号が供給されるデータ線と、上記画素回路のマトリクス配列に対して行毎に配線された少なくとも第１の制御線と、第１および第２の基準電位と、所定のプリチャージ電位と、を有し、上記各画素回路は、電界効果トランジスタと、ノードと、上記電界効果トランジスタのソースと上記電気光学素子との間に接続された第１のスイッチと、上記電界効果トランジスタのソースと上記ノードとの間に接続された第２のスイッチと、上記電界効果トランジスタのゲートと上記プリチャージ電位との間に接続された第３のスイッチと、上記データ線と上記ノードとの間に接続され、上記第１の制御線により導通制御される第４のスイッチと、上記ノードと上記電界効果トランジスタのゲートとの間に接続された結合キャパシタと、を有し、上記電気光学素子は上記第１のスイッチと第２の基準電位との間に接続されている。
【００４６】
好適には、上記第１のスイッチが第２の制御線により導通制御され、上記第２のスイッチおよび上記第３のスイッチが第３の制御線により導通制御される。
【００４７】
好適には、上記第１のスイッチが第２の制御線により導通制御され、上記第２のスイッチが第３の制御線により導通制御され、上記第３のスイッチが第４の制御線により導通制御される。
【００４８】
本発明の第７の観点は、流れる電流によって輝度が変化する電気光学素子と、第１端子と第２端子間で電流供給ラインを形成し、制御端子の電位に応じて上記電流供給ラインを流れる電流を制御する駆動トランジスタと、ノードと、上記駆動トランジスタの第１端子に接続された第１のスイッチと、上記駆動トランジスタの第１端子と上記ノードとの間に接続された第２のスイッチと、上記駆動トランジスタの制御端子と上記所定のプリチャージ電位との間に接続された第３のスイッチと、上記データ線と上記ノードとの間に接続された第４のスイッチと、上記ノードと上記駆動トランジスタの制御端子との間に接続された結合キャパシタと、を有し、上記第１の基準電位と第２の基準電位との間に、上記駆動トランジスタの電流供給ライン、上記第１のスイッチ、および上記電気光学素子が直列に接続されている画素回路の駆動方法であって、上記上記第１のスイッチ、上記第２のスイッチ、および上記第３のスイッチを所定時間導通させる第１ステップと、上記第１のスイッチを非導通状態に保持し、所定時間経過後に上記第２のスイッチおよび上記第３のスイッチを非導通状態に保持する第２ステップと、上記第４のスイッチを導通させ、上記データ線を伝播されるデータを上記ノードに書き込んだ後、上記第４のスイッチを非導通状態に保持する第３ステップと、上記第１のスイッチを導通させて、上記電気光学素子に上記データ信号に応じた電流を供給する第４ステップとを有する。
【００４９】
本発明の第８の観点は、流れる電流によって輝度が変化する電気光学素子と、電界効果トランジスタと、ノードと、上記電界効果トランジスタのソースと第１の基準電位との間に接続された第１のスイッチと、上記電界効果トランジスタのソースと上記ノードとの間に接続された第２のスイッチと、上記電界効果トランジスタのゲートと所定の電位との間に接続された第３のスイッチと、上記データ線と上記ノードとの間に接続された第４のスイッチと、上記ノードと上記電界効果トランジスタのゲートとの間に接続された結合キャパシタと、を有し、上記電気光学素子は上記電界効果トランジスタのドレインと第２の基準電位との間に接続されている画素回路の駆動方法であって、上記上記第１のスイッチ、上記第２のスイッチ、および上記第３のスイッチを所定時間導通させる第１ステップと、上記第１のスイッチを非導通状態に保持し、所定時間経過後に上記第２のスイッチおよび上記第３のスイッチを非導通状態に保持する第２ステップと、上記第４のスイッチを導通させ、上記データ線を伝播されるデータを上記ノードに書き込んだ後、上記第４のスイッチを非導通状態に保持する第３ステップと、上記第１のスイッチを導通させて、上記電気光学素子に上記データ信号に応じた電流を供給する第４ステップとを有する。
【００５０】
本発明の第９の観点は、流れる電流によって輝度が変化する電気光学素子と、電界効果トランジスタと、ノードと、上記電界効果トランジスタのソースと上記電気光学素子との間に接続された第１のスイッチと、上記電界効果トランジスタのソースと上記ノードとの間に接続された第２のスイッチと、上記電界効果トランジスタのゲートと所定の電位との間に接続された第３のスイッチと、上記データ線と上記ノードとの間に接続された第４のスイッチと、上記ノードと上記電界効果トランジスタのゲートとの間に接続された結合キャパシタと、を有し、上記電気光学素子は上記第１のスイッチと第２の基準電位との間に接続されている画素回路の駆動方法であって、上記上記第１のスイッチ、上記第２のスイッチ、および上記第３のスイッチを所定時間導通させる第１ステップと、上記第１のスイッチを非導通状態に保持し、所定時間経過後に上記第２のスイッチおよび上記第３のスイッチを非導通状態に保持する第２ステップと、上記第４のスイッチを導通させ、上記データ線を伝播されるデータを上記ノードに書き込んだ後、上記第４のスイッチを非導通状態に保持する第３ステップと、上記第１のスイッチを導通させて、上記電気光学素子に上記データ信号に応じた電流を供給する第４ステップとを有する。
【００５１】
好適には、上記第２のステップにおいて、上記第２のスイッチおよび上記第３のスイッチを非導通状態に保持する際、上記第２のスイッチを非導通状態に保持した後、上記第３のスイッチを非導通状態に保持する。
【００５２】
本発明によれば、たとえば第２の制御線、第３の制御線により、あるいは第２の制御線、第３の制御線、第４の制御線により第１のスイッチ、第２のスイッチ、および第３のスイッチを導通状態とする。
このとき、駆動トランジスタの制御端子、たとえばゲートは第３のスイッチによってプリチャージ電位Ｖｐｃとなり、結合キャパシタの入力側電位（ノード電位）は、第１および第２のスイッチが導通状態にあるため、第１の基準電位（電源電位Ｖ_DD）またはその付近まで上昇する。
そして、第２の制御線により第１のスイッチを非導通状態とする。これにより駆動トランジスタに流れる電流が遮断されるため、駆動トランジスタの第２端子（たとえばドレイン）の電位は下降するが、その電位がVpc+|Vth| まで下降した時点で駆動トランジスタは非導通状態となって電位が安定する。
このとき、キャパシタの入力側電位（ノード電位）は、第２のスイッチが導通状態にあるため、やはり Vpc+|Vth|である。ここで |Vth|は、駆動トランジスタのしきい値の絶対値である。
次に、第３の制御線により第２および第３のスイッチを非導通状態とする。あるいは、第３の制御線により第２のスイッチを非導通状態にした後、第４の制御線により第３のスイッチを非導通状態とする。キャパシタＣ３１の入力側ノードの電位は、Vpc+|Vth| であり、駆動トランジスタのゲート電位はＶｐｃである。すなわち、キャパシタＣ３１の端子間の電位差は |Vth|となる。
次いで、第１の制御線により第４のスイッチを導通状態とし、データ線から輝度データに応じた電位Ｖdataをキャパシタの入力側ノードに与える。
キャパシタ端子間の電位差は |Vth|のまま保持されるので、駆動トランジスタのゲート電位は、Ｖdata - |Vth|となる。
次に、第１の制御線により第４のスイッチを非導通状態とし、第２の制御線により第１のスイッチを導通状態とすると、駆動トランジスタおよび電気光学素子に電流が流れ、発光を開始する。
このように、本発明に係る画素回路は、画素毎にばらつく駆動トランジスタのしきい値によらず、電気光学素子に電流を供給することができるため、高品位な画像を表示する表示装置を実現することができる。特に従来の技術と比較した場合、制御線から駆動トランジスタへのノイズの影響が少ない構成であるため、より高精度なしきい値ばらつきの補正が可能である。
【００５３】
【発明の実施の形態】
以下、本発明の実施形態を、図面に関連付けて詳細に説明する。
【００５４】
第１実施形態
図５は、アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第１の実施形態を示す回路図である。
【００５５】
本第１の実施形態に係る画素回路３０は、図５に示すように、ｐチャネルＴＦＴ３１〜ＴＦＴ３５、キャパシタＣ３１，Ｃ３２、有機ＥＬ素子ＯＬＥＤ（電気光学素子）からなる発光素子３６、およびノードＮＤ３１を有する。
また、図５において、ＤＴＬ３１はデータ線を、ＳＣＮＬ３１は走査線を、ＡＺＬ３１はオートゼロ線を、ＤＲＶＬ３１は駆動線をそれぞれ示している。
これらの構成要素のうち、ＴＦＴ３１が本発明に係る電界効果トランジスタを構成、ＴＦＴ３２が第１のスイッチを構成し、ＴＦＴ３３が第２のスイッチを構成し、ＴＦＴ３５が第３のスイッチを構成し、ＴＦＴ３４が第４のスイッチを構成、キャパシタＣ３１が本発明に係るキャパシタを構成している。
また、走査線ＳＣＮＬ３１が本発明に係る第１の制御線に対応し、駆動線ＤＲＶＬ３１が第２の制御線に対応し、オートゼロ線ＡＺＬ３１が第３の制御線に対応する。
また、電源電圧Ｖ_DDの供給ライン（電源電位）が第１の基準電位に相当し、接地電位ＧＮＤが第２の基準電位に相当している。
【００５６】
画素回路３０において、ＴＦＴ３１のドレインと第２の基準電位（本実施形態では基準電位ＧＮＤ）との間に光学素子（ＯＬＥＤ）３６が接続されている。具体的には、発光素子３６のアノードがＴＦＴ３１のドレインに接続され、カソード側が接地電位ＧＮＤに接続されている。
ＴＦＴ３１のソースと電源電圧Ｖ_DDの供給ラインに第１のスイッチとしてのＴＦＴ３２のソース・ドレインがそれぞれ接続されている。そして、ＴＦＴ３２のゲートが駆動線ＤＲＶＬ３１に接続されている。
また、ＴＦＴ３１のソースとノードＮＤ３１に第２のスイッチとしてのＴＦＴ３３のソース・ドレインがそれぞれ接続されている。そして、ＴＦＴ３３のゲートがオートゼロ線ＡＺＬ３１に接続されている。
ＴＦＴ３１のゲートと所定の電位（プリチャージ電位）Ｖｐｃに第３のスイッチとしてのＴＦＴ３５のソース・ドレインがそれぞれ接続されている。そして、ＴＦＴ３５のゲートがオートゼロ線ＡＺＬ３１に接続されている。
データ線ＤＴＬ３１とノードＮＤ３１に第４のスイッチとしてのＴＦＴ３４のソース・ドレインがそれぞれ接続されている。そして、ＴＦＴ３４のゲートが走査線ＳＣＮＬ３１に接続されている。
キャパシタＣ３１の第１電極がノードＮＤ３１に接続され、第２電極がＴＦＴ３１のゲートに接続されている。
キャパシタＣ３２の第１電極がノードＮＤ３１に接続され、第２電極が電源電圧Ｖ_DDの供給ラインに接続されている。
【００５７】
この画素回路３０の動作について、図６に示すタイミングチャートを参照しながら以下に説明する。
【００５８】
ステップＳＴ３１：
まず、図６（Ａ），（Ｂ）に示すように、駆動線ＤＲＶＬ３１、オートゼロ線ＡＺＬ３１を低レベルとし、ＴＦＴ３２、ＴＦＴ３３、ＴＦＴ３５を導通状態とする。
このとき、ＴＦＴ３１のゲートは、ＴＦＴ３５によって図６（Ｆ）に示すようにプリチャージ電位Ｖｐｃとなり、キャパシタＣ３１の入力側電位ＶC31 は、ＴＦＴ３２、ＴＦＴ３３が導通状態にあるため図６（Ｅ）に示すように電源電位Ｖ_DDまたはその付近まで上昇する。
【００５９】
ステップＳＴ３２：
図６（Ａ）に示すように、駆動線ＤＲＶＬ３１を高レベルとし、ＴＦＴ３２を非導通状態とする。ＴＦＴ３１に流れる電流が遮断されるため、ＴＦＴ３１のドレイン電位は下降するが、その電位がVpc+|Vth| まで下降した時点でＴＦＴ３１は非導通状態となって電位が安定する。
このとき、キャパシタＣ３１の入力側電位ＶC31 は、ＴＦＴ３３が導通状態にあるため、図６（Ｅ）に示すように、やはり Vpc+|Vth|である。ここで |Vth|は、ＴＦＴ３１のしきい値の絶対値である。
【００６０】
ステップＳＴ３３：
図６（Ｂ）に示すように、オートゼロ線ＡＺＬ３１を高レベルとしてＴＦＴ３３およびＴＦＴ３５を非導通状態とする。キャパシタＣ３１の入力側ノードの電位ＶC31 は、図６（Ｅ）に示すように、Vpc+|Vth| であり、ＴＦＴ３１のゲート電位Ｖg31 は、図６（Ｆ）に示すように、Ｖｐｃである。すなわち、キャパシタＣ３１の端子間の電位差は |Vth|となる。
【００６１】
ステップＳＴ３４：
図６（Ｃ），（Ｄ）に示すように、走査線ＳＣＮＬ３１を低レベルとしてＴＦＴ３４を導通状態とし、データ線ＤＴＬ３１から輝度データに応じた電位ＶdataをキャパシタＣ３１の入力側ノードＮＤ３１に与える。
キャパシタＣ３１端子間の電位差は |Vth|のまま保持されるので、ＴＦＴ３１のゲート電位Ｖg31 は、図６（Ｆ）に示すように、Ｖdata - |Vth|となる。
【００６２】
ステップＳＴ３５：
図６（Ａ），（Ｃ）に示すように、走査線ＳＣＮＬ３１を高レベルとしてＴＦＴ３４を非導通とし、駆動線ＤＲＶＬ３１を低レベルとしてＴＦＴ３２を導通状態とすると、ＴＦＴ３１および発光素子（OLED）３６に電流が流れ、ＯＬＥＤが発光を開始する。
【００６３】
なお、上記のステップＳＴ３１およびＳＴ３２の動作においては、Vpc+|Vth|< VDD となるようにＶｐｃの値を設定する必要があるが、これを満たす限りＶｐｃの値は任意である。
【００６４】
上記動作を行った後に発光素子（OLED）３６に流れる電流Ｉoledを計算すると、ＴＦＴ３１が飽和領域で動作していれば、次のようになる。
【００６５】
【数４】

【００６６】
ここで、μはキャリアの移動度、Ｃｏｘは単位面積当たりのゲート容量、Ｗはゲート幅、Ｌはゲート長をそれぞれ示している。
（４）式によれば、電流ＩoledはＴＦＴ３１のしきい値Ｖｔｈに依存せず（Ｖｔｈによらず）、外部から与えられるＶdataによって制御される。
言い換えれば、図５の画素回路３０を用いれば、画素毎にばらつくＶｔｈの影響を受けず、電流の均一性、ひいては輝度の均一性が比較的高い表示装置を実現することができる。
【００６７】
また、ＴＦＴ３１がリニア領域で動作している場合においても、発光素子（OLED）３６に流れる電流Ｉoledは次のようになり、やはりＶｔｈに依存しない。
【００６８】
【数５】

【００６９】
ここで、ＶｄはＴＦＴ３１のドレイン電位を示している。
【００７０】
以上のように、本第１の実施形態によれば、しきい値Ｖｔｈのばらつきの影響をキャンセルできるという点において、図１の従来例より優れる。
図３の従来例に対しては、次の点において、より優れている。
第１に、図３の従来例においては、外部から駆動するデータ振幅ΔＶdataに対し、駆動トランジスタのゲート振幅ΔVgは（１）式に従って減少するという問題があったが、本発明においてデータ振幅はゲート振幅とほぼ等しく、したがってより小さなデータ線振幅で画素回路を駆動することができる。
これによって、より低消費電力、低ノイズの駆動が可能となる。
第２に、図３の従来例で問題となるオートゼロ線とＴＦＴのゲートとの容量結合については、図５の画素回路３０において、ＴＦＴ３３はＴＦＴ３１のゲートとは直接接続されていないため、その影響が少ない。
一方、ＴＦＴ３５はＴＦＴ３１のゲートと接続されているが、ＴＦＴ３５のソースは一定電位Ｖｐｃに接続されているため、オートゼロ動作終了時においてそのゲート電位が変化しても、ＴＦＴ３１のゲート電位はほぼＶｐｃの電位に保たれる。
このように、図５の画素回路３０においては、オートゼロ線ＡＺＬ３１とＴＦＴ３１のゲートとの結合の影響が小さく、その結果図３の画素回路より正確にＶｔｈばらつきの補正が行われる。
すなわち、本実施形態にによれば、トランジスタのしきい値のばらつきによらず、正確に画素回路の発光素子に所望の値の電流を供給し、その結果として輝度均一性の高い、高品位な画像を表示することが可能な有機ＥＬ用画素回路を実現できる。その結果、従来の類似回路より高精度なしきい値補正が可能となる。
【００７１】
なお、図５の画素回路３０では、すべてＰＭＯＳを用いているが、これは一例であって、本発明はこれに限定されるものではない。たとえば、上述したように、ＴＦＴ３２〜ＴＦＴ３５は単なるスイッチであるから、これらのすべて乃至一部をｎチャネルＭＯＳ、あるいはその他のスイッチ素子で構成することも可能なことは明らかである。
【００７２】
第２実施形態
図７は、アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第２の実施形態を示す回路図である。また、図８は、図７の画素回路の動作を説明するためのタイミングチャートである。
【００７３】
本第２の実施形態が上述した第１の実施形態と異なる点は、第３のスイッチとしてのＴＦＴ３５のソースが一定電位ではなく、データ線ＤＴＬ３１に接続されていることにある。
【００７４】
その他の構成は、上述した図５の回路と同様であり、その動作の詳細な説明はここでは省略する。
【００７５】
本第２の実施形態においては、オートゼロ動作時にはデータ線ＤＴＬ３１からプリチャージ電位Ｖｐｃが与えられるため、図５の回路のように専用の一定電位Ｖｐｃ配線を用意する必要が無いという利点がある。
ただし、データ書き込みに先立って、データ線を必ず一旦Ｖｐｃ電位にする必要がある。
【００７６】
第３実施形態
図９は、アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第３の実施形態を示す回路図である。また、図１０は、図９の画素回路の動作を説明するためのタイミングチャートである。
【００７７】
本第３の実施形態が上述した第１の実施形態と異なる点は、第２のスイッチとしてのＴＦＴ３２のゲートと第３のスイッチとしてのＴＦＴ３５のゲートを共通のオートゼロ線ＡＺＬ３１に接続する代わりに、第２のスイッチとしてのＴＦＴ３２のゲートを第３の制御線としてのオートゼロ線ＡＺＬ３１に接続し、第３のスイッチとしてのＴＦＴ３５のゲートを第４の制御線としてのオートゼロ線ＡＺＬ３２に接続し、かつ、ステップＳＴ３３のオート動作を終了させる処理において、ＴＦＴ３３とＴＦＴ３５を非導通状態に保持する際、ＴＦＴ３３を非導通状態に保持した後、ＴＦＴ３５を非導通状態に保持するように制御している点にある。
【００７８】
この画素回路３０Ｂの動作について、図１０に示すタイミングチャートを参照しながら以下に説明する。
【００７９】
ステップＳＴ３１Ｂ：
まず、図１０（Ａ），（Ｂ），（Ｃ）に示すように、駆動線ＤＲＶＬ３１、オートゼロ線ＡＺＬ３１，ＡＺＬ３２を低レベルとし、ＴＦＴ３２、ＴＦＴ３３、ＴＦＴ３５を導通状態とする。
このとき、ＴＦＴ３１のゲートは、ＴＦＴ３５によって図１０（Ｇ）に示すようにプリチャージ電位Ｖｐｃとなり、キャパシタＣ３１の入力側電位ＶC31 は、ＴＦＴ３２、ＴＦＴ３３が導通状態にあるため図６（Ｆ）に示すように電源電位Ｖ_DDまたはその付近まで上昇する。
【００８０】
ステップＳＴ３２Ｂ：
図１０（Ａ）に示すように、駆動線ＤＲＶＬ３１を高レベルとし、ＴＦＴ３２を非導通状態とする。ＴＦＴ３１に流れる電流が遮断されるため、ＴＦＴ３１のドレイン電位は下降するが、その電位がVpc+|Vth| まで下降した時点でＴＦＴ３１は非導通状態となって電位が安定する。
このとき、キャパシタＣ３１の入力側電位ＶC31 は、ＴＦＴ３３が導通状態にあるため、図１０（Ｆ）に示すように、やはり Vpc+|Vth|である。ここで |Vth|は、ＴＦＴ３１のしきい値の絶対値である。
【００８１】
ステップＳＴ３３Ｂ：
図１０（Ｃ），（Ｃ）に示すように、オートゼロ線ＡＺＬ３１を高レベルとしてＴＦＴ３３を非導通状態とした後、オートゼロ線ＡＺＬ３２を高レベルとしてＴＦＴ３５を非導通状態とする。キャパシタＣ３１の入力側ノードの電位ＶC31は、図１０（Ｆ）に示すように、Vpc+|Vth| であり、ＴＦＴ３１のゲート電位Ｖg31 は、図１０（Ｇ）に示すように、Ｖｐｃである。すなわち、キャパシタＣ３１の端子間の電位差は |Vth|となる。
【００８２】
ステップＳＴ３４Ｂ：
図１０（Ｄ），（Ｅ）に示すように、走査線ＳＣＮＬ３１を低レベルとしてＴＦＴ３４を導通状態とし、データ線ＤＴＬ３１から輝度データに応じた電位ＶdataをキャパシタＣ３１の入力側ノードＮＤ３１に与える。
キャパシタＣ３１端子間の電位差は |Vth|のまま保持されるので、ＴＦＴ３１のゲート電位Ｖg31 は、図１０（Ｇ）に示すように、Ｖdata - |Vth|となる。
【００８３】
ステップＳＴ３５Ｂ：
図１０（Ａ），（Ｄ）に示すように、走査線ＳＣＮＬ３１を高レベルとしてＴＦＴ３４を非導通とし、駆動線ＤＲＶＬ３１を低レベルとしてＴＦＴ３２を導通状態とすると、ＴＦＴ３１および発光素子（OLED）３６に電流が流れ、ＯＬＥＤが発光を開始する。
【００８４】
本第３の実施形態によれば、上述した第１の実施形態の効果と同様の効果を得られ、また、確実なオートゼロ動作を行うことができる。
【００８５】
第４実施形態
図１１は、アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第４の実施形態を示す回路図である。
【００８６】
本第４の実施形態が上述した第３の実施形態と異なる点は、第３のスイッチとしてのＴＦＴ３５のソースが一定電位ではなく、データ線ＤＴＬ３１に接続されていることにある。
【００８７】
その他の構成は、上述した図９の回路と同様であり、その動作の詳細な説明はここでは省略する。
【００８８】
本第４の実施形態においては、オートゼロ動作時にはデータ線ＤＴＬ３１からプリチャージ電位Ｖｐｃが与えられるため、図９の回路のように専用の一定電位Ｖｐｃ配線を用意する必要が無いという利点がある。
ただし、データ書き込みに先立って、データ線を必ず一旦Ｖｐｃ電位にする必要がある。
【００８９】
第５実施形態
図１２は、アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第５の実施形態を示す回路図である。
【００９０】
本第５の実施形態に係る画素回路４０は、図１２に示すように、ｎチャネルＴＦＴ４１〜ＴＦＴ４５、キャパシタＣ４１，Ｃ４２、有機ＥＬ素子ＯＬＥＤ（電気光学素子）からなる発光素子４６、およびノードＮＤ４１を有する。
また、図１２において、ＤＴＬ４１はデータ線を、ＳＣＮＬ４１は第１の制御線としての走査線を、ＡＺＬ４１は第３の制御線としてのオートゼロ線を、ＤＲＶＬ４１は第２の制御線としての駆動線をそれぞれ示している。
これらの構成要素のうち、ＴＦＴ４１が本発明に係る電界効果トランジスタを構成、ＴＦＴ４２が第１のスイッチを構成し、ＴＦＴ４３が第２のスイッチを構成し、ＴＦＴ４５が第３のスイッチを構成し、ＴＦＴ４４が第４のスイッチを構成、キャパシタＣ４１が本発明に係るキャパシタを構成している。
また、電源電圧Ｖ_DDの供給ライン（電源電位）が第１の基準電位に相当し、接地電位ＧＮＤが第２の基準電位に相当している。
【００９１】
画素回路４０において、ＴＦＴ４１のドレインが第１の基準電位（本実施形態では電源電位ＶDD）に接続されている。
ＴＦＴ４１のソースと発光素子４６（発光素子のアノード）に第１のスイッチとしてのＴＦＴ４２のソース・ドレインがそれぞれ接続されている。そして、ＴＦＴ４２のゲートが駆動線ＤＲＶＬ４１に接続されている。また、発光素子４６のカソード側が接地電位ＧＮＤに接続されている。
また、ＴＦＴ４１のソースとノードＮＤ４１に第２のスイッチとしてのＴＦＴ４３のソース・ドレインがそれぞれ接続されている。そして、ＴＦＴ４３のゲートがオートゼロ線ＡＺＬ４１に接続されている。
ＴＦＴ４１のゲートと所定の電位（プリチャージ電位）Ｖｐｃに第３のスイッチとしてのＴＦＴ４５がソース・ドレインがそれぞれ接続されている。そして、ＴＦＴ４５のゲートがオートゼロ線ＡＺＬ４１に接続されている。
データ線ＤＴＬ４１とノードＮＤ４１に第４のスイッチとしてのＴＦＴ４４のソース・ドレインがそれぞれ接続されている。そして、ＴＦＴ４４のゲートが走査線ＳＣＮＬ４１に接続されている。
キャパシタＣ４１の第１電極がノードＮＤ４１に接続され、第２電極がＴＦＴ４１のゲートに接続されている。
キャパシタＣ４２の第１電極がノードＮＤ４１に接続され、第２電極が電源電圧Ｖ_DDの供給ラインに接続されている。
【００９２】
図１２の画素回路４０と図５の画素回路３０との最も大きな違いは、発光素子（OLED）４６に流れる電流を制御するトランジスタＴＦＴ４１がＮＭＯＳであり、そのソースとＯＬＥＤとが接続されている点である。
この画素回路４０の動作について、図１３に示すタイミングチャートを参照しながら以下に説明する。
【００９３】
ステップＳＴ４１：
図１３（Ａ），（Ｂ）に示すように、駆動線ＤＲＶＬ４１、オートゼロ線ＡＺＬ４１を高レベルとし、ＴＦＴ４２、ＴＦＴ４３、ＴＦＴ４５を導通状態とする。このとき、ＴＦＴ４１のゲート電位Ｖg41 はＴＦＴ４５によって、図１３（Ｆ）に示すように、プリチャージ電位Ｖｐｃとなる。Ｖｐｃを十分高い電位とすればＴＦＴ４１が導通状態となり、ＴＦＴ４１および発光素子（OLED）４６に電流が流れる。
【００９４】
ステップＳＴ４２：
図１３（Ａ）に示すように、駆動線ＤＲＶＬ４１を低レベルとし、ＴＦＴ４２を非導通状態とする。ＴＦＴ４１に流れる電流が遮断されるため、ＴＦＴ４１のソース電位は上昇するが、その電位が（Vpc-Vth ）まで上昇した時点でＴＦＴ４１は非導通状態となって電位が安定する。
このとき、キャパシタＣ４１の入力側電位ＶC41 は、ＴＦＴ４３が導通状態にあるため、図１３（Ｅ）に示すように、やはり（ Vpc-Vth）である。ここでＶｔｈは、ＴＦＴ４１のしきい値である。
【００９５】
ステップＳＴ４３：
図１３（Ｂ）に示すように、オートゼロ線ＡＺＬ４１を低レベルとしてＴＦＴ４３およびＴＦＴ４５を非導通状態とする。キャパシタＣ４１の入力側ノードＮＤ４１の電位ＶC41 は、図１３（Ｅ）に示すように、（Vpc - Vth ）であり、ＴＦＴ４１のゲート電位Ｖg41 は、図１３（Ｆ）に示すようにＶｐｃである。すなわち、キャパシタＣ４１の端子間の電位差はＶｔｈとなる。
【００９６】
ステップＳＴ４４：
図１３（Ｃ），（Ｄ）に示すように、走査線ＳＣＮＬ４５１を高レベルとしてＴＦＴ４４を導通状態とし、データ線ＤＴＬ４１から輝度データに応じた電位ＶdataをキャパシタＣ４１の入力側ノードＮＤ４１に与える。キャパシタＣ４１の端子間の電位差はＶｔｈのまま保持されるので、ＴＦＴ４１のゲート電位Ｖg41は、図１３（Ｆ）に示すように、（Vdata + Vth ）となる。
【００９７】
ステップＳＴ４５：
図１３（Ａ），（Ｃ）に示すように、走査線ＳＣＮＬ４１を低レベルとしてＴＦＴ４４を非導通状態とし、駆動線ＤＲＶＬ４１を高レベルとしてＴＦＴ４２を導通状態とすると、ＴＦＴ４１および発光素子（OLED）４６に電流が流れ、OLEDが発光を開始する。
【００９８】
なお、上記ステップＳＴ４１およびＳＴ４２の動作においては、Vth ＿elをOLEDのしきい値としたとき、Vpc-Vth>Vth ＿elとなるようにＶｐｃの値を設定する必要があるが、これを満たす限りＶｐｃの値は任意である。
【００９９】
上記動作を行った後に発光素子（OLED）４６に流れる電流Ｉoledを計算すると、ＴＦＴ３１が飽和領域で動作していれば、次のようになる。
【０１００】
【数６】

【０１０１】
ここで、μはキャリアの移動度、Ｃｏｘは単位面積当たりのゲート容量、Ｗはゲート幅、Ｌはゲート長をそれぞれ示している。
（６）式によれば、発光素子（OLED）４６に流れる電流ＩoledはＴＦＴ４１のしきい値Ｖｔｈによらず、外部から与えられるＶdataによって制御される。
言い換えれば、図１２の画素回路４０を用いれば、画素毎にばらつくＶｔｈの影響を受けず、電流の均一性、ひいては輝度の均一性が比較的高い表示装置を実現することができる。これは、ＴＦＴ４１がリニア領域で動作する場合においても同様である。
【０１０２】
なお、図１２ではすべてＮＭＯＳを用いているが、これは一例であって、本発明はこれに限定されるものではない。たとえば、上述したように、ＴＦＴ４２〜ＴＦＴ４５は単なるスイッチであるから、これらのすべて乃至一部をＰＭＯＳ、あるいはその他のスイッチ素子で構成することも可能なことは明らかである。
【０１０３】
第６実施形態
図１４は、アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第４の実施形態を示す回路図である。
【０１０４】
本第６の実施形態が上述した第５の実施形態と異なる点は、第３のスイッチとしてのＴＦＴ４５のソースが一定電位ではなく、データ線ＤＴＬ４１に接続されていることにある。
【０１０５】
その他の構成は、上述した図１２の回路と同様であり、その動作の詳細な説明はここでは省略する。
【０１０６】
本第６の実施形態においては、オートゼロ動作時にはデータ線ＤＴＬ４１からプリチャージ電位Ｖｐｃが与えられるため、図１２の回路のように専用の一定電位Ｖｐｃ配線を用意する必要が無いという利点がある。
ただし、データ書き込みに先立って、データ線を必ず一旦Ｖｐｃ電位にする必要がある。
【０１０７】
第７実施形態
図１５は、アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第７の実施形態を示す回路図である。また、図１６は、図１５の画素回路の動作を説明するためのタイミングチャートである。
【０１０８】
本第７の実施形態が上述した第５の実施形態と異なる点は、第２のスイッチとしてのＴＦＴ４２のゲートと第３のスイッチとしてのＴＦＴ４５のゲートを共通のオートゼロ線ＡＺＬ４１に接続する代わりに、第２のスイッチとしてのＴＦＴ４２のゲートを第３の制御線としてのオートゼロ線ＡＺＬ４１に接続し、第３のスイッチとしてのＴＦＴ４５のゲートを第４の制御線としてのオートゼロ線ＡＺＬ４２に接続し、かつ、ステップＳＴ４３のオート動作を終了させる処理において、ＴＦＴ４３とＴＦＴ４５を非導通状態に保持する際、ＴＦＴ４３を非導通状態に保持した後、ＴＦＴ４５を非導通状態に保持するように制御している点にある。
【０１０９】
この画素回路４０Ｂの動作について、図１６に示すタイミングチャートを参照しながら以下に説明する。
【０１１０】
ステップＳＴ４１Ｂ：
図１６（Ａ），（Ｂ），（Ｃ）に示すように、駆動線ＤＲＶＬ４１、オートゼロ線ＡＺＬ４１を高レベルとし、ＴＦＴ４２、ＴＦＴ４３、ＴＦＴ４５を導通状態とする。このとき、ＴＦＴ４１のゲート電位Ｖg41 はＴＦＴ４５によって、図１６（Ｇ）に示すように、プリチャージ電位Ｖｐｃとなる。Ｖｐｃを十分高い電位とすればＴＦＴ４１が導通状態となり、ＴＦＴ４１および発光素子（OLED）４６に電流が流れる。
【０１１１】
ステップＳＴ４２Ｂ：
図１６（Ａ）に示すように、駆動線ＤＲＶＬ４１を低レベルとし、ＴＦＴ４２を非導通状態とする。ＴＦＴ４１に流れる電流が遮断されるため、ＴＦＴ４１のソース電位は上昇するが、その電位が（Vpc-Vth ）まで上昇した時点でＴＦＴ４１は非導通状態となって電位が安定する。
このとき、キャパシタＣ４１の入力側電位ＶC41 は、ＴＦＴ４３が導通状態にあるため、図１６（Ｆ）に示すように、やはり（ Vpc-Vth）である。ここでＶｔｈは、ＴＦＴ４１のしきい値である。
【０１１２】
ステップＳＴ４３Ｂ：
図１６（Ｂ），（Ｃ）に示すように、オートゼロ線ＡＺＬ４１を低レベルとしてＴＦＴ４３を非導通状態とした後、オートゼロ線ＡＺＬ４２を低レベルとしてＴＦＴ４５を非導通状態とする。キャパシタＣ４１の入力側ノードＮＤ４１の電位ＶC41 は、図１６（Ｆ）に示すように、（Vpc - Vth ）であり、ＴＦＴ４１のゲート電位Ｖg41 は、図１６（Ｇ）に示すようにＶｐｃである。すなわち、キャパシタＣ４１の端子間の電位差はＶｔｈとなる。
【０１１３】
ステップＳＴ４４Ｂ：
図１６（Ｄ），（Ｅ）に示すように、走査線ＳＣＮＬ４５１を高レベルとしてＴＦＴ４４を導通状態とし、データ線ＤＴＬ４１から輝度データに応じた電位ＶdataをキャパシタＣ４１の入力側ノードＮＤ４１に与える。キャパシタＣ４１の端子間の電位差はＶｔｈのまま保持されるので、ＴＦＴ４１のゲート電位Ｖg41は、図１６（Ｇ）に示すように、（Vdata + Vth ）となる。
【０１１４】
ステップＳＴ４５Ｂ：
図１６（Ａ），（Ｄ）に示すように、走査線ＳＣＮＬ４１を低レベルとしてＴＦＴ４４を非導通状態とし、駆動線ＤＲＶＬ４１を高レベルとしてＴＦＴ４２を導通状態とすると、ＴＦＴ４１および発光素子（OLED）４６に電流が流れ、OLEDが発光を開始する。
【０１１５】
本第７の実施形態によれば、上述した第５の実施形態の効果と同様の効果を得られ、また、確実なオートゼロ動作を行うことができる。
【０１１６】
第８実施形態
図１７は、アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第８の実施形態を示す回路図である。
【０１１７】
本第８の実施形態が上述した第７の実施形態と異なる点は、第３のスイッチとしてのＴＦＴ４５のソースが一定電位ではなく、データ線ＤＴＬ４１に接続されていることにある。
【０１１８】
その他の構成は、上述した図１５の回路と同様であり、その動作の詳細な説明はここでは省略する。
【０１１９】
本第４の実施形態においては、オートゼロ動作時にはデータ線ＤＴＬ４１からプリチャージ電位Ｖｐｃが与えられるため、図１５の回路のように専用の一定電位Ｖｐｃ配線を用意する必要が無いという利点がある。
ただし、データ書き込みに先立って、データ線を必ず一旦Ｖｐｃ電位にする必要がある。
【０１２０】
第９実施形態
本第９の実施形態では、図５の画素回路３０および図１２の画素回路４０を適用可能なアクティブマトリクス型画像表示装置の構成例について説明する。
【０１２１】
図１８は、本第９の実施形態に係るアクティブマトリクス型画像表示装置の構成例を示すブロック図である。
【０１２２】
本第９の実施形態におけるアクティブマトリクス型画像表示装置１００は、図１８に示すように、画素回路３０（または４０）がｎ×ｍのマトリクス状に配列されている。
この画素回路３０（４０）のマトリクス配列に対して、データ線駆動回路（ＤＴＬＤＲＶ）１０１により駆動されるｍ列分のデータ線ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎが画素列毎に配線されている。
また、走査線駆動回路、オートゼロ線駆動回路、および駆動線駆動回路を含むゲート駆動回路（ＧＴＤＲＶ）１０２により駆動される複数系統（本実施形態では３系統）の走査線ＳＣＮＬ１０１−１，オートゼロ線ＡＺＬ１０１−１，駆動線ＤＬＶＬ１０１−１、・・・、走査線ＳＣＮＬ１０１−ｍ、オートゼロ線ＡＺＬ１０１−ｍ，駆動線ＤＬＶＬ１０１−ｍが画素行毎にそれぞれ配線されている。
【０１２３】
なお、図１８の構成においては、各画素回路３０（４０）の第３のスイッチとしてのＴＦＴ３５（またはＴＦＴ４５）のソースは、プリチャージ電位Ｖｐｃに接続されている。
また、走査線ＳＣＮＬ１０１−１〜ＳＣＮＬ１０１−ｍは、図５の走査線３１（図１２の走査線４１）に相当し、オートゼロ線ＡＺＬ１０１−１〜ＡＺＬ１０１−ｍは、図５のオートゼロ線ＡＺＬ３１（図１２のオートゼロ線ＡＺＬ４１）に相当し、駆動線ＤＬＶ１０１−１〜ＤＬＶＬ１０１−ｍは、図５の駆動線ＤＲＶＬ３１（図１２の駆動線ＤＬＶＬ４１）に相当する。
【０１２４】
ゲート駆動回路１０２の、走査線ＳＣＮＬ１０１−１〜ＳＣＮＬ１０１−ｍ、オートゼロ線ＡＺＬ１０１−１〜ＡＺＬ１０１−ｍ、駆動線ＤＬＶ１０１−１〜ＤＬＶＬ１０１−ｍの駆動方法、並びに、データ線駆動回路１０１のデータ線ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎの駆動方法は、図６または図１３に関連付けて説明した画素回路の駆動方法と実質的に同様に行われる。したがって、ここではその詳細な説明は省略する。
【０１２５】
本第９の実施形態によれば、高品位な画像を表示することが可能なアクティブマトリクス型画像表示装置を実現することができる。
【０１２６】
第１０実施形態
本第１０の実施形態では、図７の画素回路３０Ａおよび図１４の画素回路４０Ａを適用可能なアクティブマトリクス型画像表示装置の構成例について説明する。
【０１２７】
図１９は、本第１０の実施形態に係るアクティブマトリクス型画像表示装置の構成例を示すブロック図である。
【０１２８】
本第１０の実施形態におけるアクティブマトリクス型画像表示装置１００Ａは、図１９に示すように、画素回路３０Ａ（または４０Ａ）がｎ×ｍのマトリクス状に配列されている。
この画素回路３０Ａ（４０Ａ）のマトリクス配列に対して、データ線駆動回路（ＤＴＬＤＲＶ）１０１Ａにより駆動されるｍ列分のデータ線ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎが画素列毎に配線されている。
また、走査線駆動回路、オートゼロ線駆動回路、および駆動線駆動回路を含むゲート駆動回路（ＧＴＤＲＶ）１０２により駆動される複数系統（本実施形態では３系統）の走査線ＳＣＮＬ１０１−１，オートゼロ線ＡＺＬ１０１−１，駆動線ＤＬＶＬ１０１−１、・・・、走査線ＳＣＮＬ１０１−ｍ、オートゼロ線ＡＺＬ１０１−ｍ，駆動線ＤＬＶＬ１０１−ｍが画素行毎にそれぞれ配線されている。
【０１２９】
なお、図１９の構成においては、各画素回路３０Ａ（４０Ａ）の第３のスイッチとしてのＴＦＴ３５（またはＴＦＴ４５）のソースは、対応する列に配線されたデータ線ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎに接続されている。
したがって、本第１０の実施形態に係るデータ駆動回路１０１Ａは、データ書き込みに先立って、データ線を必ず一旦Ｖｐｃ電位に設定する。すなわち、オートゼロ動作時には所望のデータ線ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎからプリチャージ電位Ｖｐｃを与える。
また、走査線ＳＣＮＬ１０１−１〜ＳＣＮＬ１０１−ｍは、図７の走査線３１（図１４の走査線４１）に相当し、オートゼロ線ＡＺＬ１０１−１〜ＡＺＬ１０１−ｍは、図７のオートゼロ線ＡＺＬ３１（図１４のオートゼロ線ＡＺＬ４１）に相当し、駆動線ＤＬＶ１０１−１〜ＤＬＶＬ１０１−ｍは、図７の駆動線ＤＲＶＬ３１（図１４の駆動線ＤＬＶＬ４１）に相当する。
【０１３０】
ゲート駆動回路１０２の、走査線ＳＣＮＬ１０１−１〜ＳＣＮＬ１０１−ｍ、オートゼロ線ＡＺＬ１０１−１〜ＡＺＬ１０１−ｍ、駆動線ＤＬＶ１０１−１〜ＤＬＶＬ１０１−ｍの駆動方法、並びに、データ線駆動回路１０１のデータ線ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎの駆動方法は、図８に関連付けて説明した画素回路の駆動方法と実質的に同様に行われる。したがって、ここではその詳細な説明は省略する。
【０１３１】
本第１０の実施形態によれば、高品位な画像を表示することが可能なアクティブマトリクス型画像表示装置を実現することができる。
【０１３２】
第１１実施形態
本第１１の実施形態では、図９の画素回路３０Ｂおよび図１５の画素回路４０Ｂを適用可能なアクティブマトリクス型画像表示装置の構成例について説明する。
【０１３３】
図２０は、本第１１の実施形態に係るアクティブマトリクス型画像表示装置の構成例を示すブロック図である。
【０１３４】
本第１１の実施形態におけるアクティブマトリクス型画像表示装置１００Ｂは、図２０に示すように、画素回路３０Ｂ（または４０Ｂ）がｎ×ｍのマトリクス状に配列されている。
この画素回路３０Ｂ（４０Ｂ）のマトリクス配列に対して、データ線駆動回路（ＤＴＬＤＲＶ）１０１により駆動されるｍ列分のデータ線ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎが画素列毎に配線されている。
また、走査線駆動回路、オートゼロ線駆動回路、および駆動線駆動回路を含むゲート駆動回路（ＧＴＤＲＶ）１０２Ｂにより駆動される複数系統（本実施形態では３系統）の走査線ＳＣＮＬ１０１−１，オートゼロ線ＡＺＬ１０１−１，オートゼロ線ＡＺＬ１０２−１，駆動線ＤＬＶＬ１０１−１、・・・、走査線ＳＣＮＬ１０１−ｍ、オートゼロ線ＡＺＬ１０１−ｍ，オートゼロ線ＡＺＬ１０２−ｍ，駆動線ＤＬＶＬ１０１−ｍが画素行毎にそれぞれ配線されている。
【０１３５】
なお、図２０の構成においては、各画素回路３０Ｂ（４０Ｂ）の第３のスイッチとしてのＴＦＴ３５（またはＴＦＴ４５）のソースは、プリチャージ電位Ｖｐｃに接続されている。
また、走査線ＳＣＮＬ１０１−１〜ＳＣＮＬ１０１−ｍは、図９の走査線３１（図１５の走査線４１）に相当し、オートゼロ線ＡＺＬ１０１−１〜ＡＺＬ１０１−ｍは、図９のオートゼロ線ＡＺＬ３１（図１５のオートゼロ線ＡＺＬ４１）に相当し、オートゼロ線ＡＺＬ１０２−１〜ＡＺＬ１０２−ｍは、図９のオートゼロ線ＡＺＬ３２（図１５のオートゼロ線ＡＺＬ４２）に相当し、駆動線ＤＬＶ１０１−１〜ＤＬＶＬ１０１−ｍは、図９の駆動線ＤＲＶＬ３１（図１５の駆動線ＤＬＶＬ４１）に相当する。
【０１３６】
ゲート駆動回路１０２Ｂの、走査線ＳＣＮＬ１０１−１〜ＳＣＮＬ１０１−ｍ、オートゼロ線ＡＺＬ１０１−１〜ＡＺＬ１０１−ｍ、オートゼロ線ＡＺＬ１０２−１〜ＡＺＬ１０２−ｍ、駆動線ＤＬＶ１０１−１〜ＤＬＶＬ１０１−ｍの駆動方法、並びに、データ線駆動回路１０１のデータ線ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎの駆動方法は、図１０または図１６に関連付けて説明した画素回路の駆動方法と実質的に同様に行われる。したがって、ここではその詳細な説明は省略する。
【０１３７】
本第１１の実施形態によれば、高品位な画像を表示することが可能なアクティブマトリクス型画像表示装置を実現することができる。
【０１３８】
第１２実施形態
本第１２の実施形態では、図１１の画素回路３０Ｃおよび図１７の画素回路４０Ｃを適用可能なアクティブマトリクス型画像表示装置の構成例について説明する。
【０１３９】
図２１は、本第１２の実施形態に係るアクティブマトリクス型画像表示装置の構成例を示すブロック図である。
【０１４０】
本第１２の実施形態におけるアクティブマトリクス型画像表示装置１００Ｃは、図２１に示すように、画素回路３０Ｃ（または４０Ｃ）がｎ×ｍのマトリクス状に配列されている。
この画素回路３０Ｃ（４０Ｃ）のマトリクス配列に対して、データ線駆動回路（ＤＴＬＤＲＶ）１０１Ａにより駆動されるｍ列分のデータ線ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎが画素列毎に配線されている。
また、走査線駆動回路、オートゼロ線駆動回路、および駆動線駆動回路を含むゲート駆動回路（ＧＴＤＲＶ）１０２Ｃにより駆動される複数系統（本実施形態では３系統）の走査線ＳＣＮＬ１０１−１，オートゼロ線ＡＺＬ１０１−１，オートゼロ線ＡＺＬ１０２−１，駆動線ＤＬＶＬ１０１−１、・・・、走査線ＳＣＮＬ１０１−ｍ，オートゼロ線ＡＺＬ１０１−ｍ，オートゼロ線ＡＺＬ１０２−ｍ，駆動線ＤＬＶＬ１０１−ｍが画素行毎にそれぞれ配線されている。
【０１４１】
なお、図２１の構成においては、各画素回路３０Ｃ（４０Ｃ）の第３のスイッチとしてのＴＦＴ３５（またはＴＦＴ４５）のソースは、対応する列に配線されたデータ線ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎに接続されている。
したがって、本第１２の実施形態に係るデータ駆動回路１０１Ａは、データ書き込みに先立って、データ線を必ず一旦Ｖｐｃ電位に設定する。すなわち、オートゼロ動作時には所望のデータ線ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎからプリチャージ電位Ｖｐｃを与える。
また、走査線ＳＣＮＬ１０１−１〜ＳＣＮＬ１０１−ｍは、図１１の走査線３１（図１７の走査線４１）に相当し、オートゼロ線ＡＺＬ１０１−１〜ＡＺＬ１０１−ｍは、図１１のオートゼロ線ＡＺＬ３１（図１７のオートゼロ線ＡＺＬ４１）に相当し、オートゼロ線ＡＺＬ１０２−１〜ＡＺＬ１０２−ｍは、図１１のオートゼロ線ＡＺＬ３２（図１７のオートゼロ線ＡＺＬ４２）に相当し、駆動線ＤＬＶ１０１−１〜ＤＬＶＬ１０１−ｍは、図１１の駆動線ＤＲＶＬ３１（図１７４の駆動線ＤＬＶＬ４１）に相当する。
【０１４２】
ゲート駆動回路１０２Ｃの、走査線ＳＣＮＬ１０１−１〜ＳＣＮＬ１０１−ｍ、オートゼロ線ＡＺＬ１０１−１〜ＡＺＬ１０１−ｍ、オートゼロ線ＡＺＬ１０２−１〜ＡＺＬ１０２−ｍ、駆動線ＤＬＶ１０１−１〜ＤＬＶＬ１０１−ｍの駆動方法、並びに、データ線駆動回路１０１のデータ線ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎの駆動方法は、上述した画素回路の駆動方法と実質的に同様に行われる。したがって、ここではその詳細な説明は省略する。
【０１４３】
本第１２の実施形態によれば、高品位な画像を表示することが可能なアクティブマトリクス型画像表示装置を実現することができる。
【０１４４】
【発明の効果】
以上説明したように、本発明によれば、画素毎にばらつく駆動トランジスタのしきい値によらず、電気光学素子に電流を供給することができる。
このため、高品位な画像を表示する表示装置を提供することができる。
【図面の簡単な説明】
【図１】従来の画素回路の第１の構成例を示す回路図である。
【図２】従来の画像表示装置の構成例を示す図である。
【図３】従来の画素回路の第２の構成例を示す回路図である。
【図４】図３の画素回路の駆動方法を説明するためのタイミングチャートである。
【図５】アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第１の実施形態を示す回路図である。
【図６】図５の画素回路の動作を説明するためのタイミングチャートである。
【図７】アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第２の実施形態を示す回路図である。
【図８】図７の画素回路の動作を説明するためのタイミングチャートである。
【図９】アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第３の実施形態を示す回路図である。
【図１０】図９の画素回路の動作を説明するためのタイミングチャートである。
【図１１】アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第４の実施形態を示す回路図である。
【図１２】アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第５の実施形態を示す回路図である。
【図１３】図１２の画素回路の動作を説明するためのタイミングチャートである。
【図１４】アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第６の実施形態を示す回路図である。
【図１５】アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第７の実施形態を示す回路図である。
【図１６】図１５の画素回路の動作を説明するためのタイミングチャートである。
【図１７】アクティブマトリクス型画像表示装置に適用可能な本発明に係る画素回路の第８の実施形態を示す回路図である。
【図１８】第９の実施形態に係るアクティブマトリクス型画像表示装置の構成例を示すブロック図である。
【図１９】第１０の実施形態に係るアクティブマトリクス型画像表示装置の構成例を示すブロック図である。
【図２０】第１１の実施形態に係るアクティブマトリクス型画像表示装置の構成例を示すブロック図である。
【図２１】第１２の実施形態に係るアクティブマトリクス型画像表示装置の構成例を示すブロック図である。
【符号の説明】
３０，３０Ａ〜３０Ｃ，４０，４０Ａ〜４０Ｃ…画素回路、３１〜３５，４１〜４５…ＴＦＴ、Ｃ３１，Ｃ３２，Ｃ４１，Ｃ４２…キャパシタ、ＮＤ３１，ＮＤ４１…ノード、ＳＣＮＬ３１，ＳＣＮＬ４１…走査線（第１の制御線）、ＡＺＬ３１，ＡＺＬ４１…オートゼロ線（第３の制御線）、ＡＺＬ４２…オートゼロ線（第４の制御線）、ＤＲＶＬ３１，ＤＲＶＬ４１…駆動線（第２の制御線）、１００，１００Ａ〜１００Ｃ…アクティブマトリクス型画像表示装置、１０１，１０１Ａ…データ線駆動回路、１０２，１０２Ｂ，１０２Ｃ…ゲート駆動回路、ＳＣＮＬ１０１−１〜ＳＣＮＬ１０１−ｍ…走査線、ＡＺＬ１０１−１〜ＡＺＬ１０１−ｍ…オートゼロ線、ＡＺＬ１０２−１〜ＡＺＬ１０２−ｍ…オートゼロ線、ＤＬＶ１０１−１〜ＤＬＶＬ１０１−ｍ…駆動線、ＤＴＬ１０１−１〜ＤＴＬ１０１−ｎ…データ線。[0001]
BACKGROUND OF THE INVENTION
The present invention particularly relates to a pixel circuit having an electro-optic element whose luminance is controlled by a current value, such as an organic EL (Electroluminescence) display, and an image display device in which the pixel circuit is arranged in a matrix. The present invention relates to a so-called active matrix type image display device in which the value of a current flowing through an electro-optic element is controlled by an insulated gate field effect transistor provided in the substrate.
[0002]
[Prior art]
In an image display device, such as a liquid crystal display, an image is displayed by arranging a large number of pixels in a matrix and controlling the light intensity for each pixel in accordance with image information to be displayed.
This is the same for an organic EL display or the like, but the organic EL display is a so-called self-luminous display having a light emitting element in each pixel circuit, and has a higher image visibility than a liquid crystal display. There are advantages such as unnecessary and high response speed.
Further, the brightness of each light emitting element is controlled by the value of the current flowing therethrough, that is, it is greatly different from a liquid crystal display or the like in that the light emitting element is a current control type.
[0003]
In the organic EL display, as with the liquid crystal display, a simple matrix method and an active matrix method can be used. However, although the former has a simple structure, it is difficult to realize a large and high-definition display. Due to problems, active matrix systems are actively developed to control the current flowing through the light emitting elements inside each pixel by active elements (typically TFT: Thin Film Transistor) provided inside the pixel. .
[0004]
FIG. 1 is a circuit diagram showing a configuration example of a pixel circuit in an active matrix organic EL display (see, for example, Patent Documents 1 and 2).
A pixel circuit 10 in FIG. 1 includes a p-channel thin film field effect transistor (hereinafter referred to as TFT) 11 and TFT 12, a capacitor C11, and an organic EL element OLED13 which is a light emitting element. In FIG. 1, DTL indicates a data line, and SCNL indicates a scanning line.
Since organic EL elements often have rectifying properties, they are sometimes referred to as OLEDs (Organic Light Emitting Diodes). In FIG. 1 and others, the symbol of a diode is used as a light emitting element. It does not require rectification.
In FIG. 1, the source of the TFT 11 is the power supply potential V_DDThe cathode (cathode) of the light emitting element 13 is connected to the ground potential GND. The operation of the pixel circuit 10 in FIG. 1 is as follows.
[0005]
Step ST1:
When the scanning line SCNL is selected (here, at a low level) and the write potential Vdata is applied to the data line DTL, the TFT 12 becomes conductive and the capacitor C11 is charged or discharged, and the gate potential of the TFT 11 becomes Vdata.
[0006]
Step ST2:
When the scanning line is in a non-selected state (here, high level), the data line DTL and the TFT 11 are electrically disconnected, but the gate potential of the TFT 11 is stably held by the capacitor C11.
[0007]
Step ST3:
The current flowing through the TFT 11 and the light emitting element 13 has a value corresponding to the gate-source voltage Vgs of the TFT 11, and the light emitting element 13 continues to emit light with a luminance corresponding to the current value.
The operation of selecting the scanning line SCNL and transmitting the luminance information given to the data line to the inside of the pixel as in step ST1 is hereinafter referred to as “writing”.
As described above, in the pixel circuit 10 of FIG. 1, once Vdata is written, the light emitting element 13 continues to emit light with a constant luminance until the next rewriting.
[0008]
As shown in FIG. 2, a large number of such pixels are arranged in an n × m matrix, and writing is repeated from the data lines DTL1 to DTLn while sequentially selecting the scanning lines SCNL1 to SCNLm. Can be configured. In FIG. 2, the data lines DTL1 to DTLn are driven by the data line driving circuit (DTLDRV) 15, and the scanning lines SCNL1 to SCNLm are driven by the scanning line driving circuit (SCNLDRV) 16.
[0009]
In the simple matrix image display device, each light emitting element emits light only at the selected moment, whereas in the active matrix, the light emitting element continues to emit light even after the writing is completed. This is particularly advantageous for large-sized and high-definition displays in that peak luminance and peak current can be reduced.
[0010]
Incidentally, in an active matrix organic EL display, a TFT (Thin Film Transistor) formed on a glass substrate is generally used as an active element.
However, it is well known that TFTs have large variations in characteristics. In particular, when a polysilicon TFT is formed on a relatively large glass substrate, in order to avoid problems such as thermal deformation of the glass substrate, crystallization is usually performed by laser annealing after the formation of the amorphous silicon film. . However, it is difficult to uniformly irradiate a large glass substrate with laser energy, and it is inevitable that the crystallization state of polysilicon varies depending on the location in the substrate.
As a result, it is not uncommon for TFTs formed on the same substrate to vary in Vth (threshold) of several hundred mV depending on the pixel, and in some cases 1 V or more.
In this case, for example, even when the same potential Vdata is written to different pixels, the threshold voltage Vth of the TFT 11 varies depending on the pixel. As a result, the current Ids flowing through the light emitting element (OLED) 13 varies greatly from pixel to pixel and is completely different from the desired value. As a result, the display cannot be expected to have high image quality.
[0011]
A number of pixel circuits have been proposed in order to improve this problem. A typical example is shown in FIG. 3 (see, for example, Patent Document 3 or Patent Document 4).
[0012]
The pixel circuit 20 in FIG. 3 includes p-channel TFTs 21 to 24, capacitors C21 and C22, and an organic EL element OLED25 that is a light emitting element. In FIG. 1, DTL indicates a data line, SCNL indicates a scanning line, AZL indicates an auto-zero line, and DRVL indicates a drive line.
The operation of the pixel circuit 20 will be described below with reference to the timing chart shown in FIG.
[0013]
Step ST11:
As shown in FIGS. 4A and 4B, the drive line DRVL and the auto zero line AZL are set to a low level, and the TFTs 22 and 23 are turned on. At this time, since the TFT 21 is connected to the light emitting element (OLED) 25 in a diode-connected state, a current flows through the TFT 21.
[0014]
Step ST12:
As shown in FIG. 4A, the drive line DRVL is set to a high level, and the TFT 22 is turned off. At this time, as shown in FIG. 4C, the scanning line SCNL is at a low level and the TFT 24 is turned on, and the reference potential Vref is applied to the data line DTL as shown in FIG. 4D. Since the current flowing through the TFT 21 is cut off, the gate potential Vg of the TFT 21 rises as shown in FIG. 4E, but when the potential rises to VDD− | Vth |, the TFT 21 becomes non-conductive. Potential stabilizes. Hereinafter, this operation may be referred to as “auto-zero operation”.
[0015]
Step ST13:
As shown in FIGS. 4B and 4D, the auto zero line AZL is set to a high level to turn off the TFT 23, and the potential of the data line DTL is set to a potential that is lower by ΔVdata from Vref. This change in the data line potential lowers the gate potential of the TFT 21 by ΔVg through the capacitor C21 as shown in FIG.
[0016]
Step ST14:
As shown in FIGS. 4A and 4C, when the scanning line SCNL is at a high level and the TFT 24 is turned off, and the driving line DRVL is at a low level and the TFT 22 is turned on, the TFT 21 and the light emitting element (OLED) 25 are turned on. Current flows through the OLED and the OLED starts to emit light.
[0017]
If the parasitic capacitance can be ignored in step ST13, ΔVg and the gate potential Vg of the TFT 21 are as follows.
[0018]
[Expression 1]
ΔVg = ΔVdata × C1 / (C1 + C2) (1)
[0019]
[Expression 2]
Vg = V_DD− | Vth | −ΔVdata × C1 / (C1 + C2) (2)
[0020]
Here, C1 indicates the capacitance value of the capacitor C21, and C2 indicates the capacitance value of the capacitor C22.
[0021]
On the other hand, if the current flowing through the light emitting element (OLED) 25 is Ioled in step ST14, the current value is controlled by the TFT 21 connected in series with the OLED. Assuming that the TFT 21 operates in the saturation region, the following relationship is obtained using the well-known MOS transistor equation and the above equation (2).
[0022]
[Equation 3]

[0023]
Here, μ represents carrier mobility, Cox represents gate capacitance per unit area, W represents gate width, and L represents gate length.
[0024]
According to the equation (3), Ioled is controlled by ΔVdata given from the outside regardless of the threshold value Vth of the TFT 21. In other words, if the pixel circuit 20 of FIG. 3 is used, it is possible to realize a display device that is relatively unaffected by the threshold value Vth that varies from pixel to pixel and that has a relatively high current uniformity and, consequently, luminance uniformity.
[0025]
[Patent Document 1]
USP 5,684,365
[Patent Document 2]
JP-A-8-234683
[Patent Document 3]
USP 6,229,506
[Patent Document 4]
Fig. 1 of JP-T-2002-514320. 3
[0026]
[Problems to be solved by the invention]
As described above, when the pixel circuit 10 as shown in FIG. 1 is used, the uniformity of luminance between pixels is impaired due to variations in the threshold voltage Vth of the transistor, and a high-quality display device can be configured. Have difficulty.
[0027]
On the other hand, if the pixel circuit of FIG. 3 is used, a display device with relatively high luminance uniformity can be realized, but this has the following problems.
[0028]
The first problem is that the gate amplitude ΔVg of the drive transistor decreases according to the equation (1) with respect to the data amplitude ΔVdata driven from the outside. Conversely, in order to obtain the same ΔVg, it is necessary to give a large ΔVdata, which is undesirable from the viewpoint of power consumption and noise.
[0029]
The second problem is that the above description of the operation relating to the pixel circuit 20 of FIG. 3 is ideal, and in practice, the influence of variations in Vth of the TFT 21 that drives the light emitting element (OLED) 25 is not eliminated. .
This is because the auto zero line AZL and the gate node of the TFT 21 are coupled by the gate capacitance of the TFT 23, and the channel charge of the TFT 23 becomes the gate of the TFT 21 in the process in which the auto zero line AZL transitions to a high level and the TFT 23 becomes nonconductive. This is because it flows into the node. The reason for this will be described next.
[0030]
That is, the gate potential of the TFT 21 should ideally be VDD− | Vth | after the completion of the auto-zero operation, but actually becomes a slightly higher potential due to the inflow of the charge, and the inflow amount of the charge is It varies depending on the value of Vth. This is because the gate potential of the TFT 21 immediately before the end of the auto-zero operation is approximately VDD− | Vth |. Therefore, this potential is higher as | Vth | is smaller, for example.
On the other hand, when the auto zero operation ends, when the potential of the auto zero line AZL rises and the TFT 23 switches to non-conduction, the higher the source potential, that is, the gate potential of the TFT 21, the more delayed the timing at which the TFT 23 becomes non-conducting. Will flow into the gate of the TFT 21. As a result, the gate potential of the TFT 21 after completion of the auto-zero operation is affected by | Vth |. Therefore, the above-described equations (2) and (3) are not strictly established, and are affected by Vth which varies from pixel to pixel. become.
[0031]
The present invention has been made in view of such circumstances, and an object of the present invention is to stably and accurately supply a current of a desired value to a light emitting element of each pixel regardless of variations in threshold values of active elements inside the pixel. An object of the present invention is to provide a pixel circuit, a display device, and a driving method of the pixel circuit that can be supplied and can display a high-quality image as a result.
[0032]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of the present invention is a pixel circuit for driving an electro-optical element whose luminance changes according to a flowing current, and at least a data line to which a data signal corresponding to luminance information is supplied, Forming a current supply line between at least the first control line, the node, the first and second reference potentials, the predetermined precharge potential, and the first terminal and the second terminal, And a drive transistor for controlling a current flowing through the current supply line, a first switch connected to the first terminal of the drive transistor, and a first switch connected to the first terminal of the drive transistor and the node. A second switch, a third switch connected between the control terminal of the driving transistor and the predetermined precharge potential, and a connection between the data line and the node. A fourth switch controlled to be conducted by the first control line, and a coupling capacitor connected between the node and a control terminal of the driving transistor, and the first reference potential and the first switch Between the two reference potentials, the current supply line of the drive transistor, the first switch, and the electro-optic element are connected in series.
[0033]
According to a second aspect of the present invention, there is provided a pixel circuit for driving an electro-optical element whose luminance is changed by a flowing current, wherein at least a data line to which a signal corresponding to luminance information is supplied, at least a first control line, , First and second reference potentials, a predetermined precharge potential, a field effect transistor, a node, and a first switch connected between the source of the field effect transistor and the first reference potential A second switch connected between the source of the field effect transistor and the node; a third switch connected between the gate of the field effect transistor and the precharge potential; and the data line. Between the node and the gate of the field-effect transistor, and a fourth switch connected between the node and the node and controlled in conduction by the first control line. It includes a coupling capacitor that is, a, the electro-optical element is connected between the drain and the second reference potential of the field effect transistor.
[0034]
According to a third aspect of the present invention, there is provided a pixel circuit that drives an electro-optical element whose luminance changes according to a flowing current, at least a data line to which a signal corresponding to luminance information is supplied, at least a first control line, First and second reference potentials, a predetermined precharge potential, a field effect transistor, a node, a first switch connected between the source of the field effect transistor and the electro-optic element, A second switch connected between the source of the field effect transistor and the node; a third switch connected between the gate of the field effect transistor and the precharge potential; and the data line; A fourth switch connected between the node and controlled to be conductive by the first control line; and between the node and the gate of the field effect transistor. It has a connection binding capacitors, and the electro-optical element is connected between the first switch and the second reference potential.
[0035]
Preferably, a storage capacitor is connected to the node.
[0036]
Preferably, the predetermined precharge potential is supplied through the data line.
[0037]
Preferably, the conduction of the first switch is controlled by a second control line, and the conduction of the second switch and the third switch is controlled by a third control line.
[0038]
Preferably, the first switch is conductively controlled by a second control line, the second switch is conductively controlled by a third control line, and the third switch is controlled by a fourth control line. Conductivity is controlled.
[0039]
Preferably, when driving the electro-optical element, the first switch, the second switch, and the third switch are used as the first stage by the second control line and the third control line. Is made conductive for a predetermined time, and as the second stage, the first switch is held in a non-conductive state by the second control line, and after the predetermined time has elapsed, the second switch and the second switch are made by the third control line. 3 is held in the non-conductive state, and as the third stage, the fourth switch is made conductive by the first control line, and the data propagated through the data line is written to the node. The fourth switch is held in a non-conductive state, and as the fourth stage, the first switch is made conductive by the second control line, and the data signal is transmitted to the electro-optical element. Depending supplies a current was.
[0040]
Preferably, when the electro-optical element is driven, the first switch is configured by the second control line, the third control line, and the fourth control line as the first stage. 2 switch and the third switch are turned on for a predetermined time, and the second control line is held in a non-conductive state by a second control line as a second stage, and the third control is performed after a predetermined time has passed. After the second switch is held in a non-conductive state by a line, the third switch is held in a non-conductive state by the fourth control line, and as the third stage, the first control line After the fourth switch is turned on and data propagated through the data line is written to the node, the fourth switch is held in a non-conductive state, and the second control line is used as a fourth stage. By Been made conductive is the first switch, for supplying a current corresponding to the data signal to the electro-optical element.
[0041]
In the second aspect, preferably, the precharge potential is set to a value smaller than a value obtained by subtracting the absolute value of the threshold value of the field effect transistor from the first reference potential.
[0042]
In the third aspect, preferably, the precharge potential is set to a value larger than a sum of a threshold value of the electro-optic element and a threshold value of the field effect transistor.
[0043]
A display device according to a fourth aspect of the present invention includes a plurality of pixel circuits arranged in a matrix and wiring for each column with respect to the matrix arrangement of the pixel circuits, and at least a data signal corresponding to luminance information is supplied. A data line, at least a first control line wired for each row with respect to the matrix arrangement of the pixel circuit, first and second reference potentials, and a predetermined precharge potential, Each pixel circuit forms a current supply line between a node, a first terminal and a second terminal, and controls a current flowing through the current supply line in accordance with a potential of a control terminal, and a first transistor of the drive transistor A first switch connected to one terminal; a second switch connected between the first terminal of the driving transistor and the node; a control terminal of the driving transistor; and the predetermined switch. A third switch connected between the charge potential, a fourth switch connected between the data line and the node and controlled to be conductive by the first control line, the node and the drive; A coupling capacitor connected between a control terminal of the transistor and a current supply line of the driving transistor, the first switch, between the first reference potential and the second reference potential, The electro-optical elements are connected in series.
[0044]
A display device according to a fifth aspect of the present invention is provided with a plurality of pixel circuits arranged in a matrix, and wiring for each column with respect to the matrix arrangement of the pixel circuits, and at least a data signal corresponding to luminance information is supplied. A data line, at least a first control line wired for each row with respect to the matrix arrangement of the pixel circuit, first and second reference potentials, and a predetermined precharge potential, Each pixel circuit includes a field effect transistor, a node, a first switch connected between the source of the field effect transistor and a first reference potential, the conduction of which is controlled by the first control line, A second switch connected between the source of the field effect transistor and the node; and a third switch connected between the gate of the field effect transistor and the precharge potential. A fourth switch connected between the data line and the node and controlled to be conductive by the first control line; a coupling capacitor connected between the node and the gate of the field effect transistor; The electro-optic element is connected between the drain of the field effect transistor and a second reference potential.
[0045]
A display device according to a sixth aspect of the present invention includes a plurality of pixel circuits arranged in a matrix and wiring for each column with respect to the matrix arrangement of the pixel circuits, and at least a data signal corresponding to luminance information is supplied. A data line, at least a first control line wired for each row with respect to the matrix arrangement of the pixel circuit, first and second reference potentials, and a predetermined precharge potential, Each pixel circuit includes a field effect transistor, a node, a first switch connected between the source of the field effect transistor and the electro-optic element, and between the source of the field effect transistor and the node. A second switch connected; a third switch connected between the gate of the field effect transistor and the precharge potential; and between the data line and the node. A fourth switch connected and controlled in conduction by the first control line; and a coupling capacitor connected between the node and the gate of the field effect transistor; Connected between the first switch and the second reference potential.
[0046]
Preferably, the conduction of the first switch is controlled by a second control line, and the conduction of the second switch and the third switch is controlled by a third control line.
[0047]
Preferably, the conduction of the first switch is controlled by a second control line, the conduction of the second switch is controlled by a third control line, and the conduction of the third switch is controlled by a fourth control line. Is done.
[0048]
According to a seventh aspect of the present invention, an electro-optical element whose luminance is changed by a flowing current, a current supply line is formed between the first terminal and the second terminal, and the current supply line flows according to the potential of the control terminal. A drive transistor for controlling current; a node; a first switch connected to the first terminal of the drive transistor; a second switch connected between the first terminal of the drive transistor and the node; A third switch connected between the control terminal of the drive transistor and the predetermined precharge potential; a fourth switch connected between the data line and the node; the node; A coupling capacitor connected between the control terminal of the drive transistor and a current supply line of the drive transistor between the first reference potential and the second reference potential A driving method of a pixel circuit in which the first switch and the electro-optic element are connected in series, wherein the first switch, the second switch, and the third switch are turned on for a predetermined time. A first step for holding the first switch in a non-conductive state, a second step for maintaining the second switch and the third switch in a non-conductive state after elapse of a predetermined time, and the fourth step After the switch is turned on and the data propagated through the data line is written to the node, the third step of holding the fourth switch in a non-conductive state and the first switch are turned on, and the electrical And a fourth step of supplying a current corresponding to the data signal to the optical element.
[0049]
According to an eighth aspect of the present invention, there is provided a first electro-optical element whose luminance is changed by a flowing current, a field effect transistor, a node, a source of the field effect transistor, and a first reference potential connected between the first reference potential. A second switch connected between the source of the field effect transistor and the node, a third switch connected between the gate of the field effect transistor and a predetermined potential, A fourth switch connected between the data line and the node; and a coupling capacitor connected between the node and the gate of the field effect transistor. The electro-optic element includes the field effect. A driving method of a pixel circuit connected between a drain of a transistor and a second reference potential, wherein the first switch, the second switch, and the upper A first step of turning on the third switch for a predetermined time; a first step of holding the first switch in a non-conductive state; and holding the second switch and the third switch in a non-conductive state after a predetermined time has elapsed. Two steps, a third step of turning on the fourth switch, writing data propagated through the data line to the node, and then holding the fourth switch in a non-conductive state; and the first step A fourth step of turning on the switch and supplying a current corresponding to the data signal to the electro-optic element.
[0050]
According to a ninth aspect of the present invention, there is provided a first electro-optical element whose luminance is changed by a flowing current, a field effect transistor, a node, a source of the field effect transistor and the electro-optical element connected between the first and second electro-optical elements. A switch, a second switch connected between the source of the field effect transistor and the node, a third switch connected between the gate of the field effect transistor and a predetermined potential, and the data A fourth switch connected between a line and the node; and a coupling capacitor connected between the node and a gate of the field effect transistor, wherein the electro-optic element includes the first switch. A driving method of a pixel circuit connected between a switch and a second reference potential, wherein the first switch, the second switch, and the third switch And a second step of holding the first switch in a non-conducting state and holding the second switch and the third switch in a non-conducting state after elapse of a predetermined time; A third step of conducting the fourth switch and writing the data propagated through the data line to the node; then, holding the fourth switch in a non-conducting state; and conducting the first switch. And a fourth step of supplying a current corresponding to the data signal to the electro-optic element.
[0051]
Preferably, in the second step, when the second switch and the third switch are held in a non-conductive state, the third switch is held after the second switch is held in a non-conductive state. Is kept in a non-conductive state.
[0052]
According to the present invention, the first switch, the second switch, and the second control line, the third control line, or the second control line, the third control line, the fourth control line, for example, The third switch is turned on.
At this time, the control terminal of the driving transistor, for example, the gate is set to the precharge potential Vpc by the third switch, and the input side potential (node potential) of the coupling capacitor is the first and second switches in the conductive state. 1 reference potential (power supply potential V_DD) Or near it.
Then, the first switch is turned off by the second control line. As a result, the current flowing through the drive transistor is cut off, so that the potential of the second terminal (for example, drain) of the drive transistor falls, but when the potential falls to Vpc + | Vth |, the drive transistor becomes non-conductive. To stabilize the potential.
At this time, the input side potential (node potential) of the capacitor is also Vpc + | Vth | because the second switch is in a conductive state. Here, | Vth | is the absolute value of the threshold value of the driving transistor.
Next, the second and third switches are turned off by the third control line. Alternatively, after the second switch is turned off by the third control line, the third switch is turned off by the fourth control line. The potential of the input side node of the capacitor C31 is Vpc + | Vth |, and the gate potential of the driving transistor is Vpc. That is, the potential difference between the terminals of the capacitor C31 is | Vth |.
Next, the fourth switch is turned on by the first control line, and the potential Vdata corresponding to the luminance data is applied from the data line to the input side node of the capacitor.
Since the potential difference between the capacitor terminals is maintained as | Vth |, the gate potential of the driving transistor is Vdata− | Vth |.
Next, when the fourth switch is turned off by the first control line and the first switch is turned on by the second control line, a current flows through the driving transistor and the electro-optical element, and light emission starts. .
As described above, the pixel circuit according to the present invention can supply a current to the electro-optical element regardless of the threshold value of the driving transistor that varies from pixel to pixel, thereby realizing a display device that displays a high-quality image. can do. In particular, when compared with the prior art, the influence of noise from the control line to the drive transistor is small, and therefore, more accurate threshold variation correction can be performed.
[0053]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0054]
First embodiment
FIG. 5 is a circuit diagram showing a first embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device.
[0055]
As shown in FIG. 5, the pixel circuit 30 according to the first embodiment includes p-channel TFTs 31 to 35, capacitors C31 and C32, a light-emitting element 36 including an organic EL element OLED (electro-optical element), and a node ND31. Have.
In FIG. 5, DTL 31 indicates a data line, SCNL 31 indicates a scanning line, AZL 31 indicates an auto-zero line, and DRVL 31 indicates a drive line.
Among these components, the TFT 31 constitutes a field effect transistor according to the present invention, the TFT 32 constitutes a first switch, the TFT 33 constitutes a second switch, the TFT 35 constitutes a third switch, and the TFT 34 Constitutes a fourth switch, and the capacitor C31 constitutes a capacitor according to the present invention.
Further, the scanning line SCNL31 corresponds to the first control line according to the present invention, the drive line DRVL31 corresponds to the second control line, and the auto zero line AZL31 corresponds to the third control line.
Also, the power supply voltage V_DDThe supply line (power supply potential) corresponds to the first reference potential, and the ground potential GND corresponds to the second reference potential.
[0056]
In the pixel circuit 30, an optical element (OLED) 36 is connected between the drain of the TFT 31 and the second reference potential (in this embodiment, the reference potential GND). Specifically, the anode of the light emitting element 36 is connected to the drain of the TFT 31, and the cathode side is connected to the ground potential GND.
TFT 31 source and power supply voltage V_DDThe source and drain of a TFT 32 as a first switch are connected to the supply line. The gate of the TFT 32 is connected to the drive line DRVL31.
The source and drain of the TFT 33 as the second switch are connected to the source of the TFT 31 and the node ND31, respectively. The gate of the TFT 33 is connected to the auto zero line AZL31.
The source and drain of the TFT 35 as a third switch are connected to the gate of the TFT 31 and a predetermined potential (precharge potential) Vpc. The gate of the TFT 35 is connected to the auto zero line AZL31.
The source / drain of the TFT 34 as the fourth switch is connected to the data line DTL 31 and the node ND 31, respectively. The gate of the TFT 34 is connected to the scanning line SCNL31.
A first electrode of the capacitor C31 is connected to the node ND31, and a second electrode is connected to the gate of the TFT31.
The first electrode of the capacitor C32 is connected to the node ND31, and the second electrode is the power supply voltage V_DDConnected to the supply line.
[0057]
The operation of the pixel circuit 30 will be described below with reference to the timing chart shown in FIG.
[0058]
Step ST31:
First, as shown in FIGS. 6A and 6B, the drive line DRVL31 and the auto-zero line AZL31 are set to a low level, and the TFT 32, TFT 33, and TFT 35 are turned on.
At this time, the gate of the TFT 31 becomes the precharge potential Vpc by the TFT 35 as shown in FIG. 6F, and the input side potential VC31 of the capacitor C31 is shown in FIG. 6E because the TFT 32 and the TFT 33 are in the conductive state. Power supply potential V_DDOr rise to the vicinity.
[0059]
Step ST32:
As shown in FIG. 6A, the drive line DRVL31 is set to a high level, and the TFT 32 is turned off. Since the current flowing through the TFT 31 is cut off, the drain potential of the TFT 31 decreases. However, when the potential decreases to Vpc + | Vth |, the TFT 31 becomes non-conductive and the potential is stabilized.
At this time, the input-side potential VC31 of the capacitor C31 is also Vpc + | Vth | as shown in FIG. 6E because the TFT 33 is in a conductive state. Here, | Vth | is the absolute value of the threshold value of the TFT 31.
[0060]
Step ST33:
As shown in FIG. 6B, the auto zero line AZL31 is set to a high level to turn off the TFT 33 and the TFT 35. The potential VC31 of the input side node of the capacitor C31 is Vpc + | Vth | as shown in FIG. 6E, and the gate potential Vg31 of the TFT 31 is Vpc as shown in FIG. 6F. That is, the potential difference between the terminals of the capacitor C31 is | Vth |.
[0061]
Step ST34:
As shown in FIGS. 6C and 6D, the scanning line SCNL31 is set to a low level to turn on the TFT 34, and the potential Vdata corresponding to the luminance data is applied from the data line DTL31 to the input side node ND31 of the capacitor C31.
Since the potential difference between the terminals of the capacitor C31 is held as | Vth |, the gate potential Vg31 of the TFT 31 becomes Vdata− | Vth | as shown in FIG.
[0062]
Step ST35:
As shown in FIGS. 6A and 6C, when the scanning line SCNL31 is at a high level and the TFT 34 is turned off, and the drive line DRVL31 is at a low level and the TFT 32 is turned on, the TFT 31 and the light emitting element (OLED) 36 are connected. A current flows and the OLED starts to emit light.
[0063]
In the operations of steps ST31 and ST32, it is necessary to set the value of Vpc so that Vpc + | Vth | <VDD. However, as long as this value is satisfied, the value of Vpc is arbitrary.
[0064]
When the current Ioled flowing through the light emitting element (OLED) 36 is calculated after the above operation is performed, if the TFT 31 operates in the saturation region, the following is obtained.
[0065]
[Expression 4]

[0066]
Here, μ represents carrier mobility, Cox represents gate capacitance per unit area, W represents gate width, and L represents gate length.
According to the equation (4), the current Ioled does not depend on the threshold value Vth of the TFT 31 (regardless of Vth) and is controlled by Vdata supplied from the outside.
In other words, when the pixel circuit 30 in FIG. 5 is used, it is possible to realize a display device that is relatively free from the influence of Vth, which varies from pixel to pixel, and that has relatively high current uniformity and consequently luminance uniformity.
[0067]
Further, even when the TFT 31 operates in the linear region, the current Ioled flowing through the light emitting element (OLED) 36 is as follows and is not dependent on Vth.
[0068]
[Equation 5]

[0069]
Here, Vd indicates the drain potential of the TFT 31.
[0070]
As described above, according to the first embodiment, the influence of the variation in the threshold value Vth can be canceled, which is superior to the conventional example of FIG.
3 is superior to the conventional example of FIG. 3 in the following points.
First, the conventional example of FIG. 3 has a problem that the gate amplitude ΔVg of the driving transistor decreases according to the equation (1) with respect to the data amplitude ΔVdata driven from the outside. The pixel circuit can be driven with a data line amplitude that is substantially equal to the amplitude and therefore smaller.
This enables driving with lower power consumption and lower noise.
Second, regarding the capacitive coupling between the auto-zero line and the TFT gate, which is a problem in the conventional example of FIG. 3, the TFT 33 is not directly connected to the gate of the TFT 31 in the pixel circuit 30 of FIG. Less is.
On the other hand, the TFT 35 is connected to the gate of the TFT 31, but since the source of the TFT 35 is connected to the constant potential Vpc, even if the gate potential changes at the end of the auto-zero operation, the gate potential of the TFT 31 is approximately Vpc. Kept at potential.
Thus, in the pixel circuit 30 of FIG. 5, the influence of the coupling between the auto zero line AZL 31 and the gate of the TFT 31 is small, and as a result, the Vth variation is corrected more accurately than the pixel circuit of FIG.
That is, according to the present embodiment, a current having a desired value is accurately supplied to the light emitting element of the pixel circuit regardless of variations in the threshold value of the transistor, and as a result, high luminance uniformity and high quality are achieved. An organic EL pixel circuit capable of displaying an image can be realized. As a result, the threshold value can be corrected with higher accuracy than the conventional similar circuit.
[0071]
In the pixel circuit 30 of FIG. 5, all the PMOS is used, but this is an example, and the present invention is not limited to this. For example, as described above, since the TFTs 32 to 35 are merely switches, it is obvious that all or a part of them can be constituted by an n-channel MOS or other switching elements.
[0072]
Second embodiment
FIG. 7 is a circuit diagram showing a second embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device. FIG. 8 is a timing chart for explaining the operation of the pixel circuit of FIG.
[0073]
The second embodiment differs from the first embodiment described above in that the source of the TFT 35 as the third switch is not at a constant potential but is connected to the data line DTL31.
[0074]
Other configurations are the same as those of the circuit of FIG. 5 described above, and a detailed description of the operation is omitted here.
[0075]
In the second embodiment, since the precharge potential Vpc is applied from the data line DTL31 during the auto-zero operation, there is an advantage that it is not necessary to prepare a dedicated constant potential Vpc wiring unlike the circuit of FIG.
However, prior to data writing, the data line must be once set to the Vpc potential.
[0076]
Third embodiment
FIG. 9 is a circuit diagram showing a third embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device. FIG. 10 is a timing chart for explaining the operation of the pixel circuit of FIG.
[0077]
The third embodiment is different from the first embodiment described above in that instead of connecting the gate of the TFT 32 as the second switch and the gate of the TFT 35 as the third switch to the common auto-zero line AZL31, The gate of the TFT 32 as the second switch is connected to the auto-zero line AZL31 as the third control line, the gate of the TFT 35 as the third switch is connected to the auto-zero line AZL32 as the fourth control line, and In the process of terminating the automatic operation in step ST33, when the TFT 33 and the TFT 35 are held in a non-conductive state, the TFT 35 is controlled to be held in a non-conductive state after the TFT 33 is held in a non-conductive state. .
[0078]
The operation of the pixel circuit 30B will be described below with reference to the timing chart shown in FIG.
[0079]
Step ST31B:
First, as shown in FIGS. 10A, 10B, and 10C, the drive line DRVL31 and the auto-zero lines AZL31 and AZL32 are set to a low level, and the TFTs 32, 33, and 35 are turned on.
At this time, the gate of the TFT 31 becomes the precharge potential Vpc by the TFT 35 as shown in FIG. 10G, and the input side potential VC31 of the capacitor C31 is shown in FIG. 6F because the TFT 32 and the TFT 33 are in the conductive state. Power supply potential V_DDOr rise to the vicinity.
[0080]
Step ST32B:
As shown in FIG. 10A, the drive line DRVL31 is set to a high level, and the TFT 32 is turned off. Since the current flowing through the TFT 31 is cut off, the drain potential of the TFT 31 decreases. However, when the potential decreases to Vpc + | Vth |, the TFT 31 becomes non-conductive and the potential is stabilized.
At this time, the input-side potential VC31 of the capacitor C31 is also Vpc + | Vth | as shown in FIG. Here, | Vth | is the absolute value of the threshold value of the TFT 31.
[0081]
Step ST33B:
As shown in FIGS. 10C and 10C, after the auto zero line AZL31 is set to the high level and the TFT 33 is turned off, the auto zero line AZL32 is set to the high level and the TFT 35 is turned off. The potential VC31 of the input side node of the capacitor C31 is Vpc + | Vth | as shown in FIG. 10 (F), and the gate potential Vg31 of the TFT 31 is Vpc as shown in FIG. 10 (G). That is, the potential difference between the terminals of the capacitor C31 is | Vth |.
[0082]
Step ST34B:
As shown in FIGS. 10D and 10E, the scanning line SCNL31 is set to a low level to make the TFT 34 conductive, and the potential Vdata corresponding to the luminance data is supplied from the data line DTL31 to the input side node ND31 of the capacitor C31.
Since the potential difference between the terminals of the capacitor C31 is held as | Vth |, the gate potential Vg31 of the TFT 31 becomes Vdata− | Vth | as shown in FIG.
[0083]
Step ST35B:
As shown in FIGS. 10A and 10D, when the scanning line SCNL31 is high and the TFT 34 is non-conductive, and the drive line DRVL31 is low and the TFT 32 is conductive, the TFT 31 and the light emitting element (OLED) 36 are connected. A current flows and the OLED starts to emit light.
[0084]
According to the third embodiment, the same effects as those of the first embodiment described above can be obtained, and a reliable auto-zero operation can be performed.
[0085]
Fourth embodiment
FIG. 11 is a circuit diagram showing a fourth embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device.
[0086]
The fourth embodiment is different from the third embodiment described above in that the source of the TFT 35 as the third switch is not at a constant potential but is connected to the data line DTL31.
[0087]
Other configurations are the same as those of the circuit of FIG. 9 described above, and a detailed description of the operation is omitted here.
[0088]
In the fourth embodiment, since the precharge potential Vpc is supplied from the data line DTL31 during the auto zero operation, there is an advantage that it is not necessary to prepare a dedicated constant potential Vpc wiring unlike the circuit of FIG.
However, prior to data writing, the data line must be once set to the Vpc potential.
[0089]
Fifth embodiment
FIG. 12 is a circuit diagram showing a fifth embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device.
[0090]
As shown in FIG. 12, the pixel circuit 40 according to the fifth embodiment includes n-channel TFTs 41 to 45, capacitors C41 and C42, a light-emitting element 46 including an organic EL element OLED (electro-optical element), and a node ND41. Have.
In FIG. 12, DTL 41 is a data line, SCNL 41 is a scan line as a first control line, AZL 41 is an auto-zero line as a third control line, and DRVL 41 is a drive line as a second control line. Each is shown.
Among these components, the TFT 41 constitutes a field effect transistor according to the present invention, the TFT 42 constitutes a first switch, the TFT 43 constitutes a second switch, the TFT 45 constitutes a third switch, and the TFT 44 Constitutes a fourth switch, and the capacitor C41 constitutes a capacitor according to the present invention.
Also, the power supply voltage V_DDThe supply line (power supply potential) corresponds to the first reference potential, and the ground potential GND corresponds to the second reference potential.
[0091]
In the pixel circuit 40, the drain of the TFT 41 is connected to the first reference potential (power supply potential VDD in the present embodiment).
The source and drain of the TFT 42 as the first switch are connected to the source of the TFT 41 and the light emitting element 46 (the anode of the light emitting element). The gate of the TFT 42 is connected to the drive line DRVL41. In addition, the cathode side of the light emitting element 46 is connected to the ground potential GND.
Further, the source and drain of the TFT 43 as the second switch are connected to the source of the TFT 41 and the node ND41, respectively. The gate of the TFT 43 is connected to the auto zero line AZL41.
A TFT 45 as a third switch is connected to the gate of the TFT 41 and a predetermined potential (precharge potential) Vpc at its source and drain. The gate of the TFT 45 is connected to the auto zero line AZL41.
The source / drain of the TFT 44 as the fourth switch is connected to the data line DTL41 and the node ND41, respectively. The gate of the TFT 44 is connected to the scanning line SCNL41.
A first electrode of the capacitor C41 is connected to the node ND41, and a second electrode is connected to the gate of the TFT 41.
The first electrode of the capacitor C42 is connected to the node ND41, and the second electrode is connected to the power supply voltage V_DDConnected to the supply line.
[0092]
The biggest difference between the pixel circuit 40 of FIG. 12 and the pixel circuit 30 of FIG. 5 is that the transistor TFT 41 for controlling the current flowing through the light emitting element (OLED) 46 is an NMOS, and its source is connected to the OLED. It is.
The operation of the pixel circuit 40 will be described below with reference to the timing chart shown in FIG.
[0093]
Step ST41:
As shown in FIGS. 13A and 13B, the drive line DRVL41 and the auto-zero line AZL41 are set to a high level, and the TFT 42, TFT 43, and TFT 45 are turned on. At this time, the gate potential Vg41 of the TFT 41 becomes the precharge potential Vpc by the TFT 45 as shown in FIG. If Vpc is set to a sufficiently high potential, the TFT 41 becomes conductive, and a current flows through the TFT 41 and the light emitting element (OLED) 46.
[0094]
Step ST42:
As shown in FIG. 13A, the drive line DRVL41 is set to a low level, and the TFT 42 is turned off. Since the current flowing through the TFT 41 is cut off, the source potential of the TFT 41 rises, but when the potential rises to (Vpc−Vth), the TFT 41 becomes non-conductive and the potential is stabilized.
At this time, the input-side potential VC41 of the capacitor C41 is still (Vpc−Vth) as shown in FIG. 13E because the TFT 43 is in a conductive state. Here, Vth is a threshold value of the TFT 41.
[0095]
Step ST43:
As shown in FIG. 13B, the auto-zero line AZL41 is set to a low level, and the TFT 43 and the TFT 45 are made non-conductive. The potential VC41 of the input side node ND41 of the capacitor C41 is (Vpc−Vth) as shown in FIG. 13E, and the gate potential Vg41 of the TFT 41 is Vpc as shown in FIG. 13F. That is, the potential difference between the terminals of the capacitor C41 is Vth.
[0096]
Step ST44:
As shown in FIGS. 13C and 13D, the scanning line SCNL451 is set to a high level to turn on the TFT 44, and the potential Vdata corresponding to the luminance data is supplied from the data line DTL41 to the input side node ND41 of the capacitor C41. Since the potential difference between the terminals of the capacitor C41 is held at Vth, the gate potential Vg41 of the TFT 41 is (Vdata + Vth) as shown in FIG.
[0097]
Step ST45:
As shown in FIGS. 13A and 13C, when the scanning line SCNL41 is at a low level and the TFT 44 is turned off, and the driving line DRVL41 is at a high level and the TFT 42 is turned on, the TFT 41 and the light emitting element (OLED) 46 are turned on. Current flows through the OLED and the OLED starts to emit light.
[0098]
In the operations of steps ST41 and ST42, it is necessary to set the value of Vpc so that Vpc_Vth> Vth_el when Vth_el is the threshold value of OLED. The value of is arbitrary.
[0099]
When the current Ioled flowing through the light emitting element (OLED) 46 is calculated after the above operation is performed, if the TFT 31 operates in the saturation region, the following is obtained.
[0100]
[Formula 6]

[0101]
Here, μ represents carrier mobility, Cox represents gate capacitance per unit area, W represents gate width, and L represents gate length.
According to the equation (6), the current Ioled flowing through the light emitting element (OLED) 46 is controlled by Vdata applied from the outside regardless of the threshold value Vth of the TFT 41.
In other words, by using the pixel circuit 40 in FIG. 12, it is possible to realize a display device that is relatively free from the influence of Vth, which varies from pixel to pixel, and that has relatively high current uniformity and consequently luminance uniformity. This is the same when the TFT 41 operates in the linear region.
[0102]
In FIG. 12, all NMOSs are used, but this is only an example, and the present invention is not limited to this. For example, as described above, since the TFTs 42 to 45 are mere switches, it is obvious that all or a part of them can be composed of PMOS or other switch elements.
[0103]
Sixth embodiment
FIG. 14 is a circuit diagram showing a fourth embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device.
[0104]
The sixth embodiment is different from the fifth embodiment described above in that the source of the TFT 45 as the third switch is connected to the data line DTL 41 instead of a constant potential.
[0105]
Other configurations are the same as those of the circuit of FIG. 12 described above, and a detailed description of the operation is omitted here.
[0106]
In the sixth embodiment, since the precharge potential Vpc is applied from the data line DTL41 during the auto-zero operation, there is an advantage that it is not necessary to prepare a dedicated constant potential Vpc wiring unlike the circuit of FIG.
However, prior to data writing, the data line must be once set to the Vpc potential.
[0107]
Seventh embodiment
FIG. 15 is a circuit diagram showing a seventh embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device. FIG. 16 is a timing chart for explaining the operation of the pixel circuit of FIG.
[0108]
The seventh embodiment is different from the fifth embodiment described above in that instead of connecting the gate of the TFT 42 as the second switch and the gate of the TFT 45 as the third switch to the common auto zero line AZL41, The gate of the TFT 42 as the second switch is connected to the auto-zero line AZL41 as the third control line, the gate of the TFT 45 as the third switch is connected to the auto-zero line AZL42 as the fourth control line, and In the process of terminating the automatic operation in step ST43, when the TFT 43 and the TFT 45 are held in the non-conductive state, the TFT 45 is held in the non-conductive state and then the TFT 45 is controlled to be held in the non-conductive state. .
[0109]
The operation of the pixel circuit 40B will be described below with reference to the timing chart shown in FIG.
[0110]
Step ST41B:
As shown in FIGS. 16A, 16B, and 16C, the drive line DRVL41 and the auto-zero line AZL41 are set to a high level, and the TFTs 42, 43, and 45 are turned on. At this time, the gate potential Vg41 of the TFT 41 becomes the precharge potential Vpc by the TFT 45 as shown in FIG. If Vpc is set to a sufficiently high potential, the TFT 41 becomes conductive, and a current flows through the TFT 41 and the light emitting element (OLED) 46.
[0111]
Step ST42B:
As shown in FIG. 16A, the drive line DRVL41 is set to a low level, and the TFT 42 is turned off. Since the current flowing through the TFT 41 is cut off, the source potential of the TFT 41 rises, but when the potential rises to (Vpc−Vth), the TFT 41 becomes non-conductive and the potential is stabilized.
At this time, the input side potential VC41 of the capacitor C41 is still (Vpc−Vth) as shown in FIG. Here, Vth is a threshold value of the TFT 41.
[0112]
Step ST43B:
As shown in FIGS. 16B and 16C, after the auto zero line AZL41 is set to a low level to make the TFT 43 non-conductive, the auto zero line AZL42 is set to a low level to make the TFT 45 non-conductive. The potential VC41 of the input side node ND41 of the capacitor C41 is (Vpc−Vth) as shown in FIG. 16F, and the gate potential Vg41 of the TFT 41 is Vpc as shown in FIG. That is, the potential difference between the terminals of the capacitor C41 is Vth.
[0113]
Step ST44B:
As shown in FIGS. 16D and 16E, the scanning line SCNL451 is set to a high level to turn on the TFT 44, and the potential Vdata corresponding to the luminance data is supplied from the data line DTL41 to the input side node ND41 of the capacitor C41. Since the potential difference between the terminals of the capacitor C41 is maintained at Vth, the gate potential Vg41 of the TFT 41 is (Vdata + Vth) as shown in FIG.
[0114]
Step ST45B:
As shown in FIGS. 16A and 16D, when the scanning line SCNL41 is at a low level and the TFT 44 is turned off, and the driving line DRVL41 is at a high level and the TFT 42 is turned on, the TFT 41 and the light emitting element (OLED) 46 are turned on. Current flows through the OLED and the OLED starts to emit light.
[0115]
According to the seventh embodiment, the same effect as that of the fifth embodiment described above can be obtained, and a reliable auto-zero operation can be performed.
[0116]
Eighth embodiment
FIG. 17 is a circuit diagram showing an eighth embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device.
[0117]
The eighth embodiment is different from the seventh embodiment described above in that the source of the TFT 45 as the third switch is not at a constant potential but is connected to the data line DTL41.
[0118]
Other configurations are the same as those of the circuit of FIG. 15 described above, and a detailed description of the operation is omitted here.
[0119]
In the fourth embodiment, since the precharge potential Vpc is supplied from the data line DTL41 during the auto-zero operation, there is an advantage that it is not necessary to prepare a dedicated constant potential Vpc wiring unlike the circuit of FIG.
However, prior to data writing, the data line must be once set to the Vpc potential.
[0120]
Ninth embodiment
In the ninth embodiment, a configuration example of an active matrix image display device to which the pixel circuit 30 in FIG. 5 and the pixel circuit 40 in FIG. 12 can be applied will be described.
[0121]
FIG. 18 is a block diagram showing a configuration example of an active matrix image display apparatus according to the ninth embodiment.
[0122]
In the active matrix image display device 100 according to the ninth embodiment, as shown in FIG. 18, pixel circuits 30 (or 40) are arranged in an n × m matrix.
Data lines DTL 101-1 to DTL 101-n for m columns driven by the data line driving circuit (DTLDRV) 101 are wired for each pixel column in the matrix arrangement of the pixel circuits 30 (40).
Also, a plurality of (three in this embodiment) scanning lines SCNL 101-1 and auto-zero lines AZL101 driven by a gate driving circuit (GTDRV) 102 including a scanning line driving circuit, an auto-zero line driving circuit, and a driving line driving circuit. −1, drive line DLVL101-1,..., Scan line SCNL101-m, auto zero line AZL101-m, and drive line DLVL101-m are wired for each pixel row.
[0123]
In the configuration of FIG. 18, the source of the TFT 35 (or TFT 45) as the third switch of each pixel circuit 30 (40) is connected to the precharge potential Vpc.
The scanning lines SCNL101-1 to SCNL101-m correspond to the scanning line 31 in FIG. 5 (scanning line 41 in FIG. 12), and the autozero lines AZL101-1 to AZL101-m correspond to the autozero line AZL31 in FIG. And the drive lines DLV101-1 to DLVL101-m correspond to the drive line DRVL31 in FIG. 5 (drive line DLVL41 in FIG. 12).
[0124]
Driving method of scanning lines SCNL 101-1 to SCNL 101-m, auto zero lines AZL 101-1 to AZL 101-m, driving lines DLV 101-1 to DLVL 101-m, and data line DTL 101 of data line driving circuit 101 of gate driving circuit 102 The driving method of −1 to DTL 101-n is substantially the same as the driving method of the pixel circuit described in relation to FIG. 6 or FIG. Therefore, detailed description thereof is omitted here.
[0125]
According to the ninth embodiment, an active matrix image display device capable of displaying a high-quality image can be realized.
[0126]
Tenth embodiment
In the tenth embodiment, a configuration example of an active matrix image display device to which the pixel circuit 30A in FIG. 7 and the pixel circuit 40A in FIG. 14 can be applied will be described.
[0127]
FIG. 19 is a block diagram illustrating a configuration example of an active matrix image display device according to the tenth embodiment.
[0128]
In the active matrix image display device 100A according to the tenth embodiment, as shown in FIG. 19, pixel circuits 30A (or 40A) are arranged in an n × m matrix.
Data lines DTL101-1 to DTL101-n for m columns driven by the data line driving circuit (DTLDRV) 101A are wired to the matrix arrangement of the pixel circuits 30A (40A) for each pixel column.
Also, a plurality of (three in this embodiment) scanning lines SCNL 101-1 and auto-zero lines AZL101 driven by a gate driving circuit (GTDRV) 102 including a scanning line driving circuit, an auto-zero line driving circuit, and a driving line driving circuit. −1, drive line DLVL101-1,..., Scan line SCNL101-m, auto zero line AZL101-m, and drive line DLVL101-m are wired for each pixel row.
[0129]
In the configuration of FIG. 19, the source of the TFT 35 (or TFT 45) as the third switch of each pixel circuit 30A (40A) is connected to the data lines DTL101-1 to DTL101-n wired in the corresponding column. Has been.
Therefore, the data drive circuit 101A according to the tenth embodiment always sets the data line to the Vpc potential before writing data. That is, the precharge potential Vpc is applied from the desired data lines DTL101-1 to DTL101-n during the auto zero operation.
The scanning lines SCNL101-1 to SCNL101-m correspond to the scanning line 31 in FIG. 7 (scanning line 41 in FIG. 14), and the autozero lines AZL101-1 to AZL101-m correspond to the autozero line AZL31 in FIG. 14 auto-zero lines AZL41), and the drive lines DLV101-1 to DLVL101-m correspond to the drive line DRVL31 of FIG. 7 (drive line DLVL41 of FIG. 14).
[0130]
Driving method of scanning lines SCNL 101-1 to SCNL 101-m, auto zero lines AZL 101-1 to AZL 101-m, driving lines DLV 101-1 to DLVL 101-m, and data line DTL 101 of data line driving circuit 101 of gate driving circuit 102 The driving method of −1 to DTL 101-n is performed in substantially the same manner as the driving method of the pixel circuit described with reference to FIG. Therefore, detailed description thereof is omitted here.
[0131]
According to the tenth embodiment, an active matrix image display device capable of displaying a high-quality image can be realized.
[0132]
Eleventh embodiment
In the eleventh embodiment, a configuration example of an active matrix image display device to which the pixel circuit 30B in FIG. 9 and the pixel circuit 40B in FIG. 15 can be applied will be described.
[0133]
FIG. 20 is a block diagram illustrating a configuration example of the active matrix image display apparatus according to the eleventh embodiment.
[0134]
In the active matrix image display device 100B according to the eleventh embodiment, as shown in FIG. 20, pixel circuits 30B (or 40B) are arranged in an n × m matrix.
Data lines DTL101-1 to DTL101-n for m columns driven by the data line driving circuit (DTLDRV) 101 are wired for each pixel column in the matrix arrangement of the pixel circuits 30B (40B).
Further, a plurality of lines (three lines in this embodiment) of scanning lines SCNL 101-1 and auto-zero lines AZL101 driven by a gate driving circuit (GTDRV) 102B including a scanning line driving circuit, an auto-zero line driving circuit, and a driving line driving circuit. −1, auto zero line AZL102-1, drive line DLVL101-1,..., Scanning line SCNL101-m, autozero line AZL101-m, autozero line AZL102-m, and driveline DLVL101-m are wired for each pixel row. ing.
[0135]
In the configuration of FIG. 20, the source of the TFT 35 (or TFT 45) as the third switch of each pixel circuit 30B (40B) is connected to the precharge potential Vpc.
The scanning lines SCNL101-1 to SCNL101-m correspond to the scanning line 31 in FIG. 9 (scanning line 41 in FIG. 15), and the autozero lines AZL101-1 to AZL101-m correspond to the autozero line AZL31 in FIG. 15 auto-zero line AZL41), auto-zero lines AZL102-1 to AZL102-m correspond to auto-zero line AZL32 in FIG. 9 (auto-zero line AZL42 in FIG. 15), and drive lines DLV101-1 to DLVL101-m are This corresponds to the drive line DRVL31 in FIG. 9 (drive line DLVL41 in FIG. 15).
[0136]
Driving method of scanning lines SCNL101-1 to SCNL101-m, auto-zero lines AZL101-1 to AZL101-m, auto-zero lines AZL102-1 to AZL102-m, drive lines DLV101-1 to DLVL101-m in the gate drive circuit 102B, and The driving method of the data lines DTL 101-1 to DTL 101-n of the data line driving circuit 101 is substantially the same as the driving method of the pixel circuit described in relation to FIG. 10 or FIG. Therefore, detailed description thereof is omitted here.
[0137]
According to the eleventh embodiment, an active matrix type image display device capable of displaying a high-quality image can be realized.
[0138]
12th embodiment
In the twelfth embodiment, a configuration example of an active matrix image display device to which the pixel circuit 30C in FIG. 11 and the pixel circuit 40C in FIG. 17 can be applied will be described.
[0139]
FIG. 21 is a block diagram illustrating a configuration example of an active matrix image display apparatus according to the twelfth embodiment.
[0140]
In an active matrix image display device 100C according to the twelfth embodiment, as shown in FIG. 21, pixel circuits 30C (or 40C) are arranged in an n × m matrix.
Data lines DTL101-1 to DTL101-n for m columns driven by the data line driving circuit (DTLDRV) 101A are wired for each pixel column in the matrix arrangement of the pixel circuit 30C (40C).
Also, a plurality of (three in this embodiment) scanning lines SCNL 101-1 and auto-zero lines AZL101 driven by a gate driving circuit (GTDRV) 102C including a scanning line driving circuit, an auto-zero line driving circuit, and a driving line driving circuit. −1, auto-zero line AZL102-1, drive line DLVL101-1,..., Scanning line SCNL101-m, autozero line AZL101-m, autozero line AZL102-m, and driveline DLVL101-m are wired for each pixel row. ing.
[0141]
In the configuration of FIG. 21, the source of the TFT 35 (or TFT 45) as the third switch of each pixel circuit 30C (40C) is connected to the data lines DTL101-1 to DTL101-n wired in the corresponding column. Has been.
Therefore, the data driving circuit 101A according to the twelfth embodiment always sets the data line to the Vpc potential before writing data. That is, the precharge potential Vpc is applied from the desired data lines DTL101-1 to DTL101-n during the auto zero operation.
The scanning lines SCNL101-1 to SCNL101-m correspond to the scanning line 31 in FIG. 11 (scanning line 41 in FIG. 17), and the autozero lines AZL101-1 to AZL101-m correspond to the autozero line AZL31 in FIG. 17 auto-zero line AZL41), auto-zero lines AZL102-1 to AZL102-m correspond to auto-zero line AZL32 in FIG. 11 (auto-zero line AZL42 in FIG. 17), and drive lines DLV101-1 to DLVL101-m are This corresponds to the drive line DRVL31 in FIG. 11 (drive line DLVL41 in FIG. 174).
[0142]
Driving method of scanning lines SCNL101-1 to SCNL101-m, auto zero lines AZL101-1 to AZL101-m, autozero lines AZL102-1 to AZL102-m, drive lines DLV101-1 to DLVL101-m, and gate drive circuit 102C The driving method of the data lines DTL 101-1 to DTL 101-n of the data line driving circuit 101 is substantially the same as the driving method of the pixel circuit described above. Therefore, detailed description thereof is omitted here.
[0143]
According to the twelfth embodiment, an active matrix image display apparatus capable of displaying a high-quality image can be realized.
[0144]
【The invention's effect】
As described above, according to the present invention, a current can be supplied to the electro-optic element regardless of the threshold value of the driving transistor that varies from pixel to pixel.
For this reason, the display apparatus which displays a high quality image can be provided.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a first configuration example of a conventional pixel circuit.
FIG. 2 is a diagram illustrating a configuration example of a conventional image display apparatus.
FIG. 3 is a circuit diagram illustrating a second configuration example of a conventional pixel circuit.
4 is a timing chart for explaining a driving method of the pixel circuit of FIG. 3;
FIG. 5 is a circuit diagram showing a first embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device.
6 is a timing chart for explaining the operation of the pixel circuit of FIG. 5;
FIG. 7 is a circuit diagram showing a second embodiment of a pixel circuit according to the present invention applicable to an active matrix image display device.
8 is a timing chart for explaining the operation of the pixel circuit of FIG. 7;
FIG. 9 is a circuit diagram showing a third embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device.
10 is a timing chart for explaining the operation of the pixel circuit of FIG. 9;
FIG. 11 is a circuit diagram showing a fourth embodiment of a pixel circuit according to the present invention applicable to an active matrix image display device.
FIG. 12 is a circuit diagram showing a fifth embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device.
13 is a timing chart for explaining the operation of the pixel circuit of FIG. 12;
FIG. 14 is a circuit diagram showing a sixth embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device.
FIG. 15 is a circuit diagram showing a seventh embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device.
16 is a timing chart for explaining the operation of the pixel circuit of FIG. 15;
FIG. 17 is a circuit diagram showing an eighth embodiment of a pixel circuit according to the present invention which can be applied to an active matrix image display device.
FIG. 18 is a block diagram illustrating a configuration example of an active matrix image display device according to a ninth embodiment.
FIG. 19 is a block diagram illustrating a configuration example of an active matrix image display device according to a tenth embodiment.
FIG. 20 is a block diagram illustrating a configuration example of an active matrix image display device according to an eleventh embodiment.
FIG. 21 is a block diagram illustrating a configuration example of an active matrix image display device according to a twelfth embodiment.
[Explanation of symbols]
30, 30A to 30C, 40, 40A to 40C ... Pixel circuit, 31-35, 41-45 ... TFT, C31, C32, C41, C42 ... Capacitor, ND31, ND41 ... Node, SCNL31, SCNL41 ... Scanning line (first Control line), AZL31, AZL41 ... auto zero line (third control line), AZL42 ... auto zero line (fourth control line), DRVL31, DRVL41 ... drive line (second control line), 100, 100A to 100C ... Active matrix type image display device, 101, 101A ... Data line driving circuit, 102, 102B, 102C ... Gate driving circuit, SCNL 101-1 to SCNL 101-m ... Scanning line, AZL 101-1 to AZL 101-m ... Auto zero line, AZL 102 -1 to AZL102-m ... Auto-zero wire, DLV101-1 DLVL101-m ... driving lines, DTL101-1~DTL101-n ... data line.

Claims (40)

A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A data line to which a data signal corresponding to at least luminance information is supplied;
At least a first control line;
Nodes,
First and second reference potentials;
A predetermined precharge potential;
A drive transistor that forms a current supply line between the first terminal and the second terminal and controls the current flowing through the current supply line in accordance with the potential of the control terminal;
A first switch connected to the first terminal of the drive transistor;
A second switch connected between the first terminal of the driving transistor and the node;
A third switch connected between the control terminal of the drive transistor and the predetermined precharge potential;
A fourth switch connected between the data line and the node and controlled in conduction by the first control line;
A coupling capacitor connected between the node and the control terminal of the driving transistor;
A pixel circuit in which a current supply line of the driving transistor, the first switch, and the electro-optic element are connected in series between the first reference potential and the second reference potential. The pixel circuit according to claim 1, wherein a storage capacitor is connected to the node. 2. The pixel circuit according to claim 1, wherein the predetermined precharge potential is supplied through the data line. 2. The pixel circuit according to claim 1, wherein conduction of the first switch is controlled by a second control line, and conduction of the second switch and the third switch is controlled by a third control line. The conduction of the first switch is controlled by a second control line, the conduction of the second switch is controlled by a third control line, and the conduction of the third switch is controlled by a fourth control line. 1. The pixel circuit according to 1. When driving the electro-optic element,
As a first stage, the first switch, the second switch, and the third switch are turned on for a predetermined time by the second control line and the third control line,
As the second stage, the first switch is held in the non-conductive state by the second control line, and the second switch and the third switch are in the non-conductive state by the third control line after a predetermined time has elapsed. Held in
As a third stage, the fourth switch is turned on by the first control line, and after the data propagated through the data line is written to the node, the fourth switch is held in a non-conductive state. And
5. The pixel circuit according to claim 4, wherein as the fourth stage, the first switch is made conductive by the second control line, and a current corresponding to the data signal is supplied to the electro-optical element. When driving the electro-optic element,
As the first stage, the first switch, the second switch, and the third switch are turned on for a predetermined time by the second control line, the third control line, and the fourth control line. And
As the second stage, after the first switch is held in the non-conductive state by the second control line, and after the predetermined time has elapsed, the second switch is held in the non-conductive state by the third control line, The third switch is held in a non-conductive state by the fourth control line;
As a third stage, the fourth switch is turned on by the first control line, and after the data propagated through the data line is written to the node, the fourth switch is held in a non-conductive state. And
The pixel circuit according to claim 5, wherein as the fourth stage, the first switch is made conductive by the second control line, and a current corresponding to the data signal is supplied to the electro-optical element. A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A data line to which a signal corresponding to at least luminance information is supplied;
At least a first control line;
First and second reference potentials;
A predetermined precharge potential;
A field effect transistor;
Nodes,
A first switch connected between the source of the field effect transistor and a first reference potential;
A second switch connected between the source of the field effect transistor and the node;
A third switch connected between the gate of the field effect transistor and the precharge potential;
A fourth switch connected between the data line and the node and controlled in conduction by the first control line;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The electro-optic element is a pixel circuit connected between the drain of the field effect transistor and a second reference potential. The pixel circuit according to claim 8, wherein a storage capacitor is connected to the node. 9. The pixel circuit according to claim 8, wherein the predetermined precharge potential is supplied through the data line. 9. The pixel circuit according to claim 8, wherein the conduction of the first switch is controlled by a second control line, and the conduction of the second switch and the third switch is controlled by a third control line. The conduction of the first switch is controlled by a second control line, the conduction of the second switch is controlled by a third control line, and the conduction of the third switch is controlled by a fourth control line. 9. The pixel circuit according to 8. When driving the electro-optic element,
As a first stage, the first switch, the second switch, and the third switch are turned on for a predetermined time by the second control line and the third control line,
As the second stage, the first switch is held in the non-conductive state by the second control line, and the second switch and the third switch are in the non-conductive state by the third control line after a predetermined time has elapsed. Held in
As a third stage, the fourth switch is turned on by the first control line, and after the data propagated through the data line is written to the node, the fourth switch is held in a non-conductive state. And
12. The pixel circuit according to claim 11, wherein as the fourth stage, the first switch is made conductive by the second control line, and a current corresponding to the data signal is supplied to the electro-optical element. When driving the electro-optic element,
As the first stage, the first switch, the second switch, and the third switch are turned on for a predetermined time by the second control line, the third control line, and the fourth control line. And
As the second stage, after the first switch is held in the non-conductive state by the second control line, and after the predetermined time has elapsed, the second switch is held in the non-conductive state by the third control line, The third switch is held in a non-conductive state by the fourth control line;
As a third stage, the fourth switch is turned on by the first control line, and after the data propagated through the data line is written to the node, the fourth switch is held in a non-conductive state. And
13. The pixel circuit according to claim 12, wherein as the fourth stage, the first switch is made conductive by the second control line, and a current corresponding to the data signal is supplied to the electro-optical element. 14. The pixel circuit according to claim 13, wherein the precharge potential is set to a value smaller than a value obtained by subtracting an absolute value of a threshold value of the field effect transistor from the first reference potential. 15. The pixel circuit according to claim 14, wherein the precharge potential is set to a value smaller than a value obtained by subtracting an absolute value of a threshold value of the field effect transistor from the first reference potential. A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A data line to which a signal corresponding to at least luminance information is supplied;
At least a first control line;
First and second reference potentials;
A predetermined precharge potential;
A field effect transistor;
Nodes,
A first switch connected between a source of the field effect transistor and the electro-optic element;
A second switch connected between the source of the field effect transistor and the node;
A third switch connected between the gate of the field effect transistor and the precharge potential;
A fourth switch connected between the data line and the node and controlled in conduction by the first control line;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The electro-optical element is a pixel circuit connected between the first switch and a second reference potential. The pixel circuit according to claim 17, wherein a storage capacitor is connected to the node. 18. The pixel circuit according to claim 17, wherein the predetermined precharge potential is supplied through the data line. 18. The pixel circuit according to claim 17, wherein the first switch is conductively controlled by a second control line, and the second switch and the third switch are conductively controlled by a third control line. The conduction of the first switch is controlled by a second control line, the conduction of the second switch is controlled by a third control line, and the conduction of the third switch is controlled by a fourth control line. 18. A pixel circuit according to item 17. When driving the electro-optic element,
As a first stage, the first switch, the second switch, and the third switch are turned on for a predetermined time by the second control line and the third control line,
As the second stage, the first switch is held in the non-conductive state by the second control line, and the second switch and the third switch are in the non-conductive state by the third control line after a predetermined time has elapsed. Held in
As a third stage, the fourth switch is turned on by the first control line, and after the data propagated through the data line is written to the node, the fourth switch is held in a non-conductive state. And
21. The pixel circuit according to claim 20, wherein as the fourth stage, the first switch is made conductive by the second control line, and a current corresponding to the data signal is supplied to the electro-optical element. When driving the electro-optic element,
As the first stage, the first switch, the second switch, and the third switch are turned on for a predetermined time by the second control line, the third control line, and the fourth control line. And
As the second stage, after the first switch is held in the non-conductive state by the second control line, and after the predetermined time has elapsed, the second switch is held in the non-conductive state by the third control line, The third switch is held in a non-conductive state by the fourth control line;
As a third stage, the fourth switch is turned on by the first control line, and after the data propagated through the data line is written to the node, the fourth switch is held in a non-conductive state. And
23. The pixel circuit according to claim 21, wherein as the fourth stage, the first switch is made conductive by the second control line, and a current corresponding to the data signal is supplied to the electro-optical element. 23. The pixel circuit according to claim 22, wherein the precharge potential is set to a value larger than a sum of a threshold value of the electro-optic element and a threshold value of the field effect transistor. 24. The pixel circuit according to claim 23, wherein the precharge potential is set to a value larger than a sum of a threshold value of the electro-optic element and a threshold value of the field effect transistor. A plurality of pixel circuits arranged in a matrix;
A data line that is wired for each column with respect to the matrix arrangement of the pixel circuit and is supplied with a data signal according to at least luminance information;
At least a first control line wired for each row to the matrix arrangement of the pixel circuit;
First and second reference potentials;
A predetermined precharge potential, and
Each pixel circuit is
Nodes,
A drive transistor that forms a current supply line between the first terminal and the second terminal and controls the current flowing through the current supply line in accordance with the potential of the control terminal;
A first switch connected to the first terminal of the drive transistor;
A second switch connected between the first terminal of the driving transistor and the node;
A third switch connected between the control terminal of the drive transistor and the predetermined precharge potential;
A fourth switch connected between the data line and the node and controlled in conduction by the first control line;
A coupling capacitor connected between the node and the control terminal of the driving transistor;
A display device in which a current supply line of the drive transistor, the first switch, and the electro-optic element are connected in series between the first reference potential and the second reference potential. 27. The display device according to claim 26, wherein conduction of the first switch is controlled by a second control line, and conduction of the second switch and the third switch is controlled by a third control line. The conduction of the first switch is controlled by a second control line, the conduction of the second switch is controlled by a third control line, and the conduction of the third switch is controlled by a fourth control line. 26. The display device according to 26. A plurality of pixel circuits arranged in a matrix;
A data line that is wired for each column with respect to the matrix arrangement of the pixel circuit and is supplied with a data signal according to at least luminance information;
At least a first control line wired for each row to the matrix arrangement of the pixel circuit;
First and second reference potentials;
A predetermined precharge potential, and
Each pixel circuit is
A field effect transistor;
Nodes,
A first switch connected between the source of the field effect transistor and a first reference potential, the conduction of which is controlled by the first control line;
A second switch connected between the source of the field effect transistor and the node;
A third switch connected between the gate of the field effect transistor and the precharge potential;
A fourth switch connected between the data line and the node and controlled in conduction by the first control line;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The display device, wherein the electro-optic element is connected between a drain of the field effect transistor and a second reference potential. 30. The display device according to claim 29, wherein conduction of the first switch is controlled by a second control line, and conduction of the second switch and the third switch is controlled by a third control line. The conduction of the first switch is controlled by a second control line, the conduction of the second switch is controlled by a third control line, and the conduction of the third switch is controlled by a fourth control line. 29. The display device according to 29. A plurality of pixel circuits arranged in a matrix;
A data line that is wired for each column with respect to the matrix arrangement of the pixel circuit and is supplied with a data signal according to at least luminance information;
At least a first control line wired for each row to the matrix arrangement of the pixel circuit;
First and second reference potentials;
A predetermined precharge potential, and
Each pixel circuit is
A field effect transistor;
Nodes,
A first switch connected between a source of the field effect transistor and the electro-optic element;
A second switch connected between the source of the field effect transistor and the node;
A third switch connected between the gate of the field effect transistor and the precharge potential;
A fourth switch connected between the data line and the node and controlled in conduction by the first control line;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The display device, wherein the electro-optic element is connected between the first switch and a second reference potential. The display device according to claim 32, wherein the first switch is conductively controlled by a second control line, and the second switch and the third switch are conductively controlled by a third control line. The conduction of the first switch is controlled by a second control line, the conduction of the second switch is controlled by a third control line, and the conduction of the third switch is controlled by a fourth control line. 32. The display device according to 32. An electro-optic element whose luminance varies depending on the flowing current;
A drive transistor that forms a current supply line between the first terminal and the second terminal and controls the current flowing through the current supply line in accordance with the potential of the control terminal;
Nodes,
A first switch connected to the first terminal of the drive transistor;
A second switch connected between the first terminal of the driving transistor and the node;
A third switch connected between the control terminal of the drive transistor and the predetermined precharge potential;
A fourth switch connected between the data line and the node;
A coupling capacitor connected between the node and the control terminal of the driving transistor;
A driving method of a pixel circuit in which a current supply line of the driving transistor, the first switch, and the electro-optic element are connected in series between the first reference potential and the second reference potential. And
A first step of conducting the first switch, the second switch, and the third switch for a predetermined time;
A second step of holding the first switch in a non-conductive state and holding the second switch and the third switch in a non-conductive state after a predetermined time has elapsed;
A third step of turning on the fourth switch and writing the data propagated through the data line to the node and then holding the fourth switch in a non-conductive state;
And a fourth step of supplying a current corresponding to the data signal to the electro-optic element by turning on the first switch. In the second step, when the second switch and the third switch are held in a non-conductive state, the third switch is held in a non-conductive state after the second switch is held in a non-conductive state. 36. A method of driving a pixel circuit according to claim 35, wherein An electro-optic element whose luminance varies depending on the flowing current;
A field effect transistor;
Nodes,
A first switch connected between the source of the field effect transistor and a first reference potential;
A second switch connected between the source of the field effect transistor and the node;
A third switch connected between the gate of the field effect transistor and a predetermined potential;
A fourth switch connected between the data line and the node;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The electro-optic element is a driving method of a pixel circuit connected between a drain of the field effect transistor and a second reference potential,
A first step of conducting the first switch, the second switch, and the third switch for a predetermined time;
A second step of holding the first switch in a non-conductive state and holding the second switch and the third switch in a non-conductive state after a predetermined time has elapsed;
A third step of turning on the fourth switch and writing the data propagated through the data line to the node and then holding the fourth switch in a non-conductive state;
And a fourth step of supplying a current corresponding to the data signal to the electro-optic element by turning on the first switch. In the second step, when the second switch and the third switch are held in a non-conductive state, the second switch is held in a non-conductive state, and then the third switch is turned off. 38. A driving method of a pixel circuit according to claim 37, wherein An electro-optic element whose luminance varies depending on the flowing current;
A field effect transistor;
Nodes,
A first switch connected between a source of the field effect transistor and the electro-optic element;
A second switch connected between the source of the field effect transistor and the node;
A third switch connected between the gate of the field effect transistor and a predetermined potential;
A fourth switch connected between the data line and the node;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The electro-optical element is a driving method of a pixel circuit connected between the first switch and a second reference potential,
A first step of conducting the first switch, the second switch, and the third switch for a predetermined time;
A second step of holding the first switch in a non-conductive state and holding the second switch and the third switch in a non-conductive state after a predetermined time has elapsed;
A third step of turning on the fourth switch and writing the data propagated through the data line to the node and then holding the fourth switch in a non-conductive state;
And a fourth step of supplying a current corresponding to the data signal to the electro-optic element by turning on the first switch. In the second step, when the second switch and the third switch are held in a non-conductive state, the third switch is held in a non-conductive state after the second switch is held in a non-conductive state. 40. The pixel circuit driving method according to claim 39, wherein the pixel circuit is held in the pixel circuit.

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