JP3898894B2 - 堅固な相互接続構造 - Google Patents

堅固な相互接続構造 Download PDF

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Publication number
JP3898894B2
JP3898894B2 JP2000620678A JP2000620678A JP3898894B2 JP 3898894 B2 JP3898894 B2 JP 3898894B2 JP 2000620678 A JP2000620678 A JP 2000620678A JP 2000620678 A JP2000620678 A JP 2000620678A JP 3898894 B2 JP3898894 B2 JP 3898894B2
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Prior art keywords
layer
interconnect structure
copper
structure according
thickness
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Expired - Lifetime
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JP2000620678A
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JP2003500860A (ja
Inventor
エーデルステイン、ダニエル
マックゲイヘイ、ビンセント
ニー、ヘンリー
オッテイ、ブライアン
プライス、ウィリアム
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International Business Machines Corp
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International Business Machines Corp
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    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
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  • Connector Housings Or Holding Contact Members (AREA)
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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【０００１】
【技術分野】
本発明は金属相互接続に関し、詳細には堅固な銅相互接続構造に関する。本発明は特に、ＶＬＳＩおよびＵＬＳＩの銅相互接続、とりわけパッケージング用の銅相互接続に適用可能である。
【０００２】
【背景技術】
半導体デバイス中の相互接続として銅を使用することへの関心が高まっている。これは、より伝統的なアルミニウムまたはアルミニウム合金相互接続に比べ抵抗率が低く、またエレクトロマイグレーション故障が生じにくいためである。
【０００３】
しかし銅は、相互接続メタラジ中に使用したときに二酸化シリコンなどの周囲の誘電材料内に拡散する傾向を持つため、そのキャッピングが不可欠である。キャッピングはこの拡散を妨げる。広く提案されている１つのキャッピング方法は、銅相互接続の側壁および底面に沿って導電性バリア層を使用することを含む。このようなバリア層は一般にタンタルまたはチタンである。銅相互接続の上面のキャッピングには通常、窒化シリコンが使用される。
【０００４】
しかし窒化シリコンは、さまざまな接着処理を施しても銅表面に対して強い接着性を示さない。したがって窒化シリコン−銅界面は、機械的な荷重条件下で層間剥離しやすい。
【０００５】
例えば、パッケージの信頼性を保証するためには、製品が経験する機械的応力に耐えられるようＣ４（controlled collapse chip connection）の構造的完全性（integrity）が健全でなければならない。銅相互接続上のＣ４パッドの最近の研究によれば、Ｃ４の構造的完全性が比較的に弱いことが明らかになった。窒化シリコン・キャップのその下の銅に対するもともと比較的に弱い接着に起因して、リワークおよびバーンイン操作中に故障が生じた。
【０００６】
【発明の開示】
本発明の実施形態は、銅ＢＥＯＬ上のＣ４を含む銅相互接続の構造的完全性を向上させる。本発明は、機械的応力に対して堅固な相互接続を提供する。
【０００７】
具体的には本発明の構造は、銅層、パッド制限層、および前記銅層とパッド制限層の間に配置されたＡｌＣｕ層およびバリア層を含む。
【０００８】
本発明の実施形態はさらに、銅層と、前記銅層の上に位置し、前記銅層の一部分を露出させるバイアを有する誘電絶縁層と、前記バイアの中の前記銅層の上に位置するバリア層と、前記バリア層の上に位置するＡｌＣｕ層と、前記ＡｌＣｕ層の上に位置するパッド制限層を含む相互接続構造に関する。
【０００９】
本発明の実施形態の他の目的および利点は、単に発明を実施するための最良の形態を例示することによって本発明の好ましい実施形態だけを示し説明した以下の詳細な説明から当業者には容易に明らかとなろう。本発明が他のさまざまな実施形態を包含し、そのいくつかの詳細が、本発明から逸脱しない明白なさまざまな点での修正を包含することを理解されたい。したがってこの説明は例示的なものとみるべきであって、限定的なものと解釈してはならない。
【００１０】
【発明を実施するための最良の形態】
本発明の理解を容易にするため図面を参照する。
【００１１】
具体的には図１は、従来技術のＣ４／Ｃｕ ＢＥＯＬ構造（C4 over Cu BEOL structure）の概略図である。分離領域３を通る開口またはバイアの内部に銅パッド１があり、導体２に接続されている。導体２と分離領域３の間の銅パッドの側面および底面には一般に、バリアまたはライナ層（図示せず）が存在する。
【００１２】
分離領域３は一般に二酸化シリコンである。銅層の厚さは一般に約０．３から約２μｍ、より典型的には約０．５から約１．２μｍである。
【００１３】
銅層の上方に窒化シリコンなどのキャッピング層４が設けられる。窒化シリコンの場合、周知のプラズマ化学蒸着プロセス（ＰＥＣＶＤ）によってこの層を付着させることができる。このようなプロセスは、シランなどのシリコン含有ガス化学種ならびにアンモニアなどの窒素含有ガス化学種および／または窒素をプラズマの存在下で導入することを含む。この他のシリコン含有ガス化学種には、ジシラン、ジクロロシラン、オルトケイ酸テトラエチルなどがある。他のシリコン含有ガス化学種にはヘキサメチルジシランが含まれる。窒化シリコンの付着は通常、約３００から約４５０℃、より典型的には約３５０から約４００℃の温度で実施される。層４の厚さは一般に約１００から約２０，０００Åであり、窒化シリコンに対しては一般に約１００から約１０００Å、より典型的には約３５０から約７００Åである。
【００１４】
キャッピング層４には、後段のＣ４パッドへの相互接続のためのアクセスを提供するバイアまたは開口が存在する。
【００１５】
キャッピング層４の上にはパッシベーション層５が設けられる。パッシベーション層５も、後段のＣ４パッドとの相互接続のためのアクセスを提供する開口またはバイアを含む。パッシベーション層５は一般に二酸化シリコン、窒化シリコン、オキシ窒化シリコンまたはこれらの組合せである。二酸化シリコンの場合、パッシベーション層５は、プラズマ化学蒸着などの周知の技法によって付着させることができる。好ましい層５は、二酸化シリコン層とこれに続く窒化シリコン層の組合せである。層５の厚さは一般に約１０００から約９０００Åである。
【００１６】
パッシベーション層５の上方には誘電層６が設けられる。誘電層６も、後段のＣ４パッドとの相互接続のためのアクセスを提供する開口またはバイアを含む。
【００１７】
好ましい誘電層６はポリイミドである。適当なポリイミドには、無修飾ポリイミド、ポリエステルイミド、ポリイミド−イミド−エステル、ポリイミド−イミド、ポリシロキサンイミドなどの修飾ポリイミド、ならびにその他の混合ポリイミドが含まれる。これらについては従来技術でも知られており、本明細書で詳細に説明する必要はない。誘電層６は一般に、ポリイミド前駆体でコーティングし、次いで加熱によって硬化ポリイミドに転化させることによって提供される。市販のポリイミド前駆体（ポリアミド酸）またはさまざまなポリイミド前駆体が、デュポン（DuPont）社からPyralinの商品名で入手可能である。これらのポリイミド前駆体には多くのグレードがあり、これには、ＰＩ−２５５５、ＰＩ−２５４５、ＰＩ−２５６０、ＰＩ−５８７８、ＰＩＨ−６１４５４およびＰＩ−２５４０の商品名で販売されているものが含まれる。これらのいくつかは、ピロメリト酸二無水物−オキシジアニリン（ＰＭＤＡ−ＯＤＡ）ポリイミド前駆体である。
【００１８】
誘電層６の厚さは一般に約０．４から約５ミクロン、より典型的には約１０，０００から約４０，０００Åである。
【００１９】
現在実施されている技術では、銅１の上にパッド制限メタラジ７が配置される。層７は、キャッピング層４、パッシベーション層５および誘電層６の開口の側壁にも存在する。
【００２０】
パッド制限メタラジ層７は一般に、窒化チタン、銅、金、チタン−タングステン、クロムであり、これらは、米国特許第４４３４４３４号明細書または米国特許第５６２９５６４号明細書の記載に従って付着させることができる。これらの明細書の開示は参照によって本明細書に組み込まれる。パッド制限メタラジでは一般に層の組合せが使用される。特定の１つの組合せは順にＴｉＷ、ＣｒＣｕ、Ｃｕの組合せである。ＴｉＷ層の厚さは一般に約２５０から約２０００Åである。ＣｒＣｕ層の厚さは一般に１００から約２０００Åである。銅層の厚さは一般に約１０００から約２０，０００Åである。第１の金属の付着の前には一般にｉｎ−ｓｉｔｕのスパッタ洗浄が実施される。
【００２１】
めっきＣ４パッドまたはバンプ構造８が、誘電層６、パッシベーション層５およびキャッピング層４の開口またはバイア内のパッド制限層７に直接に接続する。
【００２２】
Ｃ４コンタクト・バンプ構造８はたいていＰｂ−Ｓｎはんだであり、基板と相互接続するため集積回路チップ上に設けられる。接着を強化するためコンタクト・バンプ構造８は一般に金属層７に付着される。Ｃ４バンプは、集積回路チップの表面から上方に約０．１００ミリメートル延びており、集積回路チップの上面に平行な断面が円形であって、その側面から上面に向かって湾曲しており、この上面で基板が支持する他の電極に相互接続される。
【００２３】
チップ・プル・リワークまたはポスト・バーンインの間に、銅１の上にあるキャップ４には垂直力または剪断力がかかる。接着が不十分であるため、キャップに亀裂が入り、銅表面からキャップが剥離する可能性がある。この故障モードは、マルチチップ・モジュール応用およびいくつかのシングル・チップ用途に対するＣｕ相互接続技術の信頼性を低める。
【００２４】
本発明によれば、図２に示すように、銅層１とパッド制限層７の間にＡｌＣｕ層９およびバリア１０が設けられる。ＡｌＣｕ層は一般に、約９６から約９９．５原子％のＡｌ、およびこれに対応した約４から約０．５原子％のＣｕを含む。ＡｌＣｕ層９の厚さは一般に約０．５０から約１．２ミクロンである。この層は、周知のスパッタ技法によって適用することができる。
【００２５】
バリア層１０は一般にチタン、窒化チタン、タンタル、窒化タンタル、あるいはこれらの混合物、組合せまたは合金である。さらに、これらのバリア層の組合せがしばしば使用される。特定の１つの組合せは順にＴａＮ、Ｔｉ、ＴｉＮの組合せである。ＴａＮ層の厚さは一般に約５０から約１０００Åである。Ｔｉ層の厚さは一般に２００から７００Åである。ＴｉＮ層の厚さは一般に２００から７００Åである。第１の金属の付着の前には一般にｉｎ−ｓｉｔｕのスパッタ洗浄が実施される。
【００２６】
本発明の好ましい態様によれば、ＡｌＣｕ層９およびバリア層１０がパッシベーション層５よりも上方に延び、かつパッシベーション層５とオーバラップする。さらに、その幅が銅層１の幅と実質的に等しいことが好ましい。
【００２７】
好ましい構成ではさらに、誘電層６がＡｌＣｕ層９の前記オーバラップ部分とオーバラップし、パッド制限層７が誘電層６の一部分とオーバラップする。
【００２８】
ＡｌＣｕ層とバリア層は、Ｃ４パッドへのＣｕの堅固な相互接続を提供する。実施した引張り試験によれば、本発明に基づく構造によって欠陥率は、図１に示した従来技術の構造の５０〜７０％から本発明の構造の０％まで引き下げられた。
【００２９】
以上に本発明を例示し説明した。本明細書の開示は、本発明の好ましい実施形態だけを示し説明するものであるが、先に述べたとおり、他のさまざまな組合せ、修正および環境で本発明を使用できること、ならびに、本発明が、以上の教示に対応する本明細書に表現した発明の概念および／あるいは関連技術の技能または知識の範囲に含まれる変更または修正を包含することを理解されたい。さらに本明細書に記載した実施形態は、発明実施の最良の形態を説明し、このような実施形態または他の実施形態において、および本発明の特定の応用または用途に必要なさまざまな修正を加えて、当業者が本発明を利用できるようにすることを意図したものである。したがって以上の説明は、本明細書に開示した形態に本発明を限定することを意図したものではない。さらに、添付の請求項は代替の実施形態を含むものと解釈されたい。
【図面の簡単な説明】
【図１】 従来技術のＣ４／Ｃｕ ＢＥＯＬ構造（C4 over Cu BEOL structure）の概略図である。
【図２】 本発明に基づくＣ４／Ｃｕ ＢＥＯＬ構造の概略図である。

Claims (20)

  1. 銅層と、
    前記銅層の上に位置し、前記銅層の一部分を露出させるバイアを有する窒化シリコン・キャッピング層と、
    前記キャッピング層の上に位置し、前記バイアと一致したバイアを有するパッシベーション層と、
    前記バイアの中の、前記銅層と前記キャッピング層と前記パッシベーション層を覆い、かつ前記パッシベーション層よりも上方に延びて、前記パッシベーション層とオーバラップするバリア層と、
    前記バイアの中の前記バリア層を覆い、かつ前記バリア層よりも上方に延びて、前記バリア層とオーバラップするＡｌＣｕ層と、
    前記ＡｌＣｕ層の前記オーバラップ部分とオーバラップする誘電層と、
    前記バイアの中のＡｌＣｕ層を覆い、かつ前記誘電層よりも上方に延びて、前記誘電層とオーバラップするパッド制限層と、を備える相互接続構造。
  2. 前記パッド制限層と接触したＣ４コンタクト・バンプをさらに含む、請求項１に記載の相互接続構造。
  3. 前記ＡｌＣｕ層の幅が前記銅層の幅と実質的に等しい、請求項１または２のいずれか一項に記載の相互接続構造。
  4. 前記バリア層の幅が前記銅層の幅と実質的に等しい、請求項１ないし３のいずれか一項に記載の相互接続構造。
  5. 前記銅層の厚さが０．３から２μｍである、請求項１ないし４のいずれか一項に記載の相互接続構造。
  6. 前記ＡｌＣｕ層がＡｌを９６から９９．５原子％含む、請求項１ないし５のいずれか一項に記載の相互接続構造。
  7. 前記ＡｌＣｕ層の厚さが０．５から１．２ミクロンである、請求項１ないし６のいずれか一項に記載の相互接続構造。
  8. 前記バリア層が、チタン、タンタル、これらの窒化物、これらの混合物、これらの組合せおよびこれらの合金から成るグループから選択された、請求項１ないし７のいずれか一項に記載の相互接続構造。
  9. 前記バリア層の厚さが５０から１０００Åである、請求項１ないし８のいずれか一項に記載の相互接続構造。
  10. 前記バリア層が、ＴａＮ層、Ｔｉ層およびＴｉＮ層の組合せからなる、請求項１ないし９のいずれか一項に記載の相互接続構造。
  11. 前記ＴｉＮ層の厚さが２００から７００Å、前記Ｔｉ層の厚さが２００から７００Å、前記ＴａＮ層の厚さが５０から１０００Åである、請求項１０に記載の相互接続構造。
  12. 前記キャッピング層の厚さが１００から１０００Åである、請求項１ないし１１のいずれか一項に記載の相互接続構造。
  13. 前記Ｃ４コンタクト・バンプがＳｎ−Ｐｂはんだである、請求項２に記載の相互接続構造。
  14. 前記パッシベーション層が、二酸化シリコン、窒化シリコン、オキシ窒化シリコンおよびこれらの組合せから成るグループから選択された、請求項１ないし１３のいずれか一項に記載の相互接続構造。
  15. 前記パッシベーション層の厚さが１０００から９０００Åである、請求項１４に記載の相互接続構造。
  16. 前記誘電層がポリイミドである、請求項１ないし１４のいずれか一項に記載の相互接続構造。
  17. 前記パッド制限層が、窒化チタン、銅、金、チタン−タングステン、クロムおよびこれらの組合せから成るグループの少なくとも１つから選択された、請求項１ないし１６のいずれか一項に記載の相互接続構造。
  18. 前記パッド制限層が、ＴｉＷ層と、これに続くＣｒＣｕ層と、これに続くＣｕ層を含む、請求項１ないし１６のいずれか一項に記載の相互接続構造。
  19. 前記銅層が絶縁層に設けられた開口に充填された銅からなる、請求項１に記載の相互接続構造。
  20. 前記絶縁層が前記キャッピング層に接する、請求項１９に記載の相互接続構造。
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Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6187680B1 (en) * 1998-10-07 2001-02-13 International Business Machines Corporation Method/structure for creating aluminum wirebound pad on copper BEOL
JP3387083B2 (ja) * 1999-08-27 2003-03-17 日本電気株式会社 半導体装置及びその製造方法
US6451681B1 (en) * 1999-10-04 2002-09-17 Motorola, Inc. Method of forming copper interconnection utilizing aluminum capping film
US6191023B1 (en) * 1999-11-18 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of improving copper pad adhesion
US6387793B1 (en) 2000-03-09 2002-05-14 Hrl Laboratories, Llc Method for manufacturing precision electroplated solder bumps
JP3651765B2 (ja) * 2000-03-27 2005-05-25 株式会社東芝 半導体装置
US6551931B1 (en) * 2000-11-07 2003-04-22 International Business Machines Corporation Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped
US20030116845A1 (en) * 2001-12-21 2003-06-26 Bojkov Christo P. Waferlevel method for direct bumping on copper pads in integrated circuits
JP3759909B2 (ja) * 2002-02-22 2006-03-29 松下電器産業株式会社 半導体装置及びその製造方法
US20030227091A1 (en) * 2002-06-06 2003-12-11 Nishant Sinha Plating metal caps on conductive interconnect for wirebonding
US6875693B1 (en) * 2003-03-26 2005-04-05 Lsi Logic Corporation Via and metal line interface capable of reducing the incidence of electro-migration induced voids
US6835580B1 (en) * 2003-06-26 2004-12-28 Semiconductor Components Industries, L.L.C. Direct chip attach structure and method
US6951775B2 (en) * 2003-06-28 2005-10-04 International Business Machines Corporation Method for forming interconnects on thin wafers
US20050098605A1 (en) * 2003-11-06 2005-05-12 International Business Machines Corporation Apparatus and method for low pressure wirebond
US7068138B2 (en) * 2004-01-29 2006-06-27 International Business Machines Corporation High Q factor integrated circuit inductor
KR100605315B1 (ko) 2004-07-30 2006-07-28 삼성전자주식회사 집적회로 칩의 입출력 패드 구조
JP2006120677A (ja) * 2004-10-19 2006-05-11 Alps Electric Co Ltd 配線基板の接続端子構造
US7282433B2 (en) * 2005-01-10 2007-10-16 Micron Technology, Inc. Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
US20100117231A1 (en) * 2006-08-30 2010-05-13 Dennis Lang Reliable wafer-level chip-scale solder bump structure
JP2008159948A (ja) * 2006-12-25 2008-07-10 Rohm Co Ltd 半導体装置
US20080157382A1 (en) * 2006-12-28 2008-07-03 Chinthakindi Anil K Direct termination of a wiring metal in a semiconductor device
US7935408B2 (en) * 2007-10-26 2011-05-03 International Business Machines Corporation Substrate anchor structure and method
JP5627835B2 (ja) 2007-11-16 2014-11-19 ローム株式会社 半導体装置および半導体装置の製造方法
US7868453B2 (en) * 2008-02-15 2011-01-11 International Business Machines Corporation Solder interconnect pads with current spreading layers
CN101630667A (zh) * 2008-07-15 2010-01-20 中芯国际集成电路制造(上海)有限公司 形成具有铜互连的导电凸块的方法和系统
US7851346B2 (en) * 2008-07-21 2010-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding metallurgy for three-dimensional interconnect
JP5249080B2 (ja) * 2009-02-19 2013-07-31 セイコーインスツル株式会社 半導体装置
JP5316261B2 (ja) * 2009-06-30 2013-10-16 富士通株式会社 マルチチップモジュールおよびプリント基板ユニット並びに電子機器
US8610283B2 (en) * 2009-10-05 2013-12-17 International Business Machines Corporation Semiconductor device having a copper plug
US8446006B2 (en) 2009-12-17 2013-05-21 International Business Machines Corporation Structures and methods to reduce maximum current density in a solder ball
US9214385B2 (en) 2009-12-17 2015-12-15 Globalfoundries Inc. Semiconductor device including passivation layer encapsulant
US8492892B2 (en) 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
US20120326299A1 (en) * 2011-06-24 2012-12-27 Topacio Roden R Semiconductor chip with dual polymer film interconnect structures
CN104051323B (zh) * 2013-03-13 2017-12-29 中芯国际集成电路制造(上海)有限公司 一种半导体封装结构及其制备方法
CN104241146B (zh) * 2013-06-09 2017-10-31 中芯国际集成电路制造(上海)有限公司 金属垫的形成方法及半导体结构
US10002834B2 (en) * 2015-03-11 2018-06-19 Applied Materials, Inc. Method and apparatus for protecting metal interconnect from halogen based precursors
CN106505031B (zh) * 2015-09-07 2019-12-31 中芯国际集成电路制造(上海)有限公司 一种铜互连结构的制作方法、铜互连结构及电子装置
US10461026B2 (en) 2016-06-30 2019-10-29 International Business Machines Corporation Techniques to improve reliability in Cu interconnects using Cu intermetallics
US10535698B2 (en) * 2017-11-28 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor with pad structure
JP7430481B2 (ja) * 2018-05-31 2024-02-13 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4434434A (en) * 1981-03-30 1984-02-28 International Business Machines Corporation Solder mound formation on substrates
US5268072A (en) * 1992-08-31 1993-12-07 International Business Machines Corporation Etching processes for avoiding edge stress in semiconductor chip solder bumps
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
US5545927A (en) * 1995-05-12 1996-08-13 International Business Machines Corporation Capped copper electrical interconnects
EP0751566A3 (en) * 1995-06-30 1997-02-26 Ibm Metal thin film barrier for electrical connections
US5785236A (en) * 1995-11-29 1998-07-28 Advanced Micro Devices, Inc. Advanced copper interconnect system that is compatible with existing IC wire bonding technology
US5731624A (en) * 1996-06-28 1998-03-24 International Business Machines Corporation Integrated pad and fuse structure for planar copper metallurgy
US6020640A (en) * 1996-12-19 2000-02-01 Texas Instruments Incorporated Thick plated interconnect and associated auxillary interconnect
JPH11340265A (ja) * 1998-05-22 1999-12-10 Sony Corp 半導体装置及びその製造方法

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MY118419A (en) 2004-10-30
AU4933500A (en) 2000-12-12
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EP1186034A1 (en) 2002-03-13
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