JP3872733B2 - 絶縁体上シリコン（ｓｏｉ）ベースの回路における履歴効果を緩和するための方法及び装置 - Google Patents

絶縁体上シリコン（ｓｏｉ）ベースの回路における履歴効果を緩和するための方法及び装置 Download PDF

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JP3872733B2
JP3872733B2 JP2002222365A JP2002222365A JP3872733B2 JP 3872733 B2 JP3872733 B2 JP 3872733B2 JP 2002222365 A JP2002222365 A JP 2002222365A JP 2002222365 A JP2002222365 A JP 2002222365A JP 3872733 B2 JP3872733 B2 JP 3872733B2
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Prior art keywords
data
sense amplifier
clock
complementary
manipulation method
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Japanese (ja)
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JP2003124801A (ja
JP2003124801A5 (cg-RX-API-DMAC7.html
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フィリップ・エル・バーンズ
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HP Inc
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Hewlett Packard Co
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356139—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
    • H03K3/356191—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes with synchronous operation

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  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)
  • Dram (AREA)
JP2002222365A 2001-08-10 2002-07-31 絶縁体上シリコン（ｓｏｉ）ベースの回路における履歴効果を緩和するための方法及び装置 Expired - Fee Related JP3872733B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/927,673 US6476645B1 (en) 2001-08-10 2001-08-10 Method and apparatus for mitigating the history effect in a silicon-on-insulator (SOI)-based circuit
US09/927673 2001-08-10

Publications (3)

Publication Number Publication Date
JP2003124801A JP2003124801A (ja) 2003-04-25
JP2003124801A5 JP2003124801A5 (cg-RX-API-DMAC7.html) 2005-06-23
JP3872733B2 true JP3872733B2 (ja) 2007-01-24

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Family Applications (1)

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JP2002222365A Expired - Fee Related JP3872733B2 (ja) 2001-08-10 2002-07-31 絶縁体上シリコン（ｓｏｉ）ベースの回路における履歴効果を緩和するための方法及び装置

Country Status (2)

Country Link
US (2) US6476645B1 (cg-RX-API-DMAC7.html)
JP (1) JP3872733B2 (cg-RX-API-DMAC7.html)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100455398B1 (ko) * 2002-12-13 2004-11-06 삼성전자주식회사 동작 속도가 향상된 데이터 래치 회로.
US6833737B2 (en) * 2003-01-30 2004-12-21 International Business Machines Corporation SOI sense amplifier method and apparatus
US6995598B2 (en) * 2003-02-13 2006-02-07 Texas Instruments Incorporated Level shifter circuit including a set/reset circuit
US6819155B1 (en) 2003-06-23 2004-11-16 Teradyne, Inc. High-speed duty cycle control circuit
DE10331544B3 (de) * 2003-07-11 2004-09-30 Infineon Technologies Ag Verfahren zum Ansteuern eines Transistors
US7417468B2 (en) * 2003-09-17 2008-08-26 The Regents Of The University Of California Dynamic and differential CMOS logic with signal-independent power consumption to withstand differential power analysis
US20050162193A1 (en) * 2004-01-27 2005-07-28 Texas Instruments Incorporated High performance sense amplifiers
US8681084B2 (en) 2004-09-17 2014-03-25 Gold Charm Limited Semiconductor device, method for driving same, display device using same and personal digital assistant
KR100699862B1 (ko) * 2005-08-26 2007-03-27 삼성전자주식회사 반도체 장치의 이중 기준 입력 수신기 및 이의 입력 데이터신호 수신방법
US7333379B2 (en) * 2006-01-12 2008-02-19 International Business Machines Corporation Balanced sense amplifier circuits with adjustable transistor body bias
KR100771878B1 (ko) * 2006-08-09 2007-11-01 삼성전자주식회사 세미-듀얼 기준전압을 이용한 데이터 수신 장치
US7564266B2 (en) * 2007-06-25 2009-07-21 Qualcomm Incorporated Logic state catching circuits
US8067917B2 (en) * 2008-04-08 2011-11-29 Liebert Corporation Hysteresis mitigation and control method
WO2010005343A2 (en) * 2008-07-08 2010-01-14 Marat Vadimovich Evtukhov Rebreather respiratory loop failure detector
US8130567B2 (en) * 2008-12-24 2012-03-06 Stmicroelectronics Pvt. Ltd. Write circuitry for hierarchical memory architecture
US8108816B2 (en) * 2009-06-15 2012-01-31 International Business Machines Corporation Device history based delay variation adjustment during static timing analysis
US8141014B2 (en) * 2009-08-10 2012-03-20 International Business Machines Corporation System and method for common history pessimism relief during static timing analysis
JP2012227588A (ja) * 2011-04-15 2012-11-15 Fujitsu Semiconductor Ltd 比較回路及びアナログデジタル変換回路
US9443567B1 (en) * 2015-04-16 2016-09-13 Intel Corporation High speed sense amplifier latch with low power rail-to-rail input common mode range
KR20170045542A (ko) * 2015-10-19 2017-04-27 삼성전자주식회사 에지 검출기 및 이를 포함하는 신호 특성 분석 시스템
US11328771B2 (en) * 2020-09-15 2022-05-10 Integrated Silicon Solution, (Cayman) Inc. Sense amplifier circuit for preventing read disturb

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1238022B (it) * 1989-12-22 1993-06-23 Cselt Centro Studi Lab Telecom Discriminatore differenziale di tensione in tecnologia c-mos.
KR100223675B1 (ko) * 1996-12-30 1999-10-15 윤종용 고속동작용 반도체 메모리 장치에 적합한 데이터 출력관련 회로
US5929660A (en) * 1997-12-29 1999-07-27 United Technologies Corporation Dynamic, single-ended sense amplifier
US6188259B1 (en) * 1999-11-03 2001-02-13 Sun Microsystems, Inc. Self-reset flip-flop with self shut-off mechanism
US6288932B1 (en) * 2000-04-25 2001-09-11 Sun Microsystems, Inc. Dynamic flop with power down mode
US6608789B2 (en) * 2001-12-21 2003-08-19 Motorola, Inc. Hysteresis reduced sense amplifier and method of operation

Also Published As

Publication number Publication date
US6717443B2 (en) 2004-04-06
US20030052715A1 (en) 2003-03-20
JP2003124801A (ja) 2003-04-25
US6476645B1 (en) 2002-11-05

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