JP3755214B2 - Driving method of plasma display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a so-called subfield method driving circuit and a method for reducing high-frequency noise generated from the panel, which are one of the driving methods capable of gradation display of a plasma display panel (hereinafter referred to as PDP).
[0002]
[Prior art]
Conventionally, a driving method called a subfield method disclosed in JP-A-4-195087 or the like has been used as one of driving methods capable of displaying PDP gradations. Hereinafter, this method will be described with reference to the drawings.
[0003]
FIG. 2 is a time chart when one frame is divided into eight subfields (SF1 to SF8) and gradation display of an 8-bit video signal (256 gradations) is performed. In FIG. 2, each subfield includes a writing period and a sustaining period. The writing period is for storing the presence or absence of discharge in the subsequent sustain period in each pixel arranged in a matrix of the PDP, and the storage operation is performed in order from the first row. Also, as shown in the figure, if the number of discharge pulses in the sustain period is “1”, “2”, “4”, “8”, “16”, “32”, “64”, “128”, respectively, A weight (luminance) corresponding to each of the 8 bits of signal can be given. Now, when a certain pixel is lit with a luminance of “129”,
Since “129” = “1” + “128”, writing may be performed only during the writing period of the first and eighth subfields.
[0004]
[Problems to be solved by the invention]
As described above, all the pixels are written in the writing period, and all the pixels are discharged simultaneously in the subsequent sustaining period based on the writing, so that the harmonics of the discharge pulse frequency in the sustaining period are unnecessary radiation waves. As emitted from the drive circuit and the PDP. In the case of the conventional PDP television using the subfield method, the unnecessary radiation wave is mixed in the tuner, and depending on the channel to be selected, there is a problem that interference such as oblique stripes occurs in the projected image.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, the PDP driving method of the present invention changes the frequency of a clock for performing display control for each frame or for each subfield.
[0006]
According to the present invention, it is possible to obtain a PDP television that changes the frequency of the discharge pulse in the sustain period, disperses the harmonics of the frequency, reduces interference with a specific channel, and displays a beautiful image.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
The invention according to claim 1 of the present invention is a plasma display in which one frame corresponding to the time of one screen of an external input signal is composed of a plurality of subfields having different relative luminances, and displays a plurality of gradation images. In this driving method, the processing time of one frame is within the period of the vertical synchronizing signal of the external input signal, and a pause period during which the display operation is stopped after the end of a plurality of subfields until the start of the next one frame is set. The harmonics of the discharge pulse frequency in the sustain period change by changing the frequency of the clock for performing display control for one frame so as to change the time of the pause period for each frame. Interferences such as diagonal stripes that enter the tuner and change on the screen change from screen to screen (every frame). It has the effect of displaying an image on the PDP TV.
[0008]
Next, according to the fourth aspect of the present invention, one frame corresponding to the time of one screen of the external input signal is composed of a plurality of subfields having different relative luminance, and a multi-gradation video is displayed. In the plasma display driving method, the processing time of the one frame is within the period of the vertical synchronization signal of the external input signal, and the processing time of the subfields is changed so that the processing time of each of the plurality of subfields constituting the one frame is changed. Since the harmonics of the discharge pulse frequency during the sustain period change by changing the frequency of the clock for performing display control, the harmonics are mixed into the tuner, and obstructions such as diagonal stripes generated on the screen are sub-screened in one screen. Since it changes by the number of times of the field, it has an effect of displaying a beautiful video that is not detected by human eyes on the PDP television.
[0009]
In addition, since the invention described in claims 2 and 5 of the present invention performs the operation shown in the claims 1 and 4 using a clock generator controlled by random noise, the diagonal stripes generated on the screen, etc. Interference can be made discontinuous and more beautiful video can be displayed on a PDP television.
[0010]
Further, according to the third and sixth aspects of the present invention, by using a clock switching circuit that switches between a plurality of clock generators and the plurality of clocks, by selecting several types of discharge pulse frequencies in the sustain period, The frequency dependence of the harmonics of the discharge pulse frequency can be reduced, and a stable and beautiful image can be displayed on the PDP television.
[0011]
(Embodiment 1)
An embodiment of the invention described in claim 1 of the present invention will be described below with reference to FIG.
[0012]
FIG. 1 is a block diagram of a PDP driving method according to an embodiment of the present invention. In FIG. 1, when analog video signals R, G, and B, a horizontal synchronizing signal HD, and a vertical synchronizing signal VD are input from the outside, the analog video signal is sampled according to the number of horizontal pixels of the plasma display panel (PDP) 8. For this purpose, a synchronous clock is input to the write pulse inputs of the A / D converter 1 and the frame memory 2, and a video signal digitized into , for example, 8 bits is written into the frame memory 2. It said synchronization clock, the control circuit 4 and the synchronizing signal generating circuit 3, is generated in accordance with the number of horizontal pixels of the PDP8 by the horizontal synchronizing signal HD and the PLL operation. The PLL operation is general, and details are omitted. Next, the digital video signals written in the frame memory 2 are sequentially read out from the least significant bit in accordance with the subfield method, and the subfield logic circuit 6 in the next stage uses the diagram used for the description in the conventional example. Used to turn on / off the writing period of the time chart of 2. Here, the display clock used for the reading is generated by the frequency variable display clock generation circuit 5 and the control circuit 4. The important thing here is that the display clock does not need to be synchronized with the external input signal, and the processing time of one frame in the time chart of FIG. 2 is the time for one screen of the external input signal , that is, the vertical synchronization signal. It suffices to be within the period (1 / VD). Subsequently, the subfield signal output from the subfield logic circuit 6 is amplified to a voltage necessary for discharging the PDP 8 by the driving circuit 7 to drive the PDP 8.
[0013]
Next, characteristics of the PDP driving method in Embodiment 1 of the present invention will be described. 3, the processing time of a certain frame (n-th frame) is determined by the frequency of the display clock. Now, the processing time of one frame is always kept within the period of the vertical synchronization signal (1 / VD), and the two time differences between the processing time of the one frame and the period of the vertical synchronization signal are set as a pause period (as shown in FIG. 3). In addition, if the display operation is stopped as a period from the end of the plurality of subfields SF1 to SF8 to the start of the next frame, subfield driving can be performed while maintaining synchronization with the external input signal. That is, as shown by tn and tn + 1 in FIG. 3, by providing a pause period for each frame and changing the frequency of the display clock for each frame , the harmonics of the discharge pulse frequency in the sustain period change. Since the above harmonics are mixed in the tuner and the interference such as diagonal stripes generated on the screen changes every screen (every frame), a beautiful video that is hardly detected by human eyes is actually displayed on the PDP TV. be able to.
[0014]
(Embodiment 2)
An embodiment of the invention described in claim 4 of the present invention will be described below with reference to the drawings.
[0015]
Since the basic driving method is almost the same as in the first embodiment, the characteristics of the PDP driving method in the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is an enlarged view of the sustain pulse in the sustain period of the mth and (m + 1) th subfields in the time chart of FIG. In the figure, even if the periods 1 / fm and 1 / f (m + 1) of the above two types of sustain pulses are changed, the processing time of 8 subfields (= 1 frame processing time) is the same as in the first embodiment. If it is within the vertical synchronizing signal cycle (1 / VD) from the outside, subfield driving can be performed while maintaining synchronization with the external input signal. That is, the harmonics of the discharge pulse frequency in the sustain period change by changing the frequency of the clock that performs display control so as to change the sustain pulse period for each subfield, so that the harmonics are mixed into the tuner. Since the disturbance such as diagonal stripes generated on the screen changes by the number of subfields in one screen, it has the effect of displaying a beautiful video that is not detected by human eyes on the PDP television (Embodiment 3).
Hereinafter, an embodiment of the invention described in claims 2 and 5 of the present invention will be described with reference to FIG.
[0016]
Although the basic driving method is almost the same as in the first and second embodiments, the frequency variable display clock generation circuit in FIG. 1 is replaced with a clock generator controlled by random noise, and the processing time of eight subfields (= 1 frame) If the processing time is within the external vertical sync signal period (1 / VD), subfield driving can be performed while maintaining synchronization with the external input signal, and obstructions such as diagonal stripes generated on the screen are discontinuous. More beautiful video can be displayed on the PDP television.
[0017]
(Embodiment 4)
Hereinafter, an embodiment of the invention described in claims 3 and 6 of the present invention will be described with reference to FIG.
[0018]
Although the basic driving method is almost the same as in the first and second embodiments, the frequency variable display clock generation circuit in FIG. 1 is replaced with a plurality of clock generators and a clock switching circuit that switches between the plurality of clocks, If the processing time (= 1 frame processing time) is set to be within the vertical synchronizing signal period (1 / VD) from the outside, subfield driving can be performed while maintaining synchronization with the external input signal. Here, the frequency dependency of the harmonics of the discharge pulse frequency is reduced by selecting several types of discharge pulse frequencies during the sustain period using a plurality of clock generators and a clock switching circuit for switching the plurality of clocks. In addition, stable and beautiful images can be displayed on the PDP television.
[0019]
【The invention's effect】
As described above, according to the first PDP driving method of the present invention, the harmonic of the discharge pulse frequency in the sustain period changes by changing the frequency of the clock for performing display control for each frame. Since the above harmonics are mixed in the tuner and the interference such as diagonal stripes generated on the screen changes every screen (every frame), a PDP television that displays beautiful images that are hardly detected by human eyes actually. Can be provided.
[0020]
Further, according to the second PDP driving method of the present invention, since the harmonic of the discharge pulse frequency in the sustain period is changed by changing the frequency of the clock for performing display control for each subfield, the above harmonics Is mixed in the tuner, and obstructions such as diagonal stripes generated on the screen change by the number of subfields in one screen, so that it is possible to provide a PDP television that displays beautiful video that is not detected by human eyes.
[0021]
Further, according to the third PDP driving method of the present invention, the clock generator controlled by random noise is used to perform the operations described in the first and second embodiments, so that the diagonal stripes generated on the screen, etc. Interference can be made discontinuous, and a PDP television that displays even more beautiful images can be provided.
[0022]
Furthermore, according to the fourth PDP driving method of the present invention, by using a clock switching circuit that switches between a plurality of clock generators and the plurality of clocks, by selecting several types of discharge pulse frequencies in the sustain period, It is possible to provide a PDP television that reduces the frequency dependence of the harmonics of the discharge pulse frequency and stably displays beautiful images.
[Brief description of the drawings]
FIG. 1 is a block diagram of a PDP driving method according to an embodiment of the present invention. FIG. 2 is a time chart when gradation display of a video signal of 8 bits (256 gradations) is performed by a subfield method. FIG. 4 is a diagram showing characteristics of a PDP driving method according to Embodiment 1 of the present invention. FIG. 4 is a diagram showing characteristics of a PDP driving method according to Embodiment 2 of the present invention.
R, G, B Analog video signal input from outside HD Horizontal synchronization signal input from outside VD Vertical synchronization signal input from outside 1 A / D converter 2 Frame memory 3 Synchronous clock generation circuit 4 Control circuit 5 Frequency Variable display clock generation circuit 6 Subfield logic circuit 7 Drive circuit 8 Plasma display panel (PDP)
SF1-8 subfield tn, tn + 1 idle period

Claims (6)

In the method of driving a plasma display in which one frame corresponding to the time of one screen of an external input signal is composed of a plurality of subfields having different relative luminances and displaying a multi-gradation image, the processing time of the one frame is as within the period of the vertical synchronizing signal of the external input signal, a pause period to stop the display operation during after completion of the plurality of sub-fields to the start of the next frame is provided, the display control for one frame for each of the frame A method for driving a plasma display, characterized by changing a frequency of a clock for performing the operation.   2. The plasma display driving method according to claim 1, wherein a clock generator controlled by random noise is used.   2. The plasma display driving method according to claim 1, wherein a plurality of clock generators and a clock switching circuit for switching the plurality of clocks are used. In the method of driving a plasma display in which one frame corresponding to the time of one screen of an external input signal is composed of a plurality of subfields having different relative luminances and displaying a multi-gradation image, the processing time of the one frame is Within the period of the vertical synchronizing signal of the external input signal, the frequency of the clock for performing the display control of the subfield is changed so that the period of the sustain pulse is changed for each of the plurality of subfields constituting the one frame. A method for driving a plasma display.   5. The plasma display driving method according to claim 4, wherein a clock generator controlled by random noise is used.   5. The plasma display driving method according to claim 4, wherein a plurality of clock generators and a clock switching circuit for switching the plurality of clocks are used.

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