JPH10149136A - Driving method for plasma display - Google Patents
Driving method for plasma displayInfo
- Publication number
- JPH10149136A JPH10149136A JP8310341A JP31034196A JPH10149136A JP H10149136 A JPH10149136 A JP H10149136A JP 8310341 A JP8310341 A JP 8310341A JP 31034196 A JP31034196 A JP 31034196A JP H10149136 A JPH10149136 A JP H10149136A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- frequency
- pdp
- driving method
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Control Of Gas Discharge Display Tubes (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、プラズマディスプ
レイパネル（以下、ＰＤＰと記す）の階調表示可能な駆
動方法の１つである、いわゆるサブフィールド法の駆動
回路およびパネルから発生する高周波ノイズの軽減方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a so-called subfield method, which is one of driving methods capable of displaying a gradation of a plasma display panel (hereinafter referred to as a PDP), and a method of removing high-frequency noise generated from the panel. It is about the mitigation method.
【０００２】[0002]
【従来の技術】従来、ＰＤＰの階調表示可能な駆動方法
の１つとして、特開平４−１９５０８７号公報等に示さ
れるサブフィールド法と呼ばれる駆動方法が用いられて
いる。以下、この方法について図面を参照しながら説明
する。2. Description of the Related Art Conventionally, as one of driving methods capable of displaying a gradation of a PDP, a driving method called a subfield method disclosed in Japanese Patent Application Laid-Open No. H4-195087 has been used. Hereinafter, this method will be described with reference to the drawings.
【０００３】図２は、１フレームを８つのサブフィール
ド（ＳＦ１〜８）に分割し、映像信号８ビット（２５６
階調）の階調表示を行う時のタイムチャートである。図
２において、各サブフィールドは書き込み期間と維持期
間からなっている。書き込み期間は、ＰＤＰのマトリッ
クス状に並んだ各画素に、続く維持期間の放電の有無を
記憶させるためのものであり、上記記憶動作は第１行か
ら順番に行われる。また図のように、維持期間の放電パ
ルス数をそれぞれ「１」、「２」、「４」、「８」、
「１６」、「３２」、「６４」、「１２８」とすれば、
映像信号８ビットにそれぞれ対応する重み（輝度）を持
たせることができる。いま、ある画素を「１２９」の輝
度で光らせる場合、 「１２９」＝「１」＋「１２８」 であるから、第１および第８サブフィールドの書き込み
期間のみに書き込みを行えばよい。FIG. 2 shows that one frame is divided into eight subfields (SF1 to SF8), and the video signal is divided into 8 bits (256 bits).
5 is a time chart when performing gradation display of (gradation). In FIG. 2, each subfield includes a write period and a sustain period. The writing period is for storing the presence or absence of the discharge in the subsequent sustain period in each pixel arranged in a matrix of the PDP, and the above-described storage operation is performed in order from the first row. Further, as shown in the figure, the number of discharge pulses in the sustain period is set to “1”, “2”, “4”, “8”,
"16", "32", "64", "128"
A weight (luminance) corresponding to each of the 8 bits of the video signal can be given. Now, in the case where a certain pixel is illuminated with the luminance of “129”, since “129” = “1” + “128”, writing needs to be performed only in the writing period of the first and eighth subfields.
【０００４】[0004]
【発明が解決しようとする課題】上述のように、書き込
み期間にすべての画素に書き込みを行い、上記書き込み
に基づいて、続く維持期間に全画素が一斉に放電を行う
ため、維持期間の放電パルス周波数の高調波が、不要輻
射波として駆動回路およびＰＤＰから放射される。従来
のサブフィールド法を用いたＰＤＰテレビの場合、チュ
ーナに上記不要輻射波が混入し、選局するチャンネルに
よっては、映し出される映像に斜め縞等の妨害が発生す
るという課題を有していた。As described above, all the pixels are written during the writing period, and all the pixels simultaneously discharge during the subsequent sustaining period based on the writing. Harmonics of the frequency are radiated from the drive circuit and the PDP as unnecessary radiation. In the case of the PDP television using the conventional subfield method, there is a problem that the unnecessary radiation wave is mixed into the tuner, and depending on the channel to be selected, obstruction such as oblique stripes occurs in the projected image.
【０００５】[0005]
【課題を解決するための手段】前記課題を解決するため
に、本発明のＰＤＰの駆動方法は、フレーム毎、あるい
はサブフィールド毎に表示制御を行うクロックの周波数
を変化させる。In order to solve the above-mentioned problems, a driving method of a PDP according to the present invention changes the frequency of a clock for performing display control for each frame or each subfield.
【０００６】本発明により、維持期間の放電パルスの周
波数を変化させ、上記周波数の高調波を分散させ、特定
のチャンネルに対する妨害を軽減し、美しい映像を表示
するＰＤＰテレビを得ることができる。According to the present invention, it is possible to obtain a PDP television that displays a beautiful image by changing the frequency of the discharge pulse during the sustain period, dispersing harmonics of the frequency, reducing interference with a specific channel.
【０００７】[0007]
【発明の実施の形態】本発明の請求項１に記載の発明
は、フレーム毎に表示制御を行うクロックの周波数を変
化させることにより、維持期間の放電パルス周波数の高
調波が変化するため、上記高調波がチューナに混入し、
画面に発生する斜め縞等の妨害が１画面毎（１フレーム
毎）に変化するので、実際にはほとんど人間の目に検知
されない美しい映像をＰＤＰテレビに表示するという作
用を有する。According to the first aspect of the present invention, the harmonics of the discharge pulse frequency in the sustain period change by changing the frequency of the clock for performing the display control for each frame. Harmonics get into the tuner,
Since the obstruction such as oblique stripes generated on the screen changes every screen (every frame), it has an effect of displaying a beautiful image which is hardly detected by human eyes on the PDP television.
【０００８】つぎに、本発明の請求項４に記載の発明
は、サブフィールド毎に表示制御を行うクロックの周波
数を変化させることにより、維持期間の放電パルス周波
数の高調波が変化するため、上記高調波がチューナに混
入し、画面に発生する斜め縞等の妨害が１画面中サブフ
ィールドの回数だけ変化するので、さらに人間の目に検
知されない美しい映像をＰＤＰテレビに表示するという
作用を有する。Next, in the invention according to claim 4 of the present invention, the harmonic of the discharge pulse frequency in the sustain period changes by changing the frequency of the clock for performing the display control for each subfield. Since harmonics are mixed into the tuner and obstructions such as oblique stripes generated on the screen change by the number of subfields in one screen, a beautiful image which is not detected by human eyes is displayed on the PDP television.
【０００９】また、本発明の請求項２および５に記載の
発明は、ランダムノイズで制御するクロック発生器を用
いて、上記請求項１および４に示した作用を行うため、
画面に発生する斜め縞等の妨害を不連続にすることがで
き、さらに美しい映像をＰＤＰテレビに表示することが
できる。According to the second and fifth aspects of the present invention, the operation described in the first and fourth aspects is performed by using a clock generator controlled by random noise.
Disturbance such as oblique stripes generated on the screen can be made discontinuous, and more beautiful images can be displayed on a PDP television.
【００１０】さらに、本発明の請求項３および６に記載
の発明は、複数のクロック発生器と上記複数のクロック
を切り替えるクロック切り替え回路を用いて、維持期間
の放電パルス周波数を何種類か選択することにより、上
記放電パルス周波数の高調波の周波数依存性を軽減し、
安定して美しい映像をＰＤＰテレビに表示することがで
きる。Further, according to the third and sixth aspects of the present invention, several kinds of discharge pulse frequencies in the sustain period are selected by using a plurality of clock generators and a clock switching circuit for switching the plurality of clocks. By reducing the frequency dependence of harmonics of the discharge pulse frequency,
A beautiful video can be stably displayed on a PDP television.
【００１１】（実施の形態１）以下に、本発明の請求項
１に記載された発明の実施の形態について、図１を参照
しながら説明する。(Embodiment 1) An embodiment of the invention described in claim 1 of the present invention will be described below with reference to FIG.
【００１２】図１は本発明におけるＰＤＰの駆動方法の
１実施例のブロック構成図である。図１において、外部
よりアナログ映像信号Ｒ、Ｇ、Ｂおよび水平同期信号Ｈ
Ｄ、垂直同期信号ＶＤが入力されると、上記アナログ映
像信号をプラズマディスプレイパネル（ＰＤＰ）８の水
平画素数にあわせてサンプリングするための同期クロッ
クがＡ／Ｄ変換器１およびフレームメモリ２の書き込み
パルス入力に入力され、上記フレームメモリ２には例え
ば８ビットにデジタル化された映像信号が書き込まれ
る。上記同期クロックは、同期クロック発生回路３と制
御回路４により上記水平同期信号ＨＤとＰＬＬ動作によ
り上記ＰＤＰ８の水平画素数に応じて発生する。上記Ｐ
ＬＬ動作は一般的なものであり、詳細は割愛する。次
に、上記フレームメモリ２に書き込まれたデジタル映像
信号はサブフィールド法に即して最下位ビットから順に
読み出され、次段のサブフィールド論理回路６により、
従来例で説明に用いた図２のタイムチャートの書き込み
期間のオンオフに使われる。ここで、上記読みだしに用
いられる表示クロックは、周波数可変表示クロック発生
回路５と制御回路４により発生する。ここで大事なこと
は、上記表示クロックは外部入力信号と同期している必
要はなく、上記図２のタイムチャートの１フレームの処
理時間が外部入力信号の１画面分の時間すなわち垂直同
期信号周期（１／ＶＤ）以内に収まっていればよい。続
いて、上記サブフィールド論理回路６より出力されたサ
ブフィールド信号は駆動回路７によって上記ＰＤＰ８の
放電に必要な電圧まで増幅されて、上記ＰＤＰ８を駆動
する。FIG. 1 is a block diagram showing an embodiment of a PDP driving method according to the present invention. In FIG. 1, analog video signals R, G, B and a horizontal synchronizing signal H are externally supplied.
D, when the vertical synchronizing signal VD is input, a synchronizing clock for sampling the analog video signal according to the number of horizontal pixels of the plasma display panel (PDP) 8 is written into the A / D converter 1 and the frame memory 2. A pulse signal is input, and a video signal digitized to, for example, 8 bits is written in the frame memory 2. The synchronous clock is generated by the synchronous clock generating circuit 3 and the control circuit 4 according to the horizontal synchronous signal HD and the PLL operation according to the number of horizontal pixels of the PDP 8. The above P
The LL operation is general, and details are omitted. Next, the digital video signal written in the frame memory 2 is sequentially read out from the least significant bit in accordance with the subfield method, and is read by the subfield logic circuit 6 in the next stage.
It is used to turn on and off the writing period in the time chart of FIG. 2 used for explanation in the conventional example. Here, the display clock used for the reading is generated by the frequency variable display clock generation circuit 5 and the control circuit 4. What is important here is that the display clock does not need to be synchronized with the external input signal, and the processing time of one frame in the time chart of FIG. What is necessary is that it is within (1 / VD). Subsequently, the sub-field signal output from the sub-field logic circuit 6 is amplified by the driving circuit 7 to a voltage required for discharging the PDP 8, and drives the PDP 8.
【００１３】次に、本発明の実施の形態１におけるＰＤ
Ｐの駆動方法の特徴を説明する。図３において、あるフ
レーム（第ｎフレーム）の処理時間は上記表示クロック
の周波数により決まる。いま、必ず１フレームの処理時
間を上記垂直同期信号周期（１／ＶＤ）以内に収め、上
記２つの時間差を休止期間として表示動作を停止すれ
ば、外部入力信号と同期を保ったままサブフィールド駆
動をすることができる。すなわち、フレーム毎に上記表
示クロックの周波数を変化させることにより、維持期間
の放電パルス周波数の高調波が変化するため、上記高調
波がチューナに混入し、画面に発生する斜め縞等の妨害
が１画面毎（１フレーム毎）に変化するので、実際には
ほとんど人間の目に検知されない美しい映像をＰＤＰテ
レビに表示することができる。Next, the PD according to the first embodiment of the present invention will be described.
The characteristics of the driving method of P will be described. In FIG. 3, the processing time of a certain frame (n-th frame) is determined by the frequency of the display clock. Now, if the processing time of one frame is always set within the vertical synchronizing signal cycle (1 / VD) and the display operation is stopped with the time difference between the two being a halt period, the subfield driving is performed while maintaining the synchronization with the external input signal. Can be. That is, by changing the frequency of the display clock for each frame, the harmonics of the discharge pulse frequency in the sustain period change, so that the harmonics are mixed into the tuner, and obstructions such as oblique stripes generated on the screen are reduced by one. Since it changes every screen (one frame), a beautiful image which is hardly actually detected by human eyes can be displayed on the PDP television.
【００１４】（実施の形態２）以下に、本発明の請求項
４に記載された発明の実施の形態について、図を参照し
ながら説明する。(Embodiment 2) An embodiment of the present invention described in claim 4 of the present invention will be described below with reference to the drawings.
【００１５】基本的な駆動方法は実施の形態１とほぼ同
じなため、本発明の実施の形態２におけるＰＤＰの駆動
方法の特徴を図４により説明する。図４は、上記図２の
タイムチャートにおける第ｍおよび第（ｍ＋１）サブフ
ィールドの維持期間の維持パルスを拡大した図である。
図において上記２種類の維持パルスの周期１／ｆｍ、１
／ｆ（ｍ＋１）を変化させても、実施の形態１と同様
に、８つのサブフィールドの処理時間（＝１フレームの
処理時間）を上記外部からの垂直同期信号周期（１／Ｖ
Ｄ）以内とすれば、外部入力信号と同期を保ったままサ
ブフィールド駆動をすることができる。すなわち、サブ
フィールド毎に表示制御を行うクロックの周波数を変化
させることにより、維持期間の放電パルス周波数の高調
波が変化するため、上記高調波がチューナに混入し、画
面に発生する斜め縞等の妨害が１画面中サブフィールド
の回数だけ変化するので、さらに人間の目に検知されな
い美しい映像をＰＤＰテレビに表示するという作用を有
する （実施の形態３）以下に、本発明の請求項２および請求
項５に記載された発明の実施の形態について、図１を参
照しながら説明する。Since the basic driving method is almost the same as that of the first embodiment, the features of the PDP driving method according to the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is an enlarged view of the sustain pulse in the sustain period of the m-th and (m + 1) -th subfields in the time chart of FIG.
In the figure, the periods 1 / fm, 1
Even if / f (m + 1) is changed, as in the first embodiment, the processing time of eight subfields (= 1 frame processing time) is reduced by the external vertical synchronization signal cycle (1 / V).
Within D), subfield driving can be performed while maintaining synchronization with an external input signal. That is, by changing the frequency of the clock that performs the display control for each subfield, the harmonics of the discharge pulse frequency in the sustain period change, so that the harmonics are mixed into the tuner, causing oblique stripes and the like generated on the screen. Since the disturbance changes by the number of sub-fields in one screen, a beautiful image which is not detected by the human eye is displayed on the PDP television. (Third Embodiment) The following claims 2 and 3 of the present invention The embodiment of the invention described in Item 5 will be described with reference to FIG.
【００１６】基本的な駆動方法は実施の形態１および２
とほぼ同じながら、図１の周波数可変表示クロック発生
回路をランダムノイズで制御するクロック発生器に置き
換え、８つのサブフィールドの処理時間（＝１フレーム
の処理時間）を外部からの垂直同期信号周期（１／Ｖ
Ｄ）以内とすれば、外部入力信号と同期を保ったままサ
ブフィールド駆動ができ、しかも画面に発生する斜め縞
等の妨害を不連続にすることができ、さらに美しい映像
をＰＤＰテレビに表示することができる。The basic driving method is described in Embodiments 1 and 2.
1, the frequency variable display clock generation circuit of FIG. 1 is replaced with a clock generator controlled by random noise, and the processing time of eight sub-fields (= 1 frame processing time) is reduced by an external vertical synchronizing signal cycle (= 1 frame). 1 / V
Within D), sub-field driving can be performed while maintaining synchronization with an external input signal, and obstructions such as oblique stripes generated on the screen can be made discontinuous, and a more beautiful image can be displayed on a PDP television. be able to.
【００１７】（実施の形態４）以下に、本発明の請求項
３および請求項６に記載された発明の実施の形態につい
て、図１を参照しながら説明する。(Embodiment 4) An embodiment of the present invention described in claims 3 and 6 of the present invention will be described below with reference to FIG.
【００１８】基本的な駆動方法は実施の形態１および２
とほぼ同じながら、図１の周波数可変表示クロック発生
回路を複数のクロック発生器と上記複数のクロックを切
り替えるクロック切り替え回路に置き換え、８つのサブ
フィールドの処理時間（＝１フレームの処理時間）を外
部からの垂直同期信号周期（１／ＶＤ）以内とすれば、
外部入力信号と同期を保ったままサブフィールド駆動が
できる。ここで、複数のクロック発生器と上記複数のク
ロックを切り替えるクロック切り替え回路を用いて、維
持期間の放電パルス周波数を何種類か選択することによ
り、上記放電パルス周波数の高調波の周波数依存性を軽
減し、安定して美しい映像をＰＤＰテレビに表示するこ
とができる。The basic driving method is described in the first and second embodiments.
1, the frequency variable display clock generation circuit of FIG. 1 is replaced with a plurality of clock generators and a clock switching circuit for switching the plurality of clocks, and the processing time of eight sub-fields (= 1 frame processing time) is reduced Within the period of the vertical synchronization signal (1 / VD) from
Subfield driving can be performed while maintaining synchronization with an external input signal. Here, by using a plurality of clock generators and a clock switching circuit for switching the plurality of clocks, several types of discharge pulse frequencies in the sustain period are selected, thereby reducing the frequency dependence of the harmonics of the discharge pulse frequency. In addition, stable and beautiful images can be displayed on the PDP television.
【００１９】[0019]
【発明の効果】以上説明したように、本発明の第１のＰ
ＤＰの駆動方法によれば、フレーム毎に表示制御を行う
クロックの周波数を変化させることにより、維持期間の
放電パルス周波数の高調波が変化するため、上記高調波
がチューナに混入し、画面に発生する斜め縞等の妨害が
１画面毎（１フレーム毎）に変化するので、実際にはほ
とんど人間の目に検知されない美しい映像を表示するＰ
ＤＰテレビを提供できる。As described above, the first P of the present invention is obtained.
According to the DP driving method, the harmonics of the discharge pulse frequency in the sustain period are changed by changing the frequency of the clock for performing the display control for each frame, so that the harmonics are mixed into the tuner and generated on the screen. Since obstruction such as oblique stripes changes for each screen (for each frame), a beautiful image which is hardly detected by human eyes is actually displayed.
DP television can be provided.
【００２０】また、本発明の第２のＰＤＰの駆動方法に
よれば、サブフィールド毎に表示制御を行うクロックの
周波数を変化させることにより、維持期間の放電パルス
周波数の高調波が変化するため、上記高調波がチューナ
に混入し、画面に発生する斜め縞等の妨害が１画面中サ
ブフィールドの回数だけ変化するので、さらに人間の目
に検知されない美しい映像を表示するＰＤＰテレビを提
供できる。Further, according to the second driving method of the PDP of the present invention, by changing the frequency of the clock for performing the display control for each subfield, the harmonic of the discharge pulse frequency in the sustain period changes. Since the harmonics are mixed into the tuner, and obstructions such as oblique stripes generated on the screen change by the number of subfields in one screen, a PDP television that displays a beautiful image that cannot be detected by human eyes can be provided.
【００２１】また、本発明の第３のＰＤＰの駆動方法に
よれば、ランダムノイズで制御するクロック発生器を用
いて、上記実施例１および２に示した作用を行うため、
画面に発生する斜め縞等の妨害を不連続にすることがで
き、さらに美しい映像を表示するＰＤＰテレビを提供で
きる。According to the third driving method of the PDP of the present invention, the operation shown in the first and second embodiments is performed by using the clock generator controlled by random noise.
Disturbance such as oblique stripes generated on a screen can be made discontinuous, and a PDP television that displays a more beautiful image can be provided.
【００２２】さらに、本発明の第４のＰＤＰの駆動方法
によれば、複数のクロック発生器と上記複数のクロック
を切り替えるクロック切り替え回路を用いて、維持期間
の放電パルス周波数を何種類か選択することにより、上
記放電パルス周波数の高調波の周波数依存性を軽減し、
安定して美しい映像を表示するＰＤＰテレビを提供でき
る。Further, according to the fourth PDP driving method of the present invention, several types of discharge pulse frequencies in the sustain period are selected by using a plurality of clock generators and a clock switching circuit for switching the plurality of clocks. By reducing the frequency dependence of harmonics of the discharge pulse frequency,
A PDP television that stably displays beautiful images can be provided.
【図１】本発明の一実施例におけるＰＤＰの駆動方法の
ブロック構成図FIG. 1 is a block diagram of a PDP driving method according to an embodiment of the present invention.
【図２】サブフィールド法により、映像信号８ビット
（２５６階調）の階調表示を行う時のタイムチャートFIG. 2 is a time chart when gradation display of an 8-bit video signal (256 gradations) is performed by a subfield method.
【図３】本発明の実施の形態１におけるＰＤＰの駆動方
法の特徴を示す図FIG. 3 is a diagram showing characteristics of a PDP driving method according to the first embodiment of the present invention.
【図４】本発明の実施の形態２におけるＰＤＰの駆動方
法の特徴を示す図FIG. 4 is a diagram showing features of a PDP driving method according to a second embodiment of the present invention.
Ｒ、Ｇ、Ｂ 外部より入力されたアナログ映像信号 ＨＤ 外部より入力された水平同期信号 ＶＤ 外部より入力された垂直同期信号 １ Ａ／Ｄ変換器 ２ フレームメモリ ３ 同期クロック発生回路 ４ 制御回路 ５ 周波数可変表示クロック発生回路 ６ サブフィールド論理回路 ７ 駆動回路 ８ プラズマディスプレイパネル（ＰＤＰ） ＳＦ１〜８ サブフィールド ｔｎ，ｔｎ＋１ 休止期間 R, G, B Analog video signal input from outside HD Horizontal synchronization signal input from outside VD Vertical synchronization signal input from outside 1 A / D converter 2 Frame memory 3 Synchronous clock generation circuit 4 Control circuit 5 Frequency Variable display clock generation circuit 6 Subfield logic circuit 7 Drive circuit 8 Plasma display panel (PDP) SF1 to 8 Subfield tn, tn + 1 Pause period
Claims (6)
ドで１フレームを構成し、複数階調の映像を表示するプ
ラズマディスプレイの駆動方法において、上記フレーム
毎に表示制御を行うクロックの周波数を変化させること
を特徴とするプラズマディスプレイの駆動方法。1. A method for driving a plasma display in which one frame is composed of a plurality of subfields having different relative luminances and a plurality of grayscale images are displayed, wherein a frequency of a clock for performing display control is changed for each frame. A method for driving a plasma display, comprising:
器を用いることを特徴とする請求項１記載のプラズマデ
ィスプレイの駆動方法。2. The method according to claim 1, wherein a clock generator controlled by random noise is used.
ックを切り替えるクロック切り替え回路を用いることを
特徴とする請求項１記載のプラズマディスプレイの駆動
方法。3. The method according to claim 1, further comprising using a plurality of clock generators and a clock switching circuit for switching the plurality of clocks.
ドで１フレームを構成し、複数階調の映像を表示するプ
ラズマディスプレイの駆動方法において、上記サブフィ
ールド毎に表示制御を行うクロックの周波数を変化させ
ることを特徴とするプラズマディスプレイの駆動方法。4. A method of driving a plasma display which comprises a plurality of sub-fields having different relative luminances to form one frame and displays a plurality of grayscale images, wherein a frequency of a clock for controlling display is changed for each of the sub-fields. A method for driving a plasma display, comprising:
器を用いることを特徴とする請求項４記載のプラズマデ
ィスプレイの駆動方法。5. The method according to claim 4, wherein a clock generator controlled by random noise is used.
ックを切り替えるクロック切り替え回路を用いることを
特徴とする請求項４記載のプラズマディスプレイの駆動
方法。6. The method according to claim 4, wherein a plurality of clock generators and a clock switching circuit for switching the plurality of clocks are used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31034196A JP3755214B2 (en) | 1996-11-21 | 1996-11-21 | Driving method of plasma display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31034196A JP3755214B2 (en) | 1996-11-21 | 1996-11-21 | Driving method of plasma display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10149136A true JPH10149136A (en) | 1998-06-02 |
| JP3755214B2 JP3755214B2 (en) | 2006-03-15 |
Family
ID=18004074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31034196A Expired - Fee Related JP3755214B2 (en) | 1996-11-21 | 1996-11-21 | Driving method of plasma display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3755214B2 (en) |
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| JP2001282165A (en) * | 2000-03-31 | 2001-10-12 | Fujitsu Ltd | Display device and its driving method |
| US6414654B1 (en) | 1997-07-08 | 2002-07-02 | Nec Corporation | Plasma display panel having high luminance at low power consumption |
| KR20020057502A (en) * | 2001-01-05 | 2002-07-11 | 엘지전자 주식회사 | Apparatus and Method of Driving Plasma Display Panel Using Variable Sustaining Discharge |
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| US7023406B1 (en) | 1999-05-14 | 2006-04-04 | Nec Corporation | Method and apparatus for enhancing peak luminance on plasma display panel |
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| US6414654B1 (en) | 1997-07-08 | 2002-07-02 | Nec Corporation | Plasma display panel having high luminance at low power consumption |
| KR100585631B1 (en) * | 1999-04-10 | 2006-06-02 | 엘지전자 주식회사 | Method of Expressing Gray Scale in Plasma Display Panel |
| US7023406B1 (en) | 1999-05-14 | 2006-04-04 | Nec Corporation | Method and apparatus for enhancing peak luminance on plasma display panel |
| JP2001282165A (en) * | 2000-03-31 | 2001-10-12 | Fujitsu Ltd | Display device and its driving method |
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| US7321344B2 (en) | 2003-05-07 | 2008-01-22 | Pioneer Corporation | Plasma display device and method of reducing interference to radio-broadcasting waves, caused by electromagnetic waves derived from plasma display device |
| KR100733746B1 (en) * | 2003-05-07 | 2007-06-29 | 파이오니아 가부시키가이샤 | Plasma display device and method of reducing interference to radio-broadcasting waves, caused by electromagnetic waves derived from plasma display device |
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| JP2013160968A (en) * | 2012-02-07 | 2013-08-19 | Mitsubishi Electric Corp | Video display device |
| JP2014130354A (en) * | 2012-12-27 | 2014-07-10 | Fitipower Integrated Technology Inc | Display device and driving method of the same, and processing and output method of data of time schedule control circuit |
| US9570039B2 (en) | 2012-12-27 | 2017-02-14 | Fitipower Integrated Technology, Inc. | Display device, driving method of display device and data processing and outputting method of timing control circuit |
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