JP3732266B2 - Fine thick-film connection substrate and manufacturing method thereof - Google Patents

Fine thick-film connection substrate and manufacturing method thereof Download PDF

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JP3732266B2
JP3732266B2 JP00217996A JP217996A JP3732266B2 JP 3732266 B2 JP3732266 B2 JP 3732266B2 JP 00217996 A JP00217996 A JP 00217996A JP 217996 A JP217996 A JP 217996A JP 3732266 B2 JP3732266 B2 JP 3732266B2
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substrate
plating
resist
pattern
gold
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JPH09191164A (en
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亮平 小山
敬 高橋
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Asahi Kasei EMD Corp
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Asahi Kasei EMD Corp
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Description

【0001】
【発明の属する技術分野】
本発明は配線密度の高い、液晶やLSIの実装基板・接続部品とその製造方法に関するものである。
【0002】
【従来の技術】
一般に液晶の駆動回路基板は表面にLSIのチップを載せワイアボンディングで基板とLSIを接続するか、バンプを2次元的に配置したLSIチップをフェイスダウンで基板に実装後、基板の他の接続端子部分を異方導電性シート(ACF)で液晶基板の端子部に接続する。ここで液晶のVGA、S−VGAの出現により、より高密度な実装基板が必要とされ、一方では、接続端子が1次元的にチップの外周4辺にレイアウトされているため、LSIの集積度があがらずコストダウンの妨げになっている。
【0003】
また異方導電性シートで接続する場合、基板面から導体が凸になっていると接続される両方の面から飛び出た凸が互い違いにはまりこみショートしてしまう。そのため基板面のどちらか一方を平坦にすることがこういった基板では必要とされる。そこで配線密度が高く、かつ基板面から導体が飛び出ていない構造の基板が強く要求されている。
【0004】
【発明が解決しようとする課題】
従来、こう言った接続基板はエッチング法で作られてきたが、配線密度が高くなるのに従い、いわゆるメッキ法、つまりメッキで必要なところに導体を形成する方法が有力になってきた。特に導電性基板にレジストを形成し基板を陰極とし電解メッキを施すことで導体を形成し、その後メッキ面を内側にしてプリプレグで張り合わせ、導電性基板を除去して配線基板を形成する方法が最も有効である。この方法によれば導体はレジストの壁にその形状を制御され、配線密度が高くても厚みを厚くできその結果回路抵抗を低くできる。しかも基板表面には導体が飛び出ていないのでACFの接続でも良好である。
【0005】
しかし、こう言った基板では接続部はワイアボンディングやACFでの接続信頼性を上げるため金メッキを施す必要がある。金メッキ層は下地の銅と拡散を起こし熱や放置により金層が表面からなくなってしまう。そこで一般には銅の上にNiまたはその合金の様な拡散防止膜を引いてから金メッキを行う。
しかし、表面が平坦になっても更にNiメッキを行うとそのために表面が凸状になり、同時に線間も狭くなる(図2参照)。この結果下記の問題が発生する。
【0006】
▲1▼高配線密度基板ではNiメッキを例えば5μm(金メッキの下地として一般的な厚み)行うと線間はほぼその2倍の10μm狭くなる。これはNiメッキは特に平滑性が高く厚みと同じかそれ以上広がる性質があるからである。従って線間絶縁が低下する。また表面に5μm程度の凸状部分ができてしまい、微細ピッチでのACF接続では問題になる。
▲2▼表面に凸部分ができると種々の処理によりその凸部分に処理液の残留を起こし、マイグレーションの原因となる。しかも環境雰囲気にさらされる回路パターンの表面積が増加するのでマイグレーションを促進してしまう。
【0007】
【課題を解決するための手段】
そこで、本発明は前記の問題を解決するため、少なくとも1カ所以上配線ピッチが80μm以下で、その箇所の導体厚みが配線ピッチの1/2以上である微細厚膜接続基板であって、導体パターンの絶縁材料と接触していない部分が金の拡散を防止できる第1の金属層に覆われており、かつ第1の金属層を含めて導体パターンが同一の絶縁材料に埋め込まれ、更に導体パターンの一部の表面には金またはその合金からなる第2の金属層が形成されていることを特徴とする微細厚膜接続基板であり、また拡散防止金属がNi、Ti、Wのいずれかまたはその合金、またはいずれか1種を含む合金であることを特徴とする前記微細厚膜接続基板であり、拡散防止金属がNi−PまたはNi−Bであることを特徴とする前記微細厚膜接続基板を提供するものである。
【0008】
また前記問題を解決するために、導電性基板にレジストの回路パターンを形成する工程と、レジストの形成されていない基板表面に拡散防止金属をメッキする工程と、更に導電性基板の回路パターンを形成した面に導電性金属をメッキし、ピッチの1/2倍以上の厚みの導体パターンを形成する工程と、レジストを除去する工程と、形成された導体パターンを内側にして基板どうし、または絶縁基板の両面または片面に接着する工程と、基板を溶解除去する工程とからなる微細厚膜接続基板の製造方法を提供するものであり、アルミまたはその合金からなる基板にジンケート処理を行う工程と、アルカリ現像タイプドライフィルムレジストの回路パターンを形成する工程と、レジストの形成されていない基板表面にNiまたはNi−PまたはNi−Bをメッキする工程と、更に導電性基板の回路パターンを形成した面に酸性電解銅メッキを行い、基板内の最も配線密度の高い所のピッチの1/2倍以上の厚みの銅を形成する工程と、前記ドライフィルムレジストを除去する工程と、形成された導体パターンを内側にして基板どうし、または絶縁基板の両面または片面に接着する工程と、基板を溶解除去する工程とからなる微細厚膜接続基板の製造方法を提供するものである。
【0009】
【作用】
本発明では接続のための表面保護金属である金の拡散防止層、例えばNiメッキ層を含めて基板絶縁層の中に埋め込むことにより、線間の絶縁を防止することができ、表面を拡散防止層を含めて平滑にすることにより、銅マイグレーションの原因となる処理液の残留、環境雰囲気にさらされる回路パターンの表面積をなくし、信頼性を高めることができる。
【0010】
【発明の実施の形態】
以下、本発明を例を挙げて具体的に詳述する。
本発明の導電性基板としてアルミまたはその合金からなる基板が用いられる。基板はその表面性が最終製品の表面性に大きく影響を与えるためできる限り鏡面を持つ基板が好ましい。基板の厚みは自由に選択できるが、一般には10μm〜200μmが良い。薄すぎるとハンドリングでしわや傷が発生しやすく、かつ抵抗が高くなり、電解メッキの均一性を損なう。
またアルミの純度は、99%以上が良く、好ましくは99.6%以上のいわゆるJIS規格で1N30以上が好ましい。純度が低すぎるとメッキの均一性や基板エッチングでのむらを生じる。
【0011】
本発明で用いられるレジストとしては、レジスト工程以降の薬品に耐性があり、必要な導体厚み程度の厚みを有し、かつその厚みにおいて必要な解像力が得られればよいが、一般には高解像力を持つドライフィルムレジストが作業性などの特性から好ましい。更にドライフィルムの中でも環境対策や剥離の簡便性からアルカリ現像タイプのドライフィルムが好ましい。
次にアルカリ現像タイプドライフィルムレジストの回路パターンを形成する場合、更にドライフィルムレジストの密着性向上と基板面からのマスク露光時の光の反射を防止する上でレジスト工程に先だって基板に亜鉛の置換メッキ、いわゆるジンケート処理を行う方が良い。これにより微細で厚膜な導体をメッキするために必要なアスペクトの高いレジスト、つまり幅が狭く且つ厚みが厚いレジストが形成できる(図3参照)。レジスト厚みはレジストの解像力とジンケート下地の表面状態に依存するが、最終的に得ようとする導体厚み以上が好ましい。
【0012】
第1の金属層は、レジストの形成されていない基板表面に拡散防止金属のメッキを行うことにより形成される。拡散防止金属としては、Ni,Ti,Wのいずれか、またはその合金、またはいずれか1種を含む合金が用いられ、拡散防止特性や経済面から特にNiまたはその合金Ni−P、Ni−Bが好ましい。このNi(またはNi合金)層はアルミ基板の酸に対する弱さを防ぐバリア層となり、後の工程である酸性銅メッキから基板を守ることや、最終製品での基板からの銅マイグレーションを防止しつつ基板表面からの突出を防ぐ効果がある。
拡散防止金属のメッキは、電解メッキでも無電解メッキでも良いが、特に無電解メッキが設備的にも有利である。ここでメッキ液はいずれでも良いが、アルカリ性ではドライフィルムレジストが溶解してしまうため、中性または酸性のメッキ液であることが望ましい。さらに基材のメッキ液への溶解を考えると中性に近いことが望ましい。この点でNiまたはその合金は中性領域に近いメッキ液が多いので好ましい。
【0013】
次に導体パターンの主たる第2の金属層を形成する。導体パターンとしては銅、銅合金、銅銀合金などの導電性材料が用いられ、その導体厚みは配線ピッチの1/2以上であることが好ましい。例えば、基板を陰極とし、導電性基板の回路パターンを形成した面に酸性電解銅メッキを行い、基板内最小ピッチの1/2倍以上の厚みの銅を形成する(図4参照)。またメッキ厚みが薄いと形成された基板の回路抵抗が高くなり、液晶駆動回路に用いた場合には画面のS/N比が低下する。また回路抵抗が高くなることで伝達可能周波数が低下する。
酸性銅メッキを行う場合は、アルカリ性の銅メッキ液ではレジストが溶解してしまうため、良好な添加剤を選択することで良好な質の銅が低コストで形成できる硫酸銅メッキが好ましい。
メッキ終了後、ドライフィルムレジストを除去する。一般には苛性ソーダが用いられる。
【0014】
次に形成された導体パターンを内側にして基板どうし、または絶縁基板の両面または片面に接着剤を用いて接着する(図5参照)。一般に使われているプリプレグか接着剤シート(この場合シートは基材フィルムの両面に接着剤がついているものでも接着剤のみの物でも良い)を用いれば良い。
ここで用いられた接着剤は硬化後、絶縁材料となる。また基材フィルムの両面に接着剤がついている基材フィルムを含めて絶縁材料となる。
次に基板を溶解除去する。溶解する液としては導体パターンや拡散防止金属を溶解する速度より導電性基板を溶解する速度が十分大きいものを選ぶ。例えば、導体パターンが銅で拡散防止金属がNiで基板がアルミであれば10%程度の塩酸が好ましい。
【0015】
最後に必要に応じて金メッキを行う(図6参照)。実際には接合に使われるランドには金メッキをする。これは通常Niメッキの上に行う金メッキプロセスであれば何でもよいがメッキ厚みとしては通常1μm以下で行う。また、コストの上から金メッキ前にメッキ不要部分があれば耐金メッキレジストで不要部分をコーティングしても良い。
本発明の製造方法で得られた微細厚膜接続基板の導体パターンは先に述べた拡散防止金属層を含めて同一の絶縁材料に埋め込まれており、表面が平滑で、かつそのため表面における汚染がないのでマイグレーションのない微細厚膜接続基板となる(図1参照)。以下、実施例を挙げるが本発明はこれらに限定されるものではない。
【0016】
【実施例1】
厚み150μm、純度規格1N30で表面アルミ箔に上村工業(株)製ジンケート液(AZ−401−3X)を3倍に希釈した液で液温30℃、80秒処理した。水洗後、15%硝酸で20秒間洗浄し、再び前記ジンケート液で液温30℃80秒処理し、その後水洗した。
次に旭化成工業(株)製ドライフィルムレジスト(SPGー201、厚み20μm)をラミネートし、線ピッチ50μm、線幅25μm(レジストが除去される幅)、線間25μmのマスクパターンを露光器で露光し、現像した。
得られた基板を奥野製薬(株)製NiーP電解メッキ液、商標ニッケリン浴(LニッケリンDを200cc/リットル、硫酸ニッケル150g/リットル、塩化ナトリウム30g/リットル)で液温60℃、8分メッキし約5μmのNi−P層を形成した。次に硫酸銅メッキ液により銅を30μmメッキし、ピッチ50μm線幅25μmパターン厚み35μmのパターンを形成した。
【0017】
次いでドライフィルムレジストを3%苛性ソーダで除去し、日立化成工業(株)製プリプレグ(GEA−67N KLN)を介して上で得られた基板を銅メッキパターンがある側を内側にして接着した。次にアルミ基板を10%の塩酸で溶解除去した。
得られた基板は回路パターンの表面に出ている部分はNi−Pで覆われているので、その上に直接置換型無電解金メッキ液(エヌ・イーケムキャット(株)製商標Atomex)で置換メッキ後、自己触媒無電解メッキ液(エヌ・イーケムキャット(株)製商標Super Mex#600)で合計約0.5μm金を析出させた。
得られた基板は配線密度50μm、導体厚み35μmで表面はNi−P5μm+金0.5μmで覆われており、100mm×30mmの基板150枚中不良は無く、且つ線間に50Vをかけ、60℃、90〜95%環境下で1000時間後でも線間絶縁に変化は無かった。
【0018】
【実施例2】
厚み80μm、純度規格1N30で表面アルミ箔に上村工業(株)製ジンケート液(AZ−401−3X)を3倍に希釈した液で液温30℃、80秒処理した。水洗後、15%硝酸で20秒間洗浄し、再び前記ジンケート液で液温30℃、80秒処理しその後水洗した。
次に旭化成工業(株)製ドライフィルムレジスト(SPG−201、厚み20μm)をラミネートし、線ピッチ26μm、線幅13μm(レジストが除去される幅)、線間13μmのマスクパターンを露光器で露光し、現像した。
得られた基板を奥野製薬(株)製Ni無電解メッキ液(ICP−ニコロンU)を85℃処理し、約2μmのNi−Pを形成した。次に硫酸銅メッキ液により銅を15μmメッキし、ピッチ26μm、線幅13μmパターン厚み17μmのパターンを形成した。
【0019】
次いでドライフィルムレジストを3%苛性ソーダで除去し、東レデュポン(株)製ポリイミドフィルム(50μm厚み)の表面に接着剤シート、商標パイラックス(LF−0100 500H、厚み25μm、デュポンジャパンリミテッド(株)製)を介して上で得られた基板を銅メッキパターンがある側を内側にして接着した。次にアルミ基板を10%の塩酸で溶解除去した。
【0020】
得られた基板は回路パターンの表面に出ている部分はNi−Pで覆われているので、その上に直接置換型無電解金メッキ液(エヌ・イーケムキャット(株)製商標Super Mex#200)で約0.1μm金を析出させた。
得られた基板は配線ピッチ26μm、導体厚み17μmで表面はNi−P2μm+金0.1μmで覆われており、80mm×15mmの基板150枚中不良は無く、且つ線間に25Vをかけ、60℃、90〜95%環境下で1000時間後でも線間絶縁に変化は無かった。
【0021】
【実施例3】
厚み80μm、純度規格1N30で表面アルミ箔に上村工業(株)製ジンケート液(AZ−401−3X)を3倍に希釈した液で液温30℃、80秒処理した。水洗後、15%硝酸で20秒間洗浄し、再び前記ジンケート液で液温30℃、80秒処理しその後水洗した。
次に旭化成工業(株)製ドライフィルムレジスト(SPG−201、厚み20μm)をラミネートし、線ピッチ26μm、線幅13μm(レジストが除去される幅)、線間13μmのマスクパターンを露光器で露光し、現像した。
得られた基板を奥野製薬(株)製Ni−B無電解メッキ液(トップケミアロイB−1)を液温65℃で処理し約2μmのNi−Bを形成した。
【0022】
次に硫酸銅メッキ液により銅を15μmメッキし、ピッチ26μm、線幅13μmパターン厚み17μmのパターンを形成した。
次いでドライフィルムレジストを3%苛性ソーダで除去し、東レデュポン(株)製ポリイミドフィルム(50μm厚み)の表面に接着剤シート、商標パイラックス(LF−0100 500H、厚み25μm、デュポンジャパンリミテッド(株)製)を介して上で得られた基板を銅メッキパターンがある側を内側にして接着した。次にアルミ基板を10%の塩酸で溶解除去した。
【0023】
得られた基板は回路パターンの表面に出ている部分はNi−Bで覆われているのでその上に直接置換型無電解金メッキ液(エヌ・イーケムキャット(株)製商標Super Mex#200)で約0.1μm金を析出させた。
得られた基板は配線ピッチ26μm、導体厚み17μmで表面はNi−B2μm+金0.1μmで覆われており、80mm×15mmの基板150枚中不良は無く、且つ線間に25Vをかけ、60℃、90〜95%環境下で1000時間後でも線間絶縁に変化は無かった。
【0024】
【比較例1】
厚み150μm、純度規格1N30で表面アルミ箔に上村工業(株)製ジンケート液(AZ−401−3X)を3倍に希釈した液で液温30℃、80秒処理した。水洗後、15%硝酸で20秒間洗浄し、再び前記ジンケート液で液温30℃、80秒処理し、その後水洗した。
次に旭化成工業(株)製ドライフィルムレジスト(SPG−201、厚み20μm)をラミネートし、線ピッチ50μm、線幅25μm(レジストが除去される幅)、線間25μmのマスクパターンを露光器で露光し、現像した。
得られた基板をピロリン酸銅メッキで約2μmの銅を形成した。このときドライフィルムに一部剥離が見られた。
【0025】
次に硫酸銅メッキ液により銅を33μmメッキし、ピッチ50μm線幅25μmパターン厚み35μmのパターンを形成した。
次いでドライフィルムレジストを3%苛性ソーダで除去し、日立化成工業(株)製プリプレグ(GEA−67N KLN)を介して上で得られた基板を銅メッキパターンがある側を内側にして接着した。
次にアルミ基板を10%の塩酸で溶解除去した。得られた基板は回路パターンの表面に出ている部分は銅なので表面を10%硫酸で洗浄後、Ni電解メッキワット浴に荏原ユージライト(株)製光沢ニッケル#66プロセス(添加剤は#610、#62、#63を所定量添加した建浴液)で5μm、Niを形成した。
更にその上に直接電解金メッキ液(エヌ・イーケムキャット(株)製ECF−68)で約0.5μm金を析出させた。
【0026】
得られた基板は配線ピッチ50μm、導体厚み35μmで線間ギャップは平均10μmであるが、基板によってはドライフィルムの剥離によると思われるショート箇所が数多く見られ、線間ギャップが0μmに見える所もあった。100mm×30mmの基板150枚中不良は93枚あり、残る良品77枚に線間に50Vをかけ、60℃、90〜95%環境下で1000時間放置後、絶縁があったのが69枚で8枚は絶縁不良になっていた。
【0027】
【発明の効果】
本発明の微細厚膜接続基板は従来の基板に比べて、微細、且つ厚膜でありながら、接続部分の拡散防止金属層により線間のギャップが狭くなることなく、拡散防止層によりマイグレーションがない信頼性の高い基板であり、また表面の凸がないので異方導電性シートによる接続においても信頼性の高いものである。従って、高密度のLSIや液晶の実装が可能である。
また本発明の方法によれば上記の微細厚膜接続基板が短い工程で製造可能となり、低コストな接続基板を供給することができる。
【図面の簡単な説明】
【図1】本発明の微細厚膜接続基板の断面図を示す。
【図2】従来の接続基板の断面図を示す。
【図3】アルミ基板にジンケート処理を行った後ドライフィルムレジストを形成した断面図である。
【図4】更にNiメッキと銅メッキを行い、配線ピッチの1/2倍以上の厚みの導体を形成した断面図である。
【図5】アルミ基板の導体を形成した側の面を内側にしてプリプレグで接着した断面図である。
【図6】アルミ基板をエッチングした後、表面に出たNi層の上に金メッキをした断面図である。
【符号の説明】
1 銅(パターン)
2 絶縁層
3 Ni(またはNi−PまたはNi−B)層
4 Au層
5 アルミ基板
6 ドライフィルムレジスト(パターン形成後)
7 ジンケート層
8 Ni層
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal or LSI mounting board / connection component having a high wiring density and a method for manufacturing the same.
[0002]
[Prior art]
Generally, an LCD chip is mounted on the surface of a liquid crystal drive circuit board, and the board and LSI are connected by wire bonding, or an LSI chip on which bumps are two-dimensionally arranged is mounted face-down on the board, and the other connection terminals of the board The portion is connected to the terminal portion of the liquid crystal substrate with an anisotropic conductive sheet (ACF). Here, with the advent of liquid crystal VGA and S-VGA, a higher-density mounting substrate is required. On the other hand, since the connection terminals are laid out one-dimensionally on the four outer sides of the chip, the degree of integration of the LSI It does not go up and hinders cost reduction.
[0003]
Also, when connecting with an anisotropic conductive sheet, if the conductor is convex from the substrate surface, the protrusions protruding from both surfaces to be connected will be staggered and short-circuited. Therefore, it is necessary for such a substrate to flatten either one of the substrate surfaces. Therefore, there is a strong demand for a substrate having a high wiring density and a structure in which no conductor protrudes from the substrate surface.
[0004]
[Problems to be solved by the invention]
Conventionally, such a connection substrate has been made by an etching method. However, as the wiring density increases, a so-called plating method, that is, a method of forming a conductor at a necessary place by plating has become effective. In particular, the method of forming a wiring board by forming a resist on a conductive substrate, forming a conductor by performing electroplating with the substrate as a cathode, and then bonding together with a prepreg with the plated surface facing inward, and removing the conductive substrate It is valid. According to this method, the shape of the conductor is controlled by the resist wall, and even if the wiring density is high, the thickness can be increased, and as a result, the circuit resistance can be reduced. Moreover, since no conductor protrudes from the surface of the substrate, ACF connection is also good.
[0005]
However, in such a substrate, the connection portion needs to be plated with gold in order to improve connection reliability by wire bonding or ACF. The gold plating layer diffuses with the underlying copper, and the gold layer disappears from the surface due to heat and neglect. Therefore, in general, after a diffusion preventing film such as Ni or an alloy thereof is drawn on copper, gold plating is performed.
However, even if the surface becomes flat, if Ni plating is further performed, the surface becomes convex because of this, and at the same time, the space between the lines becomes narrow (see FIG. 2). As a result, the following problems occur.
[0006]
(1) On a high wiring density substrate, if Ni plating is performed, for example, by 5 μm (a general thickness as a base for gold plating), the distance between the lines becomes almost twice that of 10 μm. This is because Ni plating is particularly smooth and has the property of spreading as much as or more than the thickness. Accordingly, the insulation between lines is lowered. Further, a convex portion of about 5 μm is formed on the surface, which becomes a problem in ACF connection at a fine pitch.
{Circle around (2)} If a convex portion is formed on the surface, various treatments cause the treatment liquid to remain on the convex portion and cause migration. In addition, migration increases because the surface area of the circuit pattern exposed to the environmental atmosphere increases.
[0007]
[Means for Solving the Problems]
Therefore, in order to solve the above problems, the present invention provides a fine-thick film connection substrate having a wiring pitch of 80 μm or less at least at one place and a conductor thickness at that place being ½ or more of the wiring pitch. A portion not contacting the insulating material is covered with a first metal layer capable of preventing the diffusion of gold, and the conductor pattern including the first metal layer is embedded in the same insulating material. The second metal layer made of gold or an alloy thereof is formed on a part of the surface of the substrate, and the diffusion barrier metal is Ni, Ti, W or The fine thick film connection substrate, characterized in that it is an alloy thereof, or an alloy containing any one of them, and the diffusion preventing metal is Ni-P or Ni-B. Provide board Is shall.
[0008]
In order to solve the above problems, a step of forming a resist circuit pattern on the conductive substrate, a step of plating a diffusion preventing metal on the surface of the substrate on which the resist is not formed, and further forming a circuit pattern of the conductive substrate Plating the surface with a conductive metal to form a conductor pattern having a thickness of 1/2 or more of the pitch, removing the resist, and forming the conductor pattern inside, the substrates between each other, or an insulating substrate A method for producing a fine thick film connecting substrate comprising a step of adhering to both or one side of the substrate and a step of dissolving and removing the substrate, a step of performing a zincate treatment on a substrate made of aluminum or an alloy thereof, and an alkali A step of forming a circuit pattern of a development type dry film resist, and Ni or Ni-P or The step of plating i-B and the surface of the conductive substrate on which the circuit pattern is formed are subjected to acidic electrolytic copper plating, and copper having a thickness more than 1/2 times the pitch of the highest wiring density in the substrate is formed. A fine process comprising a step of forming, a step of removing the dry film resist, a step of bonding the substrates with the formed conductive pattern on the inside, or adhering to both or one side of an insulating substrate, and a step of dissolving and removing the substrate A method of manufacturing a thick film connection substrate is provided.
[0009]
[Action]
In the present invention, a gold diffusion prevention layer, which is a surface protective metal for connection, is embedded in a substrate insulating layer including a Ni plating layer, for example, so that insulation between lines can be prevented and the surface is prevented from diffusion. By smoothing including the layers, it is possible to eliminate the residual treatment liquid that causes copper migration and the surface area of the circuit pattern exposed to the environmental atmosphere, thereby improving the reliability.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be specifically described with reference to examples.
A substrate made of aluminum or an alloy thereof is used as the conductive substrate of the present invention. Since the surface property of the substrate greatly affects the surface property of the final product, a substrate having a mirror surface as much as possible is preferable. The thickness of the substrate can be freely selected, but generally 10 μm to 200 μm is preferable. If it is too thin, wrinkles and scratches are likely to occur during handling, and the resistance increases and the uniformity of the electrolytic plating is impaired.
Further, the purity of aluminum is preferably 99% or more, preferably 1N30 or more according to the so-called JIS standard of 99.6% or more. If the purity is too low, uniformity in plating and unevenness in substrate etching occur.
[0011]
The resist used in the present invention is resistant to chemicals after the resist process, has a thickness of about the required conductor thickness, and can obtain a necessary resolving power at that thickness, but generally has a high resolving power. A dry film resist is preferable from the viewpoint of workability. Further, among dry films, an alkali development type dry film is preferable in view of environmental measures and ease of peeling.
Next, when forming a circuit pattern of an alkali development type dry film resist, the substrate is replaced with zinc prior to the resist process in order to further improve the adhesion of the dry film resist and prevent light reflection during mask exposure from the substrate surface. It is better to perform plating, so-called zincate treatment. This makes it possible to form a resist having a high aspect necessary for plating a fine and thick conductor, that is, a resist having a narrow width and a large thickness (see FIG. 3). The resist thickness depends on the resolution of the resist and the surface state of the zincate base, but is preferably equal to or greater than the thickness of the conductor to be finally obtained.
[0012]
The first metal layer is formed by plating a diffusion preventing metal on the surface of the substrate on which no resist is formed. As the diffusion preventing metal, any one of Ni, Ti, W, or an alloy thereof, or an alloy containing any one of them is used, and Ni or its alloys Ni-P and Ni-B are particularly preferable from the viewpoint of diffusion preventing characteristics and economy. Is preferred. This Ni (or Ni alloy) layer serves as a barrier layer that prevents the acid resistance of the aluminum substrate, while protecting the substrate from acid copper plating, which is a subsequent process, and preventing copper migration from the substrate in the final product. There is an effect of preventing protrusion from the substrate surface.
The plating of the diffusion preventing metal may be electrolytic plating or electroless plating, but electroless plating is particularly advantageous in terms of equipment. Here, any plating solution may be used. However, since the dry film resist dissolves when it is alkaline, a neutral or acidic plating solution is desirable. Further, considering the dissolution of the base material in the plating solution, it is desirable that it is close to neutrality. In this respect, Ni or an alloy thereof is preferable because there are many plating solutions close to the neutral region.
[0013]
Next, the main second metal layer of the conductor pattern is formed. As the conductor pattern, a conductive material such as copper, copper alloy, copper silver alloy or the like is used, and the conductor thickness is preferably 1/2 or more of the wiring pitch. For example, acidic electrolytic copper plating is performed on the surface of the conductive substrate on which the circuit pattern is formed using the substrate as a cathode, thereby forming copper having a thickness of 1/2 times or more the minimum pitch in the substrate (see FIG. 4). Further, when the plating thickness is thin, the circuit resistance of the formed substrate increases, and when used in a liquid crystal driving circuit, the S / N ratio of the screen decreases. Moreover, the frequency which can be transmitted falls by circuit resistance becoming high.
In the case of performing acidic copper plating, the resist is dissolved by an alkaline copper plating solution. Therefore, copper sulfate plating that can form good quality copper at low cost by selecting a good additive is preferable.
After the plating is finished, the dry film resist is removed. Generally, caustic soda is used.
[0014]
Next, the formed conductor pattern is used as an inner side, and the substrates are bonded to each other or both surfaces or one surface of the insulating substrate by using an adhesive (see FIG. 5). A commonly used prepreg or an adhesive sheet (in this case, the sheet may have an adhesive on both sides of the base film or may be an adhesive only) may be used.
The adhesive used here becomes an insulating material after curing. Moreover, it becomes an insulating material including the base film which has the adhesive agent on both surfaces of the base film.
Next, the substrate is dissolved and removed. As the solution to be dissolved, a solution having a sufficiently high speed for dissolving the conductive substrate than the speed for dissolving the conductor pattern and the diffusion preventing metal is selected. For example, if the conductor pattern is copper, the diffusion preventing metal is Ni, and the substrate is aluminum, about 10% hydrochloric acid is preferable.
[0015]
Finally, gold plating is performed as necessary (see FIG. 6). Actually, the lands used for bonding are plated with gold. This may be any gold plating process usually performed on Ni plating, but the plating thickness is usually 1 μm or less. Further, from the viewpoint of cost, if there is an unnecessary part before gold plating, the unnecessary part may be coated with a gold-resistant plating resist.
The conductor pattern of the fine thick film connecting substrate obtained by the manufacturing method of the present invention is embedded in the same insulating material including the diffusion prevention metal layer described above, and the surface is smooth, and therefore, the surface is contaminated. Since there is no migration, it becomes a fine thick film connection substrate without migration (see FIG. 1). Hereinafter, although an Example is given, this invention is not limited to these.
[0016]
[Example 1]
The surface aluminum foil with a thickness of 150 μm and a purity standard of 1N30 was treated with a solution obtained by diluting Uemura Kogyo Co., Ltd. zincate solution (AZ-401-3X) three times at a liquid temperature of 30 ° C. for 80 seconds. After washing with water, it was washed with 15% nitric acid for 20 seconds, treated again with the zincate solution at a temperature of 30 ° C. for 80 seconds, and then washed with water.
Next, dry film resist (SPG-201, thickness 20 μm) manufactured by Asahi Kasei Kogyo Co., Ltd. is laminated, and a mask pattern with a line pitch of 50 μm, a line width of 25 μm (width from which the resist is removed), and a line pattern of 25 μm is exposed with an exposure device. And developed.
The obtained substrate was Ni-P electroplating solution manufactured by Okuno Pharmaceutical Co., Ltd., trademark Nickelin bath (L Nickelin D 200 cc / liter, nickel sulfate 150 g / liter, sodium chloride 30 g / liter), liquid temperature 60 ° C., 8 minutes. Plating was performed to form a Ni—P layer of about 5 μm. Next, 30 μm of copper was plated with a copper sulfate plating solution to form a pattern with a pitch of 50 μm, a line width of 25 μm, and a pattern thickness of 35 μm.
[0017]
Next, the dry film resist was removed with 3% caustic soda, and the substrate obtained above was bonded through a prepreg manufactured by Hitachi Chemical Co., Ltd. (GEA-67N KLN) with the side having the copper plating pattern inside. Next, the aluminum substrate was dissolved and removed with 10% hydrochloric acid.
Since the portion of the obtained substrate that is exposed on the surface of the circuit pattern is covered with Ni-P, the replacement plating is directly performed thereon with a replacement-type electroless gold plating solution (trademark manufactured by N.E. Chemcat Co., Ltd.). Thereafter, a total of about 0.5 μm of gold was deposited using an autocatalytic electroless plating solution (trade name Super Mex # 600 manufactured by N.E. Chemcat Co., Ltd.).
The obtained substrate had a wiring density of 50 μm, a conductor thickness of 35 μm, and the surface was covered with Ni—P 5 μm + gold 0.5 μm. There were no defects in 150 100 mm × 30 mm substrates, and 50 V was applied between the lines at 60 ° C. There was no change in insulation between lines even after 1000 hours in a 90-95% environment.
[0018]
[Example 2]
A surface aluminum foil with a thickness of 80 μm and a purity standard of 1N30 was treated with a solution obtained by diluting a 3-fold zincate solution (AZ-401-3X) manufactured by Uemura Kogyo Co., Ltd. at a liquid temperature of 30 ° C. for 80 seconds. After washing with water, it was washed with 15% nitric acid for 20 seconds, treated again with the zincate solution at a liquid temperature of 30 ° C. for 80 seconds, and then washed with water.
Next, dry film resist (SPG-201, thickness 20 μm) manufactured by Asahi Kasei Kogyo Co., Ltd. is laminated, and a mask pattern having a line pitch of 26 μm, a line width of 13 μm (width from which the resist is removed) and a line spacing of 13 μm is exposed with an exposure device. And developed.
The obtained substrate was treated with Ni electroless plating solution (ICP-Nicolon U) manufactured by Okuno Pharmaceutical Co., Ltd. at 85 ° C. to form about 2 μm of Ni—P. Next, 15 μm of copper was plated with a copper sulfate plating solution to form a pattern with a pitch of 26 μm, a line width of 13 μm, and a pattern thickness of 17 μm.
[0019]
Next, the dry film resist was removed with 3% caustic soda, and the surface of the polyimide film (50 μm thickness) manufactured by Toray DuPont Co., Ltd. was used. The substrate obtained above was bonded with the side having the copper plating pattern inside. Next, the aluminum substrate was dissolved and removed with 10% hydrochloric acid.
[0020]
Since the portion of the obtained substrate that is exposed on the surface of the circuit pattern is covered with Ni-P, a direct replacement type electroless gold plating solution (trade name Super Mex # 200 manufactured by N.E. About 0.1 μm gold was deposited.
The obtained substrate had a wiring pitch of 26 μm, a conductor thickness of 17 μm, and the surface was covered with Ni—P 2 μm + gold 0.1 μm. There were no defects in 150 substrates of 80 mm × 15 mm, and 25 V was applied between the lines at 60 ° C. There was no change in insulation between lines even after 1000 hours in a 90-95% environment.
[0021]
[Example 3]
A surface aluminum foil with a thickness of 80 μm and a purity standard of 1N30 was treated with a solution obtained by diluting a 3-fold zincate solution (AZ-401-3X) manufactured by Uemura Kogyo Co., Ltd. at a liquid temperature of 30 ° C. for 80 seconds. After washing with water, it was washed with 15% nitric acid for 20 seconds, treated again with the zincate solution at a liquid temperature of 30 ° C. for 80 seconds, and then washed with water.
Next, dry film resist (SPG-201, thickness 20 μm) manufactured by Asahi Kasei Kogyo Co., Ltd. is laminated, and a mask pattern having a line pitch of 26 μm, a line width of 13 μm (width from which the resist is removed) and a line spacing of 13 μm is exposed with an exposure device. And developed.
The obtained substrate was treated with Ni-B electroless plating solution (Top Chemialoy B-1) manufactured by Okuno Pharmaceutical Co., Ltd. at a liquid temperature of 65 ° C. to form about 2 μm of Ni-B.
[0022]
Next, 15 μm of copper was plated with a copper sulfate plating solution to form a pattern with a pitch of 26 μm, a line width of 13 μm, and a pattern thickness of 17 μm.
Next, the dry film resist was removed with 3% caustic soda, and the surface of the polyimide film (50 μm thickness) manufactured by Toray DuPont Co., Ltd. was used. The substrate obtained above was bonded with the side having the copper plating pattern inside. Next, the aluminum substrate was dissolved and removed with 10% hydrochloric acid.
[0023]
Since the obtained substrate is covered with Ni-B at the surface of the circuit pattern, it is directly replaced with an electroless gold plating solution (trade name Super Mex # 200 manufactured by N.E. Chemcat Co., Ltd.). About 0.1 μm gold was deposited.
The obtained substrate had a wiring pitch of 26 μm, a conductor thickness of 17 μm, and the surface was covered with Ni—B 2 μm + gold 0.1 μm. There were no defects in 150 substrates of 80 mm × 15 mm, and 25 V was applied between the lines at 60 ° C. There was no change in insulation between lines even after 1000 hours in a 90-95% environment.
[0024]
[Comparative Example 1]
The surface aluminum foil with a thickness of 150 μm and a purity standard of 1N30 was treated with a solution obtained by diluting Uemura Kogyo Co., Ltd. zincate solution (AZ-401-3X) three times at a liquid temperature of 30 ° C. for 80 seconds. After washing with water, it was washed with 15% nitric acid for 20 seconds, again treated with the zincate solution at a liquid temperature of 30 ° C. for 80 seconds, and then washed with water.
Next, dry film resist (SPG-201, thickness 20 μm) manufactured by Asahi Kasei Kogyo Co., Ltd. is laminated, and a mask pattern having a line pitch of 50 μm, a line width of 25 μm (width from which the resist is removed), and a line spacing of 25 μm is exposed with an exposure device. And developed.
About 2 μm of copper was formed on the obtained substrate by copper pyrophosphate plating. At this time, partial peeling was observed on the dry film.
[0025]
Next, 33 μm of copper was plated with a copper sulfate plating solution to form a pattern with a pitch of 50 μm, a line width of 25 μm, and a pattern thickness of 35 μm.
Next, the dry film resist was removed with 3% caustic soda, and the substrate obtained above was bonded through a prepreg manufactured by Hitachi Chemical Co., Ltd. (GEA-67N KLN) with the side having the copper plating pattern inside.
Next, the aluminum substrate was dissolved and removed with 10% hydrochloric acid. Since the obtained substrate is copper on the surface of the circuit pattern, the surface is washed with 10% sulfuric acid, and then Ni electrolytic plating Watt bath is used. Luminous nickel # 66 process manufactured by Ebara Eugene Corporation (additive is # 610) , # 62, # 63, a bath solution containing a predetermined amount of Ni), and 5 μm of Ni was formed.
Further, about 0.5 μm of gold was deposited directly thereon by an electrolytic gold plating solution (ECF-68 manufactured by N.E. Chemcat Co., Ltd.).
[0026]
The obtained substrate has a wiring pitch of 50 μm, a conductor thickness of 35 μm, and an average line gap of 10 μm. However, depending on the substrate, there are many short-circuited parts that are thought to be due to dry film peeling, and there are places where the line gap appears to be 0 μm. there were. There are 93 defects in 150 substrates of 100 mm x 30 mm. The remaining 77 non-defective products were subjected to 50 V between the lines and left to stand for 1000 hours in an environment of 60 ° C. and 90 to 95%. Eight sheets had poor insulation.
[0027]
【The invention's effect】
The fine thick film connection substrate of the present invention is finer and thicker than the conventional substrate, but the gap between the lines is not narrowed by the diffusion prevention metal layer of the connection portion, and there is no migration by the diffusion prevention layer. It is a highly reliable substrate, and since there is no projection on the surface, it is also highly reliable in connection with an anisotropic conductive sheet. Therefore, high-density LSI and liquid crystal can be mounted.
Further, according to the method of the present invention, the above-mentioned fine thick film connection substrate can be manufactured in a short process, and a low-cost connection substrate can be supplied.
[Brief description of the drawings]
FIG. 1 shows a cross-sectional view of a fine thick film connecting substrate of the present invention.
FIG. 2 is a cross-sectional view of a conventional connection substrate.
FIG. 3 is a cross-sectional view in which a dry film resist is formed after a zincate treatment is performed on an aluminum substrate.
FIG. 4 is a cross-sectional view in which Ni plating and copper plating are further performed to form a conductor having a thickness of ½ times or more the wiring pitch.
FIG. 5 is a cross-sectional view of an aluminum substrate bonded with a prepreg with the surface on which the conductor is formed facing inward.
FIG. 6 is a cross-sectional view in which gold plating is formed on a Ni layer exposed on the surface after etching an aluminum substrate.
[Explanation of symbols]
1 Copper (pattern)
2 Insulating layer 3 Ni (or Ni-P or Ni-B) layer 4 Au layer 5 Aluminum substrate 6 Dry film resist (after pattern formation)
7 Jincate layer 8 Ni layer

Claims (2)

少なくとも1カ所以上配線ピッチが80μm以下で、その箇所の導体厚みが配線ピッチの1/2以上である導体パターン、絶縁材料、該導体パターンの該絶縁材料と接触していない部分を覆う金の拡散を防止できる第1の金属層、及び該第1の金属層の表面を覆う金またはその合金からなる第2の金属層を有する微細厚膜接続基板の製造方法であって、
アルミまたはその合金からなる導電性基板にレジストの回路パターンを形成する工程と、レジストの形成されていない基板表面にNiまたはNi−PまたはNi−Bからなる第1の金属層をメッキする工程と、更に導電性基板の回路パターンを形成した面に銅、銅合金、及び銅銀合金からなる群から選択されるいずれかからなる導体パターンを形成する工程と、レジストを除去する工程と、形成された導体パターンを内側にして導電性基板どうし、または導電性基板を絶縁基板の両面または片面に接着剤を用いて接着する工程と、導電性基板を溶解除去する工程と、接合に使われるランドに金メッキをする工程とからなる微細厚膜接続基板の製造方法。
Diffusion of gold covering a conductor pattern, an insulating material, and a portion of the conductor pattern that is not in contact with the insulating material, wherein the wiring pitch is 80 μm or less at least at one place or more and the conductor thickness at that place is ½ or more of the wiring pitch A method for producing a fine thick film connecting substrate having a first metal layer capable of preventing the above and a second metal layer made of gold or an alloy thereof covering the surface of the first metal layer,
Forming a resist circuit pattern on a conductive substrate made of aluminum or an alloy thereof, and plating a first metal layer made of Ni, Ni-P, or Ni-B on a substrate surface on which no resist is formed; And a step of forming a conductive pattern selected from the group consisting of copper, copper alloy, and copper silver alloy on the surface of the conductive substrate on which the circuit pattern is formed , and a step of removing the resist. conductive substrate each other the conductor pattern in the inside over, or a step of adhering with a conductive substrate adhesive on both surfaces or one surface of an insulating substrate, a step of dissolving and removing the conductive substrate, the land used for joining A method for manufacturing a fine thick film connecting substrate comprising a step of gold plating .
少なくとも1カ所以上配線ピッチが80μm以下で、その箇所の導体厚みが配線ピッチの1/2以上である導体パターン、絶縁材料、該導体パターンの該絶縁材料と接触していない部分を覆う金の拡散を防止できる第1の金属層、及び該第1の金属層の表面を覆う金またはその合金からなる第2の金属層を有する微細厚膜接続基板の製造方法であって、
アルミまたはその合金からなる導電性基板にジンケート処理を行う工程と、アルカリ現像タイプドライフィルムレジストの回路パターンを形成する工程と、レジストの形成されていない基板表面にNiまたはNi−PまたはNi−Bからなる第1の金属層をメッキする工程と、更に導電性基板の回路パターンを形成した面に酸性電解銅メッキを行い銅からなる導体パターンを形成する工程と、前記ドライフィルムレジストを除去する工程と、形成された導体パターンを内側にして導電性基板どうしまたは導電性基板を絶縁基板の両面もしくは片面に接着剤を用いて接着する工程と、導電性基板を溶解除去する工程と、接合に使われるランドに金メッキをする工程とからなる微細厚膜接続基板の製造方法。
Diffusion of gold covering a conductor pattern, an insulating material, and a portion of the conductor pattern that is not in contact with the insulating material, wherein the wiring pitch is 80 μm or less at least at one place or more and the conductor thickness at that place is ½ or more of the wiring pitch A method for producing a fine thick film connecting substrate having a first metal layer capable of preventing the above and a second metal layer made of gold or an alloy thereof covering the surface of the first metal layer,
A step of performing a zincate process on a conductive substrate made of aluminum or an alloy thereof, a step of forming a circuit pattern of an alkali development type dry film resist, and Ni, Ni-P, or Ni-B on a substrate surface on which no resist is formed A step of plating the first metal layer comprising: a step of forming a conductive pattern of copper by performing acidic electrolytic copper plating on the surface of the conductive substrate on which the circuit pattern is formed; and a step of removing the dry film resist And a process of bonding conductive substrates or conductive substrates to both or one side of an insulating substrate with an adhesive with the formed conductor pattern inside, a step of dissolving and removing the conductive substrate, and bonding. A method for manufacturing a fine thick film connecting substrate comprising a step of gold-plating a land .
JP00217996A 1996-01-10 1996-01-10 Fine thick-film connection substrate and manufacturing method thereof Expired - Lifetime JP3732266B2 (en)

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JP2006344920A (en) * 2005-05-10 2006-12-21 Hitachi Chem Co Ltd Printed circuit board, manufacturing method therefor, semiconductor chip mounting substrate, manufacturing method therefor, and semiconductor package
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JP2886317B2 (en) * 1990-10-05 1999-04-26 富士通株式会社 Wiring board and method of manufacturing the same
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