JPH01195285A - Production of metallized glass substrate - Google Patents
Production of metallized glass substrateInfo
- Publication number
- JPH01195285A JPH01195285A JP1717388A JP1717388A JPH01195285A JP H01195285 A JPH01195285 A JP H01195285A JP 1717388 A JP1717388 A JP 1717388A JP 1717388 A JP1717388 A JP 1717388A JP H01195285 A JPH01195285 A JP H01195285A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- glass substrate
- ito
- metallized
- display device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 24
- 239000011521 glass Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000007772 electroless plating Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 8
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 claims description 5
- 238000006467 substitution reaction Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 229910018104 Ni-P Inorganic materials 0.000 abstract 2
- 229910018536 Ni—P Inorganic materials 0.000 abstract 2
- 239000013078 crystal Substances 0.000 abstract 2
- 238000010030 laminating Methods 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910001887 tin oxide Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000011651 chromium Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000005401 electroluminescence Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/032—Materials
- H05K2201/0326—Inorganic, non-metallic conductor, e.g. indium-tin oxide [ITO]
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Optics & Photonics (AREA)
- Non-Insulated Conductors (AREA)
- Manufacturing Of Electric Cables (AREA)
- Liquid Crystal (AREA)
- Chemically Coating (AREA)
- Chemical Vapour Deposition (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
し産業上の利用分野］
本発明は表示装置に関し、特に表示装置駆動に用いる導
電層パターンをその上に搭載したメタライズガラス基板
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application] The present invention relates to a display device, and more particularly to a method for manufacturing a metallized glass substrate on which a conductive layer pattern used for driving a display device is mounted.
［従来の技術］
液晶（ＬＣ）、エレクトロルミネッセンス（ＥＬ）など
の表示素子をガラス基板上に形成し、さらに表示素子を
駆動する駆動回路もガラス基板上に搭載する場合、ガラ
ス基板上にメタライズ層が必要とされる。たとえば駆動
用半導体ＩＣチップをガラス基板上に搭載したチップオ
ングラス構造では、チップのボンディング用およびリー
ド線のボンディング用のメタライズ領域が必要である。[Prior Art] When display elements such as liquid crystal (LC) and electroluminescence (EL) are formed on a glass substrate and a drive circuit for driving the display elements is also mounted on the glass substrate, a metallized layer is formed on the glass substrate. is required. For example, in a chip-on-glass structure in which a driving semiconductor IC chip is mounted on a glass substrate, metallized regions are required for chip bonding and lead wire bonding.
第３図に従来のメタライズ横道の例を示す、ガラス基板
１の全面にシリコン酸化物（Ｓ ｉＯ２）層１２が形成
され、その上にインジウムｌ！Ｗｆｌ化物（ＩＴＯ）層
１３．クローム（Ｃｒ）層１４が形成され、その上にア
ルミニウノ、（Ａ Ｉ ） 、ニッケル（Ｎｉ）又は金
（Ａ’ＬＩ）等からなる導電性金属層１５が形成されて
いる。 ３１０２層＋２．ＩＴＯ層！３はＣＶＤなとの
ドライプロセスで、Ｃｒ層１４．導電性金属層１５は蒸
着などのドライプロセスで基板上全面に形成し、膜形成
後エツチングでパターン化を行って所望のメタライズパ
ターンを得る。FIG. 3 shows an example of a conventional metallization lateral. A silicon oxide (SiO2) layer 12 is formed on the entire surface of a glass substrate 1, and indium l! Wflide (ITO) layer 13. A chromium (Cr) layer 14 is formed, and a conductive metal layer 15 made of aluminum UNO, (AI), nickel (Ni), gold (A'LI), etc. is formed thereon. 3102 layers +2. ITO layer! 3 is a dry process such as CVD to form a Cr layer 14. The conductive metal layer 15 is formed on the entire surface of the substrate by a dry process such as vapor deposition, and after the film is formed, it is patterned by etching to obtain a desired metallized pattern.
［発明が解決しようとする問題点］
これらのドライプロセスを大きなガラス基板上で行おう
とすると装置が大型化して制御が難しくなり、コスｌへ
も高くなる。[Problems to be Solved by the Invention] If these dry processes are attempted to be performed on a large glass substrate, the apparatus will become large and difficult to control, and the cost will also increase.
さらに微細パターン等を実現しようとするとマスク用の
アライメント露光の工程等が必要となり。In order to realize even finer patterns, a mask alignment exposure process is required.
製造プロセスが複雑化する。Manufacturing processes become more complex.
［問題点を解決するための手段］
カラス基板上に選択的にメタライズ層を形成するため、
無電解メッキできる銅（Ｃｕ）層、ニッケル燐（Ｎｉ−
Ｐ））ｔＪを採用した。ガラス基板上にインジウム錫酸
化物（ＩＴＯ）膜を形成し、パターン付けした後、＠電
解メッキを行うことで選択的メタライズ層が形成できる
。さらにその上に置換反応によって膜形成した金（Ａｕ
）層を備えることもできる。[Means for solving the problem] In order to selectively form a metallized layer on a glass substrate,
Copper (Cu) layer that can be plated electrolessly, nickel phosphorus (Ni-
P))tJ was adopted. A selective metallization layer can be formed by forming an indium tin oxide (ITO) film on a glass substrate, patterning it, and then performing @electrolytic plating. Furthermore, a gold (Au) film was formed on top of it by a substitution reaction.
) layer.
［作用］
パターン付けしたＩＴＯ層の上には銅層が選択的に無電
解メッキでき、その上にはニッケル燐層が選択的に無電
解メッキできる。このようにウェットプロセスで下地と
なるＩＴｏＫ４のパターンに自己整合したメタライズ層
が形成できる。[Function] A copper layer can be selectively electrolessly plated on the patterned ITO layer, and a nickel phosphorous layer can be selectively plated electrolessly thereon. In this way, a metallized layer that is self-aligned to the underlying IToK4 pattern can be formed by the wet process.
［実施例］
第１図に本発明の１実施例による表示装置用メタライズ
ガラス基板を示す、ガラス基板１上にパターン付けした
インジウム錫酸化物層３が形成されている０表示部Ａで
はインジウムｆ′９Ｊ酸化物層３を電極として液晶、Ｅ
Ｌ等の表示素子が形成されている。駆動部Ｂではインジ
ウム錫酸化物層３の上にメタライズ層４，５．６が形成
されている。[Example] FIG. 1 shows a metallized glass substrate for a display device according to an example of the present invention. In the display area A where a patterned indium tin oxide layer 3 is formed on the glass substrate 1, indium f '9J Liquid crystal using oxide layer 3 as an electrode, E
Display elements such as L are formed. In the drive section B, metallized layers 4, 5.6 are formed on the indium tin oxide layer 3.
ＩＣチップ１０が中央のメタライズ前５にボンディング
され、ＩＣチップ１０からのリード線７゜８が左右のメ
タライズ層４．６にボンディングされている。メタライ
ズ層４は表示部Ａに駆動電流を供給する。An IC chip 10 is bonded to the central metallized layer 5, and lead wires 7.8 from the IC chip 10 are bonded to the left and right metallized layers 4.6. The metallized layer 4 supplies the display section A with a driving current.
第２図に駆動部Ｂのメタライズ層の構成をより詳細に示
す、ガラス基板１上にシリコン酸化物（Ｓｉ０２）層２
が全面に形成されており、その上にインジウム錫酸化物
（ＩＴＯ）層３．銅（ＣＵ）層９．ニッケル燐（Ｎｉ−
Ｐ）層１０．金（Ａｕ）層１１がパターン状に積層され
てボンディングメタル層を形成している。Ｃｕ層９．Ｎ
１−２層１０は無電解メッキによりＩＴＯ層３上に選択
的に形成され、Ａｕ層１１は置換反応によってＮ１−Ｐ
層１０上に選択的に形成される。FIG. 2 shows the structure of the metallized layer of the driving part B in more detail.
is formed on the entire surface, and an indium tin oxide (ITO) layer 3. is formed on the entire surface. Copper (CU) layer 9. Nickel phosphorus (Ni-
P) Layer 10. Gold (Au) layers 11 are laminated in a pattern to form a bonding metal layer. Cu layer9. N
The 1-2 layer 10 is selectively formed on the ITO layer 3 by electroless plating, and the Au layer 11 is formed by N1-P by a substitution reaction.
selectively formed on layer 10;
表示部のＩＴＯの上に堆積するメタライズ層はメタライ
ズメロセス後フォトエツチングにより除去する。又はメ
タライズ前に表示部をホトレジストでコーＩ・シ、メタ
ライズプロセス後レジスト層をリフトオフしてもよい。The metallized layer deposited on the ITO in the display area is removed by photoetching after metallization process. Alternatively, the display portion may be coated with photoresist before metallization, and the resist layer may be lifted off after the metallization process.
このようにして、低抵抗でボンディング可能なリードお
よびボンディングメタルを実現できる。In this way, a lead and a bonding metal that can be bonded with low resistance can be realized.
１例としてワイヤボンディングの例を示したがその他フ
リッグチップ方式、タブ（ＴＡＢ）方式等に適用可能で
ある。Although wire bonding is shown as an example, it is also applicable to other methods such as a frig chip method and a tab (TAB) method.
ガラス基板１上の５ｉＯ９層２は省略してもよい。The 5iO9 layer 2 on the glass substrate 1 may be omitted.
［発明の効果］
無電解メッキを利用できるため、大型でかつ均一なメタ
ライズパターンを容易に低コストで形成できる。[Effects of the Invention] Since electroless plating can be used, a large and uniform metallized pattern can be easily formed at low cost.
また、ＩＴＯ上にのみ選択的にメッキできるため、材料
の無駄を削減できる。Furthermore, since selective plating can be performed only on ITO, material waste can be reduced.
なお、精度を要するアライメント露光を行うことなく、
パターン付けしたメタライズ層が容易に得られる。In addition, without performing alignment exposure that requires precision,
Patterned metallized layers are easily obtained.
第１図は本発明の１実施例による表示装置の部分断面図
、第２図は第１図駆動部のメタライズ補遺の拡大図、第
３図は従来技術によるメタライズガラス基板の例の断面
図である
符号の説明
１ ガラス基板
Ａ 表示部
Ｂ 駆動部
２ シリコン酸化物層
３ インジウムｊ！酸化物層９
＃１層
１０ ニッケル燐層
１１ 金層FIG. 1 is a partial cross-sectional view of a display device according to an embodiment of the present invention, FIG. 2 is an enlarged view of the metallized supplement of the drive unit shown in FIG. 1, and FIG. 3 is a cross-sectional view of an example of a metallized glass substrate according to the prior art. Explanation of certain symbols 1 Glass substrate A Display section B Drive section 2 Silicon oxide layer 3 Indium j! Oxide layer 9
#1 layer 10 Nickel phosphorus layer 11 Gold layer
Claims (2)
ズガラス基板の製造方法であつて，ガラス基板上にイン
ジウム錫酸化物層を選択的に形成する工程とインジウム
錫酸化物層の上に銅層とニッケル燐層とを無電解メッキ
で形成する工程とを含むことを特徴とするメタライズガ
ラス基板の製造方法。(1) A method for manufacturing a metallized glass substrate that constitutes a display device and mounts a drive circuit, which includes the step of selectively forming an indium tin oxide layer on the glass substrate and the step of selectively forming an indium tin oxide layer on the indium tin oxide layer. 1. A method for producing a metallized glass substrate, comprising the step of forming a layer and a nickel phosphorus layer by electroless plating.
板の製造方法であって，さらにニッケル燐層の上に金層
を置換反応によって形成する工程を含むことを特徴とす
るメタライズガラス基板の製造方法。(2) A method for manufacturing a metallized glass substrate according to claim 1, further comprising the step of forming a gold layer on the nickel phosphorus layer by a substitution reaction. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1717388A JPH01195285A (en) | 1988-01-29 | 1988-01-29 | Production of metallized glass substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1717388A JPH01195285A (en) | 1988-01-29 | 1988-01-29 | Production of metallized glass substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01195285A true JPH01195285A (en) | 1989-08-07 |
Family
ID=11936563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1717388A Pending JPH01195285A (en) | 1988-01-29 | 1988-01-29 | Production of metallized glass substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01195285A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03183781A (en) * | 1989-08-14 | 1991-08-09 | Saint Gobain Vitrage Internatl | Method and device for forming thin membrane |
| JPH03236477A (en) * | 1990-02-13 | 1991-10-22 | Optrex Corp | Partial electroless-plating method, electro-optical device and its production |
| JPH03239226A (en) * | 1990-02-16 | 1991-10-24 | Sanyo Electric Co Ltd | Liquid crystal display device |
| JPH04212934A (en) * | 1990-10-31 | 1992-08-04 | Ricoh Co Ltd | Liquid crystal display device |
| JPH06110073A (en) * | 1992-09-30 | 1994-04-22 | Kyocera Corp | Terminal lead-out structure of display element |
| JPH09191164A (en) * | 1996-01-10 | 1997-07-22 | Asahi Chem Ind Co Ltd | Fine thick film connection substrate and its manufacturing method |
| JPH1069229A (en) * | 1996-08-28 | 1998-03-10 | Kyocera Corp | Production of display element |
| JP2018115382A (en) * | 2017-01-20 | 2018-07-26 | 大日本印刷株式会社 | Light control film, method for manufacturing the same, laminate and method for manufacturing conductive plated layer |
| CN109518128A (en) * | 2018-12-29 | 2019-03-26 | 安徽立光电子材料股份有限公司 | A kind of metal composite film and its manufacture craft |
-
1988
- 1988-01-29 JP JP1717388A patent/JPH01195285A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03183781A (en) * | 1989-08-14 | 1991-08-09 | Saint Gobain Vitrage Internatl | Method and device for forming thin membrane |
| JPH03236477A (en) * | 1990-02-13 | 1991-10-22 | Optrex Corp | Partial electroless-plating method, electro-optical device and its production |
| JPH03239226A (en) * | 1990-02-16 | 1991-10-24 | Sanyo Electric Co Ltd | Liquid crystal display device |
| JPH04212934A (en) * | 1990-10-31 | 1992-08-04 | Ricoh Co Ltd | Liquid crystal display device |
| JPH06110073A (en) * | 1992-09-30 | 1994-04-22 | Kyocera Corp | Terminal lead-out structure of display element |
| JPH09191164A (en) * | 1996-01-10 | 1997-07-22 | Asahi Chem Ind Co Ltd | Fine thick film connection substrate and its manufacturing method |
| JPH1069229A (en) * | 1996-08-28 | 1998-03-10 | Kyocera Corp | Production of display element |
| JP2018115382A (en) * | 2017-01-20 | 2018-07-26 | 大日本印刷株式会社 | Light control film, method for manufacturing the same, laminate and method for manufacturing conductive plated layer |
| CN109518128A (en) * | 2018-12-29 | 2019-03-26 | 安徽立光电子材料股份有限公司 | A kind of metal composite film and its manufacture craft |
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