CN114156395A

CN114156395A - Array substrate, preparation method thereof, display panel and backlight module

Info

Publication number: CN114156395A
Application number: CN202010927603.1A
Authority: CN
Inventors: 汪建国; 刘松; 齐琪; 李永飞; 曾亭; 刘欢; 卢鑫泓; 董万如; 桂和仁; 杨健; 胡海峰; 江玉; 徐鹏; 储微微; 高琪
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-09-07
Filing date: 2020-09-07
Publication date: 2022-03-08

Abstract

The disclosure provides an array substrate, a preparation method thereof, a display panel and a backlight module, and belongs to the technical field of display. The preparation method of the array substrate comprises the steps of providing a substrate; forming a metal wiring layer on one side of a substrate; forming a first planarization layer on one side of the metal wiring layer, which is far away from the substrate; forming an electrode layer on one side of the first planarization layer, which is far away from the substrate, wherein the electrode layer comprises a copper electrode layer, a first buffer metal layer and a first copper-nickel alloy layer which are sequentially laminated on one side of the substrate; the first buffer metal layer is made of one or a mixture of molybdenum, molybdenum-niobium alloy, molybdenum-tungsten alloy, molybdenum-nickel-titanium alloy and molybdenum-magnesium-aluminum alloy; forming a second planarization layer on one side of the electrode layer, which is far away from the substrate; setting a functional device layer; the functional device layer is arranged on one side, far away from the substrate, of the second planarization layer and comprises a plurality of functional devices electrically connected with the electrode layer. The preparation method of the array substrate can improve the quality of the array substrate.

Description

Array substrate, preparation method thereof, display panel and backlight module

Technical Field

The disclosure relates to the technical field of display, and in particular relates to an array substrate, a preparation method of the array substrate, a display panel and a backlight module.

Background

A Micro Light Emitting Diode (Micro-LED) backplane may include a first copper metal layer, a planarization layer, a second copper metal layer, an organic protection layer, and a Micro Light Emitting Diode layer, which are sequentially stacked on a substrate. However, during the manufacturing process, the second copper metal layer is easily oxidized, which results in a decrease in yield and quality of the micro led backplane.

The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art that is known to a person of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to an array substrate, a method for manufacturing the array substrate, a display panel and a backlight module, which improve the quality of the array substrate.

In order to achieve the purpose, the technical scheme adopted by the disclosure is as follows:

according to a first aspect of the present disclosure, there is provided a method of manufacturing an array substrate, including:

providing a substrate base plate;

forming a metal wiring layer on one side of the substrate base plate;

forming a first planarization layer on one side of the metal wiring layer, which is far away from the substrate base plate;

forming an electrode layer on one side of the first planarization layer, which is far away from the substrate, wherein the electrode layer comprises a copper electrode layer, a first buffer metal layer and a first copper-nickel alloy layer which are sequentially laminated on one side of the substrate; the first buffer metal layer is made of one or a mixture of molybdenum, molybdenum-niobium alloy, molybdenum-tungsten alloy, molybdenum-nickel-titanium alloy and molybdenum-magnesium-aluminum alloy;

forming a second planarization layer on one side of the electrode layer, which is far away from the substrate base plate;

setting a functional device layer; the functional device layer is arranged on one side, far away from the substrate base plate, of the second planarization layer and comprises a plurality of functional devices electrically connected with the electrode layer.

In one exemplary embodiment of the present disclosure, forming an electrode layer on a side of the first planarization layer away from the substrate base plate includes:

forming a copper electrode material layer on one side of the first planarization layer, which is far away from the substrate base plate;

patterning the copper electrode material layer to form the copper electrode layer;

sequentially forming a first buffer metal material layer and a first copper-nickel alloy material layer on one side of the copper electrode layer, which is far away from the substrate base plate;

patterning the first buffer metal material layer and the first copper-nickel alloy material layer to form the first buffer metal layer and the first copper-nickel alloy layer; wherein, the orthographic projection of the copper electrode layer on the substrate base plate is positioned in the orthographic projection of the first buffer metal layer on the substrate base plate.

In one exemplary embodiment of the present disclosure, the patterning of the copper electrode material layer includes:

forming a first positive photoresist layer on the surface of the copper electrode material layer away from the substrate base plate; exposing the first positive photoresist layer by using a mask plate under first exposure intensity; developing the first positive photoresist layer; etching the copper electrode material layer to form the copper electrode layer; removing the first positive photoresist layer;

patterning the first buffer metallic material layer and the first copper-nickel alloy material layer includes:

forming a second positive photoresist layer on the surface of the first copper-nickel alloy material layer far away from the substrate base plate; exposing the second positive photoresist layer by using the mask plate under a second exposure intensity, wherein the second exposure intensity is smaller than the first exposure intensity; developing the second positive photoresist layer; etching the first buffer metal material layer and the first copper-nickel alloy material layer to form the first buffer metal layer and the first copper-nickel alloy layer; and removing the second positive photoresist layer.

sequentially forming a copper electrode material layer, a first buffer metal material layer and a first copper-nickel alloy material layer on one side of the first planarization layer, which is far away from the substrate base plate;

and carrying out a composition process on the copper electrode material layer, the first buffer metal material layer and the first copper-nickel alloy material layer to form the copper electrode layer, the first buffer metal layer and the first copper-nickel alloy layer.

and forming an electrode layer on one side of the first planarization layer, which is far away from the substrate base plate, wherein the electrode layer further comprises a second buffer metal layer positioned on the surface, close to the substrate base plate, of the copper electrode layer.

According to a second aspect of the present disclosure, there is provided an array substrate including:

a substrate base plate;

a metal wiring layer provided on one side of the substrate base plate;

the first planarization layer is arranged on one side, away from the substrate, of the metal wiring layer;

the electrode layer is arranged on one side, far away from the substrate, of the first planarization layer; the electrode layer comprises a copper electrode layer, a first buffer metal layer and a first copper-nickel alloy layer which are sequentially laminated on one side of the substrate; the first buffer metal layer is made of one or a mixture of molybdenum, molybdenum-niobium alloy, molybdenum-tungsten alloy, molybdenum-nickel-titanium alloy and molybdenum-magnesium-aluminum alloy;

the second planarization layer is arranged on one side, far away from the substrate, of the electrode layer;

and the functional device layer is arranged on one side of the second planarization layer, which is far away from the substrate base plate, and comprises a plurality of functional devices electrically connected with the electrode layer.

In an exemplary embodiment of the present disclosure, the electrode layer further includes a second buffer metal layer on a surface of the copper electrode layer close to the substrate base plate.

In an exemplary embodiment of the present disclosure, the first buffer metal layer and the first copper nickel alloy layer cover a side surface of the copper electrode layer and a surface of the copper electrode layer away from the base substrate.

In an exemplary embodiment of the present disclosure, an orthographic projection of the first copper-nickel alloy layer on the copper electrode layer is located within the copper electrode layer.

In an exemplary embodiment of the present disclosure, the first buffer metal layer has a thickness of 100 to 500 angstroms.

In an exemplary embodiment of the present disclosure, the first copper-nickel alloy layer has a thickness of 200 to 1000 angstroms.

According to a third aspect of the present disclosure, a display panel is provided, which includes the above array substrate; the functional device of the array substrate is a micro light-emitting diode or a mini light-emitting diode.

According to a fourth aspect of the present disclosure, a backlight module is provided, which includes the above array substrate; the functional device of the array substrate is a micro light-emitting diode or a mini light-emitting diode.

In the array substrate and the preparation method thereof, the display panel and the backlight module, the first buffer metal layer is arranged between the copper electrode layer and the first copper-nickel alloy layer, so that the first copper-nickel alloy layer has good appearance, a roof structure is prevented from appearing when the first copper-nickel alloy layer is etched, the appearance of the electrode layer is improved, and the quality of the array substrate is improved. The first copper-nickel alloy layer can protect the copper electrode layer and improve the adhesive force of the functional device.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is an electron microscope image of a metal layer after etching in the related art, wherein the metal layer includes a molybdenum-niobium alloy layer, a copper metal layer, and a copper-nickel alloy layer, and a mass content of nickel in the copper-nickel alloy layer is 5%.

Fig. 2 is an electron microscope image of a metal layer after etching in the related art, wherein the metal layer includes a molybdenum-niobium alloy layer, a copper metal layer, and a copper-nickel alloy layer, and the mass content of nickel in the copper-nickel alloy layer is 20%.

Fig. 3 is an electron microscope image of a metal layer after etching in the related art, wherein the metal layer includes a molybdenum-niobium alloy layer, a copper metal layer, and a copper-nickel alloy layer, and a mass content of nickel in the copper-nickel alloy layer is 30%.

Fig. 4 is an electron microscope image of a metal layer after etching in the related art, in which the metal layer includes a copper-nickel alloy layer, a copper metal layer, and a copper-nickel alloy layer, and a mass content of nickel in the copper-nickel alloy layer is 20%.

Fig. 5 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure.

Fig. 6 is a schematic structural diagram of forming a metal wiring layer according to an embodiment of the present disclosure.

Fig. 7 is a schematic structural diagram of forming a first planarizing layer according to an embodiment of the present disclosure.

Fig. 8 is a schematic structural diagram of forming a copper electrode material layer and a second buffer metal material layer according to an embodiment of the present disclosure.

Fig. 9 is a schematic structural diagram of forming a copper electrode layer and a second buffer metal layer according to an embodiment of the present disclosure.

Fig. 10 is a schematic structural diagram of forming a first buffer metal material layer and a first copper-nickel alloy material layer according to an embodiment of the disclosure.

Fig. 11 is a schematic structural diagram of forming a first buffer metal layer and a first copper-nickel alloy layer according to an embodiment of the disclosure.

Fig. 12 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 13 is a schematic structural diagram of forming a second buffer metal material layer, a copper electrode material layer, a first buffer metal material layer, and a first copper-nickel alloy material layer according to an embodiment of the disclosure.

Fig. 14 is a schematic structural diagram of forming a second buffer metal layer, a copper electrode layer, a first buffer metal layer, and a first copper-nickel alloy layer according to an embodiment of the disclosure.

Fig. 15 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 16 is an electron micrograph of the second buffer metal layer, the copper electrode layer, the first buffer metal layer, and the first copper-nickel alloy layer according to an embodiment of the present disclosure.

Fig. 17 is an electron micrograph of a first buffer metal layer and a first copper-nickel alloy layer according to an embodiment of the disclosure.

The reference numerals of the main elements in the figures are explained as follows:

100. a substrate base plate; 101. an insulating buffer layer; 200. a metal wiring layer; 300. a first planarizing layer; 400. an electrode layer; 410. a copper electrode layer; 411. a copper electrode material layer; 420. a first buffer metal layer; 421. a first buffer metal material layer; 430. a first copper-nickel alloy layer; 431. a first copper-nickel alloy material layer; 440. a second buffer metal layer; 441. a second buffer metal material layer; 500. a second planarizing layer; 600. a functional device layer; 610. a functional device; 700. and a solder layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure.

In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals denote the same or similar structures in the drawings, and thus detailed descriptions thereof will be omitted.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the primary technical ideas of the disclosure.

The terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc. The terms "first" and "second", etc. are used merely as labels, and are not limiting on the number of their objects.

In the present disclosure, any one of the film layers may include a side surface, a surface close to the substrate base plate, and a surface far from the substrate base plate, wherein the surface close to the substrate base plate and the surface far from the substrate base plate are connected through the side surface of the film layer. In the present disclosure, the thickness of any one of the film layers is the dimension of the film layer in the direction perpendicular to the substrate base plate.

The inventors have found that by preparing a copper-nickel alloy on a copper metal layer, oxidation of the copper metal layer can be prevented. However, the etch rate of copper-nickel alloys is lower than that of copper, and the higher the nickel content, the slower the etch rate. When the laminated copper metal layer and the copper-nickel alloy layer are etched, the copper-nickel alloy layer usually leaves a roof structure (Tip structure); and the higher the nickel content, the larger the roof structure; the greater the thickness of the layer of copper-nickel alloy, the slower the etching rate and the larger the roof structure. The roof structure may collapse during the use of the array substrate, which may cause the array substrate to be bad, seriously affect the production of the array substrate, and reduce the quality of the array substrate. For example, referring to fig. 1-4, the metal layers containing the copper-nickel alloy layers are etched to form roof structures.

Fig. 1 is an electron microscope image of a metal layer consisting of a molybdenum-niobium alloy layer (MoNb), a copper metal layer (Cu) and a copper-nickel alloy layer (CuNi) stacked after etching. Wherein the mass content of nickel in the copper-nickel alloy layer is 5 percent. In fig. 1, it can be seen that the layer of copper-nickel alloy forms a roof structure. Fig. 2 is an electron microscope image of a metal layer consisting of a molybdenum-niobium alloy layer (MoNb), a copper metal layer (Cu) and a copper-nickel alloy layer (CuNi) stacked after etching. Wherein the mass content of nickel in the copper-nickel alloy layer is 20%. In fig. 2, it can be seen that the layer of cupronickel alloy forms a severe roof structure. Fig. 3 is an electron microscope image of a metal layer consisting of a molybdenum-niobium alloy layer (MoNb), a copper metal layer (Cu) and a copper-nickel alloy layer (CuNi) stacked after etching. Wherein the mass content of nickel in the copper-nickel alloy layer is 30 percent. In fig. 3, it can be seen that the layer of cupronickel alloy formed a more severe roof structure, and that the roof structure had collapsed. Fig. 4 is an electron microscope image of a metal layer consisting of a copper nickel alloy layer (CuNi), a copper metal layer (Cu), and a copper nickel alloy layer (CuNi) stacked after etching. Wherein the mass content of nickel in the copper-nickel alloy layer is 20%. In fig. 4, it can be seen that the layer of cupronickel alloy forms a severe roof structure.

The present disclosure provides a method for manufacturing an array substrate, referring to fig. 5, the method for manufacturing an array substrate includes:

step S110, referring to fig. 6, providing a substrate 100;

step S120, referring to fig. 6, forming a metal wiring layer 200 on one side of the substrate base 100;

step S130, referring to fig. 7, forming a first planarization layer 300 on the side of the metal wiring layer 200 away from the substrate base plate 100;

step S140, referring to fig. 11 and 14, forming an electrode layer 400 on a side of the first planarization layer 300 away from the substrate 100, wherein the electrode layer 400 includes a copper electrode layer 410, a first buffer metal layer 420 and a first copper-nickel alloy layer 430 sequentially stacked on the substrate 100; the first buffer metal layer 420 is made of one or a mixture of molybdenum, molybdenum-niobium alloy, molybdenum-tungsten alloy, molybdenum-nickel-titanium alloy and molybdenum-magnesium-aluminum alloy;

step S150, referring to fig. 12 and 15, forming a second planarization layer 500 on the side of the electrode layer 400 away from the base substrate 100;

step S160, referring to fig. 12 and 15, a functional device layer 600 is provided; the functional device layer 600 is disposed on a side of the second planarization layer 500 away from the substrate base plate 100, and includes a plurality of functional devices 610 electrically connected to the electrode layer 400.

According to the method for manufacturing the array substrate of the present disclosure, referring to fig. 12 and 15, the manufactured array substrate includes a substrate 100, a metal wiring layer 200, a first planarization layer 300, an electrode layer 400, a second planarization layer 500, and a functional device layer 600, which are sequentially stacked; the electrode layer 400 includes a copper electrode layer 410, a first buffer metal layer 420 and a first copper-nickel alloy layer 430 sequentially stacked on one side of the substrate 100; the first buffer metal layer 420 is made of one or a mixture of molybdenum, molybdenum-niobium alloy, molybdenum-tungsten alloy, molybdenum-nickel-titanium alloy and molybdenum-magnesium-aluminum alloy; the functional device layer 600 includes a plurality of functional devices 610 electrically connected to the electrode layer 400.

In the array substrate and the method for manufacturing the same, the first buffer metal layer 420 is disposed between the copper electrode layer 410 and the first copper-nickel alloy layer 430, so that the first copper-nickel alloy layer 430 has a good morphology, a roof structure of the first copper-nickel alloy layer 430 is prevented from occurring during etching, the morphology of the electrode layer 400 is improved, and the quality of the array substrate is improved. The first copper-nickel alloy layer 430 can protect the copper electrode layer 410 and improve the adhesion of the functional device 610.

The principle, details and effects of the steps of the method for manufacturing an array substrate provided by the present disclosure will be further explained and illustrated with reference to the accompanying drawings.

In step S110, referring to fig. 6, a substrate base plate 100 may be provided. The base substrate 100 may be an inorganic base substrate 100 or an organic base substrate 100. For example, in one embodiment of the present disclosure, the material of the substrate 100 may be a glass material such as soda-lime glass (soda-lime glass), quartz glass, or sapphire glass, or may be a metal material such as stainless steel, aluminum, or nickel. In another embodiment of the present disclosure, the material of the substrate 100 may be Polymethyl methacrylate (PMMA), Polyvinyl alcohol (PVA), Polyvinyl phenol (PVP), Polyether sulfone (PES), polyimide, polyamide, polyacetal, Polycarbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN), or a combination thereof. In another embodiment of the present disclosure, the substrate 100 may also be a flexible substrate 100, for example, the material of the substrate 100 may be Polyimide (PI). The substrate 100 may also be a composite of multiple layers of materials, for example, in an embodiment of the present disclosure, the substrate 100 may include a Bottom Film layer (Bottom Film), a pressure sensitive adhesive layer, a first polyimide layer, and a second polyimide layer, which are sequentially stacked.

Alternatively, referring to fig. 6, before forming the metal wiring layer 200, an insulating buffer layer 101, such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer, may be formed on one side of the substrate 100; then, a metal wiring layer 200 is formed on a side of the insulating buffer layer 101 remote from the base substrate 100. The insulating buffer layer 101 can improve stress applied to the substrate when the metal wiring layer 200 is formed, and can insulate moisture.

In one embodiment of the present disclosure, the substrate 100 is made of glass, so that the substrate has a large size and low cost, and is convenient to be used as a backlight source of a direct-type backlight module to reduce the cost of the backlight module.

In another embodiment of the present disclosure, the substrate 100 is made of polyimide, so that the array substrate may be a flexible array substrate, which facilitates the array substrate to manufacture a flexible or foldable display panel.

In step S120, referring to fig. 6, a metal wiring layer 200 may be formed on one side of the base substrate 100. The metal wiring layer 200 may include metal leads, which may drive the respective functional devices 610 through the electrode layer 400. The metal wiring layer 200 may be formed by deposition methods including, but not limited to, sputtering, electroplating, and electroless plating, and patterning methods including, but not limited to, photolithography, growing a patterned growth layer on the patterned seed layer, growing a patterned metal pattern under the definition of the pattern defining layer, and the like.

For example, in some embodiments, the metal wiring layer 200 may be prepared by: a metal wiring material layer is sputter-formed on one side of the base substrate 100 and then patterned through a photolithography process to form the metal wiring layer 200. In this embodiment, the metal wiring material layer may include a single layer of metal material, or may include a plurality of layers of stacked metal materials.

Preferably, the metal wiring material layer includes at least a copper metal material layer so that the metal wiring has a low resistance. The thickness of the copper metal material layer is not greater than 1 μm to prevent excessive stress to the substrate 100 during sputtering of the copper metal material layer. The copper metal layer is patterned to form a copper metal layer. As such, in the prepared array substrate, the metal wiring layer 200 includes at least a copper metal layer.

Further preferably, the metal wiring material layer may further include a first adhesion material layer located on a surface of the copper metal material layer close to the substrate base plate 100, and the material of the first adhesion material layer may be molybdenum, a molybdenum-copper alloy, a molybdenum-niobium alloy, a molybdenum-copper-niobium alloy, or other metals or metal alloys. The first adhesive material layer is patterned to form a first adhesive layer. The first adhesion layer may improve adhesion between the copper metal layer and the base substrate 100 or the insulating buffer layer 101 and protect the metal copper from corrosion. In this manner, in the prepared array substrate, the metal wiring layer 200 may include a first adhesive layer and a first copper metal layer sequentially stacked on one side of the substrate 100.

Further preferably, the metal wiring material layer may further include a second adhesion material layer located on a surface of the copper metal material layer away from the substrate base plate 100, and a material of the second adhesion material layer may be molybdenum, a molybdenum-copper alloy, a molybdenum-niobium alloy, a molybdenum-copper-niobium alloy, or other metals or metal alloys. And forming a second adhesive layer after the second adhesive material layer is subjected to patterning treatment. The second adhesion layer may improve adhesion of the copper metal layer to the electrode layer 400 and protect the copper metal from corrosion. In this manner, in the prepared array substrate, the metal wiring layer 200 may include a copper metal layer and a second adhesive layer sequentially stacked on one side of the substrate 100.

Illustratively, the metal wiring layer 200 includes a molybdenum-niobium alloy layer, a copper metal layer, and a molybdenum-niobium alloy layer, which are sequentially laminated on one side of the base substrate 100.

As another example, in other embodiments, the metal wiring layer 200 may be prepared by:

a first metal wiring material layer is formed on one side of the substrate base plate 100, and the first metal wiring material layer includes a molybdenum-niobium alloy material layer, a copper metal material layer, and a molybdenum-niobium alloy material layer, which are sequentially stacked. Then, a mask plate is adopted to carry out patterning operation on the first metal wiring material layer so as to pattern the first metal wiring material layer into a first metal wiring layer. The first metal wiring layer comprises a molybdenum-niobium alloy layer, a copper metal layer and a molybdenum-niobium alloy layer which are laminated.

A second metal wiring material layer is formed on the side of the first metal wiring layer away from the substrate base plate 100, and the second metal wiring material layer includes a molybdenum-niobium alloy material layer, a copper metal material layer and a molybdenum-niobium alloy material layer which are sequentially stacked. Then, the same mask plate is used for carrying out patterning operation on the second metal wiring material layer so as to pattern the second metal wiring material layer into a second metal wiring layer. The second metal wiring layer comprises a molybdenum-niobium alloy layer, a copper metal layer and a molybdenum-niobium alloy layer which are laminated.

As such, the metal wiring layer 200 includes a first metal wiring layer and a second metal wiring layer that are laminated, and the patterns of the first metal wiring layer and the first metal wiring layer are the same. As a whole, the metal wiring layer 200 includes a molybdenum-niobium alloy layer, a copper metal layer, a molybdenum-niobium alloy layer, a copper metal layer, and a molybdenum-niobium alloy layer, which are sequentially stacked. This can increase the thickness of the metal wiring layer 200, reduce the impedance of the metal wiring layer 200, and satisfy the electrical requirements of the array substrate.

step S210, forming a seed metal material layer on one side of the substrate base plate 100 by sputtering;

step S220, forming a pattern defining layer on the surface of the seed metal material layer away from the substrate 100, wherein the pattern defining layer is made of a removable insulating material and is formed with a plurality of patterned openings exposing the seed metal material layer;

step S230, forming a copper growth material layer in the opening of the pattern limiting layer by adopting an electroplating copper method;

step S240, removing the pattern limiting layer;

step S250, removing the part of the seed metal material layer which is not covered by the copper growth material layer by adopting an etching method, so that the seed metal material layer is patterned into a seed metal layer; in the etching process, the copper growth material layer is not required to be protected, so that the surface of the copper growth material layer is partially etched to generate the copper growth layer.

In step S210, the seed metal material layer may include a copper metal material layer, and the thickness of the copper metal material layer is not greater than 1 μm. Preferably, the thickness of the copper metal material layer is 2500-3500 angstroms. Illustratively, the layer of copper metal material is 3000 angstroms thick. The copper metal layer is patterned to form a copper metal layer. Thus, in the prepared array substrate, the seed metal layer may include a copper metal layer.

Optionally, the seed metal material layer may further include a third adhesion material layer located on the surface of the copper metal material layer close to the substrate base plate 100, and the material of the third adhesion material layer may be molybdenum, a molybdenum-copper alloy, a molybdenum-niobium alloy, a molybdenum-copper-niobium alloy, or other metals or metal alloys. And patterning the second adhesive material layer to form a third adhesive layer. As such, in the prepared array substrate, the seed metal layer may include a third adhesion layer and a second copper metal layer sequentially stacked on one side of the substrate 100. Preferably, the material of the third adhesion layer is molybdenum-niobium alloy, and the thickness is 250-350 angstroms. Illustratively, the third adhesion layer has a thickness of 300 angstroms.

In step S220, the material of the pattern defining layer may be an organic insulating material, for example, a photosensitive resin; the material may be an inorganic material, for example, a material such as silicon oxide. Preferably, the material of the pattern defining layer is photoresist.

In steps S220 and S230, the thickness of the pattern defining layer may be determined according to the thickness of the copper growth material layer such that the thickness of the pattern defining layer is greater than the thickness of the copper growth material layer. The thickness of the copper growth material layer may be determined according to the resistance requirement of the array substrate to the metal wiring layer 200. The lower the resistance required of the metal wiring layer 200, the greater the thickness of the copper growth material layer may be. Optionally, in step S250, the thickness of the formed copper growth layer is 1.5 to 10 micrometers. Therefore, the metal wiring layer 200 can be provided with only one layer of metal leads, and a plurality of layers of laminated metal leads are not required to be provided to reduce impedance, so that the preparation processes and the number of masks of the array substrate can be reduced, and the cost of the array substrate can be reduced. The copper growth layer may be formed by electroplating or electroless plating.

Illustratively, in one embodiment of the present disclosure, the pattern defining layer has a thickness of 7.5 microns and the copper growth material layer has a thickness of 6.3 microns. Illustratively, in another embodiment of the present disclosure, the pattern defining layer has a thickness of 3 to 4 microns and the copper growth material layer has a thickness of 2.1 microns.

Optionally, in this embodiment, the method for manufacturing an array substrate may further include: before forming the planarization layer, a passivation layer is formed on the surface of the metal wiring layer 200 away from the base substrate 100 to protect the metal wiring layer 200. The passivation layer may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In this way, the array substrate is prepared in which the passivation layer is disposed between the metal wiring layer 200 and the first planarization layer 300.

Illustratively, the material of the passivation layer is silicon nitride, and the thickness of the passivation layer is 900-1100 angstroms.

and preparing a seed metal layer and a copper growth layer according to the methods shown in the steps S210 to S250, and then forming a second copper-nickel alloy layer by an electroplating or chemical plating method. The second copper-nickel alloy layer covers the surface and the side surfaces of the copper growth layer far from the substrate 100, and may also cover part or all of the side surfaces of the seed metal layer. Therefore, the second copper-nickel alloy layer can protect the seed metal layer and the copper growth layer and prevent the seed metal layer and the copper growth layer from being oxidized in the baking process. In this way, the prepared metal wiring layer 200 includes a seed metal layer, a copper growth layer, and a second copper nickel alloy layer sequentially stacked on one side of the base substrate 100, wherein the second copper nickel alloy layer covers a surface and a side surface of the copper growth layer away from the base substrate 100, and a part or all of the side surface of the seed metal layer.

Preferably, the second copper-nickel alloy layer contains nickel in an amount of not less than 30% by weight. Therefore, the second copper-nickel alloy layer can be ensured to have excellent oxidation resistance, and various problems caused by etching of the copper-nickel alloy with high nickel content can be avoided. Further, the weight content of nickel is more than 80%.

Preferably, the thickness of the second copper-nickel alloy layer is 500-2000 angstroms to ensure that the second copper-nickel alloy layer has excellent oxidation resistance and avoid various problems caused by etching of the copper-nickel alloy with high thickness.

Preferably, the seed metal layer and the copper growth layer may be first treated with a solution of palladium salt to form a palladium activation layer covering the surface and side of the copper growth layer away from the substrate base plate 100 and at least a part of the side of the seed metal layer; then, the palladium activation layer is treated by using a chemical plating solution containing copper salt, nickel salt, a reducing agent, a complexing agent and a pH regulator, and a second copper-nickel alloy layer is formed on the surface of the palladium activation layer away from the substrate 100.

In this embodiment, after the metal wiring layer 200 is formed, the first planarization layer 300 may be formed in step S130 without additionally providing a passivation layer. Therefore, the oxidation resistance protection of copper in the metal wiring layer 200 can be improved, the steps of deposition, etching and the like of the passivation layer can be reduced, the quality of the array substrate is improved, and the cost of the array substrate is reduced.

In step S130, referring to fig. 7, a first planarization layer 300 may be formed on a side of the metal wiring layer 200 away from the substrate base plate 100. The material of the first planarization layer 300 may be an organic material, and may be, for example, a photosensitive resin.

Optionally, the thickness of the first planarization layer 300 is 3 to 7 micrometers. Preferably, the thickness of the first planarization layer 300 is 4.5 to 5.5 micrometers.

A via hole may be disposed on the first planarization layer 300 so that the electrode layer 400 is electrically connected with the metal wiring layer 200. For example, the first planarization layer 300 may be provided with a first via and a second via, each exposing at least a portion of the metal wiring layer 200. The electrode layer 400 includes a connection electrode and a bonding pad, wherein at least a portion of the connection electrode is electrically connected to the metal wiring layer 200 through a first via, and the bonding pad is electrically connected to the metal wiring layer 200 through a second via. The bonding pad is used for electrically connecting with a circuit board (e.g., a flexible circuit board) or a driving chip, and the connection electrode is used for electrically connecting with a functional device.

In step S140, an electrode layer 400 may be formed on a side of the first planarization layer 300 away from the base substrate 100. The electrode layer 400 includes a copper electrode layer 410, a first buffer metal layer 420, and a first copper-nickel alloy layer 430, which are sequentially stacked on one side of the substrate 100. The first buffer metal layer 420 and the first copper-nickel alloy layer 430 serve as an electrode protection layer, so that the user can protect the copper electrode layer 410, prevent the surface of the copper electrode layer 410 from being oxidized, improve the adhesion between the electrode layer 400 and the functional device layer 600, particularly improve the adhesion between the electrode layer 400 and the solder layer, and prevent the functional device 610 from peeling off. The first buffer metal layer 420 may also increase adhesion between the copper electrode layer 410 and the first copper nickel alloy layer 430.

Optionally, when forming the electrode layer 400, a copper electrode layer 410 may be formed first, and then a first buffer metal layer 420 and a first copper-nickel alloy layer 430 covering the copper electrode layer 410 are formed; the copper electrode layer 410, the first buffer metal layer 420, and the first copper nickel alloy layer 430 may be formed in the same etching process.

In some embodiments, forming the electrode layer 400 on the side of the first planarization layer 300 away from the substrate base plate 100 includes the following steps:

step S310, referring to fig. 8, forming a copper electrode material layer 411 on a side of the first planarization layer 300 away from the substrate base plate 100;

step S320, referring to fig. 9, performing a patterning operation on the copper electrode material layer 411 to form a copper electrode layer 410;

step S330, referring to fig. 10, forming a first buffer metal material layer 421 and a first copper-nickel alloy material layer 431 on the side of the copper electrode layer 410 away from the substrate base plate 100 in sequence;

step S340, referring to fig. 11, performing a patterning operation on the first buffer metal material layer 421 and the first copper-nickel alloy material layer 431 to form a first buffer metal layer 420 and a first copper-nickel alloy layer 430; the orthographic projection of the copper electrode layer 410 on the substrate 100 is located in the orthographic projection of the first buffer metal layer 420 on the substrate 100.

In step S310, the copper electrode material layer 411 may be formed by sputtering, and the thickness of the copper electrode material layer 411 may be determined according to requirements, and may be 2500 angstroms to 5000 angstroms, for example. Preferably, the thickness of the copper electrode material layer 411 may be 3000 angstroms.

In step S320, the copper electrode material layer 411 may be patterned by a photolithography process, and the patterned copper electrode material layer 411 becomes the copper electrode layer 410.

Illustratively, in one embodiment of the present disclosure, the copper electrode material layer 411 may be patterned by: forming a first positive photoresist layer on the surface of the copper electrode material layer 411 away from the substrate base plate 100; exposing the first positive photoresist layer by using a mask plate under the first exposure intensity; developing the first positive photoresist layer; etching the copper electrode material layer 411 to form a copper electrode layer 410; and removing the first positive photoresist layer.

Alternatively, in one embodiment of the present disclosure, referring to fig. 8, in step S310. Before forming the copper electrode material layer 411, a second buffer metal material layer 441 may be further formed on a side of the first planarization layer 300 away from the substrate base plate 100, and then the copper electrode material layer 411 may be formed on a surface of the second buffer metal material layer 441 away from the substrate base plate 100. The second buffer metal material layer 441 is made of one or a mixture of molybdenum, a molybdenum-niobium alloy, a molybdenum-tungsten alloy, a molybdenum-nickel-titanium alloy and a molybdenum-magnesium-aluminum alloy. In step S320, when the copper electrode material layer 411 is patterned, the second buffer metal material layer 441 may also be simultaneously patterned to form the second buffer metal layer 440. During the etching process, although the material of the second buffer metal material layer 441 is difficult to etch, since the second buffer metal material layer is in contact with the copper electrode material layer 411 and is etched synchronously, an electrochemical effect is generated between the two, and electrons on the second buffer metal material layer 441 are transferred to the copper electrode material layer 411 to increase the etching speed of the second buffer metal material layer 441. Thus, the second buffer metal material layer 441 and the copper electrode material layer 411 can maintain synchronous etching, and the surface of the second buffer metal layer 440 away from the substrate base plate 100 is substantially coincident with the surface of the copper electrode layer 410 close to the substrate base plate 100. In this way, in the array substrate prepared by the present disclosure, the electrode layer 400 may include the second buffer metal layer 440, the copper electrode layer 410, the first buffer metal layer 420, and the first copper nickel alloy layer 430, which are sequentially stacked on the first planarization layer 300 on the side away from the substrate 100.

In step S330, referring to fig. 10, a first buffer metal material layer 421 and a first copper-nickel alloy material layer 431 may be sequentially formed on the surface of the copper electrode layer 410 away from the substrate base plate 100 by a sputtering method. Optionally, the thickness of the first buffer metal material layer 421 is 100 to 500 angstroms; preferably, the thickness of the first buffer metal material layer 421 is 200 to 500 angstroms. Optionally, the thickness of the first copper-nickel alloy material layer 431 is 200 to 1000 angstroms; preferably, the thickness of the first copper-nickel alloy material layer 431 is 500 to 1000 angstroms. Preferably, the material of the first buffer metal material layer 421 is a molybdenum-niobium alloy. Thus, the material of the first buffer metal layer 420 is a molybdenum-niobium alloy.

In step S340, the first buffer metal layer 421 and the first copper-nickel alloy layer 431 may be patterned by a photolithography process to form the first buffer metal layer 420 and the first copper-nickel alloy layer 430. During the etching process, the etching rates of the first buffer metal material layer 421 and the first copper-nickel alloy material layer 431 are similar, so that the first copper-nickel alloy material layer 431 does not form a roof structure. Fig. 17 is an electron microscope image of the first buffer metal layer 420 and the first copper-nickel alloy layer 430 formed after etching. As can be seen from fig. 17, the surface of the first buffer metal layer 420 away from the base substrate 100 substantially coincides with the surface of the first copper-nickel alloy layer 430 close to the base substrate 100. Here, the orthographic projection of the copper electrode layer 410 on the substrate 100 may be located within the orthographic projection of the first buffer metal layer 420 on the substrate 100. Thus, the first buffer metal layer 420 covers the surface of the copper electrode layer 410 away from the substrate base plate 100 and the side surface of the copper electrode layer 410, and the first copper-nickel alloy layer 430 also covers the surface of the copper electrode layer 410 away from the substrate base plate 100 and the side surface of the copper electrode layer 410; that is, the orthographic projection of the copper electrode layer 410 on the substrate 100 is also located in the orthographic projection of the first copper-nickel alloy layer 430 on the substrate 100

As such, in the electrode layer 400 of the array substrate, the first buffer metal layer 420 and the first copper-nickel alloy layer 430 cover the side surface of the copper electrode layer 410 and the surface of the copper electrode layer 410 away from the base substrate 100 in this embodiment. This allows the first copper-nickel alloy layer 430 to effectively protect the copper electrode layer 410 from oxidation of the copper electrode layer 410. Moreover, since the etching rates of the first buffer metal material layer 421 and the first copper-nickel alloy material layer 431 are close to each other, the first copper-nickel alloy layer 430 can be prevented from having a roof structure and thus degrading the quality of the array substrate.

For example, in step S340, the first buffer metal material layer 421 and the first copper-nickel alloy material layer 431 may be patterned by: a second positive photoresist layer may be formed on the surface of the first copper-nickel alloy material layer 431 away from the substrate base plate 100; exposing the second positive photoresist layer by using a mask plate under a second exposure intensity, wherein the second exposure intensity is smaller than the first exposure intensity; developing the second positive photoresist layer; etching the first buffer metal material layer 421 and the first copper-nickel alloy material layer 431 to form a first buffer metal layer 420 and a first copper-nickel alloy layer 430; and removing the second positive photoresist layer. The same mask plate can be used in step S340 and step S320, so as to reduce the number of mask plates and reduce the manufacturing cost of the array substrate.

Because the same mask plate is used and the weaker exposure intensity is used in step S340, the pattern of the second positive photoresist layer developed in step S340 is larger than the pattern of the first positive photoresist layer developed in step S320, and the pattern of the first positive photoresist layer developed is completely located within the pattern of the second positive photoresist layer developed. This may ensure that the first buffer metal layer 420 can cover the copper electrode layer 410.

Preferably, in order to ensure that step S320 and step S340 can share the same mask plate, the minimum value of the distance between the edge of the orthographic projection of the copper metal layer on the substrate 100 and the edge of the orthographic projection of the first metal buffer layer on the substrate 100 may be not less than 1.5 micrometers. In other words, referring to fig. 11, for any sub-structure of the electrode layer 400, such as any pad, bonding electrode, or other sub-structure located in the electrode layer 400, the FICD (Final Critical Dimension) d1 of the first buffer metal layer 420 portion of the sub-structure is at least 3 microns greater than the FICD d2 of the copper electrode layer 410 portion of the sub-structure.

In some other embodiments, forming the electrode layer 400 on the side of the first planarization layer 300 away from the substrate base plate 100 includes the following steps:

step S410, referring to fig. 13, forming a copper electrode material layer 411, a first buffer metal material layer 421 and a first copper-nickel alloy material layer 431 on the first planarization layer 300 away from the substrate 100 in sequence;

step S420, forming a photoresist layer on a side of the first copper-nickel alloy material layer 431 away from the base substrate 100;

step S430, exposing and developing the photoresist layer;

step S440, referring to fig. 14, etching the copper electrode material layer 411, the first buffer metal material layer 421 and the first copper-nickel alloy material layer 431 to form the copper electrode layer 410, the first buffer metal layer 420 and the first copper-nickel alloy layer 430;

step S450, removing the photoresist layer.

In step S410, a copper electrode material layer 411, a first buffer metal material layer 421 and a first copper-nickel alloy material layer 431 may be sequentially formed by a sputtering method. Optionally, the thickness of the first buffer metal material layer 421 is 200 to 500 angstroms. Optionally, the thickness of the first copper-nickel alloy material layer 431 is 500 to 1000 angstroms. Preferably, the material of the first buffer metal material layer 421 is a molybdenum-niobium alloy. Thus, the material of the first buffer metal layer 420 is a molybdenum-niobium alloy.

Optionally, in an embodiment of the present disclosure, before forming the copper electrode material layer 411, a second buffer metal material layer 441 may also be formed on a side of the first planarization layer 300 away from the substrate base plate 100; then, a copper electrode material layer 411 is formed on the side of the second buffer metal material layer 441 away from the substrate base plate 100. Thus, the second buffer metal material layer 441 can be etched in step S440 in synchronization with the copper electrode material layer 411, and patterned into a second buffer metal layer 440; the electrode layer 400 may include a second buffer metal layer 440, a copper electrode layer 410, a first buffer metal layer 420, and a first copper nickel alloy layer 430, which are sequentially stacked in the prepared array substrate. The second buffer metal layer 440 is made of one or a mixture of molybdenum, molybdenum-niobium alloy, molybdenum-tungsten alloy, molybdenum-nickel-titanium alloy and molybdenum-magnesium-aluminum alloy.

In step S440, the copper electrode material layer 411, the first buffer metal material layer 421 and the first copper-nickel alloy material layer 431 may be simultaneously etched, and thus the electrode layer 400 without the roof structure may be formed. In this step, although the etching rate of the first buffer metal material layer 421 and the first copper-nickel alloy material layer 431 is less than that of the copper metal material layer when there is no copper metal material layer, when the first buffer metal material layer 421 is sandwiched between the copper metal material layer and the first copper-nickel alloy material layer 431, the copper metal material layer may generate an electrochemical effect with the first buffer metal material layer 421 and the first copper-nickel alloy material layer 431. During etching, electrons on the first buffer metal material layer 421 can be transferred to the copper metal material layer, so that the etching rate of the first buffer metal material layer 421 is increased; electrons on the first cu-ni alloy material layer 431 may be transferred to the cu material layer, thereby increasing an etching rate of the first cu-ni alloy material layer 431. Finally, the copper electrode material layer 411, the first buffer metal material layer 421 and the first copper nickel alloy material layer 431 may maintain substantially simultaneous etching. The defect that a roof structure is easily generated when the copper-nickel alloy layer and the copper metal layer are etched simultaneously is overcome, the defect that the etching rate of the copper-nickel alloy layer is too low is overcome, the appearance of the electrode layer 400 can be finally improved, the preparation rate of the electrode layer 400 can be increased, the quality of the array substrate can be improved, and the cost of the array substrate can be reduced.

Fig. 16 is an electron microscope image of the electrode layer 400 prepared according to the method of step S440. Referring to fig. 16, a surface of the copper electrode layer 410 away from the substrate base plate 100 may substantially coincide with a surface of the first buffer metal layer 420 close to the substrate base plate 100; the surface of the first buffer metal layer 420 away from the base substrate 100 may substantially coincide with the surface of the first copper nickel alloy layer 430 close to the base substrate 100. When the electrode layer 400 further includes the second buffer metal layer 440, a surface of the second buffer metal layer 440 far from the substrate base plate 100 may substantially coincide with a surface of the copper electrode layer 410 near the substrate base plate 100. As can be seen in fig. 16, although the copper electrode material layer 411, the first buffer metal material layer 421 and the first copper nickel alloy material layer 431 are simultaneously etched, the roof structure is not generated.

Therefore, according to the array substrate preparation method provided by the present disclosure, the first copper-nickel alloy material layer 431 and the copper electrode material layer 411 can be simultaneously etched by using the copper etching solution, and the formed structure does not have a roof structure, so that development of a new etching solution is not needed, not only is the array substrate preparation cost reduced, but also the time for developing a new etching solution can be saved, and finally the array substrate cost is reduced. Moreover, the array substrate does not need to be provided with an ITO (indium zinc oxide) layer in a binding area of the flexible circuit board so as to improve the adhesion with the flexible circuit board and improve the anti-oxidation effect, and the preparation process and the preparation cost of the array substrate can be reduced.

In step S150, referring to fig. 12 and 15, a second planarization layer 500 may be formed on a side of the electrode layer 400 away from the base substrate 100. The second planarization layer 500 may be formed with a plurality of via holes to expose a portion of the electrode layer 400 so that the exposed electrode layer 400 is electrically connected with the functional device 610. In some embodiments, the exposed electrode layer 400 is electrically connected to a circuit board or a driving chip. For example, the electrode layer includes a connection electrode and a bonding pad; the connection electrode includes a binding region and a connection region. The second planarization layer 500 may have third and fourth vias. The third via hole can expose the binding region of the connection electrode, so that the functional device is electrically connected with the connection electrode through the third via hole; the fourth via hole may expose the bonding pad so that the circuit board or the driving chip is electrically connected with the bonding pad through the fourth via hole.

Since the electrode layer 400 is provided with the first copper-nickel alloy layer 430, there is no need to worry that the copper electrode layer 410 will be oxidized, and therefore, there is no need to provide a passivation layer on the side of the electrode layer 400 away from the layer substrate, thereby avoiding the problem that the passivation layer covers the first planarization layer 300 to cause bubbling of the first planarization layer 300. Therefore, the processes of depositing the passivation layer, etching the passivation layer and the like can be saved, the production cycle of the array substrate is improved to improve the productivity and reduce the cost, and the quality of the array substrate can be improved.

Alternatively, in some embodiments, the second planarization layer 500 may be formed by a screen printing method. Therefore, the number of the mask plates can be reduced, and the preparation cost of the array substrate can be reduced.

In step S160, referring to fig. 12 and 15, a functional device layer 600 may be provided on a side of the protective layer away from the base substrate 100. The functional device layer 600 may contain an array of distributed functional devices 610, including, for example, light emitting devices for emitting light, ultrasonic emitting devices for emitting ultrasonic waves, heating devices for generating heat, or other current driven functional devices 610.

Alternatively, the functional device 610 may be a Micro light emitting diode (Micro LED) or a Mini light emitting diode (Mini LED); the functional device 610 may be connected to the electrode layer 400 by a bulk transfer technique and a binding process. Further, the functional device 610 may be electrically connected to the electrode layer 400 through a solder layer 700, and the solder layer 700 may include tin and indium. The connection of the functional device 610 to the electrode layer 400 may be realized by, for example, printing, soldering, die bonding, reflow soldering, or the like.

It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc., are all considered part of this disclosure.

The present disclosure also provides an array substrate, referring to fig. 12 and 15, the array substrate including:

a base substrate 100;

a metal wiring layer 200 provided on one side of the base substrate 100;

a first planarization layer 300 disposed on a side of the metal wiring layer 200 away from the substrate base plate 100;

an electrode layer 400 disposed on a side of the first planarization layer 300 away from the substrate base plate 100; the electrode layer 400 includes a copper electrode layer 410, a first buffer metal layer 420, and a first copper-nickel alloy layer 430 sequentially stacked on one side of the substrate base plate 100; the first buffer metal layer 420 is made of one or a mixture of molybdenum, molybdenum-niobium alloy, molybdenum-tungsten alloy, molybdenum-nickel-titanium alloy and molybdenum-magnesium-aluminum alloy;

a second planarization layer 500 provided on a side of the electrode layer 400 away from the base substrate 100;

the functional device layer 600 is disposed on a side of the second planarization layer 500 away from the substrate 100, and includes a plurality of functional devices 610 electrically connected to the electrode layer 400.

The array substrate provided by the present disclosure can be prepared by the preparation method of the array substrate described in the above preparation method embodiment of the present disclosure, and therefore, the same or similar beneficial effects are achieved, and the present disclosure is not repeated herein.

In one embodiment of the present disclosure, the electrode layer 400 further includes a second buffer metal layer 440 on the surface of the copper electrode layer 410 close to the substrate base plate 100.

In one embodiment of the present disclosure, the first buffer metal layer 420 and the first copper nickel alloy layer 430 cover a side surface of the copper electrode layer 410 and a surface of the copper electrode layer 410 away from the base substrate 100.

In one embodiment of the present disclosure, an orthographic projection of the first copper-nickel alloy layer 430 on the copper electrode layer 410 is located within the copper electrode layer 410.

In one embodiment of the present disclosure, the thickness of the first buffer metal layer 420 is 100 to 500 angstroms. Preferably, the thickness of the first buffer metal layer 420 is 200 to 500 angstroms.

In one embodiment of the present disclosure, the thickness of the first copper-nickel alloy layer 430 is 200 to 1000 angstroms. Preferably, the thickness of the first copper-nickel alloy layer 430 is 500 to 1000 angstroms.

In one embodiment of the present disclosure, the first copper-nickel alloy layer 430 has a nickel content of greater than 20% by weight. Preferably, the first copper-nickel alloy layer 430 contains nickel 30-80 wt%.

Other details and effects of the array substrate provided by the present disclosure have been described in the above embodiment of the method for manufacturing an array substrate, or can be clearly derived from the above description of the embodiment of the method for manufacturing an array substrate, and are not repeated herein.

Embodiments of the present disclosure also provide a display panel, which includes any one of the array substrates described in the above array substrate embodiments; the functional device 610 of the array substrate is a micro light emitting diode or a mini light emitting diode. The display panel may be a cell phone screen, a television screen, a smart watch screen, an electronic painted screen, an electronic billboard, or other type of display panel. Since the display panel has any one of the array substrates described in the above embodiments of the array substrate, the display panel has the same beneficial effects, and the details of the disclosure are not repeated herein. Preferably, the functional devices 610 on the array substrate include micro light emitting diodes or mini light emitting diodes of a plurality of different colors, for example, red micro light emitting diodes or mini light emitting diodes, blue micro light emitting diodes or mini light emitting diodes and blue micro light emitting diodes or mini light emitting diodes.

The embodiment of the present disclosure further provides a backlight module, which includes any one of the array substrates described in the above embodiments of the array substrate; the functional device 610 of the array substrate is a micro light emitting diode or a mini light emitting diode. The backlight module can be a backlight module of a mobile phone screen, a backlight module of a television screen, a backlight module of a computer screen or a backlight module of other types of liquid crystal display panels. Since the backlight module has any one of the array substrates described in the above embodiments of the array substrate, the same advantages are obtained, and details are not repeated in this disclosure. It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangements of the components set forth in the specification. The present disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.

Claims

1. A preparation method of an array substrate is characterized by comprising the following steps:

providing a substrate base plate;

forming a metal wiring layer on one side of the substrate base plate;

2. The method for preparing an array substrate according to claim 1, wherein the forming an electrode layer on a side of the first planarization layer away from the substrate comprises:

3. The method for preparing the array substrate according to claim 2, wherein the patterning of the copper electrode material layer comprises:

4. The method for preparing an array substrate according to claim 1, wherein the forming an electrode layer on a side of the first planarization layer away from the substrate comprises:

sequentially forming a copper electrode material layer, a first buffer metal material layer and a first copper-nickel alloy material layer on one side of the first planarization layer, which is far away from the substrate base plate; and carrying out a composition process on the copper electrode material layer, the first buffer metal material layer and the first copper-nickel alloy material layer to form the copper electrode layer, the first buffer metal layer and the first copper-nickel alloy layer.

5. The method for preparing an array substrate according to claim 1, wherein the forming an electrode layer on a side of the first planarization layer away from the substrate comprises:

6. An array substrate, comprising:

a substrate base plate;

a metal wiring layer provided on one side of the substrate base plate;

7. The array substrate of claim 6, wherein the electrode layer further comprises a second buffer metal layer on a surface of the copper electrode layer adjacent to the substrate base plate.

8. The array substrate of claim 6, wherein the first buffer metal layer and the first copper-nickel alloy layer cover a side surface of the copper electrode layer and a surface of the copper electrode layer away from the substrate base plate.

9. The array substrate of claim 6, wherein an orthographic projection of the first copper-nickel alloy layer on the copper electrode layer is located in the copper electrode layer.

10. The array substrate of claim 6, wherein the first buffer metal layer has a thickness of 100 to 500 angstroms.

11. The array substrate of claim 6, wherein the first copper-nickel alloy layer has a thickness of 200 to 1000 angstroms.

12. A display panel comprising the array substrate according to any one of claims 6 to 11; the functional device of the array substrate is a micro light-emitting diode or a mini light-emitting diode.

13. A backlight module comprising the array substrate of any one of claims 6 to 11; the functional device of the array substrate is a micro light-emitting diode or a mini light-emitting diode.