JPH04232922A - Production of liquid crystal display device - Google Patents

Production of liquid crystal display device

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Publication number
JPH04232922A
JPH04232922A JP2408673A JP40867390A JPH04232922A JP H04232922 A JPH04232922 A JP H04232922A JP 2408673 A JP2408673 A JP 2408673A JP 40867390 A JP40867390 A JP 40867390A JP H04232922 A JPH04232922 A JP H04232922A
Authority
JP
Japan
Prior art keywords
substrate
film
conductive oxide
liquid crystal
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2408673A
Other languages
Japanese (ja)
Inventor
Norio Nakatani
紀夫 中谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2408673A priority Critical patent/JPH04232922A/en
Publication of JPH04232922A publication Critical patent/JPH04232922A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To enable formation of large-size low-resistance wiring material at low cost compared to a conventional method and to supply stable signals by using a conductive oxide film as a part of the wiring material since the conductive oxide film is stable without increase in resistance against an oxygen atmosphere, and especially to obtain a good effect when a Cu film is used as a part of wiring material by adding characteristics required to a connecting area with a driving IC. CONSTITUTION:A wiring pattern 2 is formed with using a conductive oxide film material, on which a Cu single layer film or a multilayer film 10 containing at least one Cu layer is selectively deposited by plating. Further, a metal film 4' in the area not included by a counter electrode substrate and a substrate connecting sealing material is selectively removed by etching.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、アクティブマトリック
ス液晶表示装置の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an active matrix liquid crystal display device.

【0002】0002

【従来の技術】近年、マトリックス配置された多数の画
素単位の表示電極ごとにスイッチングトランジスタとし
て動作する薄膜トランジスタ(以下TFTと称する)を
結合し、このTFTを駆動回路としたアクティブマトリ
ックス液晶表示装置が開発されているが、この液晶装置
は、非常に軽くて薄いので携帯用としても壁掛け用とし
ても、CRTに替わる薄型表示装置として注目されてい
る。
[Prior Art] In recent years, active matrix liquid crystal display devices have been developed in which thin film transistors (hereinafter referred to as TFTs) operating as switching transistors are connected to each display electrode of a large number of pixels arranged in a matrix, and these TFTs are used as drive circuits. However, since this liquid crystal device is very light and thin, it is attracting attention as a thin display device that can be used as a replacement for CRT, whether it is portable or wall-mounted.

【0003】図5(a)に従来のアクティブマトリック
ス表示装置におけるTFTの画素単位の平面図を示し、
図5(b)に図5(a)のTFTのB−B’線に沿った
断面図を示す。
FIG. 5(a) shows a plan view of each pixel of a TFT in a conventional active matrix display device.
FIG. 5(b) shows a cross-sectional view of the TFT of FIG. 5(a) taken along line BB'.

【0004】図5(b)に示す如く、TFTは、液晶表
示装置の一方の透光性絶縁基板1上に形成され、ゲート
配線20に局部的に備えたゲート電極2、基板全面に設
けられたゲート絶縁膜3、島化された半導体膜4、該半
導体膜4のソース並びにドレイン位置の各々にオーミッ
クコンタクトを形成する不純物半導体膜5、ソース電極
7並びにドレイン電極6の積層体からなるいわゆる逆ス
タガ−タイプをなし、このソース電極7に表示電極8が
結合され、ドレイン電極6に表示信号を供給するドレイ
ン配線60が結合されている。
As shown in FIG. 5(b), a TFT is formed on one transparent insulating substrate 1 of a liquid crystal display device, and has a gate electrode 2 provided locally on a gate wiring 20 and a gate electrode 2 provided on the entire surface of the substrate. A so-called inverse stack consisting of a gate insulating film 3 formed into an island, a semiconductor film 4 formed into an island, an impurity semiconductor film 5 forming ohmic contacts at the source and drain positions of the semiconductor film 4, a source electrode 7, and a drain electrode 6, respectively. A display electrode 8 is connected to the source electrode 7, and a drain wiring 60 for supplying a display signal is connected to the drain electrode 6.

【0005】上述のごときアクティブマトリックス表示
装置のTFTアレーの各電極は、半導体プロセス技術を
用いて形成する。すなわち、電極形成用材料を蒸着,ス
パッタ,CVD等の方法で堆積後、フォトエッチングに
より微細加工することで形成する。
Each electrode of the TFT array of the above-mentioned active matrix display device is formed using semiconductor process technology. That is, the electrode forming material is deposited by a method such as vapor deposition, sputtering, or CVD, and then microfabricated by photoetching.

【0006】また、液晶表示装置は、高精細化並びに大
面積化という性能アップが望まれている。高精細化並び
に大面積化する場合、TFTアレーにおけるゲート信号
を供給するゲート配線と表示信号を供給するドレイン配
線の各配線抵抗を低減し、信号遅延を極力抑える必要が
ある。例えば、Cuの抵抗はAlの抵抗に比べて約0.
7倍と低く、加えてEM(Electro  Migr
ation)耐性が高いが、Cuの特性として、ガラス
(SiO2)、SiNx等の絶縁膜との密着性があまり
よくなく、又酸素雰囲気下でCu膜酸化が内部まで進行
し抵抗が増加するという問題があるため、ガラス基板上
にCu配線パターンを形成する場合等は、Cu膜の下層
には密着性向上のための他金属膜を、又Cu膜の上層に
は酸化防止用の他金属膜を形成する必要がある。その1
例として、「JAPAN  DISPLAY  CON
FERENSE,p502(1989)」において、T
a/Cu/T aで構成された低抵抗ゲート配線が提案
されている。
[0006] Furthermore, it is desired that the performance of liquid crystal display devices be improved by providing higher definition and larger area. When achieving higher definition and larger area, it is necessary to reduce the wiring resistance of the gate wiring for supplying gate signals and the drain wiring for supplying display signals in the TFT array, and to suppress signal delay as much as possible. For example, the resistance of Cu is about 0.0% compared to the resistance of Al.
It is as low as 7 times, and in addition, EM (Electro Migr
However, due to the characteristics of Cu, its adhesion with insulating films such as glass (SiO2) and SiNx is not very good, and the oxidation of the Cu film progresses to the inside in an oxygen atmosphere, increasing the resistance. Therefore, when forming a Cu wiring pattern on a glass substrate, it is necessary to use another metal film under the Cu film to improve adhesion, and over the Cu film to prevent oxidation. need to be formed. Part 1
For example, "JAPAN DISPLAY CON
FERENSE, p502 (1989), T.
A low resistance gate wiring made of a/Cu/Ta has been proposed.

【0007】ところが、この膜付けは、スパッタ等の高
価な装置を用いること、又スループットが低いことによ
り製造コストの増大の原因となっている。
[0007] However, this film deposition requires the use of expensive equipment such as sputtering and has a low throughput, resulting in an increase in manufacturing costs.

【0008】[0008]

【発明が解決しようとする課題】このようなTFT製造
のプロセスで使用する装置は、前述の如く高価であり又
スループットが低いため、アクティブ液晶表示装置特に
TFTアレ−の製造コスト増大の主要原因となっている
[Problems to be Solved by the Invention] As mentioned above, the equipment used in the TFT manufacturing process is expensive and has a low throughput, which is a major cause of increased manufacturing costs for active liquid crystal display devices, especially TFT arrays. It has become.

【0009】また、高精細化並びに大面積化する場合、
TFTアレーにおけるゲート信号を供給するゲート配線
と表示信号を供給するドレイン配線の各配線抵抗を低減
し、信号遅延を極力抑える必要がある。前述の理由によ
り従来の製造方法では高価であり又大面積パターンにな
るほど製造コストが高くなるという課題がある。
[0009] Furthermore, when increasing the definition and area,
It is necessary to reduce the wiring resistance of the gate wiring for supplying gate signals and the drain wiring for supplying display signals in the TFT array, and to suppress signal delay as much as possible. For the above-mentioned reasons, conventional manufacturing methods are expensive, and the larger the area pattern, the higher the manufacturing cost.

【0010】さらに、酸素雰囲気下でCu膜酸化が内部
まで進行し抵抗が増加するという問題もある。
[0010] Furthermore, there is a problem that oxidation of the Cu film progresses to the inside in an oxygen atmosphere, resulting in an increase in resistance.

【0011】[0011]

【課題を解決しようとするための手段】本発明の液晶表
示装置の製造方法は、一方の透光性絶縁基板上に複数の
ゲート配線と複数のドレイン配線との各交差部に薄膜ト
ランジスタを配し、該各薄膜トランジスタを介して各々
ドレイン配線に結合される表示電極を備えた表示電極基
板と、他方の透光性絶縁基板上に該表示電極に対向した
位置に対向電極を備えた対向電極基板と、前記両電極基
板間に注入された液晶物質とからなる液晶表示装置にお
いて、導電性酸化物で該ゲート配線を形成後、該導電性
酸化物上に選択的にメッキ法にて金属を堆積することで
、導電性酸化物と金属膜で構成されるゲート配線を形成
するものである。
[Means for Solving the Problems] A method for manufacturing a liquid crystal display device of the present invention includes disposing thin film transistors at each intersection of a plurality of gate wirings and a plurality of drain wirings on one transparent insulating substrate. , a display electrode substrate provided with a display electrode coupled to each drain wiring via the respective thin film transistors, and a counter electrode substrate provided with a counter electrode at a position opposite to the display electrode on the other transparent insulating substrate. In a liquid crystal display device comprising a liquid crystal material injected between both electrode substrates, after forming the gate wiring with a conductive oxide, metal is selectively deposited on the conductive oxide by a plating method. This forms a gate wiring made of a conductive oxide and a metal film.

【0012】また、一方の透光性絶縁基板上に複数のゲ
ート配線と複数のドレイン配線との各交差部に薄膜トラ
ンジスタを配し、該各薄膜トランジスタを介して各々ド
レイン配線に結合される表示電極を備えた表示電極基板
と、他方の透光性絶縁基板上に該表示電極に対向する位
置に対向電極を備えた対向電極基板と、前記両電極基板
間に挿入された液晶物質とからなる液晶表示装置におい
て、導電性酸化物で該ドレイン配線を形成後、該導電性
酸化物上に選択的にメッキ法にて金属を堆積することで
、導電性酸化物と金属膜で構成されるドレイン配線を形
成するものである。
Furthermore, thin film transistors are arranged on one light-transmitting insulating substrate at each intersection of a plurality of gate wirings and a plurality of drain wirings, and a display electrode is connected to each drain wiring through each of the thin film transistors. a counter electrode substrate having a counter electrode on the other transparent insulating substrate at a position opposite to the display electrode, and a liquid crystal material inserted between the two electrode substrates. In the device, after forming the drain wiring with a conductive oxide, metal is selectively deposited on the conductive oxide using a plating method, thereby forming a drain wiring composed of a conductive oxide and a metal film. It is something that forms.

【0013】さらに、メッキ法で形成する金属膜がCu
単層膜、又はCuを少なくとも1層含む多層膜からなる
ものである。
Furthermore, the metal film formed by the plating method is Cu.
It consists of a single layer film or a multilayer film containing at least one layer of Cu.

【0014】さらにまた、対向電極基板と基板接続用シ
ール剤から露出した領域の金属膜を選択的にエッチング
除去することで、対向電極基板と基板接続用シール剤で
覆われた領域の表示電極基板上のゲート配線のみ導電性
酸化物と金属膜で構成され、対向電極基板と基板接続用
シール剤から露出した領域の表示電極基板上のゲート配
線が導電性酸化物で構成するものである。
Furthermore, by selectively etching and removing the metal film in the area exposed from the sealant for connecting the counter electrode substrate and the substrates, the display electrode substrate in the area covered with the sealant for connecting the counter electrode substrate and the substrates can be removed. Only the upper gate wiring is made of a conductive oxide and a metal film, and the gate wiring on the display electrode substrate in the area exposed from the counter electrode substrate and the substrate connection sealant is made of a conductive oxide.

【0015】加えて、対向電極基板と基板接続用シール
剤から露出した領域の金属膜を選択的にエッチング除去
することで、対向電極基板と基板接続用シール剤で覆わ
れた領域の表示電極基板上のドレイン配線のみ導電性酸
化物と金属膜で構成され、対向電極基板と基板接続用シ
ール剤から露出した領域の表示電極基板上のドレイン配
線が導電性酸化物で構成するものである。
In addition, by selectively etching and removing the metal film in the area exposed from the sealant for connecting the counter electrode substrate and the substrate, the area covered by the sealant for connecting the counter electrode substrate and the display electrode substrate can be removed. Only the upper drain wiring is made of a conductive oxide and a metal film, and the drain wiring on the display electrode substrate in the area exposed from the counter electrode substrate and the substrate connection sealant is made of a conductive oxide.

【0016】[0016]

【作用】本発明によれば、メッキ法を用いることにより
、低抵抗配線材料であるCu膜等の金属膜を容易に安価
で量産性が高い膜の堆積が可能であるので、装置コスト
の増加を抑えて大面積成膜が容易となる。それゆえ、従
来法に比べて低コストで低抵抗配線材料を大面積形成す
ることが可能となる。又、導電性酸化膜は酸素雰囲気下
においても、抵抗増加のない安定な材料であるため、配
線材料の一部とすることで安定な信号供給が可能となり
、特に駆動用ICとの接続領域において信頼性の高い接
着性をもたらす。
[Function] According to the present invention, by using a plating method, it is possible to easily deposit a metal film such as a Cu film, which is a low resistance wiring material, at low cost and with high mass productivity, thereby increasing equipment costs. This makes it easy to form a film over a large area. Therefore, it is possible to form a large area of low-resistance wiring material at a lower cost than in the conventional method. In addition, the conductive oxide film is a stable material that does not increase resistance even in an oxygen atmosphere, so using it as part of the wiring material enables stable signal supply, especially in the connection area with the drive IC. Provides reliable adhesion.

【0017】[0017]

【実施例】図1に本発明の製造方法によって得られるア
クティブマトリックス液晶表示装置のTFTアレ−の画
素単位の平面図を示し、図1のB−B’線に沿った各製
造工程の断面図を図2(i)乃至(vi)に示す。以下
、図2に従って本発明の製造 方法について説明する。
[Example] Fig. 1 shows a plan view of each pixel of a TFT array of an active matrix liquid crystal display device obtained by the manufacturing method of the present invention, and sectional views of each manufacturing process along line BB' in Fig. 1. are shown in FIGS. 2(i) to (vi). The manufacturing method of the present invention will be explained below with reference to FIG.

【0018】第1工程[図2(i)]ITO、In2O
3、SnO2、ZnO、Cd2SnO4等の導電性酸化
膜材料か らなるゲート電極2及び該ゲート電極2が局
部的に備えられたゲート配線20とを形成する。
First step [FIG. 2(i)] ITO, In2O
3. A gate electrode 2 made of a conductive oxide film material such as SnO2, ZnO, Cd2SnO4, etc. and a gate wiring 20 locally provided with the gate electrode 2 are formed.

【0019】ここで、チャネル部を遮光するために導電
性酸化膜材料のゲート電極は透光性であるのでゲート電
極を不透明にする必要がある。
Here, since the gate electrode made of a conductive oxide film material is transparent in order to shield the channel portion from light, it is necessary to make the gate electrode opaque.

【0020】第2工程[図2(ii)]そこで、前記導
電性酸化膜材料で形成されたゲート配線20及びゲート
配線20に電気的に接続しているゲート電極2にメッキ
法にて金属膜10を堆積する。この工程によりゲート配
線20の低抵抗化とゲート電極2の不透明化が実現され
る。このメッキする金属膜10の材料としては、Au、
Cu、Ni、Pd、Ag、Pt、In、Ru、Rh、C
r、Sn、Pb、Sn−Pb(半田)、Zn、Co、F
e等の金属が堆積可能である。このような金属膜の中で
、低抵抗且つ低コストという観点ではCuが最も優れて
いる。しかしながら、Cuは導電性酸化膜材料との密着
性があまりよくなく、Cu膜と導電性酸化膜材料との間
に他金属膜を介在させると更に密着性が向上する。その
介在させる金属膜としては、Ni、In、Sn、Pb、
Sn−Pb(半田)、Zn、Co、Cr等の金属が優れ
ている。又、Cu膜は酸化しやすいので、酸化防止用の
他金属膜例えばAu、Pt、Pd、Cr、Ni等の金属
をCu膜上に堆積してもよい。このようにメッキ法で堆
積する金属膜は単層膜でもよく、多層膜でもよい。 又導電性酸化膜上に堆積する金属膜はCuに限定するも
のではなく、メッキ法で導電性酸化膜上に堆積でき且つ
配線抵抗を下げる材料であればよい。メッキ法としては
電解メッキ法と無電解メッキ法が適用可能である。
Second step [FIG. 2(ii)] Then, a metal film is formed by plating on the gate wiring 20 formed of the conductive oxide film material and the gate electrode 2 electrically connected to the gate wiring 20. Deposit 10. Through this step, the resistance of the gate wiring 20 can be reduced and the gate electrode 2 can be made opaque. The material of the metal film 10 to be plated includes Au,
Cu, Ni, Pd, Ag, Pt, In, Ru, Rh, C
r, Sn, Pb, Sn-Pb (solder), Zn, Co, F
Metals such as e can be deposited. Among such metal films, Cu is the most excellent in terms of low resistance and cost. However, Cu does not have very good adhesion to the conductive oxide film material, and the adhesion is further improved if another metal film is interposed between the Cu film and the conductive oxide film material. The intervening metal film includes Ni, In, Sn, Pb,
Metals such as Sn-Pb (solder), Zn, Co, and Cr are excellent. Further, since the Cu film is easily oxidized, other metal films for preventing oxidation, such as Au, Pt, Pd, Cr, Ni, etc., may be deposited on the Cu film. The metal film deposited by plating in this manner may be a single layer film or a multilayer film. Further, the metal film deposited on the conductive oxide film is not limited to Cu, but any material can be used as long as it can be deposited on the conductive oxide film by a plating method and lowers the wiring resistance. As the plating method, electrolytic plating method and electroless plating method can be applied.

【0021】第3工程[図2(iii)]第1絶縁膜3
(ゲート絶縁膜),半導体膜4,第2絶縁膜5(パッシ
ベ−ション絶縁膜)をプラズマCVD等により連続的に
堆積し、第2絶縁膜5を島化する。
Third step [FIG. 2(iii)] First insulating film 3
(gate insulating film), semiconductor film 4, and second insulating film 5 (passivation insulating film) are successively deposited by plasma CVD or the like, and the second insulating film 5 is formed into an island.

【0022】第4工程[図2(iv)]プラズマCVD
により不純物半導体膜4’を堆積した後、半導体膜4と
不純物半導体膜4’を島化する。
Fourth step [FIG. 2(iv)] Plasma CVD
After depositing the impurity semiconductor film 4', the semiconductor film 4 and the impurity semiconductor film 4' are formed into islands.

【0023】第5工程[図2(v)]ITO、In2O
3、SnO2、ZnO、Cd2SnO4等の導電性酸化
膜材料を 堆積し、該導電性酸化膜材料によりドレイン
電極6と、ソ−ス電極7と、表示電極8と、ドレイン配
線60とを同時に形成する。その後、チャネル部の不純
物半導体膜4’をエッチング除去する。
Fifth step [FIG. 2(v)] ITO, In2O
3. Deposit a conductive oxide film material such as SnO2, ZnO, Cd2SnO4, etc., and simultaneously form the drain electrode 6, source electrode 7, display electrode 8, and drain wiring 60 using the conductive oxide film material. . Thereafter, the impurity semiconductor film 4' in the channel portion is removed by etching.

【0024】第6工程[図2(vi)]導電性酸化膜で
形成したドレイン配線60及びドレイン配線60に電気
的に接続しているドレイン電極6にメッキ法にて金属膜
11を堆積する。このメッキする金属膜11の材料とし
ては、高精細化並びに大面積化する場合、TFTアレー
におけるゲート信号を供給するゲート配線と表示信号を
供給するドレイン配線の各配線抵抗を低減し、信号遅延
を極力抑える必要があるので、Au、Cu、Ni、Pd
、Ag、Pt、In、Ru、Rh、Cr、Sn、Pb、
Sn−Pb(半田)、Zn、Co、Fe等の金属が堆積
可能である。このような金属の中で、低抵抗且つ低コス
トという観点ではCuが最も優れている。Cuの抵抗は
Alの抵抗に比べて約0.7倍と低く、加えてEM(E
lectro  Migration)耐性が高い。し
かしながら、Cu膜はガラス(SiO2)、SiNx等
の絶縁膜との密着性がよくないので、図2(vi)に示
す如く、ITO膜で形成したドレイン電極6及びドレイ
ン配線60とCu膜11との間に他金属膜12を介在さ
せると密着性が向上する。その介在させる金属膜12の
材料としては、Ni、In、Sn、Pb、Sn−Pb(
半田)、Zn、Co、Cr等の金属が優れている。又、
酸素雰囲気下でCu膜酸化が内部まで進行し抵抗が増加
するという問題があるため、酸化防止用の他金属膜例え
ばAu、Pt、Pd、Cr、Ni等の金属をCu膜上に
堆積してもよい。このように堆積する金属膜は単層膜で
もよく、多層膜でもよい。又導電性酸化膜上に堆積する
金属膜はCuに限定するものではなく、前述の如くメッ
キ法で導電性酸化膜上に堆積でき且つ配線抵抗を下げる
材料であればよい。
Sixth step [FIG. 2(vi)] A metal film 11 is deposited by plating on the drain wiring 60 formed of a conductive oxide film and the drain electrode 6 electrically connected to the drain wiring 60. The material for the metal film 11 to be plated should be selected to reduce the wiring resistance of the gate wiring for supplying gate signals and the drain wiring for supplying display signals in the TFT array, and to reduce signal delay when achieving high definition and large area. Au, Cu, Ni, Pd must be suppressed as much as possible.
, Ag, Pt, In, Ru, Rh, Cr, Sn, Pb,
Metals such as Sn--Pb (solder), Zn, Co, and Fe can be deposited. Among these metals, Cu is the most superior in terms of low resistance and cost. The resistance of Cu is about 0.7 times lower than that of Al, and in addition, the resistance of Cu is about 0.7 times lower than that of Al.
(electro migration) resistance. However, since the Cu film does not have good adhesion to insulating films such as glass (SiO2) and SiNx, as shown in FIG. Adhesion is improved by interposing another metal film 12 between them. The intervening metal film 12 is made of Ni, In, Sn, Pb, Sn-Pb (
Solder), metals such as Zn, Co, and Cr are excellent. or,
Since there is a problem that the Cu film oxidation progresses to the inside in an oxygen atmosphere and the resistance increases, other metal films for preventing oxidation, such as Au, Pt, Pd, Cr, Ni, etc., are deposited on the Cu film. Good too. The metal film deposited in this manner may be a single layer film or a multilayer film. Further, the metal film deposited on the conductive oxide film is not limited to Cu, but any material can be used as long as it can be deposited on the conductive oxide film by the plating method as described above and lowers the wiring resistance.

【0025】メッキ法としては電解メッキ法が適してい
る。無電解メッキ法も適用可能であるが、その場合は金
属膜を堆積しない領域をレジストでコーテイングする必
要がある。すなわち、無電解メッキ法を適用する場合は
、マスク工程が1工程付加されることになる。又電解メ
ッキ法を適用する場合は、チャネル部の不純物半導体膜
4’を前もってエッチング除去する必要がある。チャネ
ル部に不純物半導体膜4’が存在すると、ソース電極7
と表示電極8の導電性酸化膜上にも金属膜10が堆積し
、好ましくない。
[0025] As the plating method, electrolytic plating is suitable. Electroless plating can also be applied, but in that case it is necessary to coat the areas where the metal film is not deposited with a resist. That is, when electroless plating is applied, one mask process is added. Further, when electrolytic plating is applied, it is necessary to remove the impurity semiconductor film 4' in the channel portion by etching in advance. When the impurity semiconductor film 4' is present in the channel part, the source electrode 7
The metal film 10 is also deposited on the conductive oxide film of the display electrode 8, which is undesirable.

【0026】図3に、前記プロセスで作成したアクティ
ブマトリックス基板30の平面図を示す。図3において
、走査線20(ゲート配線)、信号線60(ドレイン配
線)、駆動ICを実装するゲート端子21とドレイン端
子61の端子電極、走査線20と信号線60の交点のT
FT13、及び該TFT13のソース電極7に連結して
なる表示電極8で構成される。図3のアクティブマトリ
ックス基板30に対向電極基板40を貼り合わせ、液晶
を注入して、アクティブ液晶表示パネルが完成する。 完成したアクティブ液晶表示パネルの平面図を図4に示
す。ところが、走査線20又は信号線60の構成材料に
金属膜を使用した場合、酸素(空気)と接触する領域で
は金属膜が酸化し配線抵抗が変化するという不都合が発
生する。この傾向は特にCu膜に著しく、Al,Cr等
の金属では表面に安定な不動態被膜(酸化膜)を形成し
酸化が内部に進行しにくく、酸化の影響は少ない。Cu
膜を配線材料に使用し、且つCu表面に酸化防止用他金
属膜をコーティングしない場合はこの酸化による影響を
なくす必要がある。酸化の影響を受ける領域は駆動用I
Cを実装する端子電極21,61であり、対向電極基板
及び貼り合わせ用樹脂(シ−ル剤)でコーティングされ
ている領域より内側の領域は酸素が遮断されるので酸化
の影響は考慮しなくてよい。すなわち図4において対向
電極基板より内側の領域(TFT領域)はCu膜の酸化
は発生せず、対向電極基板より外側の領域にCu膜の酸
化が発生する。この対策として■Cu膜上に樹脂をコー
ティングし酸素の進入を遮断する,■Cu膜上に酸化防
止用他金属膜(Au,Ptなど)をコーティングする,
■Cu膜をエッチング除去し導電性酸化物層を露出させ
る(導電性酸化物は酸化の影響を受けない)等が考えら
れるが、検討した結果■の方法が最も簡単で効果があっ
た。■は、アクティブマトリックス基板30に対向電極
基板40を貼り合わせ、液晶を注入して、図3に示す液
晶表示パネルを完成した後、基板をCuの腐食性ガスま
たはエッチング液で処理することでCu膜をエッチング
除去すればよく、簡単な方法でCu膜の酸化の影響を排
除できる。■の方法では駆動用ICと接続する端子電極
21,61のみが導電性酸化膜で構成されることになる
FIG. 3 shows a plan view of the active matrix substrate 30 produced by the above process. In FIG. 3, the scanning line 20 (gate wiring), the signal line 60 (drain wiring), the terminal electrodes of the gate terminal 21 and the drain terminal 61 on which the driving IC is mounted, and the T at the intersection of the scanning line 20 and the signal line 60
It is composed of an FT 13 and a display electrode 8 connected to the source electrode 7 of the TFT 13. A counter electrode substrate 40 is bonded to the active matrix substrate 30 of FIG. 3, and liquid crystal is injected to complete an active liquid crystal display panel. A plan view of the completed active liquid crystal display panel is shown in FIG. However, when a metal film is used as the constituent material of the scanning line 20 or the signal line 60, the problem arises that the metal film oxidizes in areas that come into contact with oxygen (air), resulting in a change in wiring resistance. This tendency is particularly noticeable in Cu films, and metals such as Al and Cr form a stable passive film (oxide film) on the surface, making it difficult for oxidation to progress inside, and the influence of oxidation is small. Cu
When a film is used as a wiring material and the Cu surface is not coated with another metal film for oxidation prevention, it is necessary to eliminate the effects of this oxidation. The area affected by oxidation is the drive I
These are the terminal electrodes 21 and 61 that mount C, and the area inside the area coated with the counter electrode substrate and the bonding resin (sealant) is blocked from oxygen, so the effect of oxidation is not considered. It's fine. That is, in FIG. 4, oxidation of the Cu film does not occur in the region inside the counter electrode substrate (TFT region), but oxidation of the Cu film occurs in the region outside the counter electrode substrate. As a countermeasure, ■Coating a resin on the Cu film to block the ingress of oxygen, ■Coating other metal films (Au, Pt, etc.) on the Cu film to prevent oxidation.
(2) Etching away the Cu film to expose the conductive oxide layer (conductive oxide is not affected by oxidation) is a possible method, but as a result of investigation, method (2) was found to be the simplest and most effective. In (2), after bonding the counter electrode substrate 40 to the active matrix substrate 30 and injecting liquid crystal to complete the liquid crystal display panel shown in FIG. It is sufficient to remove the film by etching, and the influence of oxidation on the Cu film can be eliminated by a simple method. In method (2), only the terminal electrodes 21, 61 connected to the driving IC are made of a conductive oxide film.

【0027】当然であるが、■乃至■の方法は酸化の影
響を受けやすい金属を配線材料の一部に使用した場合に
適用可能であり、メッキ法で金属膜を形成した場合に限
定するものではない。特に、Cu膜を配線材料の一部に
使用する場合は導電性酸化膜を付加し、対向電極基板4
0から露出した駆動用ICと接続する端子電極部のみC
u膜をエッチング除去する方法が最も効果的である。
Naturally, the methods (1) to (2) are applicable when metals that are susceptible to oxidation are used as part of the wiring material, and are limited to cases where a metal film is formed by plating. isn't it. In particular, when a Cu film is used as part of the wiring material, a conductive oxide film is added to the counter electrode substrate 4.
Only the terminal electrode part connected to the drive IC exposed from 0C
The most effective method is to remove the U film by etching.

【0028】[0028]

【発明の効果】以上の説明から明らかなように、本発明
の製造方法によれば、導電性酸化膜で形成した配線パタ
ーン上にメッキ法で金属膜(特にCu)を堆積するので
、従来法のフォトエッチングに比べて、低抵抗配線材料
である金属膜を低製造コストで形成することが可能とな
る。さらに、導電性酸化膜でドレイン配線、ドレイン電
極、ソース電極及び表示電極を形成した対向電極基板及
び基板接続用シール剤から露出した領域を有する表示電
極基板上のゲート配線及びドレイン配線を導電性酸化物
で構成することで酸化雰囲気下で安定な信号供給が可能
となる。
Effects of the Invention As is clear from the above explanation, according to the manufacturing method of the present invention, a metal film (particularly Cu) is deposited by a plating method on a wiring pattern formed of a conductive oxide film. Compared to photo-etching, it is possible to form a metal film, which is a low-resistance wiring material, at a lower manufacturing cost. Furthermore, conductive oxide was applied to the gate wiring and drain wiring on the counter electrode substrate on which the drain wiring, drain electrode, source electrode, and display electrode were formed using a conductive oxide film, and on the display electrode substrate that had areas exposed from the substrate connection sealant. By configuring it with a material, it is possible to provide a stable signal in an oxidizing atmosphere.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】(a)に本発明によって得られる表示装置のT
FT部の平面図であり、(b)は本発明によって得られ
る表示装置のTFT部の断面図である。
FIG. 1 (a) shows T of a display device obtained by the present invention.
FIG. 3B is a plan view of the FT section, and FIG. 3B is a cross-sectional view of the TFT section of the display device obtained by the present invention.

【図2】図1(a)のB−B’線に沿った各製造工程の
断面図である。
FIG. 2 is a cross-sectional view of each manufacturing process taken along line BB' in FIG. 1(a).

【図3】本発明製造工程で製造したアクティブマトリッ
クス基板の平面図である。
FIG. 3 is a plan view of an active matrix substrate manufactured by the manufacturing process of the present invention.

【図4】本発明によって得られる液晶表示パネルの平面
図である。
FIG. 4 is a plan view of a liquid crystal display panel obtained by the present invention.

【図5】従来の表示装置のTFT部の断面図である。FIG. 5 is a cross-sectional view of a TFT section of a conventional display device.

【符号の説明】[Explanation of symbols]

1  絶縁性基板 2  ゲート電極 3  ゲート絶縁膜 4  半導体膜 4’  不純物半導体膜 5  パッシベ−ション絶縁膜 6  ドレイン電極 7  ソース電極 8  表示電極 10  ゲート配線の一部を成す金属膜11  ゲート
配線の一部を成す金属膜13  TFT 20  ゲート配線 21  ゲート端子電極 30  アクティブマトリックス基板 40  対向電極基板 60  ドレイン配線 61  ドレイン端子電極
1 Insulating substrate 2 Gate electrode 3 Gate insulating film 4 Semiconductor film 4' Impurity semiconductor film 5 Passivation insulating film 6 Drain electrode 7 Source electrode 8 Display electrode 10 Metal film 11 forming part of gate wiring Part of gate wiring Metal film 13 TFT 20 Gate wiring 21 Gate terminal electrode 30 Active matrix substrate 40 Counter electrode substrate 60 Drain wiring 61 Drain terminal electrode

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】  一方の透光性絶縁基板上に複数のゲー
ト配線と複数のドレイン配線との各交差部に薄膜トラン
ジスタを配し、該各薄膜トランジスタを介して各々ドレ
イン配線に結合される表示電極を備えた表示電極基板と
、他方の透光性絶縁基板上に該表示電極に対向した位置
に対向電極を備えた対向電極基板と、前記両電極基板間
に注入された液晶物質とからなる液晶表示装置において
、導電性酸化物で該ゲート配線を形成後、該導電性酸化
物上に選択的にメッキ法にて金属を堆積することで、導
電性酸化物と金属膜で構成されるゲート配線を形成する
ことを特徴とした液晶表示装置の製造方法。
1. Thin film transistors are arranged at each intersection of a plurality of gate wirings and a plurality of drain wirings on one light-transmitting insulating substrate, and a display electrode is connected to each drain wiring through each thin film transistor. A liquid crystal display comprising: a display electrode substrate provided with a display electrode; a counter electrode substrate provided with a counter electrode on the other transparent insulating substrate at a position opposite to the display electrode; and a liquid crystal substance injected between the two electrode substrates. In the device, after forming the gate wiring with a conductive oxide, metal is selectively deposited on the conductive oxide using a plating method, thereby forming a gate wiring composed of a conductive oxide and a metal film. 1. A method of manufacturing a liquid crystal display device, characterized by forming a liquid crystal display device.
【請求項2】  一方の透光性絶縁基板上に複数のゲー
ト配線と複数のドレイン配線との各交差部に薄膜トラン
ジスタを配し、該各薄膜トランジスタを介して各々ドレ
イン配線に結合される表示電極を備えた表示電極基板と
、他方の透光性絶縁基板上に該表示電極に対向する位置
に対向電極を備えた対向電極基板と、前記両電極基板間
に挿入された液晶物質とからなる液晶表示装置において
、導電性酸化物で該ドレイン配線を形成後、該導電性酸
化物上に選択的にメッキ法にて金属を堆積することで、
導電性酸化物と金属膜で構成されるドレイン配線を形成
することを特徴とした液晶表示装置の製造方法。
2. Thin film transistors are disposed at each intersection of a plurality of gate wirings and a plurality of drain wirings on one light-transmitting insulating substrate, and a display electrode is connected to each drain wiring through each thin film transistor. a counter electrode substrate having a counter electrode on the other transparent insulating substrate at a position opposite to the display electrode, and a liquid crystal material inserted between the two electrode substrates. In the device, after forming the drain wiring with a conductive oxide, metal is selectively deposited on the conductive oxide by a plating method,
A method for manufacturing a liquid crystal display device, comprising forming a drain wiring made of a conductive oxide and a metal film.
【請求項3】  メッキ法で形成する金属膜がCu単層
膜、又はCuを少なくとも1層含む多層膜からなること
を特徴とする請求項1の液晶表示装置の製造方法。
3. The method of manufacturing a liquid crystal display device according to claim 1, wherein the metal film formed by the plating method is a Cu single layer film or a multilayer film containing at least one layer of Cu.
【請求項4】  メッキ法で形成する金属膜がCu単層
膜、又はCuを少なくとも1層含む多層膜からなること
を特徴とする請求項2の液晶表示装置の製造方法。
4. The method of manufacturing a liquid crystal display device according to claim 2, wherein the metal film formed by the plating method is a Cu single layer film or a multilayer film containing at least one layer of Cu.
【請求項5】  対向電極基板と基板接続用シール剤か
ら露出した領域の金属膜を選択的にエッチング除去する
ことで、対向電極基板と基板接続用シール剤で覆われた
領域の表示電極基板上のゲート配線のみ導電性酸化物と
金属膜で構成され、対向電極基板と基板接続用シール剤
から露出した領域の表示電極基板上のゲート配線が導電
性酸化物で構成することを特徴とする請求項1の液晶表
示装置の製造方法。
5. By selectively etching and removing the metal film in the area exposed from the counter electrode substrate and the sealant for connecting the substrate, the area on the display electrode substrate covered by the sealant for connecting the counter electrode substrate and the substrate is removed. A claim characterized in that only the gate wiring is made of a conductive oxide and a metal film, and the gate wiring on the display electrode substrate in the area exposed from the counter electrode substrate and the sealant for connecting the substrate is made of a conductive oxide. Item 1. Method for manufacturing a liquid crystal display device.
【請求項6】  対向電極基板と基板接続用シール剤か
ら露出した領域の金属膜を選択的にエッチング除去する
ことで、対向電極基板と基板接続用シール剤で覆われた
領域の表示電極基板上のドレイン配線のみ導電性酸化物
と金属膜で構成され、対向電極基板と基板接続用シール
剤から露出した領域の表示電極基板上のドレイン配線が
導電性酸化物で構成することを特徴とする請求項2の液
晶表示装置の製造方法。
6. By selectively etching and removing the metal film in the area exposed from the counter electrode substrate and the substrate connection sealant, the display electrode substrate in the area covered with the counter electrode substrate and the substrate connection sealant is removed. A claim characterized in that only the drain wiring is made of a conductive oxide and a metal film, and the drain wiring on the display electrode substrate in the area exposed from the counter electrode substrate and the sealant for connecting the substrate is made of a conductive oxide. Item 2. Method for manufacturing a liquid crystal display device.
JP2408673A 1990-12-28 1990-12-28 Production of liquid crystal display device Pending JPH04232922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2408673A JPH04232922A (en) 1990-12-28 1990-12-28 Production of liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2408673A JPH04232922A (en) 1990-12-28 1990-12-28 Production of liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH04232922A true JPH04232922A (en) 1992-08-21

Family

ID=18518096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2408673A Pending JPH04232922A (en) 1990-12-28 1990-12-28 Production of liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH04232922A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6518676B2 (en) 2000-05-25 2003-02-11 Sharp Kabushiki Kaisha Metal interconnections and active matrix substrate using the same
JP2003100750A (en) * 2001-09-20 2003-04-04 Semiconductor Energy Lab Co Ltd Semiconductor device and method of fabricating the same
US6720211B2 (en) 1999-05-18 2004-04-13 Sharp Kabushiki Kaisha Method for fabricating electric interconnections and interconnection substrate having electric interconnections fabricated by the same method
JP2004514950A (en) * 2000-12-02 2004-05-20 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Pixelation devices such as active matrix liquid crystal displays
US6798032B2 (en) 2001-05-22 2004-09-28 Sharp Kabushiki Kaisha Metal film pattern and manufacturing method thereof
US6864936B2 (en) 2000-02-25 2005-03-08 Sharp Kabushiki Kaisha Active matrix substrate, method of manufacturing the same, and display and image-capturing devices utilizing the same
JP2005354049A (en) * 2004-05-12 2005-12-22 Nichia Chem Ind Ltd Semiconductor laser device
JP2011195893A (en) * 2010-03-19 2011-10-06 Ishihara Chem Co Ltd Electrolytic copper-plating method
WO2011148409A1 (en) * 2010-05-24 2011-12-01 パナソニック株式会社 Thin film semiconductor device, display device, and process for production of thin film semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6720211B2 (en) 1999-05-18 2004-04-13 Sharp Kabushiki Kaisha Method for fabricating electric interconnections and interconnection substrate having electric interconnections fabricated by the same method
US6750475B1 (en) 1999-05-18 2004-06-15 Sharp Kabushiki Kaisha Method for fabricating electric interconnections and interconnection substrate having electric interconnections fabricated by the same method
US6864936B2 (en) 2000-02-25 2005-03-08 Sharp Kabushiki Kaisha Active matrix substrate, method of manufacturing the same, and display and image-capturing devices utilizing the same
US6518676B2 (en) 2000-05-25 2003-02-11 Sharp Kabushiki Kaisha Metal interconnections and active matrix substrate using the same
JP2004514950A (en) * 2000-12-02 2004-05-20 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Pixelation devices such as active matrix liquid crystal displays
US6798032B2 (en) 2001-05-22 2004-09-28 Sharp Kabushiki Kaisha Metal film pattern and manufacturing method thereof
JP2003100750A (en) * 2001-09-20 2003-04-04 Semiconductor Energy Lab Co Ltd Semiconductor device and method of fabricating the same
JP2005354049A (en) * 2004-05-12 2005-12-22 Nichia Chem Ind Ltd Semiconductor laser device
JP2011195893A (en) * 2010-03-19 2011-10-06 Ishihara Chem Co Ltd Electrolytic copper-plating method
WO2011148409A1 (en) * 2010-05-24 2011-12-01 パナソニック株式会社 Thin film semiconductor device, display device, and process for production of thin film semiconductor device

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