WO2011148409A1 - Thin film semiconductor device, display device, and process for production of thin film semiconductor device - Google Patents

Thin film semiconductor device, display device, and process for production of thin film semiconductor device Download PDF

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Publication number
WO2011148409A1
WO2011148409A1 PCT/JP2010/003463 JP2010003463W WO2011148409A1 WO 2011148409 A1 WO2011148409 A1 WO 2011148409A1 JP 2010003463 W JP2010003463 W JP 2010003463W WO 2011148409 A1 WO2011148409 A1 WO 2011148409A1
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Prior art keywords
electrode
transistor
thin film
wiring
semiconductor device
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PCT/JP2010/003463
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French (fr)
Japanese (ja)
Inventor
鐘ヶ江有宣
堀田定吉
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パナソニック株式会社
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Priority to PCT/JP2010/003463 priority Critical patent/WO2011148409A1/en
Publication of WO2011148409A1 publication Critical patent/WO2011148409A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • the present invention relates to a thin film semiconductor device for a display device in which thin film transistors having a semiconductor as an active layer are integrally formed on a substrate, and a display device using the thin film semiconductor device for the display device.
  • display devices such as organic EL displays and liquid crystal displays have become larger screens with the progress of manufacturing process technology, and customer needs are suitable for display devices with large screens and high image quality.
  • display devices which are drive substrates for display devices
  • development for higher performance is being carried out.
  • a thin film transistor mounted on the thin film semiconductor device for a display device is required to have a high current drive capability.
  • those using a semiconductor thin film (polycrystalline silicon, microcrystalline silicon, etc.) crystallized in the active layer are attracting attention.
  • a thin film transistor used in a thin film semiconductor device for a display device has a structure of a field effect transistor including a gate electrode, a source electrode, and a drain electrode, a gate insulating film, and a semiconductor layer. These electrodes are each wired with a conductor (mostly metal or metal oxide) to drive the thin film transistor. These wirings are formed in a matrix of m rows ⁇ n columns on the substrate, and each wiring intersects three-dimensionally with an insulating layer interposed (for example, Patent Document 1).
  • the electrical resistance of the wiring of the thin film semiconductor device for display devices and the resistance of each electrode of the thin film transistor greatly affect the electrical characteristics of the thin film transistor.
  • a display device using a conventional thin film semiconductor device for a display device a pixel including a thin film transistor is arranged in an intersection region between m rows of wiring and n columns of wiring arranged in a matrix of m rows ⁇ n columns.
  • a driving circuit that drives a thin film transistor included in each pixel is disposed at one end of the display device, and the thin film transistor is driven from this driving circuit to each pixel included in the display device. A driving signal is supplied.
  • the display device has a large screen, the distance from one end portion of the display device in which the drive circuit is arranged to the other end portion of the display device is increased. Then, there arises a problem that the electrical resistance of the wiring increases accordingly.
  • the electrical resistance of the wiring increases accordingly.
  • the organic EL display panel is a current-driven device, and is strongly influenced by the flowing current and the electric resistance voltage of the wiring.
  • each of the gate electrode, the source electrode, and the drain electrode constituting the thin film transistor is wired with a conductor for driving the thin film transistor.
  • a display unit for example, an organic EL
  • the display portion of the display device loses flatness due to the influence of the undulation of these wirings.
  • a flattening film can be interposed between the thin film semiconductor device and the display portion of the display device to prevent the influence of undulations due to the wiring.
  • the resin used for the planarization film contains moisture and oxygen. Such moisture and oxygen adversely affect the display portion of the display device.
  • the moisture and oxygen deteriorate characteristics of the organic light emitting layer and the like in the organic EL display panel.
  • it is effective to make the planarizing film as thin as possible.
  • the present invention has been made in view of the above problems, and it is possible to reduce the electrical resistance due to the wiring of the thin film semiconductor device for a display device and the electrode of the thin film transistor and at the same time ensure the flatness of the thin film semiconductor device for the display device. It is an object of the present invention to provide a thin film semiconductor device for a display device that can achieve a low process burden, and to provide a manufacturing method for manufacturing such a thin film semiconductor device for a display device.
  • a thin film semiconductor device for a display device which is one embodiment of the present invention includes a gate electrode, a gate insulating film formed over the gate electrode, and a semiconductor formed over the gate insulating film A first transistor electrode formed on the semiconductor layer; a second transistor electrode formed on the semiconductor layer; and at least one electrode of the first transistor electrode or the second transistor electrode;
  • the wiring is electrically connected and is separate from the one electrode and has a wiring that is thicker than the thickness of the one electrode.
  • the flatness of the thin film semiconductor device for a display device is reduced while reducing the electrical resistance due to the wiring of the thin film semiconductor device for the display device and the electrode of the thin film transistor. Can be achieved with less process burden. As a result, even if the display device provided with the thin film semiconductor device for display device has a large screen and the drive frequency is increased, the signal delay or voltage drop due to the electric resistance of the wiring of the thin film semiconductor device for display device or the electrode of the thin film transistor Display unevenness due to can be reduced.
  • FIG. 1 is a diagram illustrating a panel substrate according to an embodiment.
  • FIG. 2 is a perspective view of the organic EL display according to the embodiment.
  • FIG. 3 is a diagram illustrating a circuit configuration of a pixel circuit that drives the pixel according to the embodiment.
  • FIG. 4 is a plan view illustrating a configuration of a pixel according to the embodiment.
  • FIG. 5 is a cross-sectional view taken along line A-A ′ of FIG.
  • FIG. 6 is an exploded perspective view of the thin film semiconductor device for a display device according to the embodiment.
  • FIG. 7 is a cross-sectional view of the display device according to the embodiment.
  • FIG. 8A is a process sectional view of the thin film semiconductor device for display device of the embodiment.
  • FIG. 8B is a process sectional view of the thin film semiconductor device for display device of the embodiment.
  • FIG. 8C is a process cross-sectional view of the thin film semiconductor device for display device of the embodiment.
  • FIG. 8D is a process sectional view of the thin film semiconductor device for display device of the embodiment.
  • FIG. 8E is a process cross-sectional view of the thin film semiconductor device for display device of the embodiment.
  • FIG. 9A is a process cross-sectional view of a display thin film semiconductor device in a photolithography and etching process using the halftone mask of the embodiment.
  • FIG. 9B is a process sectional view of the display thin film semiconductor device in the photolithography and etching process using the halftone mask of the embodiment.
  • FIG. 9A is a process cross-sectional view of a display thin film semiconductor device in a photolithography and etching process using the halftone mask of the embodiment.
  • FIG. 9B is a process sectional view of the display thin film semiconductor device in the photo
  • FIG. 9C is a process sectional view of the display thin film semiconductor device in the photolithography and etching process using the halftone mask of the embodiment.
  • FIG. 9D is a process sectional view of the display thin film semiconductor device in a photolithography and etching process using the halftone mask of the embodiment.
  • FIG. 9E is a process sectional view of the display thin film semiconductor device in the photolithography and etching process using the halftone mask of the embodiment.
  • a thin film semiconductor device for a display device includes a gate electrode, a gate insulating film formed over the gate electrode, a semiconductor layer formed over the gate insulating film, and the semiconductor layer A first transistor electrode formed; a second transistor electrode formed on the semiconductor layer; and the one electrode formed on at least one of the first transistor electrode and the second transistor electrode. And a wiring that is separate from the one electrode and is thicker than the thickness of the one electrode.
  • the wiring is a first transistor electrode (source electrode or drain electrode) formed on the gate insulating film, or a second transistor electrode (drain electrode or formed) formed on the gate insulating film.
  • the source electrode is thicker than any one of the source electrodes).
  • a wiring that is electrically connected to either the first transistor electrode or the second transistor electrode formed on the semiconductor layer and is thicker than the thickness of the electrode is formed. Accordingly, since the electrical resistance of the wiring is inversely proportional to the cross-sectional area of the wiring, the cross-sectional area of the wiring increases and the electrical resistance decreases as the wiring film thickness increases. In addition, since the thickness of the wiring can be arbitrarily increased according to the characteristics of the thin film semiconductor device for a display device, the electrical resistance of the wiring can be reduced.
  • the wiring may be formed on the first transistor electrode or the second transistor electrode.
  • connection length between the wiring and the first transistor electrode or the second transistor electrode can be shortened, it is also suitable for reducing the electrical resistance between the electrodes electrically connected to the wiring. is there. As a result, a voltage can be applied to the electrically connected electrodes with a small delay.
  • the film thickness of the wiring formed on the one electrode is thicker than the film thickness of the one electrode, a thin film semiconductor device with reduced electric resistance of the wiring as a thin film semiconductor device can be realized.
  • the thermal influence can be reduced.
  • the transistor electrode can be extended from the wiring, and the signal voltage can be prevented from being lowered due to the electric resistance of the wiring. Therefore, it is particularly suitable for use as a switching transistor for an organic EL display device. In addition, the structure of the transistor can be simplified.
  • the switching transistor for the organic EL display device can be freely arranged in the pixel region of the organic EL display device, it is suitable for realizing optimization of the transistor layout design.
  • the first transistor electrode is a source electrode
  • the second transistor electrode is a drain electrode
  • the wiring is electrically connected to the source electrode.
  • a source wiring may be used.
  • the source electrode of the transistor can be extended from the source wiring, it is possible to prevent the power supply voltage from being lowered due to the electrical resistance of the wiring. Therefore, it is particularly suitable for use as a drive transistor for an organic EL display device.
  • the structure of the transistor can be simplified.
  • the drive transistor for the organic EL display device can be freely arranged in the pixel region of the organic EL element, which is suitable for realizing optimization of transistor layout design.
  • the first transistor electrode is a source electrode
  • the second transistor electrode is a drain electrode
  • the wiring is electrically connected to the drain electrode.
  • power supply wiring may be used.
  • the drain electrode of the transistor can be extended from the power supply wiring, it is possible to prevent the power supply voltage from being lowered due to the electrical resistance of the wiring. Therefore, it is particularly suitable for use as a drive transistor for an organic EL display device.
  • the structure of the transistor can be simplified.
  • the drive transistor for the organic EL display device can be freely arranged in the pixel region of the organic EL element, which is suitable for realizing optimization of transistor layout design.
  • the wiring is over at least one of the first transistor electrode and the second transistor electrode electrically connected to the wiring.
  • the semiconductor layer may be formed in a region at least partially overlapping with the upper side of the semiconductor layer.
  • a structure in which at least a part of the semiconductor layer is disposed below the wiring can be obtained. For this reason, the electrical resistance of the wiring between the wiring layer and the electrode can be minimized, and a decrease in the signal voltage can be prevented as much as possible.
  • it is suitable for use as a drive transistor and a switching transistor for an organic EL display device. .
  • the transistor since at least a part of the transistor is arranged below the wiring, when it is used in an organic EL display device, the pixel size is reduced, that is, the organic EL display device has ultra-high definition and the yield is improved. This is a preferable configuration.
  • At least one of the first transistor electrode and the second transistor electrode electrically connected to the wiring is outside the region of the semiconductor layer.
  • the wiring may be formed on the extended region of at least one of the first transistor electrode and the second transistor electrode electrically connected to the wiring.
  • the source electrode or the drain electrode of the transistor can be extended from the source wiring or the power supply wiring, respectively, the power supply voltage can be prevented from being lowered due to the electrical resistance of the wiring. Therefore, it is particularly suitable for use as a switching transistor or a driving transistor for an organic EL display device.
  • a switching transistor or a driving transistor for an organic EL display device can be freely arranged in the pixel region of the organic EL element, it is also suitable for realizing optimization of transistor layout design.
  • the electrical resistance of the wiring is that of at least one of the first transistor electrode and the second transistor electrode electrically connected to the wiring. It may be smaller than the electrical resistance.
  • the electrical resistance of the wiring can be made smaller than the electrical resistance of the transistor electrode. Therefore, when the thin film semiconductor device of this aspect is used for an organic EL display device, for example, it is possible to solve problems such as suppressing a voltage drop related to the electrical resistance of the wiring as the display device, and the effect is This is more noticeable as the screen becomes larger.
  • a thin film semiconductor device for a display device includes a gate wiring, a first gate electrode extending from the gate wiring, a first gate insulating film formed over the first gate electrode, A first semiconductor layer formed on the first gate insulating film; a first transistor electrode formed on the first semiconductor layer; a second transistor electrode formed on the first semiconductor layer; A second gate electrode electrically connected to the second transistor electrode; a second gate insulating film formed on the second gate electrode; a second semiconductor layer formed on the second gate insulating film; A third transistor electrode formed on the second semiconductor layer; a fourth transistor electrode formed on the second semiconductor layer; and a gate transistor interconnected with the third transistor electrode, formed on the first transistor electrode, 1 transition A first wiring thicker than the first transistor electrode and crossing the gate wiring, formed on the fourth transistor electrode, and separate from the fourth transistor electrode. Second wiring thicker than the thickness of the fourth transistor electrode, and at least one of the second transistor electrode and the third transistor electrode is formed of the first transistor electrode and the fourth transistor electrode. It is arranged between them.
  • This aspect relates to an aspect in which a plurality of thin film transistors are formed between the wirings. According to this aspect, since the thickness of the plurality of transistor electrodes can be made thinner than the thickness of the wiring, the thickness of the wiring is increased while suppressing the undulation of the surface of the thin film transistor formation region. be able to. Therefore, according to this aspect, a thin film semiconductor device in which the electrical resistance of the wiring is reduced can be realized.
  • the electrical resistance of the wiring as a thin film semiconductor device is reduced.
  • the thermal influence can be reduced.
  • This mode includes a mode in which more than two transistors are formed between the wirings. Specifically, the number of transistors is three or four, and the so-called It is also suitable for realizing an internal compensation type circuit.
  • the thin film semiconductor device for a display device is characterized in that the second transistor electrode and the third transistor electrode are disposed between the first transistor electrode and the fourth transistor electrode.
  • the second transistor electrode and the third transistor electrode are disposed between the first transistor electrode and the fourth transistor electrode, thereby sandwiching the first transistor electrode and the fourth transistor electrode. Since the formed region becomes flat, it is possible to realize a thin film semiconductor device that suppresses the occurrence of undulations on the surface of the thin film semiconductor device and reduces the electrical resistance of the wiring.
  • the first transistor electrode is a source electrode of a switching transistor
  • the second transistor electrode is a drain electrode of the switching transistor
  • the third transistor electrode is It is a source electrode of the driving transistor
  • the fourth transistor electrode is a drain electrode of the driving transistor.
  • a thin film semiconductor device having a switching transistor and a driving transistor, which are basic transistors of an active matrix type organic EL display device.
  • the thin film semiconductor device of this aspect as a drive circuit of the display device, it is possible to prevent uneven brightness of the display device due to, for example, electrical resistance of the wiring of the display device, heat generation, or the like. In particular, the effect when used in a large-screen display device is tremendous.
  • a display device is characterized in that a display device is formed over the above-described thin film semiconductor device for a display device.
  • the thin film semiconductor device of the present invention as a drive circuit for a display device, it is possible to prevent uneven brightness of the display device due to, for example, the electrical resistance of the wiring of the display device, heat generation, or the like. In particular, the effect when used in a large screen display device is tremendous.
  • a display device includes the above-described thin film semiconductor device for a display device, and each upper surface of the first wiring, the second wiring, the second transistor electrode, and the third transistor electrode includes an insulating film.
  • the first wiring and the second wiring covered by the insulating film are used as partition walls, and an anode, a cathode, and a light emitting layer interposed between the anode and cathode are laminated between the partition walls.
  • the surface of the wiring layer that is thicker than the film thickness of the first transistor electrode, the second transistor electrode, the third transistor electrode, and the fourth transistor electrode is covered with the passivation film.
  • the display device according to this aspect is configured such that the light emitting portion is covered with the passivation film and disposed between the first wiring and the second wiring having a large film thickness.
  • the first wiring and the second wiring covered with the passivation film have a function of a partition wall.
  • the partition does not have to be formed as a separate configuration, and the configuration and the manufacturing process can be simplified.
  • a step of forming a gate electrode on a substrate, a step of forming a gate insulating film on the gate electrode, and a step of forming on the gate insulating film A step of forming a semiconductor layer; a step of forming a first transistor electrode and a second transistor electrode on the semiconductor layer; and at least one of the first transistor electrode and the second transistor electrode. And forming a wiring thicker than the one electrode on the one electrode.
  • the wiring can be easily formed to have an arbitrary film thickness and larger than the film thickness of the transistor electrode.
  • the step of forming the wiring may be performed by a sputtering method, a plating method, or a printing method.
  • the wiring is formed by a sputtering method, a plating method, or a printing method.
  • the sputtering methods particularly the DC magnetron sputtering method can easily form a metal film at a high speed and in a large area, and the formed film is excellent in smoothness and film thickness uniformity, and is suitable for formation. Is the method.
  • the plating method and the printing method are simple manufacturing methods, and are suitable for realizing a manufacturing method that can be easily formed thick in a short time and has excellent mass productivity.
  • Embodiments of a thin film semiconductor device for a display device which is one embodiment of the present invention are described below with reference to the drawings. Note that in this embodiment, an organic EL (Electro Luminescence) display is described as an example of a display device using a thin film semiconductor device for a display device.
  • organic EL Electro Luminescence
  • FIGS. 1 to 3 an organic EL display and a thin film semiconductor device for a display device according to an embodiment of the present invention will be described.
  • FIG. 1 is a diagram showing a panel substrate 1 on which a plurality of organic EL displays are chamfered.
  • a panel substrate 1 on which a plurality of organic EL displays are chamfered.
  • two organic EL displays 10 are chamfered from the panel substrate 1.
  • Each organic EL display 10 includes a plurality of pixels 100.
  • FIG. 2 is an exploded perspective view showing the structure of the organic EL display 10 according to the embodiment of the present invention in an exploded manner.
  • the organic EL display 10 is a laminated structure of a thin film semiconductor device 20 for a display device, a planarizing film 11, an anode 12, an organic EL layer 13 and a transparent cathode 14 from the lower layer.
  • a plurality of pixels 100 are arranged in a matrix of m rows ⁇ n columns. Each pixel 100 is driven by a pixel circuit 30 provided therein.
  • the thin film semiconductor device 20 for display device includes a plurality of gate wirings 21 arranged in each row of the matrix and a plurality of metal wirings arranged in each column of the matrix so as to intersect the gate wiring 21 (
  • a source wiring 22 as a signal line) and a plurality of metal wirings (in this embodiment, a power supply wiring) 23 extending in parallel with the source wiring 22 are provided.
  • the gate wiring 21 connects the gates of the first thin film transistors that operate as switching elements included in each of the pixel circuits 30 for each row.
  • the source line 22 connects a source electrode 42 (not shown in FIG. 2) of a thin film transistor operating as a switching element included in each pixel circuit 30 for each column.
  • the power supply wiring 23 connects the drains of the second thin film transistors 50 that operate as drive elements included in each of the pixel circuits 30 for each column.
  • FIG. 3 is a diagram illustrating a circuit configuration of the pixel circuit 30 that drives the pixel 100.
  • the pixel circuit 30 includes two transistors, a first thin film transistor 40 that operates as a switching element, a second thin film transistor 50 that operates as a driving element, and a gate of the first thin film transistor 40 that operates as a switching element.
  • the gate line 21 is connected to the electrode 41, the source line 22, the power supply line 23, and a capacitor 60 for storing data to be displayed on the corresponding pixel.
  • the first thin film transistor 40 includes a gate electrode 41 connected to the gate line 21, a source electrode 42 connected to the source line 22, a drain electrode 43 connected to the capacitor 60 and the gate electrode 51 of the second thin film transistor 50, It is composed of a semiconductor layer.
  • the first thin film transistor 40 stores the voltage value applied to the source line 22 in the capacitor 60 as display data.
  • the second thin film transistor 50 includes a gate electrode 51 connected to the drain electrode 43 of the first thin film transistor 40, a drain electrode 52 connected to the power supply line 23 and the capacitor 60, a source electrode 53 connected to the anode 12, and a semiconductor. Composed of layers.
  • the second thin film transistor 50 supplies a current corresponding to the voltage value held by the capacitor 60 from the power supply wiring 23 to the anode 12 through the source electrode 53.
  • the organic EL display 10 having the above configuration employs an active matrix system in which display control is performed for each pixel 100 located at the intersection of the gate wiring 21 and the source wiring 22.
  • FIG. 4 is a plan view showing the configuration of the pixel 100.
  • FIG. 5 is a cross-sectional view taken along line AA ′ of FIG.
  • FIG. 6 is an exploded perspective view showing the configuration of the pixel 100.
  • the configuration of the pixel 100 includes a source line 22 and a power line 23, an insulating layer 130 formed on the gate line 21, a gate line 21, a source line 22, and a power line 23.
  • a source line 22 and a power line 23 are formed of two thin film transistors (first thin film transistor 40 and second thin film transistor 50) formed in the vicinity of the crossing region.
  • the gate wiring 21, the source wiring 22, and the power supply wiring 23 are arranged so as to intersect each other with an insulating layer 130 having a gate insulating film extending therebetween.
  • the source wiring 22 and the power supply wiring 23 are formed in the same layer, but the gate wiring 21, the source wiring 22 and the power supply wiring 23 are formed in different layers.
  • the two thin film transistors 40 and 50 formed in the vicinity of the intersecting region are, for example, two transistors, a first thin film transistor 40 that operates as a switching element and a second thin film transistor 50 that operates as a drive element.
  • the source electrode 42 of the first thin film transistor 40 extends from the source wiring 22, and the drain electrode 52 of the second thin film transistor 50 extends from the power supply wiring 23. Further, a pixel electrode extends from the source electrode 53 of the second thin film transistor 50, and the pixel electrode is electrically connected to the anode 12 (see FIG. 2) of the display unit 19 through a contact hole (not shown). Has been.
  • the source wiring 22 and the power supply wiring 23 are formed on the source electrode 42 of the first thin film transistor 40 and on the drain electrode 52 of the second thin film transistor 50.
  • the connection length between the source wiring 22 or the power supply wiring 23 and the source electrode 42 of the first thin film transistor 40 and the drain electrode 52 of the second thin film transistor 50 can be shortened, the electrical connection between each wiring and the electrode can be reduced. It is also suitable for reducing the resistance. As a result, it becomes easy to improve the operation of the thin film transistors 40 and 50.
  • the thin film semiconductor device 20 for a display device has a structure in which at least a part of the semiconductor layers 44 and 54 of the two thin film transistors 40 and 50 are respectively disposed below the source wiring 22 and the power supply wiring 23. For this reason, the electrical resistance of the wiring between each wiring layer and each electrode can be minimized, and a decrease in the signal voltage can be prevented as much as possible, and is particularly suitable for use as a driving transistor and a switching transistor for an organic EL display device. is there.
  • the pixel size is reduced, that is, the organic EL display device has a higher definition and an improved yield. This is a preferable configuration.
  • the first thin film transistor 40 is a structure including a substrate 110, a gate electrode 41, a gate insulating film 130 ⁇ / b> A, a semiconductor layer 44, a source wiring 22, a source electrode 42 formed under the source wiring 22, and a drain electrode 43.
  • the second thin film transistor 50 is a structure including the substrate 110, the gate electrode 51, the gate insulating film 130 ⁇ / b> B, the semiconductor layer 54, the source electrode 53, and the drain electrode 52 formed under the power supply wiring 23.
  • a gate insulating film 130A of the first thin film transistor 40 is extended to electrically isolate the gate electrodes 41 and 51 of the two transistors. That is, the first thin film transistor 40 and the second thin film transistor 50 are separated by the gate insulating film 130 ⁇ / b> A of the first thin film transistor 40.
  • the drain electrode 43 of the first thin film transistor 40 and the gate electrode 51 of the second thin film transistor 50 pass through the gate insulating film 130B of the second thin film transistor 50 through the contact hole 160 and are electrically connected. Therefore, the voltage of the first thin film transistor 40 can be applied to the gate electrode 51 of the second thin film transistor 50. As a result, a current corresponding to the voltage applied to the gate electrode 51 of the second thin film transistor 50 flows from the drain electrode 52 of the second thin film transistor 50 to the source electrode 53 of the second thin film transistor 50.
  • the semiconductor layer 44 of the first thin film transistor is disposed between the source electrode 42 and the drain electrode 43 on the gate insulating film 130A and at a position facing the gate electrode 41 via the gate insulating film 130A.
  • the semiconductor layer 54 of the second thin film transistor is disposed between the gate insulating film 130B, the source electrode 53, and the drain electrode 52, and at a position facing the gate electrode 51 with the gate insulating film 130B interposed therebetween.
  • the left transistor electrode in FIG. 5 is described as the source electrode 42, and the right transistor electrode in FIG. 5 is the drain electrode 43. However, the left transistor electrode in FIG. The right transistor electrode may be the source electrode.
  • the left side transistor electrode in FIG. 5 is described as the source electrode 53, and the right side transistor electrode in FIG. 5 is the drain electrode 52, but the left side transistor electrode in FIG. The right side transistor electrode may be used as the source electrode. Therefore, in the first thin film transistor 40, the left transistor electrode in FIG. 5 is referred to as a first transistor electrode, the right transistor electrode in FIG. 5 is referred to as a second transistor electrode, and the left thin film transistor in FIG. The electrode is referred to as a third transistor electrode, and the transistor electrode on the right side of FIG. 5 is referred to as a fourth transistor electrode.
  • the source wiring 22 is formed on the source electrode 42 of the thin film transistor 40.
  • the source electrode 42 of the thin film transistor 40 is formed of a thin film, and the source wiring 22 is thicker than the source electrode 42.
  • the power supply wiring 23 is formed on the drain electrode 52 of the thin film transistor 50.
  • the drain electrode 52 of the thin film transistor 50 is formed of a thin film, and the power supply wiring 23 is thicker than the drain electrode 52.
  • the source wiring 22 and the power supply wiring 23 are outside the first thin film transistor 40 formed on the gate insulating film 130A and the second thin film transistor 50 formed on the gate insulating film 130B, respectively. Is provided.
  • the film thickness of the source wiring 22 is thicker than the film thickness of the source electrode 42 of the first thin film transistor 40 to which the source wiring 22 is connected.
  • the thickness of the power supply wiring 23 is larger than the thickness of the drain electrode 52 of the second thin film transistor 50 to which the power supply wiring 23 is connected.
  • the source wiring 22 electrically connected to the source electrode 42 of the first thin film transistor 40 is a wiring thicker than the film thickness of the source electrode 42.
  • the power supply wiring 23 electrically connected to the drain electrode 52 of the second thin film transistor 50 is a wiring that is thicker than the drain electrode 52. Since the electrical resistance of the wiring is inversely proportional to the cross-sectional area of the wiring, increasing the film thickness of the wiring also increases the cross-sectional current of the wiring and decreases the electrical resistance. As a result, even if the thin film semiconductor device 20 for a display device is enlarged in response to an increase in screen size, a voltage can be applied to the electrodes of the thin film transistors electrically connected to these wirings with a small delay.
  • the film thickness of the source electrode 42 of the first thin film transistor 40 and the drain electrode 52 itself of the second thin film transistor 50 can be made as thin as possible below the pixel formation region. Therefore, since the source wiring 22 and the power supply wiring 23 are provided at the ends of the first thin film transistor 40 and the second thin film transistor 50, respectively, in the region between the source wiring 22 and the power supply wiring 23, the first thin film transistor 40 and Unevenness of the surface due to the second thin film transistor 50 can be reduced. Thereby, the problem resulting from the undulation of the surface by the thin film transistors 40 and 50 can be solved. That is, the undulations on the surfaces of the thin film transistors 40 and 50 corresponding to the lower side of the pixel formation region can be reduced. As a result, even if the display unit 19 is provided on the thin film semiconductor device 20 for a display device of the present embodiment, the influence of the undulations on the surfaces of the thin film transistors 40 and 50 on the display unit can be reduced.
  • planarizing film 11 can be thinned, moisture, oxygen, etc. contained in the planarizing film 11 can be reduced. As a result, it is possible to suppress deterioration of the organic light emitting layer in the display unit 19 due to moisture, oxygen, and the like.
  • the wiring is thick, it is possible to realize a thin film semiconductor device in which the surface of the thin film transistor formation region is reduced while reducing the electrical resistance of the wiring as the thin film semiconductor device.
  • a part of the semiconductor layers 44 and 54 is arranged below the source wiring 22 and the power supply wiring 23.
  • the pixel size can be reduced, that is, the organic EL display device can be realized with ultra high definition, an increase in the light emission area of the pixel, and an improvement in yield. .
  • heat generated in the image display of the organic EL display device can be quickly dissipated through the wiring in the in-plane direction of the substrate, the thermal influence can be reduced.
  • the electrical resistance of each wiring may be smaller than the electrical resistance of each of the above-mentioned electrodes electrically connected to each wiring. Therefore, when the thin film semiconductor device of this embodiment is used in, for example, an organic EL display device, it is possible to solve problems such as a voltage drop due to electric resistance of wiring as a display device. The larger the screen, the more prominent.
  • this invention can respond also to the aspect with more than two transistors formed between the said wiring.
  • the present invention is also suitable for realizing a so-called internal compensation circuit in which the number of thin film transistors is three or four and the characteristic variation of each of the plurality of thin film transistors is compensated.
  • a structure in which part of the semiconductor layers 44 and 54 is not disposed below the source wiring 22 and the power supply wiring 23 is also possible.
  • the source electrode 42 of the first thin film transistor 40 extends from the source wiring 22
  • the drain electrode 52 of the second thin film transistor 50 extends from the power supply wiring 23.
  • the organic EL display 10 includes a display unit in which a passivation film 15, a planarization film 11, an anode 12, an organic EL layer 13, and a transparent cathode 14 are sequentially stacked on a thin film semiconductor device 20 for a display device. 19 is formed.
  • the passivation film 15 protects the surfaces of the source wiring 22, the power supply wiring 23, and the two thin film transistors 40 and 50 of the thin film semiconductor device 20 for display devices from external damage, and ensures an electrical insulation state. It is formed.
  • the planarizing film 11 formed on the passivation film 15 is formed so as not to reflect the influence of the undulation on the surface of the thin film transistor formation region on the display unit 19.
  • the planarizing film 11 may contain a large amount of moisture and oxygen that cause deterioration of the organic EL layer of the display unit 19. For this reason, the planarizing film 11 should be as thin as possible.
  • the drain electrode 43 as the second transistor electrode of the first thin film transistor 40 and the source electrode 53 as the third transistor electrode of the second thin film transistor 50 are thinned, thereby The flatness of the thin film transistors 40 and 50 in the region corresponding to the lower side of the organic EL layer 13 is ensured.
  • a thin film is formed between the source wiring 22 and the power supply wiring 23 (range B in FIG. 7), which is a thick film of the thin film semiconductor device 20 for display devices.
  • a drain electrode 43 as a second transistor electrode of the first thin film transistor 40 and a source electrode 53 as a third transistor electrode of the second thin film transistor 50 are disposed.
  • a region sandwiched between the source wiring 22 and the power supply wiring 23 which is a thick film of the thin film semiconductor device 20 for a display device becomes flat.
  • the surface shape between the source wiring 22 and the power supply wiring 23 of the two thin film transistors can be flattened.
  • the flatness is ensured in the region where the organic EL layer 13 of the display unit 19 is laminated (range A in FIG. 7), the film thickness unevenness of the organic EL layer 13 can be reduced, resulting in luminance. Unevenness can be suppressed.
  • the source line 22 and the power line 23 are formed thicker than the drain electrode 43 and the source electrode 53.
  • the influence of the undulations of the source wiring 22 and the power supply wiring 23 on the display unit 19 does not occur.
  • the planarization film 11 can be made into a thin film, moisture or oxygen contained in the planar film 150 can be reduced, and alteration or deterioration of the organic EL layer due to moisture or oxygen can be prevented.
  • the planarization film 11 has a contact hole (not shown) for electrically connecting the pixel electrode and the anode 12 extending from the source electrode 53 of the second thin film transistor 50 of the thin film semiconductor device 20 for display device. Is formed. As a result, a current controlled by the thin film semiconductor device 20 for display device flows through the anode 12.
  • the anode 12 is laminated on the planarizing film 11.
  • the anode 12 is electrically connected to the organic EL layer 13, and a current is passed through the organic EL layer 13, that is, holes are injected.
  • the anode 12 may be, for example, a reflective electrode made of a material having a high light reflectance.
  • an organic EL layer 13 (described later) travels toward the anode 12, the light is reflected by the surface of the anode 12, so that the light path changes upward in the display unit 19. Thereby, a structure suitable for increasing the external light extraction efficiency of the organic EL layer 13 is obtained.
  • the organic EL layer 13 is laminated on the anode 12.
  • the organic EL layer 13 is made of organic molecules for light emission, and holes are injected from the anode 12 and electrons are injected from the transparent cathode 14 described later. As a result, holes and electrons are recombined in the organic EL layer 13. At that time, the organic molecule enters an excited state, and emits light when the organic molecule returns from the excited state to the ground state.
  • a transparent cathode 14 is laminated on the organic EL layer 13.
  • the transparent cathode 14 injects electrons into the organic EL layer 13. Due to the phenomenon of light emission described above, the light emitted from the organic EL layer 13 passes through the transparent cathode 14 and radiates light from the upper side of the display unit 19 to the outside.
  • the thin film semiconductor device 20 for a display device according to the present embodiment as a drive circuit for the display device, for example, the luminance unevenness of the display device due to the electrical resistance of the wiring of the thin film semiconductor device for display device is reduced. Can be prevented. In particular, the effect when used in a large screen display device is tremendous.
  • the source wiring 22, the power supply wiring 23, the drain electrode 43 of the first thin film transistor 40, and the source electrode 53 of the second thin film transistor 50 are covered with a passivation film 15.
  • the source wiring 22 and the power supply wiring 23 covered with the passivation film 15 are defined as partition walls (C in FIG. 7). Between this partition, the anode 12, the organic EL layer 13, and the transparent cathode 14 are laminated
  • the source wiring 22 and the power supply wiring 23 covered with the passivation film 15 may have a partition function. In this case, in the display device of this aspect, the partition need not be formed as a separate configuration, and the configuration and the manufacturing process can be simplified.
  • FIGS. 8A to 8E show a manufacturing method of the thin film semiconductor device 20 for a display device according to the embodiment in the AA ′ cross section in FIG. 4, that is, in the cross section of the formation region of the first thin film transistor 40 and the second thin film transistor 50. It is process drawing demonstrated for every process.
  • 9A to 9E are process diagrams showing in detail a process between the process shown in FIG. 8D and the process shown in FIG. 8E. 9A to 9E show a photolithography process using a halftone mask in the cross section of the first thin film transistor 40 and the second thin film transistor 50 in the method for manufacturing the thin film semiconductor device 20 for a display device according to the embodiment.
  • the substrate 110 is prepared.
  • the substrate 110 is generally made of an insulating material such as glass or quartz.
  • a silicon oxide film or a silicon nitride film (not shown) may be formed on the upper surface of the substrate 110, and the film thickness is about 100 nm.
  • a metal is formed by, for example, a sputtering method. Thereafter, patterning is performed by, for example, a photolithography method or an etching method to form the gate electrodes 41 and 51 of the first thin film transistor 40 and the second thin film transistor 50.
  • molybdenum is used as a material for the gate electrode, and the film thickness is set to about 100 nm.
  • the gate insulating film 130 and the semiconductor layer 140 are formed on the upper surfaces of the gate electrodes 41 and 51 of the first thin film transistor 40 and the second thin film transistor 50 without breaking the vacuum, for example, by a plasma CVD method or the like. It is laminated continuously.
  • the gate insulating film 130 is formed of a silicon oxide film (SiO 2 ), a silicon nitride film (SiN), or a composite film thereof, and the film thickness is It is about 200 nm.
  • the semiconductor layer 140 is an amorphous silicon film with a thickness of about 50 nm, for example.
  • the amorphous silicon film of the semiconductor layer 140 may be modified to a polycrystalline silicon film by performing a laser annealing process on the above-described amorphous silicon film by, for example, excimer laser or the like. .
  • Crystallization of amorphous silicon in the semiconductor layer 140 is performed, for example, by dehydrogenating in a furnace at 400 ° C. to 500 ° C., then crystallizing amorphous silicon with an excimer laser, and then for several seconds in a vacuum atmosphere. Hydrogen plasma treatment for tens of seconds is used. Through these steps, the amorphous silicon film of the semiconductor layer 140 may be modified into a polycrystalline silicon film.
  • the semiconductor layer 140 is divided into the semiconductor layer 44 of the first thin film transistor 40 and the semiconductor layer 54 of the second thin film transistor 50 by, for example, photolithography or etching. As an island. Thereafter, a contact hole 160 is formed in the gate insulating film 130B of the second thin film transistor 50 by, for example, a dry etching method. Note that a contact hole 160 is formed in order to electrically connect the drain electrode 43 of the first thin film transistor 40 and the gate electrode 51 of the second thin film transistor 50 to be formed later. Therefore, if it is for that, a shape and number will not be limited.
  • the metal layer 24 for each source / drain electrode of the first thin film transistor 40 and the second thin film transistor 50 and the wiring to each source / drain electrode, that is, the source wiring 22 and the power wiring 23 A metal layer 25 is continuously formed.
  • Mo is used for each source / drain electrode for the metal layer 24, and Cu that can be made thick as a wiring to each source / drain electrode is used for the metal layer 25.
  • the thickness of each source / drain electrode is 100 nm, and the thickness of the wiring is 2 ⁇ m.
  • the source / drain electrodes of the first thin film transistor 40 and the second thin film transistor 50 are patterned by, for example, photolithography and etching.
  • the source / drain electrodes of the two thin film transistors 40 and 50 are made as thin as possible, and wiring to the source electrode 42 of the first thin film transistor 40 and the drain electrode 52 of the second thin film transistor 50, that is, the present embodiment.
  • the source wiring 22 and the power supply wiring 23 formed on each source / drain electrode are made thick.
  • planarizing film 11 can be thinned, moisture, oxygen, etc. contained in the planarizing film 11 can be reduced. As a result, it is possible to suppress deterioration of the organic light emitting layer in the display unit 19 due to moisture, oxygen, and the like generated from the planarizing film 11.
  • the electrical resistance of the wiring is inversely proportional to the cross-sectional area of the wiring
  • increasing the film thickness of the wiring also increases the cross-sectional area of the wiring and reduces the electrical resistance.
  • a voltage can be applied without delay to the electrodes of the thin film transistor electrically connected to these wirings.
  • a low resistance semiconductor layer (not shown) is generally formed between the source electrode 42 and drain electrode 43 of the first thin film transistor 40 and the semiconductor layer 44.
  • this low resistance semiconductor layer for example, an amorphous silicon layer doped with an n-type dopant such as phosphorus or an amorphous silicon layer doped with a p-type dopant such as boron is used.
  • the film thickness is about 20 nm.
  • the source / drain electrodes formed separately and the wirings formed thereon may be formed by separate processes.
  • photolithography is performed by adopting a photolithography method using a halftone mask. The number of process steps can be reduced. A photolithography method using this halftone mask will be described in detail with reference to FIGS. 9A to 9E.
  • the source electrode 42 of the first thin film transistor 40, the drain electrode 43 of the first thin film transistor 40, the drain electrode 52 of the second thin film transistor 50, and the source electrode 53 of the second thin film transistor 50 are formed.
  • the power supply wiring 23 is also formed on the source wiring 22 on the source electrode 42 of the first thin film transistor 40 and the drain electrode 52 of the second thin film transistor 50. Then, the drain electrode 43 of the first thin film transistor 40 and the gate electrode 51 of the second thin film transistor 50 are connected through the contact hole 160.
  • the source / drain electrodes of the two thin film transistors 40 and 50 and the wirings provided on the source / drain electrodes are formed by photolithography using a halftone mask. The steps performed will be described in detail. This step is performed between FIG. 8D and FIG. 8E. Note that this embodiment mode is described using a positive photoresist material. However, a negative photoresist material can be processed in the same manner as the positive type by reversing the exposed area and the unexposed area.
  • an etching process is performed on a thin metal layer 24 to be each electrode of the thin film transistor shown in FIG. 8D and a thick metal layer 25 to be a wiring to each electrode.
  • a photoresist film 17 to be a resist mask is applied on the entire surface.
  • the film thickness is 1 ⁇ m or more.
  • the halftone mask 16 includes an area (transmission area) 18a that transmits light, an area (transmission area) 18b that transmits light at a certain ratio, and an area (light-shielding area) 18c that blocks light. That is, by disposing the light source for exposure and the photoresist film 17, a completely exposed area, an area exposed at a certain ratio, and an unexposed area can be formed on the photoresist film 17.
  • FIG. 9B development and removal processes are performed after the exposure of the photoresist film 17, so that the photoresist film 17 exposed at a certain ratio is not completely exposed to light so that the film thickness is reduced.
  • the photoresist film 17b has a certain thickness.
  • the unexposed area becomes the photoresist film 17a with the same film thickness.
  • the completely exposed photoresist film 17 is completely removed by developing and removing processes, and a thick metal layer 25 (region A in FIG. 9B) to be the underlying wiring is exposed. .
  • the metal layer 25 is etched by, for example, a wet etching process. And is shaved (region A in FIG. 9C).
  • the underlying metal layer 25 is not etched, and the photoresist films 17a and 17b serve as a resist mask.
  • the wet etching process is finished in consideration of the etching rate determined by the etching agent and the material to be etched (in this embodiment, the metal layers 24 and 25).
  • ashing is performed on the entire photoresist films 17a and 17b, the photoresist film 17b having a certain thickness is removed, and the photoresist film 17a is reduced.
  • the thick metal layer 25 to be a new underlying wiring is exposed (region B in FIG. 9D).
  • the photoresist film 17a is reduced and remains as a photoresist film 17a '.
  • a thick metal layer 25 that will be exposed under the wiring other than the region of the photoresist film 17a ′ and the underlying metal layer 25 are formed again by, for example, a wet etching process.
  • the thin metal layer 24 that becomes the electrode is etched. Then, the etching process is stopped when each layer has a desired film thickness.
  • the photoresist film 17a ' is removed (not shown).
  • the two metal layers 24 and 25 formed in succession can be formed into a desired shape shown in FIG. 8E by a patterning and etching process using one photomask.
  • a halftone mask By using a halftone mask, the number of photomasks can be reduced, and the manufacturing cost of the thin film semiconductor device can be reduced. Furthermore, since the number of man-hours can be reduced, the cost for constructing the production line can be reduced, and a significant cost reduction can be achieved overall.
  • each electrode of the transistor can be formed separately from the source wiring 22 and the power supply wiring 23. Therefore, these wirings have any film thickness and are formed thicker than the film thickness of each electrode of the transistor. Can be easily implemented.
  • the step of forming the wiring layer may be performed by, for example, a sputtering method, a plating method, or a printing method.
  • the wiring is formed by, for example, a sputtering method, a plating method, or a printing method.
  • a sputtering method particularly the DC magnetron sputtering method can easily form a metal film at a high speed and in a large area, and the formed film is excellent in smoothness and film thickness uniformity, and is suitable for formation. Is the method.
  • the plating method and the printing method are simple manufacturing methods, and are suitable for realizing a manufacturing method that can be easily formed thick in a short time and has excellent mass productivity.
  • the top emission type organic EL display 10 is manufactured. That is, the passivation film 15, the planarizing film 11, the anode 12, the organic EL layer 13 and the transparent cathode 14 are sequentially laminated on the thin film semiconductor device 20 for a display device, and a top emission type organic EL as shown in FIG. The display 10 is manufactured.
  • the passivation film 15 is formed on the thin film semiconductor device 20 for display device, and the planarizing film 11 is laminated thereon.
  • the material of the anode 12 is, for example, a conductive metal such as molybdenum, aluminum, gold, silver, or copper, or an alloy thereof, an organic conductive material such as PEDOT: PSS, zinc oxide, or lead-doped indium oxide. Material. A film made of these materials is formed by a vacuum evaporation method, an electron beam evaporation method, an RF sputtering method, a printing method, or the like to form an electrode pattern.
  • the organic EL layer 13 is configured by laminating layers such as a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer on the anode 12.
  • layers such as a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer on the anode 12.
  • copper phthalocyanine is used as the hole injection layer
  • ⁇ -NPD Bis [N- (1-Naphthyl) -N-phenyl] benzidine
  • Alq 3 tris (8- hydroquinoline) aluminum
  • an oxazole derivative as the electron transport layer
  • Alq 3 as the electron injection layer.
  • the transparent cathode 14 is a transparent electrode formed on the organic EL layer 13.
  • the material of the transparent cathode 14 is, for example, ITO (Indium Tin Oxide), SnO 2 , In 2 O 3 , ZnO, or a combination thereof.
  • a halftone process is adopted in the production of the thin film semiconductor device 20 for a display device, thereby reducing the burden on the process, and wiring requiring low resistance is formed of a thick low resistance material. Further, below the organic EL layer 13 of the display unit 19 where flatness is required, each electrode of the thin film transistor is formed as a thin film. As a result, it is possible to secure the flatness in the pixel of the display unit 19 while reducing the resistance by increasing the thickness of the wiring.
  • the partition layer serving as the partition line is composed of the source wiring 22 and the power supply wiring 23 covered with the passivation film 15 without forming the partition wall that generally serves to separate the pixels.
  • the process for creating a display device can be simplified.
  • the present embodiment is an embodiment that constitutes a top emission type of an organic EL display, but the scope of application of the present invention is not limited to this. That is, it can also be used for a bottom emission type organic EL display whose substrate is transparent. Furthermore, any device using a thin film semiconductor device using a thin film transistor (for example, a liquid crystal display, an inorganic EL display, etc.) is applicable.
  • a thin film semiconductor device using a thin film transistor for example, a liquid crystal display, an inorganic EL display, etc.
  • the resistance of the wiring and the electrode of the thin film transistor can be reduced, and the flatness of the thin film semiconductor device can be maintained. As a result, display unevenness due to signal delay and voltage drop can be suppressed. It is possible to provide a flat thin film semiconductor device capable of achieving the above.

Abstract

Disclosed is a thin film semiconductor device for use in a display device, which comprises a gate electrode (41), a gate insulating film (130A) formed on the gate electrode (41), a semiconductor layer formed on the gate insulating film (130A), a first transistor electrode (42) formed on the semiconductor layer, a second transistor electrode (43) formed on the semiconductor layer, and a wiring line (22) formed on at least one electrode selected from the first transistor electrode (42) and the second transistor electrode (43), electrically connected to the at least one electrode, separated from the at least one electrode, and having a higher thickness than that of the at least one electrode. In the thin film semiconductor device, the wiring at low resistance can be achieved by increasing the thickness of the wiring line (22) and the flatness of an area laying between the electrodes can be maintained by decreasing the thicknesses of the electrodes.

Description

薄膜半導体装置、表示装置及び薄膜半導体装置の製造方法Thin film semiconductor device, display device, and method of manufacturing thin film semiconductor device
　本発明は、半導体を活性層とする薄膜トランジスタを基板上に集積形成した表示装置用薄膜半導体装置及びその表示装置用薄膜半導体装置を用いた表示装置に関するものである。 The present invention relates to a thin film semiconductor device for a display device in which thin film transistors having a semiconductor as an active layer are integrally formed on a substrate, and a display device using the thin film semiconductor device for the display device.
　現在、有機ＥＬディスプレイや液晶ディスプレイなどの表示装置は、製造プロセスの技術の進展とともに大画面化が進み、更に顧客ニーズは大画面で高画質な表示装置に向いている。そのため、表示装置の駆動基板である表示装置用薄膜半導体装置の分野では、高性能化に向けた開発が行われている。この表示装置の大画面化や高画質化に伴い、表示装置用薄膜半導体装置に搭載されている薄膜トランジスタの高い電流駆動能力が要求されている。その中でも、活性層に結晶化した半導体薄膜（多結晶シリコン・微結晶シリコンなど）を用いたものが注目されている。 Currently, display devices such as organic EL displays and liquid crystal displays have become larger screens with the progress of manufacturing process technology, and customer needs are suitable for display devices with large screens and high image quality. For this reason, in the field of thin film semiconductor devices for display devices, which are drive substrates for display devices, development for higher performance is being carried out. As the display device has a larger screen and higher image quality, a thin film transistor mounted on the thin film semiconductor device for a display device is required to have a high current drive capability. Among them, those using a semiconductor thin film (polycrystalline silicon, microcrystalline silicon, etc.) crystallized in the active layer are attracting attention.
　従来、表示装置用薄膜半導体装置に用いられている薄膜トランジスタはゲート電極、ソース電極、ドレイン電極の３つの電極、ゲート絶縁膜、半導体層からなる電界効果トランジスタの構造である。これら電極には薄膜トランジスタを駆動させるため各々導体（多くは金属や金属酸化物）による配線がなされている。それら配線は基板上でｍ行×ｎ列のマトリクス状に形成されており、各配線が絶縁層を介在させて立体的に交差している（例えば、特許文献１）。 Conventionally, a thin film transistor used in a thin film semiconductor device for a display device has a structure of a field effect transistor including a gate electrode, a source electrode, and a drain electrode, a gate insulating film, and a semiconductor layer. These electrodes are each wired with a conductor (mostly metal or metal oxide) to drive the thin film transistor. These wirings are formed in a matrix of m rows × n columns on the substrate, and each wiring intersects three-dimensionally with an insulating layer interposed (for example, Patent Document 1).
特開平１０－２６８７９４号公報Japanese Patent Laid-Open No. 10-268794
　しかしながら、従来技術では、以下のような問題が生ずる。 However, the following problems occur in the prior art.
　即ち、表示装置が大型化し、高画質化のために駆動周波数が増大化すると、表示装置用薄膜半導体装置の配線の電気抵抗や薄膜トランジスタの各電極抵抗が薄膜トランジスタの電気特性に影響を大きく与えるようになる。従来の表示装置用薄膜半導体装置を用いた表示装置では、ｍ行×ｎ列のマトリクス状に配置されたｍ行の配線とｎ列の配線との交差領域に薄膜トランジスタを含む画素が配置されている。このような表示装置においては、各画素に含まれる薄膜トランジスタを駆動する駆動回路を、表示装置の一方の端部に配置し、この駆動回路から前記表示装置に含まれる各画素に、前記薄膜トランジスタを駆動する駆動信号を供給する。 That is, as the display device becomes larger and the drive frequency increases for higher image quality, the electrical resistance of the wiring of the thin film semiconductor device for display devices and the resistance of each electrode of the thin film transistor greatly affect the electrical characteristics of the thin film transistor. Become. In a display device using a conventional thin film semiconductor device for a display device, a pixel including a thin film transistor is arranged in an intersection region between m rows of wiring and n columns of wiring arranged in a matrix of m rows × n columns. . In such a display device, a driving circuit that drives a thin film transistor included in each pixel is disposed at one end of the display device, and the thin film transistor is driven from this driving circuit to each pixel included in the display device. A driving signal is supplied.
　そのため、表示装置が大画面化すると、前記駆動回路が配置された表示装置の一方の端部から前記表示装置の他方の端部までの距離が長くなるため、前記駆動回路と他方の端の画素ではその分の配線の電気抵抗も増大するという問題が生ずる。つまり、表示装置の大画面化に伴い、表示装置の駆動回路と他方の端の画素においては配線の電気抵抗の累積が増大することで信号遅延となり、大きな問題になる。そして、その信号遅延が表示装置の表示ムラの原因となる。そのため、薄膜半導体装置内の薄膜トランジスタの各電極への配線は、できる限り低抵抗であることが望ましい。特に、有機ＥＬ表示パネルは電流駆動型のデバイスであり、流れる電流と配線の電気抵抗の電圧の影響を強く受ける。 Therefore, when the display device has a large screen, the distance from one end portion of the display device in which the drive circuit is arranged to the other end portion of the display device is increased. Then, there arises a problem that the electrical resistance of the wiring increases accordingly. In other words, with the increase in the screen size of the display device, in the driving circuit of the display device and the pixel at the other end, the accumulation of wiring electrical resistance increases, resulting in a signal delay, which becomes a serious problem. The signal delay causes display unevenness of the display device. Therefore, it is desirable that the wiring to each electrode of the thin film transistor in the thin film semiconductor device has as low resistance as possible. In particular, the organic EL display panel is a current-driven device, and is strongly influenced by the flowing current and the electric resistance voltage of the wiring.
　さらに、薄膜トランジスタを構成するゲート電極、ソース電極及びドレイン電極の各々の電極には、薄膜トランジスタを駆動させるため各々に導体による配線がなされている。そして、その上に、表示装置用薄膜半導体装置の上に表示装置の表示部（例えば、有機ＥＬなど）が製造される。そのため、配線や薄膜トランジスタの電極の各膜厚を厚くして電気抵抗を小さくした場合、表示装置の表示部は、これら配線の起伏による影響を受けて平坦性を失うという問題が生ずる。 Furthermore, each of the gate electrode, the source electrode, and the drain electrode constituting the thin film transistor is wired with a conductor for driving the thin film transistor. Then, a display unit (for example, an organic EL) of the display device is manufactured on the thin film semiconductor device for display device. For this reason, when the electric resistance is reduced by increasing the thickness of each wiring or thin film transistor electrode, there is a problem that the display portion of the display device loses flatness due to the influence of the undulation of these wirings.
　それを防ぐために、薄膜半導体装置と表示装置の表示部との間に平坦化膜を介在させ、配線による起伏の影響を防ぐこともできる。 In order to prevent this, a flattening film can be interposed between the thin film semiconductor device and the display portion of the display device to prevent the influence of undulations due to the wiring.
　しかしながら、平坦化膜に使われている樹脂には水分や酸素が含まれている。それら水分や酸素は表示装置の表示部に悪影響を及ぼす。特に表示装置の表示部として、有機ＥＬ表示パネルを平坦化膜上に形成すると、それら水分や酸素が有機ＥＬ表示パネルにおける有機発光層等の特性を劣化させる。劣化要因を低減させるため、平坦化膜を極力薄くすることは有効である。 However, the resin used for the planarization film contains moisture and oxygen. Such moisture and oxygen adversely affect the display portion of the display device. In particular, when an organic EL display panel is formed on a planarizing film as a display unit of a display device, the moisture and oxygen deteriorate characteristics of the organic light emitting layer and the like in the organic EL display panel. In order to reduce the deterioration factor, it is effective to make the planarizing film as thin as possible.
　ところが、平坦化膜を極力薄くしつつ、配線や薄膜トランジスタの電極の電気抵抗を小さくするためにそれらの膜厚を厚くすると、薄膜トランジスタの起伏が大きくなって、その上に製造される表示装置の表示部への悪影響が大きくなるという問題がある。 However, when the planarization film is made as thin as possible and the film thickness is increased in order to reduce the electrical resistance of the wiring and the electrode of the thin film transistor, the undulation of the thin film transistor increases, and the display of the display device manufactured thereon is displayed. There is a problem that the adverse effect on the department becomes large.
　そこで、本発明は、上記課題に鑑みてなされたものであって、表示装置用薄膜半導体装置の配線と薄膜トランジスタの電極による電気抵抗を小さくすると同時に表示装置用薄膜半導体装置の平坦性の確保を、プロセス負担を少なく達成できる表示装置用薄膜半導体装置を提供すること、またそのような表示装置用薄膜半導体装置を製造するための製造方法を提供することを目的とする。 Therefore, the present invention has been made in view of the above problems, and it is possible to reduce the electrical resistance due to the wiring of the thin film semiconductor device for a display device and the electrode of the thin film transistor and at the same time ensure the flatness of the thin film semiconductor device for the display device. It is an object of the present invention to provide a thin film semiconductor device for a display device that can achieve a low process burden, and to provide a manufacturing method for manufacturing such a thin film semiconductor device for a display device.
　上記課題を解決するために、本発明の一態様である表示装置用薄膜半導体装置は、ゲート電極と、前記ゲート電極上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成された半導体層と、前記半導体層上に形成された第１トランジスタ電極と、前記半導体層上に形成された第２トランジスタ電極と、前記第１トランジスタ電極又は前記第２トランジスタ電極の少なくともいずれか一方の電極と電気的に接続され、前記一方の電極と別体であって前記一方の電極の膜厚より厚い配線と、を具備したものである。 In order to solve the above problems, a thin film semiconductor device for a display device which is one embodiment of the present invention includes a gate electrode, a gate insulating film formed over the gate electrode, and a semiconductor formed over the gate insulating film A first transistor electrode formed on the semiconductor layer; a second transistor electrode formed on the semiconductor layer; and at least one electrode of the first transistor electrode or the second transistor electrode; The wiring is electrically connected and is separate from the one electrode and has a wiring that is thicker than the thickness of the one electrode.
　上記本発明の一態様である表示装置用薄膜半導体装置によれば、表示装置用薄膜半導体装置の配線と薄膜トランジスタの電極による電気抵抗を小さくしつつ、一方で、表示装置用薄膜半導体装置の平坦性の確保を、プロセス負担を少なく達成することができる。その結果、この表示装置用薄膜半導体装置を備えた表示装置を大画面化、駆動周波数を増大化させても、表示装置用薄膜半導体装置の配線や薄膜トランジスタの電極の電気抵抗による信号遅延や電圧降下による表示ムラを減らすことができる。 According to the thin film semiconductor device for a display device which is one embodiment of the present invention, the flatness of the thin film semiconductor device for a display device is reduced while reducing the electrical resistance due to the wiring of the thin film semiconductor device for the display device and the electrode of the thin film transistor. Can be achieved with less process burden. As a result, even if the display device provided with the thin film semiconductor device for display device has a large screen and the drive frequency is increased, the signal delay or voltage drop due to the electric resistance of the wiring of the thin film semiconductor device for display device or the electrode of the thin film transistor Display unevenness due to can be reduced.
図１は、実施の形態のパネル基板を示す図である。FIG. 1 is a diagram illustrating a panel substrate according to an embodiment. 図２は、実施の形態の有機ＥＬディスプレイの斜視図である。FIG. 2 is a perspective view of the organic EL display according to the embodiment. 図３は、実施の形態の画素を駆動する画素回路の回路構成を示す図である。FIG. 3 is a diagram illustrating a circuit configuration of a pixel circuit that drives the pixel according to the embodiment. 図４は、実施の形態の画素の構成を示す平面図である。FIG. 4 is a plan view illustrating a configuration of a pixel according to the embodiment. 図５は、図４のＡ－Ａ’線における断面図である。FIG. 5 is a cross-sectional view taken along line A-A ′ of FIG. 図６は、実施の形態の表示装置用薄膜半導体装置の分解斜視図である。FIG. 6 is an exploded perspective view of the thin film semiconductor device for a display device according to the embodiment. 図７は、実施の形態の表示装置の断面図である。FIG. 7 is a cross-sectional view of the display device according to the embodiment. 図８Ａは、実施の形態の表示装置用薄膜半導体装置の工程断面図である。FIG. 8A is a process sectional view of the thin film semiconductor device for display device of the embodiment. 図８Ｂは、実施の形態の表示装置用薄膜半導体装置の工程断面図である。FIG. 8B is a process sectional view of the thin film semiconductor device for display device of the embodiment. 図８Ｃは、実施の形態の表示装置用薄膜半導体装置の工程断面図である。FIG. 8C is a process cross-sectional view of the thin film semiconductor device for display device of the embodiment. 図８Ｄは、実施の形態の表示装置用薄膜半導体装置の工程断面図である。FIG. 8D is a process sectional view of the thin film semiconductor device for display device of the embodiment. 図８Ｅは、実施の形態の表示装置用薄膜半導体装置の工程断面図である。FIG. 8E is a process cross-sectional view of the thin film semiconductor device for display device of the embodiment. 図９Ａは、実施の形態のハーフトーンマスクを用いたフォトリソグラフィ及びエッチング工程の表示薄膜半導体装置の工程断面図である。FIG. 9A is a process cross-sectional view of a display thin film semiconductor device in a photolithography and etching process using the halftone mask of the embodiment. 図９Ｂは、実施の形態のハーフトーンマスクを用いたフォトリソグラフィ及びエッチング工程の表示薄膜半導体装置の工程断面図である。FIG. 9B is a process sectional view of the display thin film semiconductor device in the photolithography and etching process using the halftone mask of the embodiment. 図９Ｃは、実施の形態のハーフトーンマスクを用いたフォトリソグラフィ及びエッチング工程の表示薄膜半導体装置の工程断面図である。FIG. 9C is a process sectional view of the display thin film semiconductor device in the photolithography and etching process using the halftone mask of the embodiment. 図９Ｄは、実施の形態のハーフトーンマスクを用いたフォトリソグラフィ及びエッチング工程の表示薄膜半導体装置の工程断面図である。FIG. 9D is a process sectional view of the display thin film semiconductor device in a photolithography and etching process using the halftone mask of the embodiment. 図９Ｅは、実施の形態のハーフトーンマスクを用いたフォトリソグラフィ及びエッチング工程の表示薄膜半導体装置の工程断面図である。FIG. 9E is a process sectional view of the display thin film semiconductor device in the photolithography and etching process using the halftone mask of the embodiment.
　本発明の一態様に係る表示装置用薄膜半導体装置は、ゲート電極と、前記ゲート電極上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成された半導体層と、前記半導体層上に形成された第１トランジスタ電極と、前記半導体層上に形成された第２トランジスタ電極と、前記第１トランジスタ電極又は前記第２トランジスタ電極の少なくともいずれか一方の電極上に形成され、前記一方の電極と電気的に接続され、前記一方の電極と別体であって前記一方の電極の膜厚より厚い配線と、を具備している。 A thin film semiconductor device for a display device according to one embodiment of the present invention includes a gate electrode, a gate insulating film formed over the gate electrode, a semiconductor layer formed over the gate insulating film, and the semiconductor layer A first transistor electrode formed; a second transistor electrode formed on the semiconductor layer; and the one electrode formed on at least one of the first transistor electrode and the second transistor electrode. And a wiring that is separate from the one electrode and is thicker than the thickness of the one electrode.
　本態様は、前記配線が、前記ゲート絶縁膜上に形成された第１トランジスタ電極（ソース電極、またはドレイン電極）、又は、前記ゲート絶縁膜上に形成された第２トランジスタ電極（ドレイン電極、またはソース電極）のいずれか一方よりも膜厚が厚い構成である。 In this embodiment, the wiring is a first transistor electrode (source electrode or drain electrode) formed on the gate insulating film, or a second transistor electrode (drain electrode or formed) formed on the gate insulating film. The source electrode is thicker than any one of the source electrodes).
　本態様によると、半導体層上に形成された第１トランジスタ電極又は第２トランジスタ電極のいずれかと電気的に接続され、その電極の膜厚より厚い配線を形成する。それにより、配線の電気抵抗は配線の断面積に反比例する関係であるので、配線の膜厚が厚くなることで、その配線の断面積も大きくなり、電気抵抗が小さくなる。また、配線の膜厚は、表示装置用薄膜半導体装置の特性に応じて任意に厚くできるので、配線の電気抵抗を小さくすることもできる。また、前記配線は、前記第１トランジスタ電極の上、又は第２トランジスタ電極の上に形成した構成とすることができる。そのため、前記配線と、第１トランジスタ電極又は第２トランジスタ電極との接続長を短くすることができるので、前記配線と電気的に接続された電極間との電気抵抗を小さくするためにも好適である。その結果、電気的に接続している電極に少ない遅延で電圧を印加できる。 According to this aspect, a wiring that is electrically connected to either the first transistor electrode or the second transistor electrode formed on the semiconductor layer and is thicker than the thickness of the electrode is formed. Accordingly, since the electrical resistance of the wiring is inversely proportional to the cross-sectional area of the wiring, the cross-sectional area of the wiring increases and the electrical resistance decreases as the wiring film thickness increases. In addition, since the thickness of the wiring can be arbitrarily increased according to the characteristics of the thin film semiconductor device for a display device, the electrical resistance of the wiring can be reduced. The wiring may be formed on the first transistor electrode or the second transistor electrode. Therefore, since the connection length between the wiring and the first transistor electrode or the second transistor electrode can be shortened, it is also suitable for reducing the electrical resistance between the electrodes electrically connected to the wiring. is there. As a result, a voltage can be applied to the electrically connected electrodes with a small delay.
　したがって、前記一方の電極上に形成された配線の膜厚は前記一方の電極の膜厚より厚いため、薄膜半導体装置としての配線の電気抵抗を低減した薄膜半導体装置を実現できるものである。 Therefore, since the film thickness of the wiring formed on the one electrode is thicker than the film thickness of the one electrode, a thin film semiconductor device with reduced electric resistance of the wiring as a thin film semiconductor device can be realized.
　また、有機ＥＬ表示装置の表示部で発生した熱を、前記配線を介して速やかに基板の面内方向に散逸させることができるので、熱影響を低減できる。 Further, since the heat generated in the display unit of the organic EL display device can be quickly dissipated through the wiring in the in-plane direction of the substrate, the thermal influence can be reduced.
　また、トランジスタの電極を配線から延設した構造とすることができ、配線の電気抵抗による信号電圧の低下を防止できる。このため、特に、有機ＥＬ表示装置用のスイッチングトランジスタとして採用する上でも好適である。また、トランジスタの構成を簡略化できることなる。 Also, the transistor electrode can be extended from the wiring, and the signal voltage can be prevented from being lowered due to the electric resistance of the wiring. Therefore, it is particularly suitable for use as a switching transistor for an organic EL display device. In addition, the structure of the transistor can be simplified.
　また、さらには、特に、有機ＥＬ表示装置用のスイッチングトランジスタを、有機ＥＬ表示装置の画素領域内で自由に配置できるため、トランジスタのレイアウト設計の最適化を実現する上でも好適である。 Furthermore, in particular, since the switching transistor for the organic EL display device can be freely arranged in the pixel region of the organic EL display device, it is suitable for realizing optimization of the transistor layout design.
　本発明の一態様に係る表示装置用薄膜半導体装置は、前記第１トランジスタ電極はソース電極であり、前記第２トランジスタ電極はドレイン電極であり、前記配線は、前記ソース電極と電気的に接続されたソース配線としてもよい。 In the thin film semiconductor device for a display device according to one embodiment of the present invention, the first transistor electrode is a source electrode, the second transistor electrode is a drain electrode, and the wiring is electrically connected to the source electrode. A source wiring may be used.
　本態様によると、トランジスタのソース電極をソース配線から延設した構造とすることもできるため、配線の電気抵抗による電源電圧の低下を防止できる。このため、特には、有機ＥＬ表示装置用の駆動トランジスタとして採用する上でも好適である。また、トランジスタの構成を簡略化できることなる。 According to this aspect, since the source electrode of the transistor can be extended from the source wiring, it is possible to prevent the power supply voltage from being lowered due to the electrical resistance of the wiring. Therefore, it is particularly suitable for use as a drive transistor for an organic EL display device. In addition, the structure of the transistor can be simplified.
　またさらには、特に、有機ＥＬ表示装置用の駆動トランジスタを、有機ＥＬ素子の画素領域内で自由に配置できるため、トランジスタレイアウト設計の最適化を実現する上でも好適である。 Furthermore, in particular, the drive transistor for the organic EL display device can be freely arranged in the pixel region of the organic EL element, which is suitable for realizing optimization of transistor layout design.
　本発明の一態様に係る表示装置用薄膜半導体装置は、前記第１トランジスタ電極はソース電極であり、前記第２トランジスタ電極はドレイン電極であり、前記配線は、前記ドレイン電極と電気的に接続された電源配線としてもよい。 In the thin film semiconductor device for a display device according to one embodiment of the present invention, the first transistor electrode is a source electrode, the second transistor electrode is a drain electrode, and the wiring is electrically connected to the drain electrode. Alternatively, power supply wiring may be used.
　本態様によると、トランジスタのドレイン電極を電源配線から延設した構造とすることもできるため、配線の電気抵抗による電源電圧の低下を防止できる。このため、特には、有機ＥＬ表示装置用の駆動トランジスタとして採用する上でも好適である。また、トランジスタの構成を簡略化できることとなる。 According to this aspect, since the drain electrode of the transistor can be extended from the power supply wiring, it is possible to prevent the power supply voltage from being lowered due to the electrical resistance of the wiring. Therefore, it is particularly suitable for use as a drive transistor for an organic EL display device. In addition, the structure of the transistor can be simplified.
　またさらには、特に、有機ＥＬ表示装置用の駆動トランジスタを、有機ＥＬ素子の画素領域内で自由に配置できるため、トランジスタレイアウト設計の最適化を実現する上でも好適である。 Furthermore, in particular, the drive transistor for the organic EL display device can be freely arranged in the pixel region of the organic EL element, which is suitable for realizing optimization of transistor layout design.
　本発明の一態様に係る表示装置用薄膜半導体装置は、前記配線は、前記配線と電気的に接続された前記第１トランジスタ電極又は前記第２トランジスタ電極の少なくともいずれか一方の電極の上であって、前記半導体層の上方と少なくとも一部が重なる領域に形成されてもよい。 In the thin film semiconductor device for a display device according to one embodiment of the present invention, the wiring is over at least one of the first transistor electrode and the second transistor electrode electrically connected to the wiring. In addition, the semiconductor layer may be formed in a region at least partially overlapping with the upper side of the semiconductor layer.
　本態様によると、前記半導体層の少なくとも一部を前記配線の下方に配置した構造とすることができる。このため、前記配線層と電極との配線の電気抵抗を極小化でき、信号電圧の低下を極力防止でき、特には、有機ＥＬ表示装置用の駆動トランジスタ、スイッチングトランジスタとして採用する上でも好適である。 According to this aspect, a structure in which at least a part of the semiconductor layer is disposed below the wiring can be obtained. For this reason, the electrical resistance of the wiring between the wiring layer and the electrode can be minimized, and a decrease in the signal voltage can be prevented as much as possible. In particular, it is suitable for use as a drive transistor and a switching transistor for an organic EL display device. .
　また、トランジスタの少なくとも一部が前記配線の下部の配置されるため、有機ＥＬ表示装置に採用した場合、画素サイズの小型化、すなわち、有機ＥＬ表示装置の超高精細度化、歩留り向上が実現できる好適な構成である。 In addition, since at least a part of the transistor is arranged below the wiring, when it is used in an organic EL display device, the pixel size is reduced, that is, the organic EL display device has ultra-high definition and the yield is improved. This is a preferable configuration.
　さらには、例えば、有機ＥＬ表示装置に採用した場合に、画素の発光面積の増加も実現できるものである。 Furthermore, for example, when employed in an organic EL display device, an increase in the light emission area of the pixel can be realized.
　本発明の一態様に係る表示装置用薄膜半導体装置は、前記配線と電気的に接続された前記第１トランジスタ電極又は前記第２トランジスタ電極の少なくともいずれか一方の電極は、前記半導体層の領域外に延設され、前記配線は、前記配線と電気的に接続された前記第１トランジスタ電極又は前記第２トランジスタ電極の少なくともいずれか一方の電極の前記延設された領域上に形成してもよい。 In the thin film semiconductor device for a display device according to one embodiment of the present invention, at least one of the first transistor electrode and the second transistor electrode electrically connected to the wiring is outside the region of the semiconductor layer. The wiring may be formed on the extended region of at least one of the first transistor electrode and the second transistor electrode electrically connected to the wiring. .
　本態様によると、トランジスタのソース電極、又はドレイン電極を、各々ソース配線、又は電源配線から延設した構造とすることもできるため、配線の電気抵抗による電源電圧の低下を防止できる。このため、特には、有機ＥＬ表示装置用のスイッチングトランジスタ、又は駆動トランジスタとして採用する上でも好適である。 According to this aspect, since the source electrode or the drain electrode of the transistor can be extended from the source wiring or the power supply wiring, respectively, the power supply voltage can be prevented from being lowered due to the electrical resistance of the wiring. Therefore, it is particularly suitable for use as a switching transistor or a driving transistor for an organic EL display device.
　またさらには、特に、有機ＥＬ表示装置用のスイッチングトランジスタ、又は駆動トランジスタを、有機ＥＬ素子の画素領域内で自由に配置できるため、トランジスタレイアウト設計の最適化を実現する上でも好適である。 Furthermore, in particular, since a switching transistor or a driving transistor for an organic EL display device can be freely arranged in the pixel region of the organic EL element, it is also suitable for realizing optimization of transistor layout design.
　本発明の一態様に係る表示装置用薄膜半導体装置において、前記配線の電気抵抗は、前記配線と電気的に接続された前記第１トランジスタ電極又は前記第２トランジスタ電極の少なくともいずれか一方の電極の電気抵抗より小さくてもよい。 In the thin film semiconductor device for a display device according to one embodiment of the present invention, the electrical resistance of the wiring is that of at least one of the first transistor electrode and the second transistor electrode electrically connected to the wiring. It may be smaller than the electrical resistance.
　本態様によると、配線の電気抵抗がトランジスタ電極の電気抵抗より小さくすることができる。そのため、本態様の薄膜半導体装置を、例えば、有機ＥＬ表示装置に用いた場合に、表示装置としての配線の電気抵抗に係る電圧低下を抑えるなどの課題を解決できるものであり、その効果は表示装置が大画面化するほど顕著である。 According to this aspect, the electrical resistance of the wiring can be made smaller than the electrical resistance of the transistor electrode. Therefore, when the thin film semiconductor device of this aspect is used for an organic EL display device, for example, it is possible to solve problems such as suppressing a voltage drop related to the electrical resistance of the wiring as the display device, and the effect is This is more noticeable as the screen becomes larger.
　本発明の一態様に係る表示装置用薄膜半導体装置は、ゲート配線と、前記ゲート配線から延設された第１ゲート電極と、前記第１ゲート電極上に形成された第１ゲート絶縁膜と、前記第１ゲート絶縁膜上に形成された第１半導体層と、前記第１半導体層上に形成された第１トランジスタ電極と、前記第１半導体層上に形成された第２トランジスタ電極と、前記第２トランジスタ電極と電気接続された第２ゲート電極と、前記第２ゲート電極上に形成された第２ゲート絶縁膜と、前記第２ゲート絶縁膜上に形成された第２半導体層と、前記第２半導体層上に形成された第３トランジスタ電極と、前記第２半導体層上に形成された第４トランジスタ電極と、前記ゲート配線と交差し、前記第１トランジスタ電極上に形成され、前記第１トランジスタ電極と別体であって前記第１トランジスタ電極の膜厚より厚い第１配線と、前記ゲート配線と交差し、前記第４トランジスタ電極上に形成され、前記第４トランジスタ電極と別体であって前記第４トランジスタ電極の膜厚より厚い第２配線と、を具備し、前記第２トランジスタ電極又は前記第３トランジスタ電極の少なくとも何れか一方は、前記第１トランジスタ電極及び前記第４トランジスタ電極の間に配置さてれていることを特徴とする。 A thin film semiconductor device for a display device according to one embodiment of the present invention includes a gate wiring, a first gate electrode extending from the gate wiring, a first gate insulating film formed over the first gate electrode, A first semiconductor layer formed on the first gate insulating film; a first transistor electrode formed on the first semiconductor layer; a second transistor electrode formed on the first semiconductor layer; A second gate electrode electrically connected to the second transistor electrode; a second gate insulating film formed on the second gate electrode; a second semiconductor layer formed on the second gate insulating film; A third transistor electrode formed on the second semiconductor layer; a fourth transistor electrode formed on the second semiconductor layer; and a gate transistor interconnected with the third transistor electrode, formed on the first transistor electrode, 1 transition A first wiring thicker than the first transistor electrode and crossing the gate wiring, formed on the fourth transistor electrode, and separate from the fourth transistor electrode. Second wiring thicker than the thickness of the fourth transistor electrode, and at least one of the second transistor electrode and the third transistor electrode is formed of the first transistor electrode and the fourth transistor electrode. It is arranged between them.
　本態様によると、配線の間に複数の薄膜トランジスタが形成された態様に係るものである。本態様によれば、前記配線の膜厚よりも前記複数のトランジスタ電極の膜厚を薄くすることができるため、薄膜トランジスタ形成領域の表面の起伏を低く抑えつつ、かつ、配線の膜厚を厚くすることができる。従って、本態様によれば、配線の電気抵抗を低減した薄膜半導体装置を実現できるものである。 This aspect relates to an aspect in which a plurality of thin film transistors are formed between the wirings. According to this aspect, since the thickness of the plurality of transistor electrodes can be made thinner than the thickness of the wiring, the thickness of the wiring is increased while suppressing the undulation of the surface of the thin film transistor formation region. be able to. Therefore, according to this aspect, a thin film semiconductor device in which the electrical resistance of the wiring is reduced can be realized.
　また、本態様によると、前記第１配線、および第２配線が厚いため、薄膜半導体装置としての配線の電気抵抗を低下する好適な構成である。 Further, according to this aspect, since the first wiring and the second wiring are thick, the electrical resistance of the wiring as a thin film semiconductor device is reduced.
　また、有機ＥＬ表示装置の画像表示で発生した熱を、前記第１配線、および第２配線を介して速やかに基板の面内方向に散逸させることができるので、熱影響を低減できる。 In addition, since the heat generated in the image display of the organic EL display device can be quickly dissipated through the first wiring and the second wiring in the in-plane direction of the substrate, the thermal influence can be reduced.
　本態様には、前記配線間に形成されるトランジスタは２個よりも多い態様をも含み、具体的にはトランジスタを３個あるいは４個とし、複数の薄膜トランジスタ個々の特性バラツキを補償する、所謂、内部補償型回路を実現する場合にも好適なものである。 This mode includes a mode in which more than two transistors are formed between the wirings. Specifically, the number of transistors is three or four, and the so-called It is also suitable for realizing an internal compensation type circuit.
　本発明の一態様に係る表示装置用薄膜半導体装置は、前記第２トランジスタ電極及び前記第３トランジスタ電極は、前記第１トランジスタ電極及び前記第４トランジスタ電極の間に配置されること特徴とする。 The thin film semiconductor device for a display device according to one embodiment of the present invention is characterized in that the second transistor electrode and the third transistor electrode are disposed between the first transistor electrode and the fourth transistor electrode.
　本態様によると、前記第１トランジスタ電極及び前記第４トランジスタ電極の間に前記第２トランジスタ電極及び前記第３トランジスタ電極を配置することにより、前記第１トランジスタ電極と前記第４トランジスタ電極とに挟まれた領域は平坦となるので、薄膜半導体装置の表面に起伏が生ずるのを抑え、かつ、配線の電気抵抗を低減した薄膜半導体装置を実現できるものである。 According to this aspect, the second transistor electrode and the third transistor electrode are disposed between the first transistor electrode and the fourth transistor electrode, thereby sandwiching the first transistor electrode and the fourth transistor electrode. Since the formed region becomes flat, it is possible to realize a thin film semiconductor device that suppresses the occurrence of undulations on the surface of the thin film semiconductor device and reduces the electrical resistance of the wiring.
　本発明の一態様に係る表示装置用薄膜半導体装置は、前記第１トランジスタ電極はスイッチングトランジスタのソース電極であり、前記第２トランジスタ電極は前記スイッチングトランジスタのドレイン電極であり、前記第３トランジスタ電極は駆動トランジスタのソース電極であり、前記第４トランジスタ電極は前記駆動トランジスタのドレイン電極であることを特徴とする。 In the thin film semiconductor device for a display device according to one embodiment of the present invention, the first transistor electrode is a source electrode of a switching transistor, the second transistor electrode is a drain electrode of the switching transistor, and the third transistor electrode is It is a source electrode of the driving transistor, and the fourth transistor electrode is a drain electrode of the driving transistor.
　本態様によると、例えば、アクティブマトリックス型の有機ＥＬ表示装置の基本構成トランジスタである、スイッチングトランジスタと駆動トランジスタとを有する薄膜半導体装置を実現できる。 According to this aspect, for example, it is possible to realize a thin film semiconductor device having a switching transistor and a driving transistor, which are basic transistors of an active matrix type organic EL display device.
　すなわち、本態様の薄膜半導体装置を表示装置の駆動回路として採用することで、例えば表示装置の配線の電気抵抗、発熱などに起因する表示装置の輝度ムラを防止できる。特には、大画面の表示装置に用いた場合での効果は絶大である。 That is, by adopting the thin film semiconductor device of this aspect as a drive circuit of the display device, it is possible to prevent uneven brightness of the display device due to, for example, electrical resistance of the wiring of the display device, heat generation, or the like. In particular, the effect when used in a large-screen display device is tremendous.
　本発明の一態様に係る表示装置は、上述の表示装置用薄膜半導体装置上に表示デバイスが形成されていることを特徴とする。  A display device according to one embodiment of the present invention is characterized in that a display device is formed over the above-described thin film semiconductor device for a display device.
　本願発明の薄膜半導体装置を表示装置の駆動回路として採用することで、例えば表示装置の配線の電気抵抗、発熱などに起因する表示装置の輝度ムラを防止できる。特には、大画面表示装置に用いた場合での効果は絶大である。 By adopting the thin film semiconductor device of the present invention as a drive circuit for a display device, it is possible to prevent uneven brightness of the display device due to, for example, the electrical resistance of the wiring of the display device, heat generation, or the like. In particular, the effect when used in a large screen display device is tremendous.
　本発明の一態様に係る表示装置は、上述の表示装置用薄膜半導体装置を備え、前記第１配線、前記第２配線、前記第２トランジスタ電極及び前記第３トランジスタ電極の各上面は、絶縁膜により被覆され、前記絶縁膜によって被覆された前記第１配線及び前記第２配線を隔壁として、この隔壁間に、陽極、陰極、前記陽極と陰極との間に介在する発光層を積層したことを特徴とする。 A display device according to one embodiment of the present invention includes the above-described thin film semiconductor device for a display device, and each upper surface of the first wiring, the second wiring, the second transistor electrode, and the third transistor electrode includes an insulating film. The first wiring and the second wiring covered by the insulating film are used as partition walls, and an anode, a cathode, and a light emitting layer interposed between the anode and cathode are laminated between the partition walls. Features.
　本態様によると、第１のトランジスタ電極、第２のトランジスタ電極、第３のトランジスタ電極及び第４のトランジスタ電極の膜厚よりも厚い配線層の表面が、パッシベーション膜で覆われている。また本態様の表示装置の構成は、前記発光部が、前記パッシベーション膜で被覆され、膜厚が厚い前記第１配線と前記第２配線との間に配置されているために、本態様の表示装置においては、前記パッシベーション膜で覆われた前記第１配線と前記第２配線とは、隔壁の機能を有することとなる。 According to this aspect, the surface of the wiring layer that is thicker than the film thickness of the first transistor electrode, the second transistor electrode, the third transistor electrode, and the fourth transistor electrode is covered with the passivation film. The display device according to this aspect is configured such that the light emitting portion is covered with the passivation film and disposed between the first wiring and the second wiring having a large film thickness. In the device, the first wiring and the second wiring covered with the passivation film have a function of a partition wall.
　すなわち、本態様の表示装置では、隔壁を別構成として形成しなくてもよく、構成と製造プロセスの簡略化が図れるものとなる。 That is, in the display device of this aspect, the partition does not have to be formed as a separate configuration, and the configuration and the manufacturing process can be simplified.
　本発明の一態様に係る表示装置用薄膜半導体装置の製造方法においては、基板上にゲート電極を形成する工程と、前記ゲート電極上にゲート絶縁膜を形成する工程と、前記ゲート絶縁膜上に半導体層を形成する工程と、前記半導体層上に第１トランジスタ電極と第２トランジスタ電極とを形成する工程と、前記第１トランジスタ電極又は第２トランジスタ電極の少なくともいずれか一方の電極と別体であって前記一方の電極よりも厚い配線を、前記一方の電極上に形成する工程と、を含む。 In the method for manufacturing a thin film semiconductor device for a display device according to one embodiment of the present invention, a step of forming a gate electrode on a substrate, a step of forming a gate insulating film on the gate electrode, and a step of forming on the gate insulating film A step of forming a semiconductor layer; a step of forming a first transistor electrode and a second transistor electrode on the semiconductor layer; and at least one of the first transistor electrode and the second transistor electrode. And forming a wiring thicker than the one electrode on the one electrode.
　本態様によると、前記トランジスタ電極と前記配線とを別工程で形成できるため、配線は任意の膜厚であって、前記トランジスタ電極の膜厚よりも厚く形成することが容易に実施できることとなる。 According to this aspect, since the transistor electrode and the wiring can be formed in separate steps, the wiring can be easily formed to have an arbitrary film thickness and larger than the film thickness of the transistor electrode.
　すなわち、前述した構造の薄膜半導体装置を製造するためにも好適な態様を実現できるものである。 That is, it is possible to realize a suitable mode for manufacturing a thin film semiconductor device having the structure described above.
　本発明の一態様に係る表示装置用薄膜半導体装置の製造方法においては、前記配線を形成する工程はスパッタ法、メッキ法、あるいは印刷法により実施されてもよい。 In the method for manufacturing a thin film semiconductor device for a display device according to one embodiment of the present invention, the step of forming the wiring may be performed by a sputtering method, a plating method, or a printing method.
　本態様によると、前記配線はスパッタ法、メッキ法、あるいは印刷法で形成される。スパッタ法の中でも、特にＤＣマグネトロンスパッタ方は、金属膜を高速に、かつ、大面積で容易に形成でき、また、形成された膜の平滑性、膜厚均一性も優れており、好適な形成方法である。 According to this aspect, the wiring is formed by a sputtering method, a plating method, or a printing method. Among the sputtering methods, particularly the DC magnetron sputtering method can easily form a metal film at a high speed and in a large area, and the formed film is excellent in smoothness and film thickness uniformity, and is suitable for formation. Is the method.
　また、メッキ法、印刷法は該配線層を簡便な製造方法であり、短時間に容易に厚く形成でき、量産性に優れた製造方法を実現する上で好適な態様である。 Further, the plating method and the printing method are simple manufacturing methods, and are suitable for realizing a manufacturing method that can be easily formed thick in a short time and has excellent mass productivity.
　以下、本発明の実施形態に係る表示装置用薄膜半導体装置、その表示装置用薄膜半導体装を用いた表示装置及び表示装置用薄膜半導体装置の製造方法について、図面を参照しながら説明する。なお、本発明は、以下の実施形態に限定されないことは言うまでもない。また、各図は、説明のための模式図であり、膜厚及び各部の大きさの比などは、必ずしも厳密ではない。 Hereinafter, a thin film semiconductor device for a display device according to an embodiment of the present invention, a display device using the thin film semiconductor device for the display device, and a manufacturing method of the thin film semiconductor device for the display device will be described with reference to the drawings. In addition, it cannot be overemphasized that this invention is not limited to the following embodiment. Each figure is a schematic diagram for explanation, and a film thickness, a ratio of sizes of parts, and the like are not necessarily strict.
（実施の形態）
　以下、本発明の一態様である表示装置用薄膜半導体装置の実施の形態について、図面を用いて説明する。なお、本実施の形態では、表示装置用薄膜半導体装置が採用される表示装置の一例として、有機ＥＬ（Ｅｌｅｃｔｒｏ　Ｌｕｍｉｎｅｓｃｅｎｃｅ）ディスプレイを用いて説明する。 (Embodiment)
Embodiments of a thin film semiconductor device for a display device which is one embodiment of the present invention are described below with reference to the drawings. Note that in this embodiment, an organic EL (Electro Luminescence) display is described as an example of a display device using a thin film semiconductor device for a display device.
　図１～図３を参照して、本発明の実施の形態に係る有機ＥＬディスプレイ及び表示装置用薄膜半導体装置について説明する。 With reference to FIGS. 1 to 3, an organic EL display and a thin film semiconductor device for a display device according to an embodiment of the present invention will be described.
　図１は、複数枚の有機ＥＬディスプレイが面取りされるパネル基板１を示す図である。図１において、パネル基板１から、例えば、２枚の有機ＥＬディスプレイ１０が面取りされる。各有機ＥＬディスプレイ１０は複数の画素１００を含んでいる。 FIG. 1 is a diagram showing a panel substrate 1 on which a plurality of organic EL displays are chamfered. In FIG. 1, for example, two organic EL displays 10 are chamfered from the panel substrate 1. Each organic EL display 10 includes a plurality of pixels 100.
　図２は、本発明の実施の形態に係る有機ＥＬディスプレイ１０の構造を分解して示した分解斜視図である。図２において、有機ＥＬディスプレイ１０は、下層より、表示装置用薄膜半導体装置２０、平坦化膜１１、陽極１２、有機ＥＬ層１３及び透明陰極１４の積層構造体である。表示装置用薄膜半導体装置２０には、複数の画素１００がｍ行×ｎ列のマトリクス状に配置されている。各画素１００は、それぞれに設けられた画素回路３０によって駆動される。また、表示装置用薄膜半導体装置２０は、前記マトリクス状の各行に配置される複数のゲート配線２１と、ゲート配線２１と交差するように前記マトリクス状の各列に配置される複数の金属配線（本実施の形態では、一例として信号線としてのソース配線）２２と、ソース配線２２に平行に延びる複数の金属配線（本実施の形態では、一例として電源配線）２３とを備える。このゲート配線２１は、画素回路３０のそれぞれに含まれるスイッチング素子として動作する第１薄膜トランジスタのゲートを行毎に接続する。ソース配線２２は、画素回路３０のそれぞれに含まれるスイッチング素子として動作する薄膜トランジスタのソース電極４２（図２では図示省略）を列毎に接続する。電源配線２３は、画素回路３０のそれぞれに含まれる駆動素子として動作する第２薄膜トランジスタ５０のドレインを列毎に接続する。 FIG. 2 is an exploded perspective view showing the structure of the organic EL display 10 according to the embodiment of the present invention in an exploded manner. In FIG. 2, the organic EL display 10 is a laminated structure of a thin film semiconductor device 20 for a display device, a planarizing film 11, an anode 12, an organic EL layer 13 and a transparent cathode 14 from the lower layer. In the thin film semiconductor device 20 for display device, a plurality of pixels 100 are arranged in a matrix of m rows × n columns. Each pixel 100 is driven by a pixel circuit 30 provided therein. Further, the thin film semiconductor device 20 for display device includes a plurality of gate wirings 21 arranged in each row of the matrix and a plurality of metal wirings arranged in each column of the matrix so as to intersect the gate wiring 21 ( In this embodiment, as an example, a source wiring 22 as a signal line) and a plurality of metal wirings (in this embodiment, a power supply wiring) 23 extending in parallel with the source wiring 22 are provided. The gate wiring 21 connects the gates of the first thin film transistors that operate as switching elements included in each of the pixel circuits 30 for each row. The source line 22 connects a source electrode 42 (not shown in FIG. 2) of a thin film transistor operating as a switching element included in each pixel circuit 30 for each column. The power supply wiring 23 connects the drains of the second thin film transistors 50 that operate as drive elements included in each of the pixel circuits 30 for each column.
　図３は、画素１００を駆動する画素回路３０の回路構成を示す図である。 FIG. 3 is a diagram illustrating a circuit configuration of the pixel circuit 30 that drives the pixel 100.
　画素回路３０は、図３に示されるように、スイッチング素子として動作する第１薄膜トランジスタ４０と、駆動素子として動作する第２薄膜トランジスタ５０の２つのトランジスタと、スイッチング素子として動作する第１薄膜トランジスタ４０のゲート電極４１に接続されている１本のゲート配線２１と、ソース配線２２と、電源配線２３と、対応する画素に表示するデータを記憶するキャパシタ６０とで構成される。 As shown in FIG. 3, the pixel circuit 30 includes two transistors, a first thin film transistor 40 that operates as a switching element, a second thin film transistor 50 that operates as a driving element, and a gate of the first thin film transistor 40 that operates as a switching element. The gate line 21 is connected to the electrode 41, the source line 22, the power supply line 23, and a capacitor 60 for storing data to be displayed on the corresponding pixel.
　第１薄膜トランジスタ４０は、ゲート配線２１に接続されるゲート電極４１と、ソース配線２２に接続されるソース電極４２と、キャパシタ６０及び第２薄膜トランジスタ５０のゲート電極５１に接続されるドレイン電極４３と、半導体層とで構成される。この第１薄膜トランジスタ４０は、接続されたゲート配線２１及びソース配線２２に電圧が印加されると、ソース配線２２に印加された電圧値を表示データとしてキャパシタ６０に保存する。 The first thin film transistor 40 includes a gate electrode 41 connected to the gate line 21, a source electrode 42 connected to the source line 22, a drain electrode 43 connected to the capacitor 60 and the gate electrode 51 of the second thin film transistor 50, It is composed of a semiconductor layer. When a voltage is applied to the connected gate line 21 and source line 22, the first thin film transistor 40 stores the voltage value applied to the source line 22 in the capacitor 60 as display data.
　第２薄膜トランジスタ５０は、第１薄膜トランジスタ４０のドレイン電極４３に接続されるゲート電極５１と、電源配線２３及びキャパシタ６０に接続されるドレイン電極５２と、陽極１２に接続されるソース電極５３と、半導体層とで構成される。この第２薄膜トランジスタ５０は、キャパシタ６０が保持している電圧値に対応する電流を電源配線２３からソース電極５３を通じて陽極１２に供給する。 The second thin film transistor 50 includes a gate electrode 51 connected to the drain electrode 43 of the first thin film transistor 40, a drain electrode 52 connected to the power supply line 23 and the capacitor 60, a source electrode 53 connected to the anode 12, and a semiconductor. Composed of layers. The second thin film transistor 50 supplies a current corresponding to the voltage value held by the capacitor 60 from the power supply wiring 23 to the anode 12 through the source electrode 53.
　すなわち、上記構成の有機ＥＬディスプレイ１０は、ゲート配線２１とソース配線２２との交点に位置する画素１００毎に表示制御を行うアクティブマトリックス方式を採用している。 That is, the organic EL display 10 having the above configuration employs an active matrix system in which display control is performed for each pixel 100 located at the intersection of the gate wiring 21 and the source wiring 22.
（表示装置用薄膜半導体装置の構成）
　次に、図４から図６を参照して、表示装置用薄膜半導体装置２０を構成する画素１００の構造を説明する。なお、図４は、画素１００の構成を示す平面図である。図５は、図４のＡ－Ａ’線における断面図である。図６は、画素１００の構成を示す分解斜視図である。 (Configuration of thin film semiconductor device for display device)
Next, the structure of the pixel 100 constituting the thin film semiconductor device 20 for display device will be described with reference to FIGS. FIG. 4 is a plan view showing the configuration of the pixel 100. FIG. 5 is a cross-sectional view taken along line AA ′ of FIG. FIG. 6 is an exploded perspective view showing the configuration of the pixel 100.
　図４から図６に示されるように、画素１００の構成は、ソース配線２２及び電源配線２３、ゲート配線２１の上に形成されている絶縁層１３０、ゲート配線２１とソース配線２２及び電源配線２３との交差領域近傍に形成される２つの薄膜トランジスタ（第１薄膜トランジスタ４０、第２薄膜トランジスタ５０）からなっている。 As shown in FIGS. 4 to 6, the configuration of the pixel 100 includes a source line 22 and a power line 23, an insulating layer 130 formed on the gate line 21, a gate line 21, a source line 22, and a power line 23. Are formed of two thin film transistors (first thin film transistor 40 and second thin film transistor 50) formed in the vicinity of the crossing region.
　ゲート配線２１と、ソース配線２２及び電源配線２３とはそれぞれゲート絶縁膜を延設した絶縁層１３０を介在させて、交差して配置されている。ここでは、例えば、ソース配線２２及び電源配線２３は同層に形成されているが、ゲート配線２１と、ソース配線２２及び電源配線２３とは、異なる層に形成されている。 The gate wiring 21, the source wiring 22, and the power supply wiring 23 are arranged so as to intersect each other with an insulating layer 130 having a gate insulating film extending therebetween. Here, for example, the source wiring 22 and the power supply wiring 23 are formed in the same layer, but the gate wiring 21, the source wiring 22 and the power supply wiring 23 are formed in different layers.
　その交差領域の近傍に形成されている２つの薄膜トランジスタ４０、５０は、例えば、それぞれ、スイッチング素子として動作する第１薄膜トランジスタ４０と、駆動素子として動作する第２薄膜トランジスタ５０の２つのトランジスタである。 The two thin film transistors 40 and 50 formed in the vicinity of the intersecting region are, for example, two transistors, a first thin film transistor 40 that operates as a switching element and a second thin film transistor 50 that operates as a drive element.
　第１薄膜トランジスタ４０のソース電極４２はソース配線２２から延設され、第２薄膜トランジスタ５０のドレイン電極５２は電源配線２３から延設されている。さらに第２薄膜トランジスタ５０のソース電極５３から画素用電極が延設されており、この画素用電極が表示部１９の陽極１２（図２参照）にコンタクトホール（不図示）を介して電気的に接続されている。 The source electrode 42 of the first thin film transistor 40 extends from the source wiring 22, and the drain electrode 52 of the second thin film transistor 50 extends from the power supply wiring 23. Further, a pixel electrode extends from the source electrode 53 of the second thin film transistor 50, and the pixel electrode is electrically connected to the anode 12 (see FIG. 2) of the display unit 19 through a contact hole (not shown). Has been.
　また、ソース配線２２及び電源配線２３は、第１薄膜トランジスタ４０のソース電極４２の上及び第２薄膜トランジスタ５０のドレイン電極５２の上に形成した構成である。この構成は、ソース配線２２又は電源配線２３と、第１薄膜トランジスタ４０のソース電極４２及び第２薄膜トランジスタ５０のドレイン電極５２との接続長を短くすることができるので、各配線と電極間での電気抵抗を小さくするためにも好適である。その結果、薄膜トランジスタ４０、５０の動作を良好にすることが容易となる。 The source wiring 22 and the power supply wiring 23 are formed on the source electrode 42 of the first thin film transistor 40 and on the drain electrode 52 of the second thin film transistor 50. In this configuration, since the connection length between the source wiring 22 or the power supply wiring 23 and the source electrode 42 of the first thin film transistor 40 and the drain electrode 52 of the second thin film transistor 50 can be shortened, the electrical connection between each wiring and the electrode can be reduced. It is also suitable for reducing the resistance. As a result, it becomes easy to improve the operation of the thin film transistors 40 and 50.
　また、表示装置用薄膜半導体装置２０は、２つの薄膜トランジスタ４０、５０それぞれの半導体層４４、５４の少なくとも一部をそれぞれソース配線２２、電源配線２３の下方に配置した構造である。このため、各配線層と各電極との配線の電気抵抗を極小化でき、信号電圧の低下を極力防止でき、特には、有機ＥＬ表示装置用の駆動トランジスタ、スイッチングトランジスタとして採用する上でも好適である。 Further, the thin film semiconductor device 20 for a display device has a structure in which at least a part of the semiconductor layers 44 and 54 of the two thin film transistors 40 and 50 are respectively disposed below the source wiring 22 and the power supply wiring 23. For this reason, the electrical resistance of the wiring between each wiring layer and each electrode can be minimized, and a decrease in the signal voltage can be prevented as much as possible, and is particularly suitable for use as a driving transistor and a switching transistor for an organic EL display device. is there.
　また、薄膜トランジスタの少なくとも一部が上記配線の下部の配置されるため、有機ＥＬ表示装置に採用した場合、画素サイズの小型化、すなわち、有機ＥＬ表示装置の超高精細度化、歩留り向上が実現できる好適な構成である。 In addition, since at least a part of the thin film transistor is disposed below the wiring, when it is used in an organic EL display device, the pixel size is reduced, that is, the organic EL display device has a higher definition and an improved yield. This is a preferable configuration.
　次に、図４におけるＡ－Ａ’断面を、図５を用いてより詳細に説明する。図５において、画素１００中における２つの薄膜トランジスタが形成されている。第１薄膜トランジスタ４０は、基板１１０、ゲート電極４１、ゲート絶縁膜１３０Ａ、半導体層４４、ソース配線２２、ソース配線２２の下に形成されるソース電極４２、ドレイン電極４３からなる構造体である。一方、第２薄膜トランジスタ５０は、基板１１０、ゲート電極５１、ゲート絶縁膜１３０Ｂ、半導体層５４、ソース電極５３、電源配線２３の下に形成されるドレイン電極５２からなる構造体である。これら２つのトランジスタの間に、２つのトランジスタのゲート電極４１と５１を電気的に分離するために第１薄膜トランジスタ４０のゲート絶縁膜１３０Ａを延設する。即ち、第１薄膜トランジスタ４０と第２薄膜トランジスタ５０とは、第１薄膜トランジスタ４０のゲート絶縁膜１３０Ａによって区切られている。 Next, the A-A ′ cross section in FIG. 4 will be described in more detail with reference to FIG. In FIG. 5, two thin film transistors in the pixel 100 are formed. The first thin film transistor 40 is a structure including a substrate 110, a gate electrode 41, a gate insulating film 130 </ b> A, a semiconductor layer 44, a source wiring 22, a source electrode 42 formed under the source wiring 22, and a drain electrode 43. On the other hand, the second thin film transistor 50 is a structure including the substrate 110, the gate electrode 51, the gate insulating film 130 </ b> B, the semiconductor layer 54, the source electrode 53, and the drain electrode 52 formed under the power supply wiring 23. Between these two transistors, a gate insulating film 130A of the first thin film transistor 40 is extended to electrically isolate the gate electrodes 41 and 51 of the two transistors. That is, the first thin film transistor 40 and the second thin film transistor 50 are separated by the gate insulating film 130 </ b> A of the first thin film transistor 40.
　また、第１薄膜トランジスタ４０のドレイン電極４３と第２薄膜トランジスタ５０のゲート電極５１とはコンタクトホール１６０により第２薄膜トランジスタ５０のゲート絶縁膜１３０Ｂを貫通し、電気的に接続されている。そのため、第１薄膜トランジスタ４０の電圧を、第２薄膜トランジスタ５０のゲート電極５１に印加できる。その結果、第２薄膜トランジスタ５０のゲート電極５１に印加された電圧に対応する電流が、第２薄膜トランジスタ５０のドレイン電極５２から第２薄膜トランジスタ５０のソース電極５３に流れる。 In addition, the drain electrode 43 of the first thin film transistor 40 and the gate electrode 51 of the second thin film transistor 50 pass through the gate insulating film 130B of the second thin film transistor 50 through the contact hole 160 and are electrically connected. Therefore, the voltage of the first thin film transistor 40 can be applied to the gate electrode 51 of the second thin film transistor 50. As a result, a current corresponding to the voltage applied to the gate electrode 51 of the second thin film transistor 50 flows from the drain electrode 52 of the second thin film transistor 50 to the source electrode 53 of the second thin film transistor 50.
　第１薄膜トランジスタの半導体層４４は、ゲート絶縁膜１３０Ａ上でソース電極４２とドレイン電極４３との間で、且つゲート電極４１にゲート絶縁膜１３０Ａを介して相対する位置に配置される。同様に、第２薄膜トランジスタの半導体層５４は、ゲート絶縁膜１３０Ｂとソース電極５３とドレイン電極５２との間で、且つゲート電極５１にゲート絶縁膜１３０Ｂを介して相対する位置に配置される。 The semiconductor layer 44 of the first thin film transistor is disposed between the source electrode 42 and the drain electrode 43 on the gate insulating film 130A and at a position facing the gate electrode 41 via the gate insulating film 130A. Similarly, the semiconductor layer 54 of the second thin film transistor is disposed between the gate insulating film 130B, the source electrode 53, and the drain electrode 52, and at a position facing the gate electrode 51 with the gate insulating film 130B interposed therebetween.
　なお、第１薄膜トランジスタ４０において、図５の左側のトランジスタ電極をソース電極４２、図５の右側のトランジスタ電極をドレイン電極４３として説明したが、図５の左側のトランジスタ電極をドレイン電極、図５の右側のトランジスタ電極をソース電極としてもよい。同様に、第２薄膜トランジスタ５０において、図５の左側のトランジスタ電極をソース電極５３、図５の右側のトランジスタ電極をドレイン電極５２として説明したが、図５の左側のトランジスタ電極をドレイン電極、図５の右側のトランジスタ電極をソース電極としてもよい。そのため、第１薄膜トランジスタ４０において、図５の左側のトランジスタ電極を第１トランジスタ電極、図５の右側のトランジスタ電極を第２トランジスタ電極と称し、また、第２薄膜トランジスタ５０において、図５の左側のトランジスタ電極を第３トランジスタ電極、図５の右側のトランジスタ電極を第４トランジスタ電極と称することにする。 In the first thin film transistor 40, the left transistor electrode in FIG. 5 is described as the source electrode 42, and the right transistor electrode in FIG. 5 is the drain electrode 43. However, the left transistor electrode in FIG. The right transistor electrode may be the source electrode. Similarly, in the second thin film transistor 50, the left side transistor electrode in FIG. 5 is described as the source electrode 53, and the right side transistor electrode in FIG. 5 is the drain electrode 52, but the left side transistor electrode in FIG. The right side transistor electrode may be used as the source electrode. Therefore, in the first thin film transistor 40, the left transistor electrode in FIG. 5 is referred to as a first transistor electrode, the right transistor electrode in FIG. 5 is referred to as a second transistor electrode, and the left thin film transistor in FIG. The electrode is referred to as a third transistor electrode, and the transistor electrode on the right side of FIG. 5 is referred to as a fourth transistor electrode.
　次に、図６を用いて２つの薄膜トランジスタ４０、５０の各電極、ソース配線２２及び電源配線２３の配置について説明する。 Next, the arrangement of the electrodes of the two thin film transistors 40 and 50, the source wiring 22 and the power supply wiring 23 will be described with reference to FIG.
　薄膜トランジスタ４０のソース電極４２の上にソース配線２２が形成されている。薄膜トランジスタ４０のソース電極４２は薄膜で形成され、ソース配線２２はそのソース電極４２よりも厚膜である。一方、薄膜トランジスタ５０のドレイン電極５２の上に電源配線２３が形成されている。薄膜トランジスタ５０のドレイン電極５２は薄膜で形成され、電源配線２３はそのドレイン電極５２よりも厚膜である。 The source wiring 22 is formed on the source electrode 42 of the thin film transistor 40. The source electrode 42 of the thin film transistor 40 is formed of a thin film, and the source wiring 22 is thicker than the source electrode 42. On the other hand, the power supply wiring 23 is formed on the drain electrode 52 of the thin film transistor 50. The drain electrode 52 of the thin film transistor 50 is formed of a thin film, and the power supply wiring 23 is thicker than the drain electrode 52.
　ここで、本実施の形態では、ソース配線２２及び電源配線２３は、各々、ゲート絶縁膜１３０Ａ上に形成された第１薄膜トランジスタ４０及びゲート絶縁膜１３０Ｂ上に形成された第２薄膜トランジスタ５０の外側に設けられている。ソース配線２２の膜厚は、ソース配線２２が接続されている第１薄膜トランジスタ４０のソース電極４２の膜厚よりも厚い構成である。同様に、電源配線２３の膜厚は、電源配線２３が接続されている第２薄膜トランジスタ５０のドレイン電極５２の膜厚よりも厚い構成である。 Here, in the present embodiment, the source wiring 22 and the power supply wiring 23 are outside the first thin film transistor 40 formed on the gate insulating film 130A and the second thin film transistor 50 formed on the gate insulating film 130B, respectively. Is provided. The film thickness of the source wiring 22 is thicker than the film thickness of the source electrode 42 of the first thin film transistor 40 to which the source wiring 22 is connected. Similarly, the thickness of the power supply wiring 23 is larger than the thickness of the drain electrode 52 of the second thin film transistor 50 to which the power supply wiring 23 is connected.
　このように、第１薄膜トランジスタ４０のソース電極４２と電気的に接続されているソース配線２２は、ソース電極４２の膜厚より厚い配線である。同様に、第２薄膜トランジスタ５０のドレイン電極５２と電気的に接続されている電源配線２３は、ドレイン電極５２の膜厚より厚い配線である。配線の電気抵抗は配線の断面積に反比例する関係であるので、配線の膜厚が厚くなることで、その配線の断面積電も大きくなって、電気抵抗が小さくなる。その結果、大画面化に対応して、表示装置用薄膜半導体装置２０を大きくしても、それら配線と電気的に接続している薄膜トランジスタの電極に少ない遅延で電圧を印加できる。 Thus, the source wiring 22 electrically connected to the source electrode 42 of the first thin film transistor 40 is a wiring thicker than the film thickness of the source electrode 42. Similarly, the power supply wiring 23 electrically connected to the drain electrode 52 of the second thin film transistor 50 is a wiring that is thicker than the drain electrode 52. Since the electrical resistance of the wiring is inversely proportional to the cross-sectional area of the wiring, increasing the film thickness of the wiring also increases the cross-sectional current of the wiring and decreases the electrical resistance. As a result, even if the thin film semiconductor device 20 for a display device is enlarged in response to an increase in screen size, a voltage can be applied to the electrodes of the thin film transistors electrically connected to these wirings with a small delay.
　また同時に、画素形成領域の下方において、第１薄膜トランジスタ４０のソース電極４２及び第２薄膜トランジスタ５０のドレイン電極５２自体の膜厚を極力薄くすることができる。そのため、ソース配線２２及び電源配線２３は、各々、第１薄膜トランジスタ４０及び第２薄膜トランジスタ５０の端に設けられているので、ソース配線２２と電源配線２３との間の領域では、第１薄膜トランジスタ４０及び第２薄膜トランジスタ５０による表面の起伏を小さくすることができる。これにより、薄膜トランジスタ４０、５０による表面の起伏に起因する課題を解決できる。即ち、画素形成領域の下方に該当する薄膜トランジスタ４０、５０の表面の起伏を低減できる。そのことにより、本実施の形態の表示装置用薄膜半導体装置２０の上に表示部１９を設けても、表示部に与える薄膜トランジスタ４０、５０の表面の起伏の影響を低減できる。 At the same time, the film thickness of the source electrode 42 of the first thin film transistor 40 and the drain electrode 52 itself of the second thin film transistor 50 can be made as thin as possible below the pixel formation region. Therefore, since the source wiring 22 and the power supply wiring 23 are provided at the ends of the first thin film transistor 40 and the second thin film transistor 50, respectively, in the region between the source wiring 22 and the power supply wiring 23, the first thin film transistor 40 and Unevenness of the surface due to the second thin film transistor 50 can be reduced. Thereby, the problem resulting from the undulation of the surface by the thin film transistors 40 and 50 can be solved. That is, the undulations on the surfaces of the thin film transistors 40 and 50 corresponding to the lower side of the pixel formation region can be reduced. As a result, even if the display unit 19 is provided on the thin film semiconductor device 20 for a display device of the present embodiment, the influence of the undulations on the surfaces of the thin film transistors 40 and 50 on the display unit can be reduced.
　さらには、平坦化膜１１を薄くすることができるため、平坦化膜１１中に含まれる水分、酸素などを減らすことができる。その結果、水分、酸素などによる表示部１９における有機発光層の劣化を抑えることができる。 Furthermore, since the planarizing film 11 can be thinned, moisture, oxygen, etc. contained in the planarizing film 11 can be reduced. As a result, it is possible to suppress deterioration of the organic light emitting layer in the display unit 19 due to moisture, oxygen, and the like.
　したがって、本態様によると、前記配線が厚いため、薄膜半導体装置としての配線の電気抵抗を低減しつつ、薄膜トランジスタ形成領域の表面の起伏を小さくした薄膜半導体装置を実現できる。 Therefore, according to this aspect, since the wiring is thick, it is possible to realize a thin film semiconductor device in which the surface of the thin film transistor formation region is reduced while reducing the electrical resistance of the wiring as the thin film semiconductor device.
　本実施の形態によると、上記半導体層４４、５４の一部をソース配線２２及び電源配線２３の下方に配置した構造である。このため、例えば、有機ＥＬ表示装置に採用した場合、画素サイズの小型化、すなわち、有機ＥＬ表示装置の超高精細度化、画素の発光面積の増加、歩留り向上が実現できる好適な構成である。 According to the present embodiment, a part of the semiconductor layers 44 and 54 is arranged below the source wiring 22 and the power supply wiring 23. For this reason, for example, when employed in an organic EL display device, the pixel size can be reduced, that is, the organic EL display device can be realized with ultra high definition, an increase in the light emission area of the pixel, and an improvement in yield. .
　また、有機ＥＬ表示装置の画像表示で発生した熱を、前記配線を介して速やかに基板の面内方向に散逸させることができるので、熱影響を低減できる。 Further, since heat generated in the image display of the organic EL display device can be quickly dissipated through the wiring in the in-plane direction of the substrate, the thermal influence can be reduced.
　また、各配線の電気抵抗は、各配線と電気的に接続されたそれぞれの上記の電極の電気抵抗より小さくてもよい。そのため、本態様の薄膜半導体装置を、例えば、有機ＥＬ表示装置に用いた場合に、表示装置としての配線の電気抵抗による電圧低下などの課題を解決できるものであり、その効果は該表示装置が大画面化するほど顕著である。 Also, the electrical resistance of each wiring may be smaller than the electrical resistance of each of the above-mentioned electrodes electrically connected to each wiring. Therefore, when the thin film semiconductor device of this embodiment is used in, for example, an organic EL display device, it is possible to solve problems such as a voltage drop due to electric resistance of wiring as a display device. The larger the screen, the more prominent.
　また、配線と電極を電気的に接続するための絶縁層にコンタクトホールを設ける必要が無く、プロセス上の負担も小さい。 Also, it is not necessary to provide a contact hole in the insulating layer for electrically connecting the wiring and the electrode, and the burden on the process is small.
　なお、本発明は、前記配線間に形成されるトランジスタは２個よりも多い態様にも対応できる。具体的には、薄膜トランジスタの数を３個あるいは４個とし、複数の薄膜トランジスタ個々の特性バラツキを補償する、所謂、内部補償型回路を実現する場合にも好適なものである。 In addition, this invention can respond also to the aspect with more than two transistors formed between the said wiring. Specifically, the present invention is also suitable for realizing a so-called internal compensation circuit in which the number of thin film transistors is three or four and the characteristic variation of each of the plurality of thin film transistors is compensated.
　なお、上記半導体層４４、５４の一部をソース配線２２及び電源配線２３の下方に配置しない構造も可能である。すなわち、第１薄膜トランジスタ４０のソース電極４２をソース配線２２から延設し、第２薄膜トランジスタ５０のドレイン電極５２を電源配線２３から延設した構造である。 A structure in which part of the semiconductor layers 44 and 54 is not disposed below the source wiring 22 and the power supply wiring 23 is also possible. In other words, the source electrode 42 of the first thin film transistor 40 extends from the source wiring 22, and the drain electrode 52 of the second thin film transistor 50 extends from the power supply wiring 23.
　続いて、本実施の形態に係る表示装置用薄膜半導体装置２０をトップエミッション型の有機ＥＬディスプレイに用いた有機ＥＬディスプレイ１０の構造について図７を用いて説明する。 Subsequently, the structure of the organic EL display 10 using the thin film semiconductor device 20 for a display device according to the present embodiment for a top emission type organic EL display will be described with reference to FIG.
　図７に示すように、有機ＥＬディスプレイ１０は、表示装置用薄膜半導体装置２０の上に、パッシベーション膜１５、平坦化膜１１、陽極１２、有機ＥＬ層１３及び透明陰極１４を順に積層した表示部１９を形成した構造である。 As shown in FIG. 7, the organic EL display 10 includes a display unit in which a passivation film 15, a planarization film 11, an anode 12, an organic EL layer 13, and a transparent cathode 14 are sequentially stacked on a thin film semiconductor device 20 for a display device. 19 is formed.
　パッシベーション膜１５は、表示装置用薄膜半導体装置２０のソース配線２２、電源配線２３及び２つの薄膜トランジスタ４０、５０の各電極の表面を外的な損傷から保護し、電気的絶縁状態を確保するために形成される。 The passivation film 15 protects the surfaces of the source wiring 22, the power supply wiring 23, and the two thin film transistors 40 and 50 of the thin film semiconductor device 20 for display devices from external damage, and ensures an electrical insulation state. It is formed.
　パッシベーション膜１５の上に形成される平坦化膜１１は、薄膜トランジスタ形成領域の表面の起伏による影響を表示部１９に反映させないために成膜される。ただし、この平坦化膜１１は、表示部１９の有機ＥＬ層の劣化の原因である水分と酸素を多く含む場合がある。そのため、この平坦化膜１１はできるだけ薄膜であるほうがよい。 The planarizing film 11 formed on the passivation film 15 is formed so as not to reflect the influence of the undulation on the surface of the thin film transistor formation region on the display unit 19. However, the planarizing film 11 may contain a large amount of moisture and oxygen that cause deterioration of the organic EL layer of the display unit 19. For this reason, the planarizing film 11 should be as thin as possible.
　本実施の形態の有機ＥＬディスプレイ１０では第１薄膜トランジスタ４０の第２トランジスタ電極としてのドレイン電極４３及び第２薄膜トランジスタ５０の第３トランジスタ電極としてのソース電極５３を薄膜化することで、表示部１９の有機ＥＬ層１３の下方に該当する領域の薄膜トランジスタ４０、５０の平坦性を確保している。換言すれば、本実施の形態では、図７に示すように、表示装置用薄膜半導体装置２０の厚膜であるソース配線２２と電源配線２３との間（図７中のＢの範囲）に薄膜である第１薄膜トランジスタ４０の第２トランジスタ電極としてのドレイン電極４３及び第２薄膜トランジスタ５０の第３トランジスタ電極としてのソース電極５３を配置している。そのため、表示装置用薄膜半導体装置２０の厚膜であるソース配線２２と電源配線２３との間に挟まれた領域は平坦になる。これにより、２つの薄膜トランジスタのソース配線２２と電源配線２３との間の表面形状を平坦にできる。このように、表示部１９の有機ＥＬ層１３が積層される領域（図７中Ａの範囲）は平坦性が確保されるため、有機ＥＬ層１３の膜厚ムラを低減でき、結果として、輝度ムラを抑えることができる。 In the organic EL display 10 according to the present embodiment, the drain electrode 43 as the second transistor electrode of the first thin film transistor 40 and the source electrode 53 as the third transistor electrode of the second thin film transistor 50 are thinned, thereby The flatness of the thin film transistors 40 and 50 in the region corresponding to the lower side of the organic EL layer 13 is ensured. In other words, in the present embodiment, as shown in FIG. 7, a thin film is formed between the source wiring 22 and the power supply wiring 23 (range B in FIG. 7), which is a thick film of the thin film semiconductor device 20 for display devices. A drain electrode 43 as a second transistor electrode of the first thin film transistor 40 and a source electrode 53 as a third transistor electrode of the second thin film transistor 50 are disposed. Therefore, a region sandwiched between the source wiring 22 and the power supply wiring 23 which is a thick film of the thin film semiconductor device 20 for a display device becomes flat. As a result, the surface shape between the source wiring 22 and the power supply wiring 23 of the two thin film transistors can be flattened. Thus, since the flatness is ensured in the region where the organic EL layer 13 of the display unit 19 is laminated (range A in FIG. 7), the film thickness unevenness of the organic EL layer 13 can be reduced, resulting in luminance. Unevenness can be suppressed.
　一方、有機ＥＬ層１３の下方に該当しない第１薄膜トランジスタ４０の第１トランジスタ電極としてのソース電極４２及び第２薄膜トランジスタ５０の第４トランジスタ電極としてドレイン電極５２の上方では、ソース配線２２及び電源配線２３を配線による電気抵抗の小さくするため、ソース配線２２及び電源配線２３の膜厚をドレイン電極４３及びソース電極５３の膜厚より厚く形成されている。しかし、有機ＥＬ層１３の下方に該当しない領域であるため、表示部１９へのソース配線２２及び電源配線２３の起伏の影響は生じない。これにより、平坦化膜１１を薄膜にすることができるので、平坦膜１５０に含まれている水分又は酸素を低減でき、上記有機ＥＬ層の水分又は酸素による変質又は劣化を防ぐことができる。 On the other hand, above the source electrode 42 as the first transistor electrode of the first thin film transistor 40 and the drain electrode 52 as the fourth transistor electrode of the second thin film transistor 50 that do not fall below the organic EL layer 13, the source line 22 and the power line 23. In order to reduce the electrical resistance due to the wiring, the source wiring 22 and the power supply wiring 23 are formed thicker than the drain electrode 43 and the source electrode 53. However, since the region does not fall under the organic EL layer 13, the influence of the undulations of the source wiring 22 and the power supply wiring 23 on the display unit 19 does not occur. Thereby, since the planarization film 11 can be made into a thin film, moisture or oxygen contained in the planar film 150 can be reduced, and alteration or deterioration of the organic EL layer due to moisture or oxygen can be prevented.
　平坦化膜１１には表示装置用薄膜半導体装置２０の第２薄膜トランジスタ５０のソース電極５３から延設されている画素用電極と陽極１２を電気的に接続するために、コンタクトホール（図示されない）が形成されている。これにより、表示装置用薄膜半導体装置２０で制御された電流が陽極１２に流れる。 The planarization film 11 has a contact hole (not shown) for electrically connecting the pixel electrode and the anode 12 extending from the source electrode 53 of the second thin film transistor 50 of the thin film semiconductor device 20 for display device. Is formed. As a result, a current controlled by the thin film semiconductor device 20 for display device flows through the anode 12.
　陽極１２は、上記平坦化膜１１の上に積層される。陽極１２は、有機ＥＬ層１３と電気的に接続されており、有機ＥＬ層１３に電流を流す、つまり、正孔を注入する。 The anode 12 is laminated on the planarizing film 11. The anode 12 is electrically connected to the organic EL layer 13, and a current is passed through the organic EL layer 13, that is, holes are injected.
　陽極１２は、例えば、光反射率が高い材料により構成される反射電極であってもよい。後述の有機ＥＬ層１３で発光した光が陽極１２に向けて進んできた場合に、光が陽極１２の表面で反射することで、光の行路が表示部１９の上方向に変わる。それにより、有機ＥＬ層１３の外部光取り出し効率が上がることに好適な構造となる。 The anode 12 may be, for example, a reflective electrode made of a material having a high light reflectance. When light emitted from an organic EL layer 13 (described later) travels toward the anode 12, the light is reflected by the surface of the anode 12, so that the light path changes upward in the display unit 19. Thereby, a structure suitable for increasing the external light extraction efficiency of the organic EL layer 13 is obtained.
　有機ＥＬ層１３は、上記陽極１２の上に積層される。有機ＥＬ層１３は、発光のための有機分子からなり、陽極１２から正孔が、後述の透明陰極１４から電子がそれぞれ注入される。そのことにより、有機ＥＬ層１３内で正孔と電子が再結合する。その際に、有機分子が励起状態になり、その有機分子が励起状態から基底状態に戻るときに光を発する。 The organic EL layer 13 is laminated on the anode 12. The organic EL layer 13 is made of organic molecules for light emission, and holes are injected from the anode 12 and electrons are injected from the transparent cathode 14 described later. As a result, holes and electrons are recombined in the organic EL layer 13. At that time, the organic molecule enters an excited state, and emits light when the organic molecule returns from the excited state to the ground state.
　透明陰極１４が、有機ＥＬ層１３の上に積層される。透明陰極１４は、有機ＥＬ層１３に電子を注入する。上述の発光の現象により、有機ＥＬ層１３で発せられた光は、透明陰極１４を透過して、表示部１９の上側より外部に光を放射する。 A transparent cathode 14 is laminated on the organic EL layer 13. The transparent cathode 14 injects electrons into the organic EL layer 13. Due to the phenomenon of light emission described above, the light emitted from the organic EL layer 13 passes through the transparent cathode 14 and radiates light from the upper side of the display unit 19 to the outside.
　このように、本実施の形態の表示装置用薄膜半導体装置２０を表示装置の駆動回路として採用することで、例えば、表示装置用薄膜半導体装置の配線の電気抵抗に起因する表示装置の輝度ムラを防止できる。特には、大画面表示装置に用いた場合での効果は絶大である。 As described above, by adopting the thin film semiconductor device 20 for a display device according to the present embodiment as a drive circuit for the display device, for example, the luminance unevenness of the display device due to the electrical resistance of the wiring of the thin film semiconductor device for display device is reduced. Can be prevented. In particular, the effect when used in a large screen display device is tremendous.
　なお、本実施の形態の表示装置に用いられている上述の表示装置用薄膜半導体装置２０において、ソース配線２２、電源配線２３、第１薄膜トランジスタ４０のドレイン電極４３及び第２薄膜トランジスタ５０のソース電極５３の各上面は、パッシベーション膜１５により被覆される。このパッシベーション膜１５によって被覆されるソース配線２２及び電源配線２３を隔壁（図７中のＣ）とする。この隔壁間に、陽極１２、有機ＥＬ層１３及び透明陰極１４を積層している。このように、本実施の形態の表示装置の構成は、パッシベーション膜１５によって被覆されたソース配線２２及び電源配線２３に、隔壁の機能を持たせてもよい。この場合、本態様の表示装置では、隔壁を別構成として形成しなくてもよく、構成と製造プロセスの簡略化が図れる。 Note that in the above-described thin film semiconductor device 20 for a display device used in the display device of the present embodiment, the source wiring 22, the power supply wiring 23, the drain electrode 43 of the first thin film transistor 40, and the source electrode 53 of the second thin film transistor 50. Each upper surface is covered with a passivation film 15. The source wiring 22 and the power supply wiring 23 covered with the passivation film 15 are defined as partition walls (C in FIG. 7). Between this partition, the anode 12, the organic EL layer 13, and the transparent cathode 14 are laminated | stacked. As described above, in the structure of the display device of this embodiment, the source wiring 22 and the power supply wiring 23 covered with the passivation film 15 may have a partition function. In this case, in the display device of this aspect, the partition need not be formed as a separate configuration, and the configuration and the manufacturing process can be simplified.
（表示装置用薄膜半導体装置の製造方法）
　図８Ａ～図８Ｅ及び図９Ａ～図９Ｅを用いて、実施の形態に係る表示装置用薄膜半導体装置２０の製造方法について説明する。図８Ａ～図８Ｅは、実施の形態に係る表示装置用薄膜半導体装置２０の製造方法を、図４におけるＡ－Ａ’断面、即ち、第１薄膜トランジスタ４０及び第２薄膜トランジスタ５０の形成領域の断面において各工程ごとに説明した工程図である。図９Ａ～図９Ｅは、図８Ｄに示す工程と図８Ｅに示す工程との間の工程を詳細に示した工程図である。図９Ａ～図９Ｅにおいては、実施の形態に係る表示装置用薄膜半導体装置２０の製造方法において、第１薄膜トランジスタ４０及び第２薄膜トランジスタ５０断面においてハーフトーンマスクによるフォトリソグラフィ工程を示している。 (Method for manufacturing thin film semiconductor device for display device)
A method for manufacturing the thin film semiconductor device 20 for a display device according to the embodiment will be described with reference to FIGS. 8A to 8E and FIGS. 9A to 9E. 8A to 8E show a manufacturing method of the thin film semiconductor device 20 for a display device according to the embodiment in the AA ′ cross section in FIG. 4, that is, in the cross section of the formation region of the first thin film transistor 40 and the second thin film transistor 50. It is process drawing demonstrated for every process. 9A to 9E are process diagrams showing in detail a process between the process shown in FIG. 8D and the process shown in FIG. 8E. 9A to 9E show a photolithography process using a halftone mask in the cross section of the first thin film transistor 40 and the second thin film transistor 50 in the method for manufacturing the thin film semiconductor device 20 for a display device according to the embodiment.
　まず、基板１１０を準備する。基板１１０には、一般的に、ガラス、石英等、絶縁性の材料を使用する。基板１１０からの不純物の拡散を防止するために、図示しない酸化珪素膜もしくは窒化珪素膜を基板１１０の上面に形成しても良く、その膜厚は１００ｎｍ程度である。 First, the substrate 110 is prepared. The substrate 110 is generally made of an insulating material such as glass or quartz. In order to prevent diffusion of impurities from the substrate 110, a silicon oxide film or a silicon nitride film (not shown) may be formed on the upper surface of the substrate 110, and the film thickness is about 100 nm.
　次に、図８Ａに示すように、第１薄膜トランジスタ４０及び第２薄膜トランジスタ５０のゲート電極４１、５１のために、金属を、例えば、スパッタリング法により成膜する。その後、例えば、フォトリソグラフィ法、エッチング法などによりパターニングを行い、第１薄膜トランジスタ４０及び第２薄膜トランジスタ５０のゲート電極４１、５１を形成する。本実施の形態では、ゲート電極の材料としてモリブデンを用い、その膜厚を１００ｎｍ程度とした。 Next, as shown in FIG. 8A, for the gate electrodes 41 and 51 of the first thin film transistor 40 and the second thin film transistor 50, a metal is formed by, for example, a sputtering method. Thereafter, patterning is performed by, for example, a photolithography method or an etching method to form the gate electrodes 41 and 51 of the first thin film transistor 40 and the second thin film transistor 50. In this embodiment mode, molybdenum is used as a material for the gate electrode, and the film thickness is set to about 100 nm.
　続いて図８Ｂに示すように、第１薄膜トランジスタ４０及び第２薄膜トランジスタ５０のゲート電極４１、５１の上面にゲート絶縁膜１３０及び半導体層１４０が、真空を破ることなく、例えば、プラズマＣＶＤ法等により連続的に積層される。本実施の形態では、ゲート絶縁膜１３０の材料としては、例えば、酸化珪素膜（ＳｉＯ２）、窒化珪素膜（ＳｉＮ）、もしくはその複合膜によって、ゲート絶縁膜１３０が形成され、その膜厚は２００ｎｍ程度である。また、半導体層１４０は、例えば、５０ｎｍ程度の非晶質シリコン膜である。 Subsequently, as shown in FIG. 8B, the gate insulating film 130 and the semiconductor layer 140 are formed on the upper surfaces of the gate electrodes 41 and 51 of the first thin film transistor 40 and the second thin film transistor 50 without breaking the vacuum, for example, by a plasma CVD method or the like. It is laminated continuously. In this embodiment, as the material of the gate insulating film 130, for example, the gate insulating film 130 is formed of a silicon oxide film (SiO 2 ), a silicon nitride film (SiN), or a composite film thereof, and the film thickness is It is about 200 nm. The semiconductor layer 140 is an amorphous silicon film with a thickness of about 50 nm, for example.
　この後、上述の非晶質シリコン膜に対して、例えば、エキシマレーザ等により、レーザーアニールの工程を行うことで半導体層１４０の非晶質シリコン膜が多結晶シリコン膜に改質させてもよい。半導体層１４０の非晶質シリコンの結晶化は、例えば、４００℃～５００℃の炉内で脱水素を行ったのち、エキシマレーザによって非晶質シリコンを結晶化させ、その後、真空雰囲気下で数秒～数１０秒の水素プラズマ処理が用いられる。これら工程により、半導体層１４０の非晶質シリコン膜を多結晶シリコン膜に改質してもよい。 Thereafter, the amorphous silicon film of the semiconductor layer 140 may be modified to a polycrystalline silicon film by performing a laser annealing process on the above-described amorphous silicon film by, for example, excimer laser or the like. . Crystallization of amorphous silicon in the semiconductor layer 140 is performed, for example, by dehydrogenating in a furnace at 400 ° C. to 500 ° C., then crystallizing amorphous silicon with an excimer laser, and then for several seconds in a vacuum atmosphere. Hydrogen plasma treatment for tens of seconds is used. Through these steps, the amorphous silicon film of the semiconductor layer 140 may be modified into a polycrystalline silicon film.
　次に、図８Ｃに示すように、２つのトランジスタの領域では、半導体層１４０を、例えば、フォトリソグラフィ法、エッチング法等によりに第１薄膜トランジスタ４０の半導体層４４及び第２薄膜トランジスタ５０の半導体層５４として島状に加工される。その後に、第２薄膜トランジスタ５０のゲート絶縁膜１３０Ｂにコンタクトホール１６０を例えば、ドライエッチング法により形成する。なお、後に形成される第１薄膜トランジスタ４０のドレイン電極４３と、第２薄膜トランジスタ５０のゲート電極５１とを電気的に接続するためにコンタクトホール１６０は形成される。したがって、そのためであれば、形状及び数は限定されない。 Next, as shown in FIG. 8C, in the region of the two transistors, the semiconductor layer 140 is divided into the semiconductor layer 44 of the first thin film transistor 40 and the semiconductor layer 54 of the second thin film transistor 50 by, for example, photolithography or etching. As an island. Thereafter, a contact hole 160 is formed in the gate insulating film 130B of the second thin film transistor 50 by, for example, a dry etching method. Note that a contact hole 160 is formed in order to electrically connect the drain electrode 43 of the first thin film transistor 40 and the gate electrode 51 of the second thin film transistor 50 to be formed later. Therefore, if it is for that, a shape and number will not be limited.
　続いて図８Ｄに示すように、第１薄膜トランジスタ４０及び第２薄膜トランジスタ５０の各ソース・ドレイン電極のための金属層２４及び各ソース・ドレイン電極への配線、即ち、ソース配線２２及び電源配線２３のための金属層２５が連続的に成膜される。なお、本実施の形態では金属層２４には各ソース・ドレイン電極としてＭｏ、また金属層２５には各ソース・ドレイン電極への配線として厚膜にすることのできるＣｕを用いている。また、各ソース・ドレイン電極の膜厚は１００ｎｍ、配線の膜厚は２μｍの厚さである。 Subsequently, as shown in FIG. 8D, the metal layer 24 for each source / drain electrode of the first thin film transistor 40 and the second thin film transistor 50 and the wiring to each source / drain electrode, that is, the source wiring 22 and the power wiring 23 A metal layer 25 is continuously formed. In the present embodiment, Mo is used for each source / drain electrode for the metal layer 24, and Cu that can be made thick as a wiring to each source / drain electrode is used for the metal layer 25. The thickness of each source / drain electrode is 100 nm, and the thickness of the wiring is 2 μm.
　続いて図８Ｅに示すように、例えば、フォトリソグラフィ法、エッチング法により、第１薄膜トランジスタ４０及び第２薄膜トランジスタ５０の各ソース・ドレイン電極のパターニングを行う。 Subsequently, as shown in FIG. 8E, the source / drain electrodes of the first thin film transistor 40 and the second thin film transistor 50 are patterned by, for example, photolithography and etching.
　このように、２つの薄膜トランジスタ４０、５０の各ソース・ドレイン電極は、極力薄膜にして、その第１薄膜トランジスタ４０のソース電極４２及び第２薄膜トランジスタ５０のドレイン電極５２への配線、即ち、本実施の形態では各ソース・ドレイン電極上に形成しているソース配線２２及び電源配線２３を厚膜にする。そのことにより、画素領域下部に当たる薄膜トランジスタ４０、５０全体の起伏を低減できる。そのことにより、本実施の形態の表示装置用薄膜半導体装置２０の上に表示部１９を設けても、表示部に与える起伏の影響を低減できる。 In this manner, the source / drain electrodes of the two thin film transistors 40 and 50 are made as thin as possible, and wiring to the source electrode 42 of the first thin film transistor 40 and the drain electrode 52 of the second thin film transistor 50, that is, the present embodiment. In the embodiment, the source wiring 22 and the power supply wiring 23 formed on each source / drain electrode are made thick. As a result, the undulations of the entire thin film transistors 40 and 50 hitting the lower part of the pixel region can be reduced. As a result, even if the display unit 19 is provided on the thin film semiconductor device 20 for a display device according to the present embodiment, the influence of undulations on the display unit can be reduced.
　また、平坦化膜１１を薄くすることができるため、平坦化膜１１中に含まれる水分、酸素などを減らすことができる。その結果、平坦化膜１１から生じる水分、酸素などによる表示部１９における有機発光層の劣化を抑えることができる。 Further, since the planarizing film 11 can be thinned, moisture, oxygen, etc. contained in the planarizing film 11 can be reduced. As a result, it is possible to suppress deterioration of the organic light emitting layer in the display unit 19 due to moisture, oxygen, and the like generated from the planarizing film 11.
　また、配線の電気抵抗は配線の断面積に反比例する関係であるので、配線の膜厚が厚くなることで、その配線の断面積電も大きくなり、電気抵抗が小さくなる。その結果、表示大画面化に対応して、表示装置用薄膜半導体装置２０を大きくしても、それら配線と電気的に接続している薄膜トランジスタの電極に遅延無く電圧を印加できる。 Also, since the electrical resistance of the wiring is inversely proportional to the cross-sectional area of the wiring, increasing the film thickness of the wiring also increases the cross-sectional area of the wiring and reduces the electrical resistance. As a result, even if the thin film semiconductor device 20 for a display device is enlarged in response to an increase in the display screen, a voltage can be applied without delay to the electrodes of the thin film transistor electrically connected to these wirings.
　従って、本態様によると、表面の起伏が小さく、かつ、前記配線が厚いため、薄膜半導体装置としての配線の電気抵抗を低減した薄膜半導体装置を実現できるものである。 Therefore, according to this aspect, since the undulation on the surface is small and the wiring is thick, a thin film semiconductor device with reduced electrical resistance of the wiring as a thin film semiconductor device can be realized.
　また、第１薄膜トランジスタ４０のソース電極４２及びドレイン電極４３と半導体層４４との間には、一般的に、図示しない低抵抗半導体層が形成される。この低抵抗半導体層は、例えば、リン等のｎ型ドーパントがドーピングされた非晶質シリコン層、もしくはボロン等のｐ型ドーパントがドーピングされた非晶質シリコン層が使用される。例えば、膜厚としては２０ｎｍ程度である。結晶化された半導体層４４とドーピングされた非晶質シリコン層との間にさらに非晶質シリコン等の半導体層があってもよい。これらの膜はデバイス特性を向上させるために必要になる場合がある。 In addition, a low resistance semiconductor layer (not shown) is generally formed between the source electrode 42 and drain electrode 43 of the first thin film transistor 40 and the semiconductor layer 44. As this low resistance semiconductor layer, for example, an amorphous silicon layer doped with an n-type dopant such as phosphorus or an amorphous silicon layer doped with a p-type dopant such as boron is used. For example, the film thickness is about 20 nm. There may be a semiconductor layer such as amorphous silicon between the crystallized semiconductor layer 44 and the doped amorphous silicon layer. These films may be required to improve device characteristics.
　また、別体からなるソース・ドレイン電極とその上に形成される各配線の形成を別々のプロセスで行ってもよいが、例えば、ハーフトーンマスクを用いたフォトリソグラフィ法を採用することでフォトリソグラフィ工程の工数を削減することができる。このハーフトーンマスクを用いたフォトリソグラフィ法については図９Ａ～図９Ｅで詳述する。この工程により、第１薄膜トランジスタ４０のソース電極４２、第１薄膜トランジスタ４０のドレイン電極４３、第２薄膜トランジスタ５０のドレイン電極５２、第２薄膜トランジスタ５０のソース電極５３が形成される。また、第１薄膜トランジスタ４０のソース電極４２の上のソース配線２２、第２薄膜トランジスタ５０のドレイン電極５２の上に、電源配線２３も形成される。そして、第１薄膜トランジスタ４０のドレイン電極４３と第２薄膜トランジスタ５０のゲート電極５１とがコンタクトホール１６０を介して接続される。 In addition, the source / drain electrodes formed separately and the wirings formed thereon may be formed by separate processes. For example, photolithography is performed by adopting a photolithography method using a halftone mask. The number of process steps can be reduced. A photolithography method using this halftone mask will be described in detail with reference to FIGS. 9A to 9E. By this step, the source electrode 42 of the first thin film transistor 40, the drain electrode 43 of the first thin film transistor 40, the drain electrode 52 of the second thin film transistor 50, and the source electrode 53 of the second thin film transistor 50 are formed. Further, the power supply wiring 23 is also formed on the source wiring 22 on the source electrode 42 of the first thin film transistor 40 and the drain electrode 52 of the second thin film transistor 50. Then, the drain electrode 43 of the first thin film transistor 40 and the gate electrode 51 of the second thin film transistor 50 are connected through the contact hole 160.
　続いて、図９Ａ～図９Ｅを用いて、２つの薄膜トランジスタ４０、５０の各ソース・ドレイン電極及びその各ソース・ドレイン電極上に設けられた配線を、ハーフトーンマスクを用いたフォトリソグラフィ法で形成した工程について詳述する。この工程は図８Ｄと図８Ｅの間に行われる工程である。なお、本実施の形態ではポジ型のフォトレジスト材を用いて説明する。ただし、ネガ型のフォトレジスト材でも露光する領域と露光しない領域を反転することでポジ型と同様のプロセスが可能である。 9A to 9E, the source / drain electrodes of the two thin film transistors 40 and 50 and the wirings provided on the source / drain electrodes are formed by photolithography using a halftone mask. The steps performed will be described in detail. This step is performed between FIG. 8D and FIG. 8E. Note that this embodiment mode is described using a positive photoresist material. However, a negative photoresist material can be processed in the same manner as the positive type by reversing the exposed area and the unexposed area.
　まず、図９Ａに示すように、図８Ｄに図示されている薄膜トランジスタの各電極になる薄膜の金属層２４及びその各電極への配線になる厚膜の金属層２５の上に、エッチング工程の際のレジストマスクになるフォトレジスト膜１７を全面に塗布する。例えば、その膜厚は１μｍ以上である。フォトレジスト膜１７を乾燥させた後、ハーフトーンマスク１６を用いて、フォトレジスト膜１７の一部を露光する。このハーフトーンマスク１６は、光を透過する領域（透過領域）１８ａ、光をある割合で透過する領域（半透過領域）１８ｂ、そして光を遮光する領域（遮光領域）１８ｃからなる。つまり、露光用光源とフォトレジスト膜１７との間に配置することで、フォトレジスト膜１７上に、完全に露光する領域、ある割合で露光する領域、露光しない領域ができる。 First, as shown in FIG. 9A, an etching process is performed on a thin metal layer 24 to be each electrode of the thin film transistor shown in FIG. 8D and a thick metal layer 25 to be a wiring to each electrode. A photoresist film 17 to be a resist mask is applied on the entire surface. For example, the film thickness is 1 μm or more. After drying the photoresist film 17, a part of the photoresist film 17 is exposed using the halftone mask 16. The halftone mask 16 includes an area (transmission area) 18a that transmits light, an area (transmission area) 18b that transmits light at a certain ratio, and an area (light-shielding area) 18c that blocks light. That is, by disposing the light source for exposure and the photoresist film 17, a completely exposed area, an area exposed at a certain ratio, and an unexposed area can be formed on the photoresist film 17.
　次に、図９Ｂに示すように、フォトレジスト膜１７の露光後に、現像及び除去工程を行うことで、ある割合で露光されたフォトレジスト膜１７は、完全には感光していないため減膜し、ある割合の膜厚のフォトレジスト膜１７ｂになる。一方、露光されなかった領域は、そのままの膜厚でフォトレジスト膜１７ａになる。また、完全に露光されたフォトレジスト膜１７は、現像及び除去工程を行うことで、完全に除去され、下地の配線になる厚膜の金属層２５（図９Ｂ中のＡの領域）が露出する。 Next, as shown in FIG. 9B, development and removal processes are performed after the exposure of the photoresist film 17, so that the photoresist film 17 exposed at a certain ratio is not completely exposed to light so that the film thickness is reduced. The photoresist film 17b has a certain thickness. On the other hand, the unexposed area becomes the photoresist film 17a with the same film thickness. Further, the completely exposed photoresist film 17 is completely removed by developing and removing processes, and a thick metal layer 25 (region A in FIG. 9B) to be the underlying wiring is exposed. .
　次に、図９Ｃに示すように、フォトレジスト膜１７ａ、１７ｂが無く下地の配線になる厚膜の金属層２５が露出している領域では、例えば、ウェットエッチング工程により、その金属層２５がエッチングされ、削られる（図９Ｃ中のＡの領域）。フォトレジスト膜１７ａ、１７ｂがある領域では、下地の金属層２５がエッチングされることなく、フォトレジスト膜１７ａ、１７ｂはレジストマスクの役割を果たしている。そして、各層の最終膜厚を達成できるように、エッチング剤とエッチングされる材料（本実施の形態では金属層２４、２５）とによって決まるエッチングレートを考慮し、ウェットエッチング工程を終える。 Next, as shown in FIG. 9C, in the region where the thick metal layer 25 which is the underlying wiring without the photoresist films 17a and 17b is exposed, the metal layer 25 is etched by, for example, a wet etching process. And is shaved (region A in FIG. 9C). In the region where the photoresist films 17a and 17b are present, the underlying metal layer 25 is not etched, and the photoresist films 17a and 17b serve as a resist mask. Then, in order to achieve the final film thickness of each layer, the wet etching process is finished in consideration of the etching rate determined by the etching agent and the material to be etched (in this embodiment, the metal layers 24 and 25).
　次に、図９Ｄに示すように、フォトレジスト膜１７ａ、１７ｂの全体にアッシング処理を行い、ある割合の膜厚のフォトレジスト膜１７ｂを除去し、フォトレジスト膜１７ａを減膜する。つまり、ある割合の膜厚のフォトレジスト膜１７ｂを除去することで、新たに下地の配線になる厚膜の金属層２５が露出する（図９ＤのＢの領域）。また、フォトレジスト膜１７ａは減膜し、フォトレジスト膜１７ａ’として残る。 Next, as shown in FIG. 9D, ashing is performed on the entire photoresist films 17a and 17b, the photoresist film 17b having a certain thickness is removed, and the photoresist film 17a is reduced. In other words, by removing the photoresist film 17b having a certain thickness, the thick metal layer 25 to be a new underlying wiring is exposed (region B in FIG. 9D). Further, the photoresist film 17a is reduced and remains as a photoresist film 17a '.
　最後に、図９Ｅに示すように、再度、例えば、ウェットエッチング工程などにより、フォトレジスト膜１７ａ’の領域以外の露出した下地の配線になる厚膜の金属層２５及びその下に形成されている電極になる薄膜の金属層２４がエッチングされる。そして、各層が所望の膜厚になるところで、エッチング工程を止める。最後にフォトレジスト膜１７ａ’を除去する（図示していない。）。 Finally, as shown in FIG. 9E, a thick metal layer 25 that will be exposed under the wiring other than the region of the photoresist film 17a ′ and the underlying metal layer 25 are formed again by, for example, a wet etching process. The thin metal layer 24 that becomes the electrode is etched. Then, the etching process is stopped when each layer has a desired film thickness. Finally, the photoresist film 17a 'is removed (not shown).
　このようにして、連続して形成されている２層の金属層２４、２５を１つのフォトマスクによりパターニング及びエッチング工程で図８Ｅに示す所望の形状に形成できる。ハーフトーンマスクを用いることで、フォトマスク枚数が減り、薄膜半導体装置の製造コストを削減できる。更には、工数を削減できることで、生産ライン構築のコストも削減でき、全体で大幅なコスト削減を達成できる。 In this way, the two metal layers 24 and 25 formed in succession can be formed into a desired shape shown in FIG. 8E by a patterning and etching process using one photomask. By using a halftone mask, the number of photomasks can be reduced, and the manufacturing cost of the thin film semiconductor device can be reduced. Furthermore, since the number of man-hours can be reduced, the cost for constructing the production line can be reduced, and a significant cost reduction can be achieved overall.
　本実施の形態では、トランジスタの各電極とソース配線２２及び電源配線２３を別体で形成できるため、これら配線は任意の膜厚であって、トランジスタの各電極の膜厚よりも厚く形成することが容易に実施できる。 In this embodiment mode, each electrode of the transistor can be formed separately from the source wiring 22 and the power supply wiring 23. Therefore, these wirings have any film thickness and are formed thicker than the film thickness of each electrode of the transistor. Can be easily implemented.
　本発明の一態様に係る表示装置用薄膜半導体装置の製造方法においては、前記配線層を形成する工程は、例えば、スパッタ法、メッキ法あるいは印刷法により実施されてもよい。 In the method for manufacturing a thin film semiconductor device for a display device according to an aspect of the present invention, the step of forming the wiring layer may be performed by, for example, a sputtering method, a plating method, or a printing method.
　本態様によると、前記配線は、例えば、スパッタ法、メッキ法あるいは印刷法で形成される。スパッタ法の中でも、特にＤＣマグネトロンスパッタ方は、金属膜を高速に、かつ、大面積で容易に形成でき、また、形成された膜の平滑性、膜厚均一性も優れており、好適な形成方法である。 According to this aspect, the wiring is formed by, for example, a sputtering method, a plating method, or a printing method. Among the sputtering methods, particularly the DC magnetron sputtering method can easily form a metal film at a high speed and in a large area, and the formed film is excellent in smoothness and film thickness uniformity, and is suitable for formation. Is the method.
　また、メッキ法及び印刷法は、該配線層を簡便な製造方法であり、短時間に容易に厚く形成でき、量産性に優れた製造方法を実現する上で好適な態様である。 Further, the plating method and the printing method are simple manufacturing methods, and are suitable for realizing a manufacturing method that can be easily formed thick in a short time and has excellent mass productivity.
　以上の工程の後に、実施の形態に係るトップエミッション型の有機ＥＬディスプレイ１０を製造する。即ち、上記の表示装置用薄膜半導体装置２０上にパッシベーション膜１５、平坦化膜１１、陽極１２、有機ＥＬ層１３及び透明陰極１４を順次積層され、図６に示すようなトップエミッション型の有機ＥＬディスプレイ１０が製造される。 After the above steps, the top emission type organic EL display 10 according to the embodiment is manufactured. That is, the passivation film 15, the planarizing film 11, the anode 12, the organic EL layer 13 and the transparent cathode 14 are sequentially laminated on the thin film semiconductor device 20 for a display device, and a top emission type organic EL as shown in FIG. The display 10 is manufactured.
　具体的には、表示装置用薄膜半導体装置２０上にパッシベーション膜１５を形成し、その上に平坦化膜１１を積層する。 Specifically, the passivation film 15 is formed on the thin film semiconductor device 20 for display device, and the planarizing film 11 is laminated thereon.
　次に、陽極１２は、平坦化膜１１上に積層される。陽極１２の材料は、例えば、モリブデン、アルミニウム、金、銀、銅などの導電性金属若しくはそれらの合金、ＰＥＤＯＴ：ＰＳＳなどの有機導電性材料、酸化亜鉛、又は、鉛添加酸化インジウムのいずれかの材料である。これらの材料からなる膜を真空蒸着法、電子ビーム蒸着法、ＲＦスパッタ法、又は、印刷法などにより作製し、電極パターンを形成する。 Next, the anode 12 is laminated on the planarizing film 11. The material of the anode 12 is, for example, a conductive metal such as molybdenum, aluminum, gold, silver, or copper, or an alloy thereof, an organic conductive material such as PEDOT: PSS, zinc oxide, or lead-doped indium oxide. Material. A film made of these materials is formed by a vacuum evaporation method, an electron beam evaporation method, an RF sputtering method, a printing method, or the like to form an electrode pattern.
　次に、有機ＥＬ層１３は、陽極１２上に、正孔注入層、正孔輸送層、発光層、電子輸送層及び電子注入層などの各層が積層されて構成される。例えば、正孔注入層として銅フタロシアニンを、正孔輸送層として例えばα－ＮＰＤ（Ｂｉｓ［Ｎ－（１－Ｎａｐｈｔｈｙｌ）－Ｎ－Ｐｈｅｎｙｌ］ｂｅｎｚｉｄｉｎｅ）を、発光層として例えばＡｌｑ３（ｔｒｉｓ（８－ｈｙｄｒｏｘｙｑｕｉｎｏｌｉｎｅ）ａｌｕｍｉｎｕｍ）を、電子輸送層としてオキサゾール誘導体を、電子注入層としてＡｌｑ３を用いることができる。 Next, the organic EL layer 13 is configured by laminating layers such as a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer on the anode 12. For example, copper phthalocyanine is used as the hole injection layer, α-NPD (Bis [N- (1-Naphthyl) -N-phenyl] benzidine) is used as the hole transport layer, and Alq 3 (tris (8- hydroquinoline) aluminum), an oxazole derivative as the electron transport layer, and Alq 3 as the electron injection layer.
　最後に、透明陰極１４は、有機ＥＬ層１３上に形成される透過性を有する電極である。透明陰極１４の材料は、例えば、ＩＴＯ（Ｉｎｄｉｕｍ　Ｔｉｎ　Ｏｘｉｄｅ）、ＳｎＯ２、Ｉｎ２Ｏ３、ＺｎＯ又はこれらの組み合わせなどである。 Finally, the transparent cathode 14 is a transparent electrode formed on the organic EL layer 13. The material of the transparent cathode 14 is, for example, ITO (Indium Tin Oxide), SnO 2 , In 2 O 3 , ZnO, or a combination thereof.
　なお、上記各層の構成で列挙したこれらの材料は、あくまで一例であって同機能を有する他の材料を用いてもよい。 Note that these materials listed in the configuration of each layer are merely examples, and other materials having the same function may be used.
　本実施の形態では、表示装置用薄膜半導体装置２０の作製においてハーフトーンプロセスを採用することでプロセス上の負担を減らし、低抵抗が要求される配線は厚膜の低抵抗材料で形成する。また、平坦性が要求される表示部１９の有機ＥＬ層１３の下方においては、薄膜トランジスタの各電極を薄膜で形成する。これにより配線を厚膜化することで低抵抗にしつつ、一方で表示部１９の画素内の平坦性を確保することができる。 In the present embodiment, a halftone process is adopted in the production of the thin film semiconductor device 20 for a display device, thereby reducing the burden on the process, and wiring requiring low resistance is formed of a thick low resistance material. Further, below the organic EL layer 13 of the display unit 19 where flatness is required, each electrode of the thin film transistor is formed as a thin film. As a result, it is possible to secure the flatness in the pixel of the display unit 19 while reducing the resistance by increasing the thickness of the wiring.
　本実施の形態では、一般的に画素を区切る役割をはたす隔壁を形成することなく、パッシベーション膜１５に被覆されたソース配線２２及び電源配線２３からなる配線層で隔壁の役割を果たしている。これにより隔壁を形成する必要が無くなり、表示装置作成のプロセスを簡略化することが可能となる。 In the present embodiment, the partition layer serving as the partition line is composed of the source wiring 22 and the power supply wiring 23 covered with the passivation film 15 without forming the partition wall that generally serves to separate the pixels. As a result, it is not necessary to form partition walls, and the process for creating a display device can be simplified.
　以上のように、本実施の形態は有機ＥＬディスプレイのトップエミッション型を構成する実施の形態であるが、本発明の適用範囲はこの限りではない。つまり、基板が透明であるボトムエミッション型の有機ＥＬディスプレイにも採用可能である。更には、薄膜トランジスタを用いた薄膜半導体装置を使うもの（例えば、液晶ディスプレイ、無機ＥＬディスプレイ等）であれば適用可能である。 As described above, the present embodiment is an embodiment that constitutes a top emission type of an organic EL display, but the scope of application of the present invention is not limited to this. That is, it can also be used for a bottom emission type organic EL display whose substrate is transparent. Furthermore, any device using a thin film semiconductor device using a thin film transistor (for example, a liquid crystal display, an inorganic EL display, etc.) is applicable.
　以上のように、本発明を実施することで配線と薄膜トランジスタの電極の抵抗を小さく、かつ、薄膜半導体装置の平坦性を維持することができ、結果として信号遅延や電圧降下による表示ムラを抑えることができる平坦な薄膜半導体装置を提供することができる。 As described above, by implementing the present invention, the resistance of the wiring and the electrode of the thin film transistor can be reduced, and the flatness of the thin film semiconductor device can be maintained. As a result, display unevenness due to signal delay and voltage drop can be suppressed. It is possible to provide a flat thin film semiconductor device capable of achieving the above.
　１　パネル基板
　１０　有機ＥＬディスプレイ
　１１　平坦化膜
　１２　陽極
　１３　有機ＥＬ層
　１４　透明陰極
　１５　パッシベーション膜
　１６　ハーフトーンマスク
　１７、１７ａ、１７ａ’、１７ｂ　フォトレジスト膜
　１８ａ　透過領域
　１８ｂ　半透過領域
　１８ｃ　遮光領域
　１９　表示部
　２０　表示装置用薄膜半導体装置
　２１　ゲート配線
　２２　ソース配線
　２３　電源配線
　２４、２５　金属層
　３０　画素回路
　４０　第１薄膜トランジスタ
　４１　第１薄膜トランジスタのゲート電極
　４２　第１薄膜トランジスタの第１トランジスタ電極（ソース電極）
　４３　第１薄膜トランジスタの第２トランジスタ電極（ドレイン電極）
　４４　第１薄膜トランジスタの半導体層
　５０　第２薄膜トランジスタ
　５１　第２薄膜トランジスタのゲート電極
　５２　第２薄膜トランジスタの第４トランジスタ電極（ドレイン電極）
　５３　第２薄膜トランジスタの第３トランジスタ電極（ソース電極）
　５４　第２薄膜トランジスタの半導体層
　６０　キャパシタ
　１００　画素
　１１０　基板
　１３０　絶縁層（ゲート絶縁膜）
　１３０Ａ　第１薄膜トランジスタのゲート絶縁膜
　１３０Ｂ　第２薄膜トランジスタのゲート絶縁膜
　１４０　半導体層
　１６０　コンタクトホール DESCRIPTION OF SYMBOLS 1 Panel substrate 10 Organic EL display 11 Flattening film 12 Anode 13 Organic EL layer 14 Transparent cathode 15 Passivation film 16 Halftone mask 17, 17a, 17a ', 17b Photoresist film 18a Transmission area 18b Transflective area 18c Light-shielding area 19 Display Section 20 Thin Film Semiconductor Device for Display Device 21 Gate Wiring 22 Source Wiring 23 Power Supply Wiring 24, 25 Metal Layer 30 Pixel Circuit 40 First Thin Film Transistor 41 First Thin Film Transistor Gate Electrode 42 First Transistor Electrode (Source Electrode) of First Thin Film Transistor
43 Second transistor electrode (drain electrode) of first thin film transistor
44 Semiconductor layer of the first thin film transistor 50 Second thin film transistor 51 Gate electrode of the second thin film transistor 52 Fourth transistor electrode (drain electrode) of the second thin film transistor
53 Third transistor electrode (source electrode) of second thin film transistor
54 Semiconductor layer of second thin film transistor 60 Capacitor 100 Pixel 110 Substrate 130 Insulating layer (gate insulating film)
130A Gate insulating film of the first thin film transistor 130B Gate insulating film of the second thin film transistor 140 Semiconductor layer 160 Contact hole

Claims (13)

  1. 　ゲート電極と、
    　前記ゲート電極上に形成されたゲート絶縁膜と、
    　前記ゲート絶縁膜上に形成された半導体層と、
    　前記半導体層上に形成された第１トランジスタ電極と、
    　前記半導体層上に形成された第２トランジスタ電極と、
    　前記第１トランジスタ電極又は前記第２トランジスタ電極の少なくともいずれか一方の電極上に形成され、前記一方の電極と電気的に接続され、前記一方の電極と別体であって前記一方の電極の膜厚より厚い配線と、
    　を具備した薄膜半導体装置。     A gate electrode;
    A gate insulating film formed on the gate electrode;
    A semiconductor layer formed on the gate insulating film;
    A first transistor electrode formed on the semiconductor layer;
    A second transistor electrode formed on the semiconductor layer;
    Formed on at least one of the first transistor electrode and the second transistor electrode, electrically connected to the one electrode, and separate from the one electrode, the film of the one electrode Wiring thicker than thickness,
    A thin film semiconductor device comprising:
  2. 　前記第１トランジスタ電極はソース電極であり、
    　前記第２トランジスタ電極はドレイン電極であり、
    　前記配線は、前記ソース電極と電気的に接続されたソース配線である、
    　請求項１に記載の薄膜半導体装置。     The first transistor electrode is a source electrode;
    The second transistor electrode is a drain electrode;
    The wiring is a source wiring electrically connected to the source electrode.
    The thin film semiconductor device according to claim 1.
  3. 　前記第１トランジスタ電極はソース電極であり、
    　前記第２トランジスタ電極はドレイン電極であり、
    　前記配線は、前記ドレイン電極と電気的に接続された電源配線である、
    　請求項１に記載の薄膜半導体装置。     The first transistor electrode is a source electrode;
    The second transistor electrode is a drain electrode;
    The wiring is a power supply wiring electrically connected to the drain electrode.
    The thin film semiconductor device according to claim 1.
  4. 　前記配線は、前記配線と電気的に接続された前記第１トランジスタ電極又は前記第２トランジスタ電極の少なくともいずれか一方の電極の上であって、前記半導体層の上方と少なくとも一部が重なる領域に形成されている、
    　請求項１ないし請求項３の何れか１項に記載の薄膜半導体装置。     The wiring is on at least one of the first transistor electrode and the second transistor electrode electrically connected to the wiring, and in a region at least partially overlapping above the semiconductor layer. Formed,
    The thin film semiconductor device according to any one of claims 1 to 3.
  5. 　前記配線と電気的に接続された前記第１トランジスタ電極又は前記第２トランジスタ電極の少なくともいずれか一方の電極は、前記半導体層の領域外に延設され、
    　前記配線は、前記配線と電気的に接続された前記第１トランジスタ電極又は前記第２トランジスタ電極の少なくともいずれか一方の電極の前記延設された領域上に形成されている
    　請求項１ないし請求項３の何れか１項に記載の薄膜半導体装置。     At least one of the first transistor electrode and the second transistor electrode electrically connected to the wiring extends outside the region of the semiconductor layer,
    The wiring is formed on the extended region of at least one of the first transistor electrode and the second transistor electrode electrically connected to the wiring. 4. The thin film semiconductor device according to any one of 3 above.
  6. 　前記配線の電気抵抗は、前記配線と電気的に接続された前記第１トランジスタ電極又は前記第２トランジスタ電極の少なくともいずれか一方の電極の電気抵抗より小さいこと、
    　を特徴とする請求項１ないし請求項５の何れか１項に記載の薄膜半導体装置。      An electrical resistance of the wiring is smaller than an electrical resistance of at least one of the first transistor electrode and the second transistor electrode electrically connected to the wiring;
    The thin film semiconductor device according to claim 1, wherein:
  7. 　ゲート配線と、
    　前記ゲート配線から延設された第１ゲート電極と、
    　前記第１ゲート電極上に形成された第１ゲート絶縁膜と、
    　前記第１ゲート絶縁膜上に形成された第１半導体層と、
    　前記第１半導体層上に形成された第１トランジスタ電極と、
    　前記第１半導体層上に形成された第２トランジスタ電極と、
    　前記第２トランジスタ電極と電気接続された第２ゲート電極と、
    　前記第２ゲート電極上に形成された第２ゲート絶縁膜と、
    　前記第２ゲート絶縁膜上に形成された第２半導体層と、
    　前記第２半導体層上に形成された第３トランジスタ電極と、
    　前記第２半導体層上に形成された第４トランジスタ電極と、
    　前記ゲート配線と交差し、前記第１トランジスタ電極上に形成され、前記第１トランジスタと別体であって前記第１トランジスタ電極の膜厚より厚い第１配線と、
    　前記ゲート配線と交差し、前記第４トランジスタ電極上に形成され、前記第４トランジスタと別体であって前記第４トランジスタ電極の膜厚より厚い第２配線と、
    　を具備し、
    　前記第２トランジスタ電極又は前記第３トランジスタ電極の少なくとも何れか一方は、前記第１トランジスタ電極及び前記第４トランジスタ電極の間に配置さてれている
    　薄膜半導体装置。     Gate wiring,
    A first gate electrode extending from the gate wiring;
    A first gate insulating film formed on the first gate electrode;
    A first semiconductor layer formed on the first gate insulating film;
    A first transistor electrode formed on the first semiconductor layer;
    A second transistor electrode formed on the first semiconductor layer;
    A second gate electrode electrically connected to the second transistor electrode;
    A second gate insulating film formed on the second gate electrode;
    A second semiconductor layer formed on the second gate insulating film;
    A third transistor electrode formed on the second semiconductor layer;
    A fourth transistor electrode formed on the second semiconductor layer;
    A first wiring that intersects with the gate wiring and is formed on the first transistor electrode, is separate from the first transistor and is thicker than a film thickness of the first transistor electrode;
    A second wiring that intersects with the gate wiring and is formed on the fourth transistor electrode, is separate from the fourth transistor and is thicker than the film thickness of the fourth transistor electrode;
    Comprising
    At least one of the second transistor electrode and the third transistor electrode is disposed between the first transistor electrode and the fourth transistor electrode. A thin film semiconductor device.
  8. 　前記第２トランジスタ電極及び前記第３トランジスタ電極は、前記第１トランジスタ電極及び前記第４トランジスタ電極の間に配置さてれている
    　請求項７に記載の薄膜半導体装置。     The thin film semiconductor device according to claim 7, wherein the second transistor electrode and the third transistor electrode are disposed between the first transistor electrode and the fourth transistor electrode.
  9. 　前記第１トランジスタ電極はスイッチングトランジスタのソース電極であり、
    　前記第２トランジスタ電極は前記スイッチングトランジスタのドレイン電極であり、
    　前記第３トランジスタ電極は駆動トランジスタのソース電極であり、
    　前記第４トランジスタ電極は前記駆動トランジスタのドレイン電極である、
    　ことを特徴とする請求項７又は請求項８のいずれかに記載の薄膜半導体装置。     The first transistor electrode is a source electrode of a switching transistor;
    The second transistor electrode is a drain electrode of the switching transistor;
    The third transistor electrode is a source electrode of a driving transistor;
    The fourth transistor electrode is a drain electrode of the driving transistor;
    The thin film semiconductor device according to claim 7, wherein the thin film semiconductor device is a thin film semiconductor device.
  10. 　請求項１ないし請求項９の何れか１項に記載の薄膜半導体装置上に表示デバイスが形成されている
    　表示装置。     A display device in which a display device is formed on the thin film semiconductor device according to claim 1.
  11. 　請求項７記載の薄膜半導体装置を備え、
    　前記第１配線、前記第２配線、前記第２トランジスタ電極及び前記第３トランジスタ電極の各上面は、絶縁膜により被覆され、
    　前記絶縁膜によって被覆された前記第１配線及び前記第２配線を隔壁として、この隔壁間に、陽極、陰極、前記陽極と陰極との間に介在する発光層が積層されている
    　表示装置。     A thin film semiconductor device according to claim 7,
    Each upper surface of the first wiring, the second wiring, the second transistor electrode, and the third transistor electrode is covered with an insulating film,
    A display device in which the first wiring and the second wiring covered with the insulating film are used as partition walls, and an anode, a cathode, and a light emitting layer interposed between the anode and cathode are stacked between the partition walls.
  12. 　基板上にゲート電極を形成する工程と、
    　前記ゲート電極上にゲート絶縁膜を形成する工程と、
    　前記ゲート絶縁膜上に半導体層を形成する工程と、
    　前記半導体層上に第１トランジスタ電極と第２トランジスタ電極とを形成する工程と、
    　前記第１トランジスタ電極又は第２トランジスタ電極の少なくともいずれか一方の電極と別体であって前記一方の電極よりも厚い配線を、前記一方の電極上に形成する工程と
    　を含む薄膜半導体装置の製造方法。     Forming a gate electrode on the substrate;
    Forming a gate insulating film on the gate electrode;
    Forming a semiconductor layer on the gate insulating film;
    Forming a first transistor electrode and a second transistor electrode on the semiconductor layer;
    Forming a wiring that is separate from at least one of the first transistor electrode and the second transistor electrode and is thicker than the one electrode on the one electrode. Method.
  13. 　前記配線を形成する工程はスパッタ法、メッキ法、あるいは印刷法により実施される
    　請求項１２に記載の薄膜半導体装置の製造方法。     The method of manufacturing a thin film semiconductor device according to claim 12, wherein the step of forming the wiring is performed by a sputtering method, a plating method, or a printing method.
PCT/JP2010/003463 2010-05-24 2010-05-24 Thin film semiconductor device, display device, and process for production of thin film semiconductor device WO2011148409A1 (en)

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