JP3731191B2 - Transposition processing method for matrix data - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to transposition processing of matrix data applied to a DCT (Discrete Cosine Transform) circuit or the like.MethodAbout.
[0002]
[Prior art]
For example, in an image compression coding technique such as MPEG (Moving Picture Experts Group), determinant calculations are frequently performed when DCT processing is performed on image data. When processing a determinant product, the data in the row direction and the data in the column direction are interchanged. In orthogonal transformation such as DCT processing, so-called transposition processing is performed in various types of arithmetic processing to replace row-direction data and column-direction data of matrix-format data. Conventionally, such processing uses, for example, two sets of RAM (random access memory), writes matrix data in one RAM, and when the writing is completed, the same matrix data in the other RAM. Write. Then, while data is being written in the other RAM, the address is controlled and read out from the one RAM in which the data has already been written so as to perform conversion in the row direction and the column direction. Thereby, data written in the row direction can be read in the column direction and transposed.
[0003]
[Problems to be solved by the invention]
However, the conventional matrix data transposition processing apparatus as described above has the following problems to be solved.
In order to read data written in the memory in the row direction in the column direction, a read address completely different from the write address must be generated and read control must be performed. Therefore, after the matrix data is written to the RAM, the data is read again by switching the address counter. To speed up this process, two sets of RAM are used alternately. Therefore, there is a problem that the circuit scale becomes large.
[0004]
Further, in the above conventional method, in order to write data in the row direction and read data in the column direction, it is necessary to wait until the writing of data to be read in the column direction is completed. Accordingly, since the start of reading is delayed, there is a problem that processing in the subsequent stage of the transposed RAM is also delayed.
[0005]
[Means for Solving the Problems]
  The present invention adopts the following configuration in order to solve the above points.
<Configuration 1>
  The present invention transposes matrix data for writing / reading n × m block data to / from a matrix of n rows × m columns (n, m: an integer of 2 or more) for a memory having each port for writing and reading. A processing method comprising: starting writing of the block data in the row direction with respect to the memory; starting reading in the column direction when data is written in the nth row and the first column; Starting writing the next block data in the direction, and starting reading in the row direction when the data is written in the m-th column first row;
Is a transposition processing method of matrix format data characterized in that
[0006]
<Explanation>
The data write port and the data read port of this memory are independent of each other, and the data write address and the data read address are supplied separately, and data can be read and written simultaneously. Matrix data is data including row elements and column elements, and the contents thereof are arbitrary.
When data is sequentially written in the row direction in the memory, if the data is read in the column direction, the row elements and the column elements of the matrix data can be transposed. Therefore, the control circuit notifies the optimum timing for starting the reading.
[0007]
  On the other hand, the next group of data may be overwritten on the data that has already been read out in the memory, but when data is written in the row direction when data is read in the column direction, New data is overwritten on data that has not been read. Therefore, after writing a group of data in the row direction, data is written in the column direction. When the data writing direction is changed alternately in this way, there is no collision between the write address and the read address when data writing and reading are performed continuously, and there is little wasteful waiting time and data transposition processing using a multi-port memory Can do.
  For example, when data is being written in the row direction, if reading is started after the first column of data to be read first is written, address collision does not occur even if the writing and reading speeds are the same.
[0008]
<Configuration 2>
  In configuration 1,2. The transposition processing method of matrix format data according to claim 1, wherein writing in the same direction is started continuously after the reading is started.
[0011]
<Explanation>
  DeData is read and written one by one, DeDataRead outAs soon as possibleNextDataWrite in the same directionIt doesn't matter.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described using specific examples.
<Concrete example>
FIG. 1 is a block diagram showing a specific example of the apparatus of the present invention.
In the present invention, a two-port memory 1 is used for temporarily storing and transposing data in a matrix format as shown in the figure. A DCT circuit 2 and a DCT circuit 3 are connected to the data input terminal DI and the data output terminal DO of the 2-port memory 1, respectively. Each of the DCT circuits 2 and 3 is a circuit that executes a predetermined calculation while performing row and column conversion processing of data in a matrix format. The write address WAO generated by the write address generator 5 is input to the write address input terminal WAI of the 2-port memory 1. The read address RAO generated by the read address generator 6 is input to the read address input terminal RAI.
[0013]
A control circuit 4 is provided for controlling operations of the write address generation unit 5 and the read address generation unit 6. First, a write permission signal WR that permits writing is input to the control circuit 4 from the host device when writing is started. This signal is input not only to the control circuit 4 but also to the write address generator 5. In addition, a reset signal RS is input to reset the read permission signal and the address input to the RAM before the transposition process is started. This signal is input to the control circuit 4, the write address generation unit 5, and the read address generation unit 6.
[0014]
The write address generation unit 5 is configured to output a read timing signal WV to the control circuit 4 when it reaches a readable address after completing the write to a predetermined address. Further, as will be described later, the control circuit 4 receives this read timing signal and outputs a read permission signal RR that permits the read address generation unit 6 to start reading. The read address generation unit 6 outputs a read end signal RV to the control circuit 4 when the series of data read in the matrix format is completed.
[0015]
FIG. 2 shows a specific connection diagram of the write address generation unit.
The write address generation unit 5 includes a counter 11 and a selector 12 as shown in the figure. The counter 11 is configured to receive a reset signal RS and a write permission signal WR. The counter 11 counts up for generating an address signal every time data is written by a clock signal (not shown). The counter 11 outputs a 7-bit signal while counting up for address generation. The selector 12 is configured to receive the output of the counter 11 and select and output one of two types of address signals. That is, the 6-bit count values x0 to x5 of the counter 11 are marked with symbols A0 to A5. Further, the count value obtained by exchanging the upper 3 bits and the lower 3 bits of x0 to x5 of the counter 11 is displayed as B0 to B5.
[0016]
Of the outputs x6, x5, x4, x3, x2, x1 and x0 of the counter 11, x6 is inputted to the selection signal input terminals SA and SB of the selector 12 as shown in the figure. X5, x4, x3, x2, x1, x0 of the counter 11 are connected to A5 and B2, A4 and B1, A3 and B0, A2 and B5, A1 and B4, A0 and B3, respectively. The output WAO of the selector 12 is a write address of the 2-port memory 1 shown in FIG. The selector 12 outputs A5, A4, A3, A2, A1, A0, that is, x5, x4, x3, x2, x1, x0 when X6 = 0 (SA = 1, SB = 0), When x6 = 0 (SA = 0, SB = 1), B5, B4, B3, B2, B1, B0, that is, x2, x1, x0, x5, x4, x3 are output.
Further, the outputs x5, x4, x3, x2, x1, x0 of the counter 11 are decoded by the AND circuit 15 to become a read timing signal WV.
[0017]
FIG. 3 shows a specific connection diagram of the read address generation unit 6.
The read address generation unit 6 is also composed of a counter 13 and a selector 14. Similarly, this circuit is also configured to select the output of the counter 13 and the output obtained by inverting the upper and lower bits by the selector 14 and use it as the read address RAO. That is, y6 of the outputs y6, y5, y4, y3, y2, y1, and y0 of the counter 13 is input to the selection signal input terminals SA and SB of the selector 14 as shown in the figure. Y5, y4, y3, y2, y1, y0 of the counter 13 are connected to A5 and B2, A4 and B1, A3 and B0, A2 and B5, A1 and B4, A0 and B3, respectively. The output RAO of the selector 14 is a read address of the 2-port memory 1. The selector 12 is configured to output A5, A4, A3, A2, A1, A0, that is, y5, y4, y3, y2, y1, y0 when y6 = 1 (SA = 1, SB = 0). Has been.
The outputs y5, y4, y3, y2, y1, and y0 of the counter 13 are decoded by the AND circuit 16 and used as a read end signal RV.
[0018]
The AND circuit 15 shown in FIG. 2 has x5 × 4 × 3 × 2 × 1 = (111000)₂ = (56)_Ten“1” is output only when the AND circuit 16 shown in FIG. 3 outputs y5y4y3y2y1y0 = (111111).₂ = (63)_Ten“1” is output only when. Thus, for example, when data is written in the row direction, the AND circuit 15 outputs the read timing signal WV at the timing at which reading in the column direction becomes possible, and performs output start control of read address control. The AND circuit 16 outputs a read end signal RV after all the reading is completed, and is used as a signal for ending the transposition processing.
[0019]
For example, when writing the data of 8 × 8 matrix format, the selector 12 outputs the addresses B0 to B5 from the state where the addresses A0 to A5 were output until then when the writing of 64 data is completed. Switch to state. In this case, since the upper 3 bits and the lower 3 bits are replaced, after the data is written in the row direction, when this is completed, an address signal is output so as to write the data in the column direction. On the other hand, the selector 14 performs the operation opposite to that of the selector 12. That is, when the writing in the row direction is initially performed, the reading address in the column direction is output, and then the data writing is performed in the column direction. For the reading, a reading address in the row direction is output. The selector 12 and the selector 14 are provided for performing such an operation.
[0020]
FIG. 4 shows a specific connection diagram of the control circuit 4.
This circuit includes an AND gate 21 that receives the write permission signal WR and the read timing signal WV, a NOT gate 22 that receives the read end signal RV, an AND gate 23 that controls the outputs of the AND gate 21 and the NOT gate 22, and an OR gate. 24, an AND gate 25, and a flip-flop 26. The AND gate 23 receives the output of the flip-flop 26 and the output of the NOT gate 22. Further, the outputs of the AND gate 21 and the AND gate 23 are input to the OR gate 24. Further, the output of the OR gate 24 and the output of the NOT gate 27 are input to the AND gate 25. A reset signal RS is input to the NOT gate 27.
By configuring this circuit as shown in the figure, a sequential circuit that outputs a read permission signal at a timing described later based on a signal stored in the flip-flop 26 is configured.
[0021]
The outline of the operation of the apparatus of the specific example 1 will be described with reference to FIG.
In this specific example, for example, 8 × 8 square matrix block data is written to the 2-port memory, the block data written in the row direction is read in the row direction, and the block data written in the column direction is read in the row direction. To perform the transposition process.
First, as shown in FIG. 5 (1-a), data writing of the first block is started in the row direction from A to B in an 8 × 8 matrix area.
As writing progresses, as shown in FIG. 5 (1-a), when data is written up to the position C, that is, the address 56, data in the first block can be read, as shown in FIG. 5 (1-b). First, reading is started in the column direction from A to C.
Thereafter, writing and reading are performed in parallel, writing to the position D is completed, and writing of data in the first block is completed. At this time, the reading of the first block is completed for one column from the position of A to C, and the reading is continued until the reading of the first block of data from the next column is completed.
[0022]
If writing of data in the second block is started, writing is started in the column direction in parallel with reading out of the first block, as shown in FIG. 5 (2-a). At this time, the reading of the data of the first block proceeds as shown in FIG. 5B. Therefore, the data of the first block that has not been read is not destroyed, and the write address and the read address Will not corrupt the data.
When the reading of the data of the first block is completed and the writing of the data of the second block is performed at the position B as shown in FIG. 5 (3-a), the data of the second block can be read. As shown in 5 (3-b), reading is started in the row direction from A to B.
Thereafter, writing and reading are performed in parallel, and writing of data in the second block is completed as shown in FIG. 5 (4-a). The reading of the second block is completed up to the position C as shown in FIG. 5 (4-b), and the reading is continued until the reading of the data of the second block from the next row.
In the third and subsequent blocks, reading and writing can be performed in parallel as described above.
[0023]
FIG. 6 shows a timing chart for explaining a more specific operation of the first specific example.
(A) in the figure is an operation cycle counted from the start of data writing to the 2-port memory 1, (b) is a write permission signal WR, (c) is a write address WAO, (d) is a read timing signal WV, ( e) indicates a read permission signal RR, (f) indicates a read address RAO, (g) indicates a read end signal RV, (h) indicates write data, and (i) indicates read data.
[0024]
First, in the circuit of FIG. 1, “1” is input to the reset signal RS, the counters 11 and 13 shown in FIG. 2 are reset to “0000000”, and the D-type flip-flop 26 of the control circuit 4 of FIG. 4 is reset to “0”. Then, the read permission signal RR is also set to “0”.
Next, after the data is processed by the first-dimensional DCT circuit 2 of the two-dimensional DCT circuit shown in FIG. 1, the write permission signal WR to the 2-port memory 1 becomes “1”, and the data input from the terminal DI is written. Is done. The counter 11 in FIG. 2 counts up one by one in synchronization with a clock (not shown) when the write permission signal WR = "1". In response to this, the write address generator 5 outputs the write address 0, 1, 2, 3,... To the 2-port memory 1, and the data input to the terminal DI is written to that address. Since the read timing signal WV and the read end signal RV continue to be “0” until 56 data, that is, data is written to the addresses 0 to 55 in the 2-port memory 1, the flip-flop shown in FIG. The output Q of 26 continues to output “0”, and the read permission signal RR of the 2-port memory 1 also continues to output “0”.
[0025]
When 56 pieces of data are written in the 2-port memory 1, the output of the counter 11 shown in FIG. 2 in cycle 57 is x5x4x3x2x1x0 = (111000)₂ = (56)_TenIt becomes. At this time, data is written up to addresses 0, 1, 2,..., 55 of the 2-port memory 1.
When the next data is output from the first-dimensional DCT circuit 2 and “1” is input to the write enable signal WR, data is written to the address “56” of the 2-port memory 1. At this time, since the read permission signal WR and the read timing signal WV are input to the control circuit 4 as “1”, “1” is set to the input D of the flip-flop 26 shown in FIG. When the value is accepted in synchronization with the clock in cycle 58, Q outputs “1”.
[0026]
The control circuit 4 once sets D to “1” and Q = “1”, the reset signal RS becomes “1”, or one of WR and WV is “0” and RV is “1”. Unless "1" is input, "1" is continuously output.
As long as the output Q of the flip-flop 26 is “1”, the read permission signal RR of the 2-port memory 1 is “1”, and the reading is continued. In the 2-port memory 1, when an address is input to the address input terminal RAI, data is read from the corresponding address and output from the terminal DO.
[0027]
The counter 13 shown in FIG. 3 counts up one by one in synchronization with the clock when the read permission signal RR = “1”. In response to this, read addresses 0, 8, 16,... Are output from the terminal RAO. Thus, data reading in the column direction is performed.
After 63 pieces of data are read from the 2-port memory 1, the input RV of the control circuit 4 becomes "1". Since RR is “1”, the 64th data is read from the address 63 in the next cycle. When WR and WV are not “1”, “0” is input to the D terminal of the flip-flop 26, and reading of the 2-port memory 1 is stopped from the next cycle. If WR and WV are “1”, “1” is input to the D terminal, and reading is continued.
[0028]
After the counter 11 counts up 64, x6 = "1", so that writing to the 2-port memory 1 is performed in the order of addresses 0, 8, 16,. This is writing in the column direction. After the counter 13 counts up 64 times, y6 = "1", so that reading from the 2-port memory 1 is performed in the order of addresses 0, 1, 2, 3,. This is readout in the row direction.
In the two-dimensional DCT circuit, eight data (one row or one column) out of 64 blocks (8 rows × 8 columns) are handled and processed, so the 57th data as in the above method. If it is detected that the first to fourth DCT circuits can output the 58th to 64th data, it is possible to start reading the data.
[0029]
<Effect of specific example 1>
As described above, if a two-port memory is used as a memory so that data can be read out simultaneously with data writing, the circuit scale can be reduced as compared with the conventional method in which two memories having the same configuration are provided. In addition, by controlling the write address and the read address as described above, the data read and write can be processed simultaneously in parallel, and when the matrix data is written and read more than twice. The time delay between them can be minimized. In the above example, an example in which data in an 8 × 8 matrix format is handled has been described. However, the present invention can also be applied to a matrix that is not necessarily a square matrix and has different data amounts in the row direction and the column direction. is there. In addition to the DCT circuit, various circuits can be used as the circuits positioned before and after the circuit for the transposition processing.
[0030]
<Specific example 2>
The configuration and operation of the specific example 2 will be described below with reference to FIG. The block showing the overall configuration of Example 2 is exactly the same as that shown in FIG. The write address generation unit 5 of the specific example 2 has the configuration shown in FIG. Further, the read address generation unit 6 has the configuration shown in FIG. The counter 11 and selector 12 of the write address generation unit shown in FIG. 7 and the connections and input / output signals between them are exactly the same as those of the first specific example. In this specific example 2, an AND gate group 18 for outputting a read timing signal is provided as follows. These AND gate groups are hereinafter denoted as 18-1 to 18-8, respectively.
[0031]
The outputs x5, x4, x3, x2, x1, x0 of the counter 11 are AND circuits 18-1, 18-2, 18-3, 18-4, 18-5, 18-6, 18- as shown in the figure. 7, 18-8.
The AND circuit 18-1 has x5x4x3x2x1x0 = (000000)₂ = (0)_Ten“1” is output only when.
The AND circuit 18-2 has x5x4x3x2x1x0 = (001000)₂ = (8)_Ten“1” is output only when.
The AND circuit 18-3 has x5x4x3x2x1x0 = (010000)₂ = (16)_Ten“1” is output only when.
The AND circuit 18-4 has x5x4x3x2x1x0 = (011000)₂ = (24)_Ten“1” is output only when.
The AND circuit 18-5 has x5x4x3x2x1x0 = (100,000).₂ = (32)_Ten“1” is output only when.
The AND circuit 18-6 is x5x4x3x2x1x0 = (101000)₂ = (40)_Ten“1” is output only when.
The AND circuit 18-7 has x5x4x3x2x1x0 = (110000)₂ = (48)_Ten“1” is output only when.
The AND circuit 18-8 has x5x4x3x2x1x0 = (111000)₂ = (56)_Ten“1” is output only when.
[0032]
The read address generator shown in FIG. 8 is also connected to the counter 13 and the selector 14 in the same manner as in the first specific example. There is no change in the input / output signals. Only the AND gate group 19 for outputting the read end signal is different from the first specific example. These AND gate groups are called 19-1 to 19-8, respectively.
The outputs y5, y4, y3, y2, y1, y0 of the counter 13 are AND circuits 19-1, 19-2, 19-3, 19-4, 19-5, 19-6, 19- as shown in the figure. 7, 19-8.
The AND circuit 19-1 has y5y4y3y2y1y0 = (000000)₂ = (0)_Ten“1” is output only when.
The AND circuit 19-2 has y5y4y3y2y1y0 = (000001).₂ = (1)_Ten“1” is output only when.
The AND circuit 19-3 has y5y4y3y2y1y0 = (000010).₂ = (2)_Ten“1” is output only when.
[0033]
The AND circuit 19-4 has y5y4y3y2y1y0 = (0000011).₂ = (3)_Ten“1” is output only when.
The AND circuit 19-5 has y5y4y3y2y1y0 = (000100)₂ = (4)_Ten“1” is output only when.
The AND circuit 19-6 has y5y4y3y2y1y0 = (000101).₂ = (5)_Ten“1” is output only when.
The AND circuit 19-7 has y5y4y3y2y1y0 = (000110)₂ = (6)_Ten“1” is output only when.
The AND circuit 19-8 has y5y4y3y2y1y0 = (111111)₂ = (63)_Ten“1” is output only when.
[0034]
FIG. 9 shows a connection diagram of the control circuit of the second specific example.
In this circuit, eight sequential circuits 20A to 20H are provided. The internal connection is exactly the same as the circuit shown in FIG. The sequential circuits 20A to 20H are configured to receive the read timing signals P1 to P8 and the write timing signals J1 to J8 from the write address generation unit and the read address generation unit illustrated in FIGS. 7 and 8, respectively. Has been. The Q outputs of all the sequential circuits 20A to 20H are output as read permission signals via the OR gate 28. In this way, the read permission signal is re-input to the sequential circuits 20A to 20H.
[0035]
The above circuit operates as follows.
FIG. 10 shows an operation timing chart of the second specific example.
(A) is an operation cycle, (b) is a write permission signal WR, (c) is a read permission signal RR, (d) is a write address WAO, (e) is a read address RAO, and (f) is a read timing signal. WV, (g) indicates a read end signal RV, (h) indicates write data, and (i) indicates read data.
[0036]
First, the reset signal RS is set to “1” and the counters 11 and 13 are set to “000000” in the circuit of FIG. The signal RR is set to “0”.
Next, data is processed in the first-dimensional circuit of the two-dimensional DCT circuit, the write permission signal becomes WR = “1”, and writing is performed to the address “0” of the 2-port memory. At this time, since the counters 11 and 13 are “0000000”, WV (P1) and RV (J1) are “1”. Since WR = “1” and XV (P1) = “1”, the input D = “1” of the D flip-flop of the sequential circuit 20A.
[0037]
In the next cycle (2), the counter 11 is incremented by 1 and writing to address 1 of the 2-port memory 1 is performed. Further, since the Q terminal of the sequential circuit 20A = “1” and the read permission signal RR = “1”, the address “0” is read. At this time, WV (P1) = “0” of the sequential circuit 20A, RR = 1, RV (J1) = 1, and D = “0”.
In the next cycle (3), the counter 11 counts up by “1” and writing is performed to the address “2” of the 2-port memory 1. The counter 13 counts up by “1” and RV (J1) = “0” and RV (J2) = “1”. Further, RR = “0”, and no reading is performed.
[0038]
Thereafter, when WR = “1” and the counter 11 counts up one by one in synchronization with the clock, and the write address of the 2-port memory 1 changes to “3”, “4”, “5”,.
In cycle (10), RR = “1” and the address “8” of the 2-port memory 1 is read.
In cycle (18), RR = “1” and the address “16” of the 2-port memory 1 is read.
In cycle (26), RR = “1” and the address “24” of the 2-port memory 1 is read.
[0039]
In cycle (34), RR = "1" and the address "32" of the 2-port memory 1 is read.
In cycle (42), RR = “1” and the address “40” of the 2-port memory 1 is read.
In cycle (50), RR = “1” and the address “48” of the 2-port memory 1 is read.
In cycle (58), RR = "1" and the address "56" of the 2-port memory 1 is read out.
In the cycle (58), Q = “1”, RR = “1”, RV (J8) = “0” of the sequential circuit 20H, and D = “1”. Reading is continued in the order of RAM addresses 1, 9,...
[0040]
When the 64th data is read in the cycle (114), RR = "1" and the output of the counter 13 y5y4y3y2y1y0 = (111111)₂ = (63)_TenTherefore, RV (J8) of the sequential circuit 20H = “1”, and reading of data of one block (64 pieces) is completed.
[0041]
At this time, if the data of the next block is written in the 2-port memory 1, the reading is continued from the next cycle. Thereafter, the new block data is transferred to the 2-port memory 1.
If one or more writing has been completed, Q of sequential circuit 20A is “1” until one is read.
If writing of nine or more has been completed, Q of sequential circuit 20B is “1” until two are read.
If writing of 17 or more has been completed, Q of sequential circuit 20C is “1” until three are read.
If writing of 25 or more has been completed, Q of sequential circuit 20D is “1” until four are read.
If writing of 33 or more has been completed, Q of sequential circuit 20E is “1” until 5 are read.
If writing of 41 or more has been completed, Q of sequential circuit 20F is “1” until 6 are read.
If writing of 49 or more has been completed, Q of sequential circuit 20G is “1” until 7 are read.
If writing of 57 or more has been completed, Q of sequential circuit 20H is “1” until 64 are read.
Therefore, RR = "1" and data is read out.
[0042]
<Effect of specific example 2>
As described above, in the second specific example, the writing in the row direction is performed earlier than the first specific example, and then the reading in the column direction is started. That is, since the data reading starts earlier than when data reading is performed for the first time after 56 data writing is completed, the time delay between data writing can be further reduced.
Other functions and effects are the same as in the first specific example.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a specific example of an apparatus according to the present invention.
FIG. 2 is a connection diagram of a write address generation unit.
FIG. 3 is a connection diagram of a read address generation unit.
FIG. 4 is a connection diagram of a control circuit.
FIG. 5 is a schematic operation explanatory diagram of a specific example 1;
6 is an operation timing chart of Example 1. FIG.
FIG. 7 is a connection diagram of a write address generation unit.
FIG. 8 is a connection diagram of a read address generation unit.
FIG. 9 is a control circuit connection diagram of a specific example 2;
10 is an operation timing chart of the specific example 2. FIG.
[Explanation of symbols]
1 2-port memory
2,3 DCT circuit
4 Control circuit
5 Write address generator
6 Read address generator

Claims (2)

This is a transposition processing method of matrix format data for writing and reading n × m block data to a matrix of n rows × m columns (n, m: an integer of 2 or more) for a memory having each port for writing and reading. And
Starting writing the block data in the row direction to the memory, and starting reading in the column direction when the data is written in the nth row and the first column;
Starting writing next block data in the column direction to the memory, and starting reading in the row direction when the data is written in the m-th column first row;
A transposition processing method for matrix format data, comprising:   2. The transposition processing method for matrix format data according to claim 1, wherein writing in the same direction is started continuously after the reading is started.

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