JPH0675799A - Memory access device and memory device - Google Patents

Abstract

PURPOSE:To provide the memory access device capable of reducing the address pin of a memory and executing the decoding processing of a read Solomon product code with a minimum circuitry. CONSTITUTION:Two pairs of independent address generation sections 5 and 6 and a data bus switch circuit 16 are provided. As the independent address and the inversion of the high-order and low-order bytes of the data bus can be controlled by the access in the column and row directions of the product code, both column and row directions can be processed by one external code decoding device 3, letting the circuit be the minimum scale.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access device and a memory device used for decoding processing of Reed-Solomon product code and correction processing of error pixels of a digital video tape recorder.

[0002]

2. Description of the Related Art With the recent development of magnetic recording and reproducing technology,
Video tape recorders are becoming digital. In these devices, errors in the electromagnetic conversion system are compensated, error correction codes such as Reed-Solomon product codes are used to reproduce high-quality images, and the pixels in the previous frame are replaced to compensate for error pixels that exceed the correction capability. Image modification processing that minimizes the effects of errors is adopted. In these processes, a virtual two-dimensional array matching the structure of the Reed-Solomon product code is assumed on the memory, and a memory access device for controlling access in the row direction and the column direction is required.

A conventional memory access device will be described below. FIG. 4 is a block diagram of this conventional memory access device. In FIG. 4, the inner code decoder 1
Reference numeral 01 inputs a data block which is a unit of data input / output, and its correction output is the upper data buses 102a, 102.
output to the upper memory 103 and the lower memory 104 via b, and the inner code error information is output to the upper outer code decoder 1
05 and the lower outer code decoder 106, respectively.
An upper outer code decoder 105 is an outer code error correction unit connected to the upper memory 103 via the upper data bus 102a, and a lower outer code decoder 106 is an outer code error correction unit connected to the lower memory 104 via the lower data bus 102b. The outer code error information is supplied to the modification processing unit 107. Modification processing unit 10
Numeral 7 designates a surface switching signal for the upper memory 103 and the lower memory 1
04 as a 1-bit common signal. The input address generation unit 108 of the inner code decoder 101, the outer code address generation unit 109 of the upper outer code decoder 105 and the lower outer code decoder 106, and the output address generation unit 110 of the data output to the outside, respectively. In this case, the address is calculated and supplied to the upper memory 103 and the lower memory 104 via the common address bus 111. The upper memory 103 and the lower memory 104 are random access memories each having an N-bit address bus and an 8-bit data bus,
The lower N-1 bits of the address bus are connected to the common address bus 111 as a common signal, the most significant bits of the address bus are connected to the modification processing unit 107 as a common surface switching signal, and the data bus of the upper memory 103 is an upper data bus 102a, the data bus of the lower memory 104 is connected to the lower data bus 102b.

The operation of the memory access device configured as described above will be described below. First, the inner code decoder 101 executes error correction processing of the input data block, and outputs the corrected data block to the upper memory 10
3. When the correction result is uncorrectable, the inner code error information is notified to the upper outer code decoder 105 and the lower outer code decoder 106. FIG. 4 is a code structure diagram showing the relationship between the inner code and the outer code. In FIG. 4, the inner code and the outer code are Reed-Solomon codes orthogonal to each other, and the inner code error information of the decoding result of the inner code is used as the erasure information of the outer code. FIG. 5 is a memory map showing the storage states of the codes shown in FIG. 4 in the upper memory 103 and the lower memory 104. Since the parity of the inner code is unnecessary after the outer code decoding process, it is not stored in the upper memory 103 and the lower memory 104. In FIG. 5, the inner code and the outer code are shown as virtual two-dimensional addresses defined by the row address and the column address, but the physical address direction coincides with the row direction. In FIG. 5, H indicates a data byte stored in the upper memory 103, and L indicates a data byte stored in the lower memory 104. Two adjacent bytes of data in the same row are stored at the same physical address. Has been done. Further, a two-dimensional array of one inner code and one outer code is provided with two storage areas, a first surface and a second surface, on the upper memory 103 and the lower memory 104. Which surface is to be accessed? Is controlled by the surface switching signal. The data block of the processing result of the inner code decoder 101 is stored in the upper memory 103 and the lower memory 104.
5, the input address generation unit 108 calculates a physical address from the row address and column address shown in FIG. 5, and the retouching processing unit 107 determines whether the first surface or the second surface is to be used. By generating the plane switching signal, the inner code decoder 101 stores the corrected data in units of 2 bytes in the row direction.

Next, the upper outer code decoder 105, the lower outer code decoder 106, and the outer code address generator 109 start the decoding process of the outer code. The outer code address generation unit 109 calculates a physical address from the row address and column address shown in FIG. 5, and the retouching processing unit 107 determines, for each row, which surface, the first surface or the second surface, is to be used. , By generating the surface switching signal, sequential access is started in the column direction of the virtual two-dimensional array. At this time, the upper byte and the lower byte stored in the same physical address in the upper memory 103 and the lower memory 104 belong to different column addresses, that is, different outer codes, as shown in FIG. Therefore, the upper outer code decoder 105 performs error correction processing on the upper byte and the lower outer code decoder 106 independently on the lower byte, and the corrected data is independently processed on the upper memory 103 and the lower memory 10.
It will be written back to 4.

Finally, the correction processing section 107 and the output address generation section 110 execute the correction processing and output the data after the correction processing to the outside. The output address generator 110 is shown in FIG.
Then, the physical address is sequentially calculated from the 0th row in the row direction and is output to the common address bus. The correction processing unit 107 outputs the plane switching signal in synchronization with the output timing of the common address of the output address generation unit 110, but the upper outer code decoder 105 and the lower outer code decoder 106 are provided for each row, that is, for each data block. When it is determined that the reliability is lacking based on the outer code error information given from, the signal indicating the surface opposite to the surface used for the inner code decoding processing and the outer code decoding processing, that is, the inverted surface switching signal is Output.
As the data output to the outside via the upper data bus 102a and the lower data bus 102b, the data confirmed to have sufficient reliability by the inner code decoding process and the outer code decoding process is output, and the data lacks reliability. In this case, the reliability is confirmed in the past, and the correction processing in data block units is realized in which the data stored and held in either of the two surfaces of the upper memory 103 and the lower memory 104 is output as correction data. ing.

As described above, in the above-mentioned conventional example, by sharing the address bus of the upper memory 103 and the lower memory 104, the number of output pins can be reduced when integrated into a circuit, and while realizing in a small package, Code decoding process,
Outer code decoding processing and correction processing are executed.

[0008]

However, the above conventional configuration has a problem that two outer code decoders, a higher outer code decoder and a lower outer code decoder, are required. Generally, the circuit scale of the Reed-Solomon code decoder is large, and since the Reed-Solomon code decoder must be provided in duplicate, the circuit scale will be increased as a whole.

In view of the above problems, it is an object of the present invention to provide a memory access device which can be processed by one outer code decoder without impairing the advantage of the conventional example that the number of output pins can be reduced when integrated into a circuit. To do.

[0010]

In order to achieve this object, a memory access device of the present invention comprises a common address signal generating section for generating a NM bit common address signal, and the common address signal. Two types of connection relations are selected between the M-bit first independent address signal generation unit, the second independent address signal generation unit, the two sets of external data buses connected to the memory, and the two sets of internal data buses. And a data bus switch circuit that operates.

[0011]

According to the present invention, with the above configuration, the first independent address can be obtained by accessing the virtual two-dimensional array of the outer code and the inner code in the row direction and the column direction and by accessing the first surface and the second surface. And the second independent address generation method are switched, and the data bus switch circuit inverts the relationship between the upper byte and the lower byte of the memory as needed to connect to the internal data bus. Similar to the access in the direction, the upper byte and the lower byte of the internal data bus are data bytes of one code, and therefore can always be processed by the same outer code decoder.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a memory access device according to an embodiment of the present invention. In FIG. 1, an inner code decoder 1 inputs a data block which is a unit of data input / output, and its correction output is a higher internal data bus 2
a and the lower internal data bus 2b, and outputs the inner code error information to the outer code decoder 3. The outer code decoder 3 is an outer code error correction unit connected to the upper data bus 2a and the lower data bus 2b, and supplies outer code error information to the modification processing unit 4. The modification processing unit 4 gives the surface switching signal to the upper independent address generation unit 5 and the lower independent address generation unit 6 as a 2-bit common signal. The input logical address generation unit 7 is a virtual one for the inner code decoder 1, the outer code logical address generation unit 8 is a outer code decoder 3, and the output logical address generation unit 9 is a virtual data output to the outside. The logical address is calculated and supplied to the common address generation unit 10. The upper memory 11 and the lower memory 12 are A _N, respectively.
A random access memory having an N-bit address bus of A ₁ to an 8-bit data bus, and N-2 bits except for the most significant bit A _N and the 7th bit A ₇ of the address bus as a common address. bus 14, address bus a _N of upper memory 11, 2-bit a ₇ is in the upper independent address generation unit 5, the a _N, 2-bit a ₇ address bus of the lower memory 12 lower independent address generator 6 The data bus of the upper memory 11 is connected to the upper external data bus 15a, and the data bus of the lower memory 12 is connected to the lower external data bus 15b.
The upper memory 11 and the lower memory 12 are sealed in one memory package 13. The data bus switch 16 inputs the logical address and has two sets of data buses, an upper internal data bus 2a and a lower internal data bus 2b,
Upper external data bus 15a, Lower external data bus 15b
2 is a switch circuit for switching the connection relationship between the two sets of data buses.

The operation of the memory access device configured as described above will be described below.

The upper independent address generator 5, the lower independent address generator 6, and the data bus switch 16 have two operation modes, a column direction access mode and a row direction access mode. The memory access device of this embodiment has three types of operations. The input data block write operation has a row direction access mode, the outer code decoding operation has a column direction access mode, and the output data block read operation has a row direction access mode. It shall be automatically selected. The three types of operations will be described below in order.

First, the operation of writing the input data block into the memory package 13 will be described. The inner code decoder 1 executes an error correction process on the input data block, and outputs the corrected data block to the internal data bus 2.
The data is transferred to the upper memory 11 and the lower memory 12 via the data bus switch 16 and the external data bus 15, and when the correction result is uncorrectable, the inner code error information is notified to the outer code decoder 3. . FIG. 4 is a code structure diagram showing the relationship between the inner code and the outer code, but since this is the same as the code structure of the conventional example described above, the description thereof will be omitted. FIG. 2 is a memory map showing the storage states of the codes shown in FIG. 4 in the upper memory 11 and the lower memory 12. In FIG. 2, the inner code and the outer code are shown as virtual two-dimensional addresses of the row address and the column address, but the physical address direction coincides with the row direction. In FIG. 2, H indicates a data byte stored in the upper memory 11, and L indicates a data byte stored in the lower memory 12. Two adjacent bytes of data in the same row are stored at the same physical address. Has been done. In addition, one two-dimensional array of inner code and outer code is stored in the upper memory 1
1. On the lower memory 12, two storage areas, a first surface and a second surface, are provided. Now, the relationship between the logical address and the physical address is the formula (1) when the column address of the logical address is X, the row address is Y, and the number of bytes in one column is 128 bytes.

Physical address = int (X / 2) + 64 * Y + P (2 ^N-1 ) (1) However, P = 0 for the first surface and P = 1 for the second surface.

When storing the data block of the processing result of the inner code decoder 1 in the upper memory 11 and the lower memory 12, the input logical address generator 7 calculates a logical address consisting of a row address and a column address, and generates a common address. It is given to the unit 10, the upper independent address generation unit 5, and the lower independent address generation unit 6. The modification processing unit 4 determines which of the first surface and the second surface to use, generates a surface switching signal, and outputs the upper independent address generation unit 5 and the lower independent address generation unit 6
And supply to. The common address generator 10 calculates an N-2 bit common address excluding physical addresses A _N and A ₇ according to the equation (1) based on the given logical address. The upper independent address generation unit 5 and the lower independent address generation unit 6 are in the row direction access mode, the surface switching signal is A _N , the 7th bit of the physical address of the equation (1) is A ₇ , and the upper memory 11 is used. It is given to the lower memory 12, respectively. On the other hand, the data bus switch 16 is also in the row direction access mode, and the input logical address generator 7
Of the row address output from the upper external data bus 15a and the upper internal data bus 2a,
The lower external data bus 15b and the lower internal data bus 2b are respectively connected. If the row address is an odd number, the upper external data bus 15a and the lower internal data bus 2b are
The lower external data bus 15b and the upper internal data bus 2a are connected to each other. As a result, the inner code decoder 1 stores the corrected data in units of 2 bytes in the row direction while inverting the upper byte and the lower byte in the odd row, as shown in FIG.

Next, the memory access operation in the outer code decoding process will be described. When the write operation of the input data block is completed, the outer code decoder 3 and the outer code logical address generator 8 start the decoding process of the outer code. The outer code logical address generation unit 8 calculates a logical address composed of the column address shown in FIG. 2 and the row address of the even-numbered row, and supplies the logical address to the common address generation unit 10, and the correction processing unit 4
Determines whether to use the first surface or the second surface for each of the even-numbered row and the subsequent odd-numbered row indicated by the logical address, and outputs the 2-bit surface switching signal to the upper independent address generator 5 and the lower independent address. And the generator 6. Based on the given logical address, the common address generator 10
N excluding physical addresses A _N and A ₇ according to equation (1)
-Calculate a 2-bit common address. The upper independent address generation unit 5 enters the column direction access mode, calculates A ₇ from the equation (1), and if the column address is an even number, sets the even surface switching signal to A _N and determines that the column address is an odd number. In some cases, the surface switching signal of the odd-numbered row is given as A _N to the upper memory 11. The lower independent address generator 6 inverts A ₇ calculated from the equation (1), and when the column address is an even number, the surface switching signal of the odd row is A
_{As N} , when the column address is an odd number, the even surface switching signal is given as A _N to the lower memory 11. On the other hand, the data bus switch 16 is also in the column direction access mode, inspects the column address output from the outer code logical address generation unit 8, and if it is an even number, the upper external data bus 15a and the upper internal data bus 2a are The lower external data bus 15b and the lower internal data bus 2b are respectively connected. If the column address is odd, the upper external data bus 15a is connected to the lower internal data bus 2b, and the lower external data bus 15b is connected to the upper internal data bus 2a. As a result, the upper byte and the lower byte in the internal data bus 2 are adjacent data belonging to the same column in FIG. 2, and the outer code decoder 3 can access one outer code in 2-byte units in the row direction. You can At this time, in the outer code of the odd-numbered column, the processing order in the code and the external data bus 15
Although the relationship between the upper byte and the lower byte is reversed, the data bus switch 16 is inverted and connected to the internal data bus 2. Therefore, in the internal data bus 2, the relationship between the outer code processing order and the upper byte and lower byte is forward. Can be fixed to.

Finally, the read operation of the output data will be described. After the outer code decoding process is completed, the correction processing unit 4
The output logical address generation unit 9 executes the correction process and outputs the data after the correction process to the outside. In FIG. 2, the output logical address generation unit 9 sequentially calculates logical addresses of even columns from the 0th row in the row direction and outputs the logical addresses to the common address generation unit 10. The correction processing unit 4 outputs the plane switching signal at the timing of output of the logical address of the output logical address generation unit 9, but lacks reliability based on the outer code error information given from the outer code decoder 3 for each data block. If it is determined that the signal is a signal indicating a surface opposite to the surface used for the inner code decoding processing and the outer code decoding processing, that is, an inverted surface switching signal is output. Upper independent address generator 5,
Lower independent address generator 6 and data bus switch 16
Are row-direction access modes, generate upper independent addresses and lower independent addresses as in the write operation of the input data block, and connect the upper data bytes and lower data bytes of the external data bus 15 and the internal data bus 2. To control. As a result, the data stored by inverting the upper byte and the lower byte in the odd-numbered rows shown in FIG. 2 undergoes the same inversion processing, and is output to the internal data bus 2 in the correct data order. Further, when the reliability of the data block is lacking, the data reproduced in the past and stored and held in either of the two surfaces of the upper memory 11 and the lower memory 12 is output as a modified data block. The correction processing of is realized in the same manner as in the conventional example described above.

As described above, in this embodiment, the common address signal generator 10 for generating the N-2 bit common address signal and the upper independent signal for generating the 2-bit upper independent address signal paired with the common address. Address generator 5
, A lower independent address generator 6 that generates a lower independent address signal, and a data bus switch that selects two types of connection relationships between the two sets of external data buses 15 and the two sets of internal data buses 2 connected to the memory. 16 is provided, the row direction access mode allows the adjacent 2 bytes belonging to the same row to be always accessed as the upper byte and the lower byte while reversing the relationship between the upper byte and the lower byte in the case of an odd row, and in the column direction. In the access mode, since the adjacent 2 bytes belonging to the same column can always be accessed as the upper byte and the lower byte while reversing the relationship between the upper byte and the lower byte in the case of odd columns, the inner code decoder 1 always has one The 2-byte data belonging to the code is the outer code decoder 3
Also, 2 bytes of data belonging to one outer code can always be accessed, and each can be processed by only one outer code decoder and one outer code decoder, which is realized with the smallest scale circuit. Is what you can do.

Further, without impairing the advantages of the conventional example,
Also in the present embodiment, most of the address bus can be shared while realizing the decoding process of Reed-Solomon product code and the correction process in units of data blocks, and when the integrated circuit is used, the number of output pins is reduced and the small size. Can be realized in a package.

Further, since the memory package 13 is one in which the address buses of the upper memory 11 and the lower memory 12 are made common to reduce the number of input pins and sealed in one package, the mounting area is reduced. The device can be downsized.

In this embodiment, the upper memory 11 and the lower memory 12 have their respective independent addresses assigned to A _N and A ₇ , but they may be assigned to other address bits. Further, in the present embodiment, as shown in FIG. 2, since the correction processing using the Reed-Solomon product code of the two-dimensional array and the two planes is adopted, the upper independent address generation unit 5 and the lower independent address generation unit 6 are respectively 2 Although the configuration is such that a bit independent address is generated, the upper independent address generation unit 5 and the lower independent address can be obtained by a correction process using multiple surfaces of three or more surfaces or a multidimensional Reed-Solomon product code of three-dimensional array or more. The address generators 6 may each be configured to generate an independent address of 3 bits or more, or may be configured to omit the correction process and generate a 1-bit independent address.

Further, the memory package 13 has a structure in which two independent memory chips of the upper memory 11 and the lower memory 12 are sealed in the same package, but the upper memory 11 and the lower memory 12 are on the same semiconductor substrate. The structure may be formed, or the upper memory 11 and the lower memory 12 may be sealed in independent packages.

[0026]

As described above, the memory access device of the present invention can access the virtual two-dimensional array of the outer code and the inner code in the row direction and the column direction by the first independent address signal and the second independent address signal.
In case of row direction access, the internal data bus is switched by switching the method of generating the independent address signal of, and by inverting the relationship between the upper byte and the lower byte of the memory with the data bus switch circuit and connecting to the internal data bus. Since the upper byte and lower byte of are the adjacent 2 bytes that belong to the same row, and the upper byte and lower byte of the internal data bus are the adjacent 2 bytes that belong to the same column even in the column direction access,
With the advantage that the memory address bus can be shared, the number of outer code decoders required from two was reduced to one,
The decoding processing of the Reed-Solomon product code can be realized. Since Reed-Solomon code decoders generally have a large circuit scale, the chip area can be greatly reduced by reducing the number of outer code decoders when integrated into an integrated circuit, and the number of output pins can be reduced by sharing the address bus to realize a small package. Therefore, the cost is low, and the effect is great for downsizing the device.

Also, in the memory device of the present invention, the N-M bits of the addresses of the two memories are made common and sealed in the same package or formed on the same semiconductor substrate, so the number of memory input pins is reduced. However, the mounting area is reduced, which is effective for downsizing the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory access device according to an embodiment of the present invention.

FIG. 2 is a memory map showing a storage state of a memory in the embodiment.

FIG. 3 is a block diagram showing a configuration of a memory access device in a conventional example.

FIG. 4 is a schematic diagram showing a code structure of an inner code and an outer code in a memory.

FIG. 5 is a memory map showing a storage state of a memory in the conventional example.

[Explanation of symbols]

 1 Inner Code Decoder 2 Internal Data Bus 3 Outer Code Decoder 4 Retouching Processing Section 5 Upper Independent Address Generation Section 6 Lower Independent Address Generation Section 7 Input Logical Address Generation Section 8 Outer Code Logical Address Generation Section 9 Output Logical Address Generation Section 10 Common address generator 11 Upper memory 12 Lower memory 13 Memory package 14 Common address bus 15 External data bus 16 Data bus switch

Claims (4)

[Claims] 1. A memory access device for accessing a memory having two sets of data buses and two sets of address buses, comprising: a common address signal generation section for generating a common address signal of NM bits; and the common address. A first for generating an M-bit first independent address signal that forms an N-bit address signal paired with the signal to feed the first address bus of the memory
An independent address signal generation unit for generating an M-bit second independent address signal that forms an N-bit address signal that forms a pair with the common address signal and is supplied to the second address bus of the memory. Two
Independent address signal generation unit, two sets of internal data buses, two sets of external data buses connected to a memory, and two types of connection relationships between the two sets of internal data buses and the two sets of external data buses. A memory access device having a data bus switch circuit for selecting. 2. The common address signal generator includes means for calculating a common address from a virtual row address and a column address, and the data bus switch circuit has two operation modes, and a first operation mode. Then, the connection relation between the internal data bus and the external data bus is selected according to the state of the specific bit of the row address. In the second operation mode, the connection relation between the internal data bus and the external data bus is selected according to the state of the specific bit of the column address. The memory access device according to claim 1, further comprising selection means for selecting. 3. A semiconductor memory chip having N-bit address signals, an N-M-bit common address signal terminal to which the N-M-bit address signals of the two semiconductor memory chips are connected together, A memory device having 2M-bit independent address signal terminals to which M-bit address signals of two semiconductor memory chips are independently connected, respectively, wherein the two semiconductor memory chips are sealed in the same package. 4. A memory having two N-bit address signals, an N-M-bit common address signal terminal to which the N-M-bit address signals of the two semiconductor memory chips are connected together, A memory device having a 2-Mbit independent address signal terminal to which M-bit address signals of the semiconductor memory chip are independently connected, and wherein the two semiconductor memory chips are formed on the same semiconductor substrate.