JP3717606B2 - 制御可能な入力バッファ、それを含む集積回路、および論理装置のセットアップおよびホールド時間を調整するための方法 - Google Patents

制御可能な入力バッファ、それを含む集積回路、および論理装置のセットアップおよびホールド時間を調整するための方法 Download PDF

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Publication number
JP3717606B2
JP3717606B2 JP24317696A JP24317696A JP3717606B2 JP 3717606 B2 JP3717606 B2 JP 3717606B2 JP 24317696 A JP24317696 A JP 24317696A JP 24317696 A JP24317696 A JP 24317696A JP 3717606 B2 JP3717606 B2 JP 3717606B2
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Japan
Prior art keywords
input
signal
controllable
input signal
setup
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Expired - Fee Related
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JP24317696A
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Japanese (ja)
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JPH09162706A (ja
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デニス・アール・ブランケンシップ
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Mitsubishi Semiconductor America Inc
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Mitsubishi Semiconductor America Inc
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Publication of JPH09162706A publication Critical patent/JPH09162706A/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors
JP24317696A 1995-09-15 1996-09-13 制御可能な入力バッファ、それを含む集積回路、および論理装置のセットアップおよびホールド時間を調整するための方法 Expired - Fee Related JP3717606B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52887195A 1995-09-15 1995-09-15
US08/528871 1995-09-15

Publications (2)

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JPH09162706A JPH09162706A (ja) 1997-06-20
JP3717606B2 true JP3717606B2 (ja) 2005-11-16

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JP24317696A Expired - Fee Related JP3717606B2 (ja) 1995-09-15 1996-09-13 制御可能な入力バッファ、それを含む集積回路、および論理装置のセットアップおよびホールド時間を調整するための方法

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JP (1) JP3717606B2 (de)
DE (1) DE19637167C2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474991B1 (ko) * 1997-07-29 2005-05-27 삼성전자주식회사 반도체 메모리장치의 입력버퍼 및 입력 버퍼링 방법
DE69939291D1 (de) 1998-04-28 2008-09-25 Matsushita Electric Ind Co Ltd Eingangsschaltung
US7123046B2 (en) 2002-02-13 2006-10-17 Micron Technology, Inc Apparatus for adaptively adjusting a data receiver
KR100506063B1 (ko) 2002-12-21 2005-08-05 주식회사 하이닉스반도체 셋업/홀드 타임 제어 장치

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03219719A (ja) * 1990-01-24 1991-09-27 Mitsubishi Electric Corp 遅延回路及びそれを用いた半導体装置

Also Published As

Publication number Publication date
JPH09162706A (ja) 1997-06-20
DE19637167A1 (de) 1997-03-27
DE19637167C2 (de) 1999-11-04

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