JP3716101B2 - リードフレーム及びそれを用いた半導体装置の製造方法並びに半導体装置 - Google Patents

リードフレーム及びそれを用いた半導体装置の製造方法並びに半導体装置 Download PDF

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Publication number
JP3716101B2
JP3716101B2 JP21683798A JP21683798A JP3716101B2 JP 3716101 B2 JP3716101 B2 JP 3716101B2 JP 21683798 A JP21683798 A JP 21683798A JP 21683798 A JP21683798 A JP 21683798A JP 3716101 B2 JP3716101 B2 JP 3716101B2
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JP
Japan
Prior art keywords
semiconductor chip
die pad
lead frame
semiconductor device
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP21683798A
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English (en)
Japanese (ja)
Other versions
JP2000049272A5 (https=
JP2000049272A (ja
Inventor
孝哉 菊地
仁 松井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP21683798A priority Critical patent/JP3716101B2/ja
Publication of JP2000049272A publication Critical patent/JP2000049272A/ja
Publication of JP2000049272A5 publication Critical patent/JP2000049272A5/ja
Application granted granted Critical
Publication of JP3716101B2 publication Critical patent/JP3716101B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP21683798A 1998-07-31 1998-07-31 リードフレーム及びそれを用いた半導体装置の製造方法並びに半導体装置 Expired - Fee Related JP3716101B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21683798A JP3716101B2 (ja) 1998-07-31 1998-07-31 リードフレーム及びそれを用いた半導体装置の製造方法並びに半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21683798A JP3716101B2 (ja) 1998-07-31 1998-07-31 リードフレーム及びそれを用いた半導体装置の製造方法並びに半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2005085161A Division JP2005223352A (ja) 2005-03-24 2005-03-24 半導体装置及び半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2000049272A JP2000049272A (ja) 2000-02-18
JP2000049272A5 JP2000049272A5 (https=) 2005-02-10
JP3716101B2 true JP3716101B2 (ja) 2005-11-16

Family

ID=16694688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21683798A Expired - Fee Related JP3716101B2 (ja) 1998-07-31 1998-07-31 リードフレーム及びそれを用いた半導体装置の製造方法並びに半導体装置

Country Status (1)

Country Link
JP (1) JP3716101B2 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100552353B1 (ko) * 1992-03-27 2006-06-20 가부시키가이샤 히타치초엘에스아이시스템즈 리이드프레임및그것을사용한반도체집적회로장치와그제조방법
US6856075B1 (en) * 2001-06-22 2005-02-15 Hutchinson Technology Incorporated Enhancements for adhesive attachment of piezoelectric motor elements to a disk drive suspension
JP4055158B2 (ja) 2003-05-28 2008-03-05 ヤマハ株式会社 リードフレーム及びリードフレームを備えた半導体装置
JP2005286355A (ja) * 2005-06-23 2005-10-13 Renesas Technology Corp 半導体装置
JP2010109234A (ja) * 2008-10-31 2010-05-13 Renesas Technology Corp 半導体装置

Also Published As

Publication number Publication date
JP2000049272A (ja) 2000-02-18

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