JP3708399B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP3708399B2
JP3708399B2 JP2000068285A JP2000068285A JP3708399B2 JP 3708399 B2 JP3708399 B2 JP 3708399B2 JP 2000068285 A JP2000068285 A JP 2000068285A JP 2000068285 A JP2000068285 A JP 2000068285A JP 3708399 B2 JP3708399 B2 JP 3708399B2
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wiring board
wiring
notch
semiconductor device
substrate
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JP2001257308A (en
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薫 河合
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Computer Hardware Design (AREA)
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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、複数の半導体素子を配線基板に搭載し、これら配線基板を積層し、素子基板に搭載してなる半導体装置及びその製造方法に関するものである。
【０００２】
【従来の技術】
近年の半導体装置のパッケージは、大容量化・高集積化・薄型化の要求により半導体素子を搭載した配線基板を積み重ねてパッケージングする傾向にある。例えば、複数の接続電極及びこの接続電極に電気的に接続されたリードとを有する複数の配線基板を用意し、複数の接続電極が前記配線基板の前記リードに電気的に接続された半導体素子をそれぞれの配線基板に搭載し、この半導体素子を搭載した配線基板を外部端子が形成された素子基板に積層して、配線基板の接続電極に外部端子を電気的に接続してなる半導体装置がある。
【０００３】
【発明が解決しようとする課題】
このように、特に薄型化の要求に対しては、素子や集積回路などが形成されたシリコン半導体などのチップが搭載された配線基板からなる半導体素子の厚さそのものが、例えば、５０μｍ程度に薄くなり、これら薄型の半導体素子を複数個重ねて位置合わせや搬送を行うことは、配線基板とチップからなる半導体素子の個々の反り状態のレベル違いなどにより非常に困難であった。
本発明は、このような事情によりなされたものであり、配線基板とチップからなる薄型の半導体素子を積層する時の位置合わせや搬送を容易に行うことができる半導体装置及びその製造方法を提供するものである。
【０００４】
【課題を解決するための手段】
本発明は、半導体チップを搭載した配線基板を半導体素子として複数個素子基板に積層した半導体装置において、前記素子基板に接している第１層の配線基板上のこれ以外の配線基板には切り欠きが形成され、前記第１層の配線基板上の前記切り欠きで囲まれた領域は、配線基板保持部として用いられることを特徴としている。積層された配線基板は、第１層の配線基板に設けられた配線基板保持部に吸着ヘッドの吸着ノズルで吸着されて搬送される。吸着ヘッドには位置決めピンを設けたり、位置決めピンに温度センサや荷重センサを取り付けてこれらの機能を持たせながら積層時の加工点管理を行うことができる。
このように、本発明は、複数の配線基板を積層する際の位置決め及び搬送を行う際の手段として、半導体製造装置のＸＹＺ軸を有する吸着ヘッドに複数の突起を設けている。この複数の突起は、吸着ノズル機能を有するものであり、また積層時の加熱温度を測定する為の測温機能もしくは積層時の加圧を測定する機能を有するものである。個々の突起が有する機能により、吸着による搬送、温度測定、荷重測定を実施することが可能となる。
【０００５】
すなわち、本発明の半導体装置は、複数の接続電極及びこの接続電極に電気的に接続されたリードとを有する複数の配線基板と、前記配線基板に搭載され、複数の接続電極が前記配線基板の前記リードに電気的に接続された少なくとも１つの半導体素子と、前記複数の配線基板が積層された状態で搭載され、前記配線基板の前記接続電極に電気的に接続された外部電極を有する素子基板とを具備し、前記素子基板に接している第１層の配線基板上のこの配線基板以外の配線基板には切り欠きが形成され、前記第１層の配線基板上の前記切り欠きで囲まれた領域は、配線基板保持部として用いられることを特徴としている。
前記複数の配線基板は、矩形状であり、且つ実質的に全て同じ形状であるようにしても良い。前記第１層の配線基板以外の配線基板は複数配置されており前記切り欠きは、各配線基板の同じ領域に形成されているようにしても良い。前記配線基板にはこの配線基板の前記接続電極と電気的に接続される前記外部端子が配置される外部端子用切り欠きが形成されているようにしても良い。前記切り欠きは、前記配線基板の向い合う１対の辺の少なくともいずれか一方に形成され、前記端子用切り欠きは、前記切り欠きが形成された辺と隣接する辺に形成されているようにしても良い。
【０００６】
本発明の半導体装置の製造方法は、複数の接続電極及びこの接続電極に電気的に接続されたリードとを有する複数の配線基板に前記リードに電気的に接続された少なくとも１つの半導体素子を搭載する工程と、前記配線基板が積層搭載される素子基板に外部端子を形成する工程と、前記少なくとも１つの半導体素子が搭載された配線基板の内、前記素子基板に直接接する第１層の配線基板を除いた配線基板の所定の位置に切り欠きを形成する工程と、前記第１層の配線基板を最下層にして前記複数の配線基板を積層する工程と、前記第１層の配線基板の前記切り欠きに囲まれた領域に吸着ノズルを吸着させて前記積層された配線基板を搬送し、これを素子基板に載置する工程と、前記素子基板及びこの素子基板に積層された前記複数の配線基板とを加熱加圧することによって前記外部端子を前記配線基板の接続電極に接続する工程とを具備したことを特徴としている。
【０００７】
【発明の実施の形態】
以下、図面を参照して発明の実施の形態を説明する。
まず、図１を参照して半導体装置を説明する。
図１は、半導体装置の断面図及び半導体装置を構成するチップを搭載した配線基板の断面図である。半導体装置は、高密度実装化を目的として半導体素子を積層して用いることが多くなっている。
図１（ａ）に示すように、チップが搭載された配線基板を用いた積層型半導体装置は、配線基板１〜４に集積回路などが形成されたチップ１１を搭載し、これら配線基板１〜４を積層して構成されている。配線基板１は、はんだ等からなる外部端子１８が取り付けられた、例えば、エポキシ樹脂等を材料にした素子基板１０に直接搭載される。この第１層の上に、これら配線基板２〜４を積層して外部端子１８を配線基板１〜４の半円切り欠きの周辺に形成された接続電極１６に電気的に接続する。この積層型半導体装置は、例えば、メモリに用いられる。
【０００８】
図１（ｂ）は、例えば、積層型半導体装置を構成する配線基板１の断面図である。配線基板１は、例えば、２５μｍ厚程度のポリイミドフィルムから構成されている。配線基板１の第１の面には厚さ２０μｍ程度のメッキが施された銅箔などからなる複数のリード１７が形成されている。配線基板１の端部に近い領域には各リード１７に接続された接続電極１５が形成されている。配線基板１の第２の面に形成されている接続電極１６は、裏面のリード１７に電気的に接続されている。接続電極１６は、配線基板１に形成された半円切り欠き部分を介して接続電極１５と電気的に接続されている。チップ１１は、厚さが５０μｍ程度である。このチップ１１は、配線基板１の第１の面に搭載される。リード１７の接続電極１５が接続されている先端とは反対側の先端部にチップ１１の接続電極（図示しない）上に形成された金バンプ１４が接合されている。また、配線基板１とチップ１１との間には金バンプ１４を含む接続部を被覆するようにエポキシ樹脂などのアンダーフィル樹脂封止体１３が形成されている。
【０００９】
また、後述するように、配線基板１には配線基板保持部を設けてあるが、他の配線基板２〜４にはこの保持部に相当する領域に本発明の特徴である切り欠きが形成されている。
次に、図２及び図３を参照して半導体素子を構成するチップ及びチップが搭載された配線基板の積層された状態を詳細に説明する。
図２は、チップが搭載された配線基板の斜視図、図３は、積層された状態の配線基板の斜視図である。この実施例では半導体装置として、４つの配線基板を積層する例を示しているが、本発明では、２つ以上ならどのような枚数でも可能である。
【００１０】
配線基板１〜４は、いずれも矩形で同じ形状を有しており、最下面の配線基板１を第１層として配線基板２〜３が順次積層されている。配線基板１〜４には集積回路などが形成されているチップ１１が搭載されている。図２及び図３は概略的に記載したのでチップ１１と配線基板１〜４とを電気的に接続する接続系の記載を省略している。これら配線基板１〜４には位置決めを行うための切り欠きが形成されている。切り欠きの形成方法は、第１層の配線基板１が他のものとは異なっている。これは、切り欠き６が第４層の配線基板４から第２層の配線基板２までに施されているのに対し、最下面となる第１層の配線基板１には施されていないところに特徴がある。切欠き６の形状は、半円状であることが好ましいが、位置決め効果が得られれば特に形状を限定するものではない。また、切り欠き５が配線基板全部に形成されている。切り欠き５は、切り欠き６が形成された辺とは隣接する辺に形成されている。
【００１１】
切り欠き５、６は、いずれも位置決め用に使用されるので吸着ヘッドのピンが配置されるが、切り欠き６に囲まれた第１層の配線基板１の吸着領域１２には、吸着ヘッドの吸着ノズルが吸着されて配線基板を保持する。したがって、この切り欠き６は、吸着用切り欠きとしても用いられる。また切り欠き５は、この部分に外部端子が形成配置されるので、外部端子用切り欠きとしても用いられる。
次に、図４及び図５を参照して図１に示される半導体装置の製造方法を説明する。
【００１２】
図４及び図５は、半導体装置の製造工程断面図である。まず、積層された配線基板を搭載する素子基板１０を用意する。素子基板１０は、例えば、エポキシ樹脂などを材料としている。この素子基板１０の主面にはんだペーストを印刷する（図４（ａ））。次に、印刷されたはんだペーストをリフローしてはんだボール１８を形成する（図４（ｂ））。なお、はんだペーストを使用せず、はんだボールを使用し、リフローによりボールを形成しても良い。次に、積層した配線基板１〜４を素子基板１０に載置する。このときはんだボール１８は、配線基板の切り欠き５に入るように配置する（図４（ｃ））。その後、素子基板１０と積層された配線基板１〜４とをヒートプレス１９により加熱加圧して図１に示す積層型半導体装置を形成する。はんだボール１８は、各配線基板の切り欠き５に形成されている接続電極１５、１６に接続され、外部端子を構成する。
【００１３】
次に、図６乃至図８を参照して半導体装置の製造方法を実施する半導体製造装置を説明する。
図６は、チップを搭載した配線基板の供給工程、切り欠き形成工程、配線基板積層工程、配線基板の素子基板への搭載工程及び積層された配線基板のプレス工程及び半導体装置の搬出までを処理する半導体製造装置の概略図である。図６において、チップを搭載した配線基板の供給工程は、供給装置、切り欠き形成工程は、切断装置、配線基板積層工程は、積層装置、配線基板の素子基板への搭載工程は、搬送装置及び積層された配線基板のプレス工程は加圧装置で行われる。
ウェーハ処理により素子、集積回路などが形成されたチップをウェーハから分離し、これを配線基板に搭載する。このように形成された複数の配線基板は、基板トレイ（供給装置）に乗せて半導体製造装置に搬送する。搬送された基板トレイは、複数の配線基板を搭載して、金型などの切断装置の近傍に搬送される。
【００１４】
切断装置（金型）では、配線基板１〜４を並べ金型により、図２に示す形状に切り欠きを形成する。配線基板１には、切り欠き５が対向する１対の辺に半円形状に整列させるように形成される。配線基板２、３、４には、切り欠き５が対向する１対の辺に半円形状に整列させるように形成されと共に切り欠き５が形成された辺とは隣接する辺に切り欠き６が形成される。切り欠き５、６は、いずれも位置決め用に使用される。また、この切り欠き６は、吸着用切り欠きとしても用いられる。切り欠き５は、この部分に外部端子が配置されるので外部端子用切り欠きとしても用いられる。
【００１５】
積層装置では、切り欠き加工された配線基板を順次積層して配線基板の積層体を形成する。第１層の配線基板１は、最下層に配置され、配線基板２〜４は、その上に順次積層され、図３に示す前記積層体が形成される。切り欠き５、６は、どの配線基板も同じ位置に形成されるので、積層体の切り欠きも重なって形成される。しかし、第１層の配線基板１には切り欠き６が形成されていないので、他の配線基板の切り欠きが形成されているされるべき領域は、吸着ノズルが吸着する領域として用いられる。
【００１６】
搬送装置では、積層された配線基板を積層体の状態で加圧装置まで搬送する。搬送装置としては、図７に示される位置決めヘッドを用いる。図７は、位置決めヘッドの側面図及び底面図である。位置決めヘッド７は、対向する１対の辺に形成された少なくとも２つの位置決め兼吸着ピン（吸着ノズル）８と複数の位置決め補助ピン９を有している。また、位置決め補助ピン９の一部に、温度センサもしくは荷重測定センサ機能を持たせて積層時の加工点管理を行うことができる。なお、位置決め兼吸着ピン８の方が位置決め補助ピン９より配線基板の厚さ分だけピン長さが異なっている。さらに、図７では位置決め補助ピン９は、１０本あるが、本数に関しては特に限定するものではない。
【００１７】
次に、図８を参照して配線基板の積層体を搬送する状態を説明する。
図８は、配線基板の積層体が装着された位置決めヘッドの断面図である。配線基板の積層体は、位置決めヘッド７が下降することによって、位置決め兼吸着ピンである吸着ノズル８及び位置決め補助ピン９によって、４個の配線基板１〜４が位置決めされ、吸着ノズル８が積層体の最下面となる第１の配線基板１と接触し、位置決め兼吸着ピン８内部からのバキューム２０によって、位置決め及び固定が終了すると共に、積層時には位置決め補助ピン９の一部の温度センサ又は荷重測定センサにより積層時の加工点管理を行うことが可能となる。
以上、実施例では配線基板とチップとの電気的な接続は、チップの接続電極上のバンプにより行われていたが、本発明は、このような方法に限定されず、例えば、両者の間に異方性導電樹脂フィルムを介在させ、これに導電路を形成する方法も可能である。異方性導電樹脂フィルムは、チップと配線基板との間に設けられるので両者の間の空間を密封する樹脂封止体の役割りを果たすことになる。
【００１８】
【発明の効果】
本発明の半導体装置は、以上の構成により、配線基板とチップからなる薄型の半導体素子を積層する時の位置合わせや搬送を容易に行うことができる。また、複数の配線基板を積層する際の位置決め及び搬送を行う際の手段として、半導体製造装置のＸＹＺ軸を有する吸着ヘッドに設けた複数の突起は、吸着ノズル機能を有するものであり、また積層時の加熱温度を測定する為の測温機能もしくは積層時の加圧を測定する機能を有するものである。個々の突起が有する機能により、吸着による搬送、温度測定、荷重測定を実施することが可能となる。
【図面の簡単な説明】
【図１】本発明の半導体装置の断面図及び半導体装置を構成するチップを搭載した配線基板の断面図。
【図２】本発明の半導体装置を構成する積層された配線基板の斜視図。
【図３】本発明の半導体装置を構成する配線基板の積層を説明する斜視図。
【図４】本発明の半導体装置の製造工程断面図。
【図５】本発明の半導体装置の製造工程断面図。
【図６】本発明の半導体製造装置の概略図。
【図７】本発明の半導体製造装置を構成する搬送装置の位置決めヘッドの側面図及び底面図。
【図８】図７の位置決めヘッドの配線基板を保持する状態を説明する断面図。
【符号の説明】
１、２、３、４・・・配線基板、 ５・・・外部端子用位置決め切り欠き、
６・・・吸着用位置決め切り欠き、 ７・・・位置決めヘッド、
８・・・位置決め兼吸着ピン（吸着ノズル）、
９・・・位置決め補助ピン、 １０・・・素子基板、
１１・・・チップ、 １２・・・吸着領域、
１３・・・アンダーフィル樹脂封止体、 １４・・・金バンプ、
１５、１６・・・接続電極、 １７・・・配線、 １８・・・外部端子、
１９・・・ヒートプレス、 ２０・・・バキューム。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a plurality of semiconductor elements are mounted on a wiring board, these wiring boards are stacked, and mounted on the element board, and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, semiconductor device packages tend to be stacked and packaged with wiring boards on which semiconductor elements are mounted in response to demands for larger capacity, higher integration, and thinner thickness. For example, a plurality of wiring boards having a plurality of connection electrodes and leads electrically connected to the connection electrodes are prepared, and a semiconductor element in which the plurality of connection electrodes are electrically connected to the leads of the wiring board is prepared. There is a semiconductor device that is mounted on each wiring board, the wiring board on which this semiconductor element is mounted is stacked on an element board on which external terminals are formed, and the external terminals are electrically connected to the connection electrodes of the wiring board. .
[0003]
[Problems to be solved by the invention]
As described above, in particular, in response to a demand for thinning, the thickness of a semiconductor element made of a wiring substrate on which a chip such as a silicon semiconductor on which an element or an integrated circuit is formed is as thin as about 50 μm. Thus, it is very difficult to align and carry a plurality of these thin semiconductor elements due to a difference in level of individual warpage states of the semiconductor elements including the wiring board and the chip.
The present invention has been made under such circumstances, and provides a semiconductor device that can be easily aligned and transported when thin semiconductor elements including a wiring board and a chip are stacked, and a method for manufacturing the same. Is.
[0004]
[Means for Solving the Problems]
According to the present invention, in a semiconductor device in which a plurality of wiring substrates on which a semiconductor chip is mounted are stacked as element elements on an element substrate, the other wiring substrate on the first layer wiring substrate in contact with the element substrate is notched. The region surrounded by the notch on the first-layer wiring board is used as a wiring board holding portion. The stacked wiring boards are sucked and transported by the suction nozzle of the suction head to the wiring board holding part provided on the first-layer wiring board. The suction head can be provided with a positioning pin, or a temperature sensor or a load sensor can be attached to the positioning pin to control these processing points while providing these functions.
As described above, according to the present invention, a plurality of protrusions are provided on the suction head having the XYZ axes of the semiconductor manufacturing apparatus as means for positioning and transporting when a plurality of wiring boards are stacked. The plurality of protrusions have a suction nozzle function, and also have a temperature measuring function for measuring the heating temperature at the time of lamination or a function for measuring the pressure at the time of lamination. Due to the functions of the individual protrusions, conveyance by adsorption, temperature measurement, and load measurement can be performed.
[0005]
That is, the semiconductor device of the present invention is mounted on the wiring board having a plurality of connection electrodes and leads electrically connected to the connection electrodes, and the plurality of connection electrodes are provided on the wiring board. An element substrate having at least one semiconductor element electrically connected to the lead and an external electrode mounted in a state in which the plurality of wiring boards are stacked and electrically connected to the connection electrodes of the wiring board The wiring board other than the wiring board on the first layer wiring board in contact with the element substrate is formed with a notch, and is surrounded by the notch on the first layer wiring board. This region is used as a wiring board holding part.
The plurality of wiring boards may have a rectangular shape, and substantially all have the same shape. A plurality of wiring boards other than the first-layer wiring board may be arranged, and the cutouts may be formed in the same region of each wiring board. The wiring board may be provided with a notch for external terminal in which the external terminal electrically connected to the connection electrode of the wiring board is disposed. The cutout is formed in at least one of a pair of sides facing the wiring board, and the terminal cutout is formed in a side adjacent to the side where the cutout is formed. May be.
[0006]
According to a method of manufacturing a semiconductor device of the present invention, at least one semiconductor element electrically connected to a lead is mounted on a plurality of wiring boards having a plurality of connection electrodes and leads electrically connected to the connection electrodes. A step of forming an external terminal on an element substrate on which the wiring substrate is stacked and mounted, and a first-layer wiring substrate in direct contact with the element substrate among the wiring substrates on which the at least one semiconductor element is mounted Forming a notch at a predetermined position of the wiring board excluding the step, laminating the plurality of wiring boards with the first-layer wiring board as the bottom layer, and the first-layer wiring board A step of adsorbing a suction nozzle to a region surrounded by the notch to convey the stacked wiring board and placing it on the element substrate; and the element substrate and the plurality of wirings stacked on the element substrate. Base It is characterized by comprising a step of connecting said external terminal connection electrodes of the wiring substrate by hot pressing and.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a semiconductor device will be described with reference to FIG.
FIG. 1 is a cross-sectional view of a semiconductor device and a cross-sectional view of a wiring board on which a chip constituting the semiconductor device is mounted. Semiconductor devices are often used by stacking semiconductor elements for the purpose of high-density mounting.
As shown in FIG. 1A, a stacked semiconductor device using a wiring board on which a chip is mounted has a chip 11 on which an integrated circuit or the like is formed on the wiring boards 1 to 4, and these wiring boards 1 to 4 are mounted. 4 is laminated. The wiring board 1 is directly mounted on an element substrate 10 made of, for example, an epoxy resin or the like, to which an external terminal 18 made of solder or the like is attached. On the first layer, the wiring boards 2 to 4 are laminated, and the external terminals 18 are electrically connected to the connection electrodes 16 formed around the semicircular cutouts of the wiring boards 1 to 4. This stacked semiconductor device is used for a memory, for example.
[0008]
FIG. 1B is a cross-sectional view of a wiring substrate 1 that constitutes a stacked semiconductor device, for example. The wiring board 1 is made of, for example, a polyimide film having a thickness of about 25 μm. A plurality of leads 17 made of a copper foil or the like plated with a thickness of about 20 μm are formed on the first surface of the wiring board 1. A connection electrode 15 connected to each lead 17 is formed in a region near the end of the wiring board 1. The connection electrode 16 formed on the second surface of the wiring board 1 is electrically connected to the lead 17 on the back surface. The connection electrode 16 is electrically connected to the connection electrode 15 through a semicircular cutout formed in the wiring board 1. The chip 11 has a thickness of about 50 μm. The chip 11 is mounted on the first surface of the wiring board 1. A gold bump 14 formed on a connection electrode (not shown) of the chip 11 is bonded to the tip of the lead 17 opposite to the tip to which the connection electrode 15 is connected. Further, an underfill resin sealing body 13 such as an epoxy resin is formed between the wiring substrate 1 and the chip 11 so as to cover the connection portion including the gold bump 14.
[0009]
Further, as will be described later, the wiring board 1 is provided with a wiring board holding part, but the other wiring boards 2 to 4 are provided with notches which are the features of the present invention in regions corresponding to the holding part. ing.
Next, with reference to FIG. 2 and FIG. 3, the chip | tip which comprises a semiconductor element and the wiring board | substrate with which the chip | tip is mounted are laminated | stacked in detail.
FIG. 2 is a perspective view of the wiring board on which the chip is mounted, and FIG. 3 is a perspective view of the wiring board in a stacked state. In this embodiment, an example in which four wiring boards are stacked as a semiconductor device is shown, but in the present invention, any number of two or more is possible.
[0010]
The wiring boards 1 to 4 are all rectangular and have the same shape, and the wiring boards 2 to 3 are sequentially stacked with the lowermost wiring board 1 as the first layer. A chip 11 on which an integrated circuit or the like is formed is mounted on the wiring boards 1 to 4. 2 and 3 are schematically described, the description of the connection system for electrically connecting the chip 11 and the wiring boards 1 to 4 is omitted. These wiring boards 1 to 4 are formed with notches for positioning. The method of forming the notch is different from the other one in the first-layer wiring board 1. This is because the notch 6 is provided from the fourth layer wiring board 4 to the second layer wiring board 2 but not to the first layer wiring board 1 which is the lowermost surface. There is a feature. The shape of the notch 6 is preferably a semicircular shape, but the shape is not particularly limited as long as a positioning effect is obtained. Moreover, the notch 5 is formed in the whole wiring board. The notch 5 is formed on a side adjacent to the side on which the notch 6 is formed.
[0011]
Since the notches 5 and 6 are both used for positioning, pins of the suction head are arranged, but the suction area 12 of the first-layer wiring board 1 surrounded by the notches 6 has a suction head. The suction nozzle is sucked to hold the wiring board. Therefore, this notch 6 is also used as a suction notch. Further, the notch 5 is also used as a notch for an external terminal because an external terminal is formed and disposed in this portion.
Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS.
[0012]
4 and 5 are sectional views of the manufacturing process of the semiconductor device. First, an element substrate 10 on which a laminated wiring board is mounted is prepared. The element substrate 10 is made of, for example, an epoxy resin. A solder paste is printed on the main surface of the element substrate 10 (FIG. 4A). Next, the solder balls 18 are formed by reflowing the printed solder paste (FIG. 4B). The balls may be formed by reflow without using solder paste but using solder balls. Next, the laminated wiring boards 1 to 4 are placed on the element substrate 10. At this time, the solder ball 18 is disposed so as to enter the notch 5 of the wiring board (FIG. 4C). Thereafter, the element substrate 10 and the laminated wiring boards 1 to 4 are heated and pressurized by the heat press 19 to form the laminated semiconductor device shown in FIG. The solder ball 18 is connected to connection electrodes 15 and 16 formed in the notch 5 of each wiring board, and constitutes an external terminal.
[0013]
Next, a semiconductor manufacturing apparatus that implements the semiconductor device manufacturing method will be described with reference to FIGS.
FIG. 6 shows a process of supplying a wiring board on which a chip is mounted, a notch forming process, a wiring board stacking process, a mounting process of a wiring board onto an element substrate, a pressing process of the stacked wiring board, and a semiconductor device being carried out. It is the schematic of the semiconductor manufacturing apparatus to do. In FIG. 6, the supply process of the wiring board on which the chip is mounted is a supply apparatus, the notch formation process is a cutting apparatus, the wiring board stacking process is a stacking apparatus, and the mounting process of the wiring board to the element substrate is a transfer device and The pressing process of the laminated wiring board is performed by a pressurizing device.
A chip on which an element, an integrated circuit, etc. are formed by wafer processing is separated from the wafer and mounted on a wiring board. The plurality of wiring boards formed as described above are carried on a substrate tray (supply device) to a semiconductor manufacturing apparatus. The transported substrate tray is loaded with a plurality of wiring boards and transported in the vicinity of a cutting device such as a mold.
[0014]
In the cutting device (die), the wiring boards 1 to 4 are arranged and a notch is formed in the shape shown in FIG. In the wiring board 1, the notches 5 are formed so as to be aligned in a semicircular shape with a pair of opposing sides. In the wiring boards 2, 3, and 4, a notch 5 is formed so as to be aligned in a semicircular shape with a pair of opposite sides, and a notch 6 is adjacent to the side where the notch 5 is formed. It is formed. The notches 5 and 6 are both used for positioning. The notch 6 is also used as a suction notch. The notch 5 is also used as a notch for an external terminal because an external terminal is disposed at this portion.
[0015]
In the laminating apparatus, the cut-out processed wiring boards are sequentially laminated to form a laminated body of wiring boards. The first-layer wiring board 1 is disposed in the lowermost layer, and the wiring boards 2 to 4 are sequentially laminated thereon to form the laminate shown in FIG. Since the notches 5 and 6 are formed at the same position on all the wiring boards, the notches of the laminated body are also formed to overlap. However, since the notch 6 is not formed in the first-layer wiring board 1, the area where the notch of the other wiring board is to be formed is used as an area where the suction nozzle sucks.
[0016]
In the transfer device, the stacked wiring boards are transferred to the pressure device in the state of the stacked body. As the conveying device, the positioning head shown in FIG. 7 is used. FIG. 7 is a side view and a bottom view of the positioning head. The positioning head 7 has at least two positioning and suction pins (suction nozzles) 8 and a plurality of positioning auxiliary pins 9 formed on a pair of opposing sides. Further, a processing point management at the time of stacking can be performed by providing a part of the positioning auxiliary pin 9 with a temperature sensor or load measurement sensor function. The positioning / suction pins 8 are different in pin length from the positioning auxiliary pins 9 by the thickness of the wiring board. Further, although there are ten positioning auxiliary pins 9 in FIG. 7, the number is not particularly limited.
[0017]
Next, with reference to FIG. 8, the state which conveys the laminated body of a wiring board is demonstrated.
FIG. 8 is a cross-sectional view of a positioning head on which a laminate of wiring boards is mounted. When the positioning head 7 descends, the wiring board laminate is positioned by the suction nozzle 8 and the positioning auxiliary pin 9 that are positioning and suction pins, and the suction nozzles 8 are stacked. The first wiring board 1 which is the lowermost surface of the substrate is brought into contact with the positioning and suction pins 8 to complete the positioning and fixing, and at the time of lamination, a part of the temperature sensor or load measurement of the positioning auxiliary pins 9 is performed. It becomes possible to perform processing point management at the time of lamination by the sensor.
As described above, in the embodiments, the electrical connection between the wiring board and the chip is performed by the bumps on the connection electrodes of the chip. However, the present invention is not limited to such a method. A method of interposing an anisotropic conductive resin film and forming a conductive path in this film is also possible. Since the anisotropic conductive resin film is provided between the chip and the wiring board, it plays the role of a resin sealing body that seals the space between the two.
[0018]
【The invention's effect】
With the above configuration, the semiconductor device of the present invention can easily perform alignment and conveyance when stacking thin semiconductor elements including a wiring board and a chip. Also, as a means for positioning and transporting when a plurality of wiring boards are stacked, the plurality of protrusions provided on the suction head having the XYZ axes of the semiconductor manufacturing apparatus have a suction nozzle function, and are also stacked. It has a temperature measuring function for measuring the heating temperature at the time or a function for measuring the pressurization at the time of lamination. Due to the functions of the individual protrusions, conveyance by adsorption, temperature measurement, and load measurement can be performed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device of the present invention and a cross-sectional view of a wiring board on which a chip constituting the semiconductor device is mounted.
FIG. 2 is a perspective view of stacked wiring boards constituting the semiconductor device of the present invention.
FIG. 3 is a perspective view illustrating stacking of wiring boards constituting the semiconductor device of the present invention.
4 is a cross-sectional view of a manufacturing process of a semiconductor device of the invention. FIG.
FIG. 5 is a cross-sectional view of a manufacturing process of a semiconductor device of the present invention.
FIG. 6 is a schematic view of a semiconductor manufacturing apparatus according to the present invention.
FIGS. 7A and 7B are a side view and a bottom view of a positioning head of a transfer device constituting a semiconductor manufacturing apparatus of the present invention. FIGS.
8 is a cross-sectional view illustrating a state in which the wiring board of the positioning head of FIG. 7 is held.
[Explanation of symbols]
1, 2, 3, 4 ... wiring board, 5 ... positioning notch for external terminal,
6 ... positioning notch for suction, 7 ... positioning head,
8: Positioning and suction pin (suction nozzle),
9 ... positioning auxiliary pin, 10 ... element substrate,
11 ... chip, 12 ... adsorption region,
13 ... Underfill resin encapsulant, 14 ... Gold bump,
15, 16 ... connection electrode, 17 ... wiring, 18 ... external terminal,
19 ... heat press, 20 ... vacuum.

Claims (6)

複数の接続電極及びこの接続電極に電気的に接続されたリードとを有する複数の配線基板と、
前記配線基板に搭載され、複数の接続電極が前記配線基板の前記リードに電気的に接続された少なくとも１つの半導体素子と、
前記複数の配線基板が積層された状態で搭載され、前記配線基板の前記接続電極に電気的に接続された外部電極を有する素子基板とを具備し、
前記素子基板に接している第１層の配線基板上のこの配線基板以外の配線基板には切り欠きが形成され、前記第１層の配線基板上の前記切り欠きで囲まれた領域は、配線基板保持部として用いられることを特徴とする半導体装置。A plurality of wiring boards having a plurality of connection electrodes and leads electrically connected to the connection electrodes;
At least one semiconductor element mounted on the wiring board and having a plurality of connection electrodes electrically connected to the leads of the wiring board;
The plurality of wiring boards are mounted in a stacked state, and include an element board having an external electrode electrically connected to the connection electrode of the wiring board,
A notch is formed in a wiring board other than the wiring board on the first layer wiring board in contact with the element substrate, and a region surrounded by the notch on the first layer wiring board is a wiring A semiconductor device that is used as a substrate holding portion. 前記複数の配線基板は、矩形状であり、且つ実質的に全て同じ形状であることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the plurality of wiring boards have a rectangular shape and are substantially the same in shape. 前記第１層の配線基板以外の配線基板は複数配置されており、前記切り欠きは、各配線基板の同じ領域に形成されていることを特徴とする請求項２に記載の半導体装置。The semiconductor device according to claim 2, wherein a plurality of wiring boards other than the first-layer wiring board are arranged, and the cutout is formed in the same region of each wiring board. 前記配線基板にはこの配線基板の前記接続電極と電気的に接続される前記外部端子が配置される外部端子用切り欠きが形成されていることを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置。4. A notch for an external terminal in which the external terminal that is electrically connected to the connection electrode of the wiring board is disposed in the wiring board. A semiconductor device according to claim 1. 前記切り欠きは、前記配線基板の向い合う１対の辺の少なくともいずれか一方に形成され、前記端子用切り欠きは、前記切り欠きが形成された辺と隣接する辺に形成されていることを特徴とする請求項２乃至請求項４のいずれかに記載の半導体装置。The notch is formed on at least one of a pair of sides facing the wiring board, and the terminal notch is formed on a side adjacent to the side where the notch is formed. The semiconductor device according to claim 2, wherein the semiconductor device is a semiconductor device. 複数の接続電極及びこの接続電極に電気的に接続されたリードとを有する複数の配線基板に前記リードに電気的に接続された少なくとも１つの半導体素子を搭載する工程と、
前記配線基板が積層搭載される素子基板に外部端子を形成する工程と、
前記少なくとも１つの半導体素子が搭載された配線基板の内、前記素子基板に直接接する第１層の配線基板を除いた配線基板の所定の位置に切り欠きを形成する工程と、
前記第１層の配線基板を最下層にして前記複数の配線基板を積層する工程と、前記第１層の配線基板の前記切り欠きに囲まれた領域に吸着ノズルを吸着させて前記積層された配線基板を搬送し、これを素子基板に載置する工程と、
前記素子基板及びこの素子基板に積層された前記複数の配線基板とを加熱加圧することによって前記外部端子を前記配線基板の接続電極に接続する工程とを具備したことを特徴とする半導体装置の製造方法。Mounting at least one semiconductor element electrically connected to the leads on a plurality of wiring boards having a plurality of connection electrodes and leads electrically connected to the connection electrodes;
Forming an external terminal on an element substrate on which the wiring board is stacked and mounted;
Forming a notch at a predetermined position of the wiring board excluding the first-layer wiring board in direct contact with the element substrate among the wiring boards on which the at least one semiconductor element is mounted;
A step of laminating the plurality of wiring substrates with the first layer wiring substrate as a lowermost layer; and the layering is performed by adsorbing a suction nozzle to a region surrounded by the notch of the first layer wiring substrate. Transporting the wiring board and placing it on the element substrate;
A step of connecting the external terminal to a connection electrode of the wiring substrate by heating and pressurizing the element substrate and the plurality of wiring substrates stacked on the element substrate. Method.
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