JP2001257308A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same

Info

Publication number
JP2001257308A
JP2001257308A JP2000068285A JP2000068285A JP2001257308A JP 2001257308 A JP2001257308 A JP 2001257308A JP 2000068285 A JP2000068285 A JP 2000068285A JP 2000068285 A JP2000068285 A JP 2000068285A JP 2001257308 A JP2001257308 A JP 2001257308A
Authority
JP
Japan
Prior art keywords
wiring board
wiring
notch
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000068285A
Other languages
Japanese (ja)
Other versions
JP3708399B2 (en
Inventor
Kaoru Kawai
薫 河合
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000068285A priority Critical patent/JP3708399B2/en
Publication of JP2001257308A publication Critical patent/JP2001257308A/en
Application granted granted Critical
Publication of JP3708399B2 publication Critical patent/JP3708399B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, with which alignment between thin-type semiconductor elements, each consisting of a wiring board and a chip and transfer, can be made easily, when stacking them and a carriage of them can also be made easily, and also provide a method of manufacturing the same. SOLUTION: The semiconductor device consists of a plurality of semiconductor elements as wiring boards, mounted with a semiconductor chip 11 which are stacked on an element substrate. The wiring boards 2, 3, 4, except for the first-layer wiring board 1 which is in contact with the element substrate, have cutouts 6. Regions 12 of the first-layer wiring board surrounded by the cutouts 6 are used as wiring board holding sections. The stacked wiring boards are carried with the wiring board holding sections formed in the first-layer wiring board which is chucked by a chucking nozzle of a chucking head. The chucking head can be equipped with a positioning pin, and the positioning pin can be equipped with a temperature sensor and a load sensor to manage processing points at the time of stacking, imparted with these functions for the pin and sensors.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、複数の半導体素子
を配線基板に搭載し、これら配線基板を積層し、素子基
板に搭載してなる半導体装置及びその製造方法に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of semiconductor elements mounted on a wiring board, stacking these wiring boards, and mounting the semiconductor element on an element substrate, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年の半導体装置のパッケージは、大容
量化・高集積化・薄型化の要求により半導体素子を搭載
した配線基板を積み重ねてパッケージングする傾向にあ
る。例えば、複数の接続電極及びこの接続電極に電気的
に接続されたリードとを有する複数の配線基板を用意
し、複数の接続電極が前記配線基板の前記リードに電気
的に接続された半導体素子をそれぞれの配線基板に搭載
し、この半導体素子を搭載した配線基板を外部端子が形
成された素子基板に積層して、配線基板の接続電極に外
部端子を電気的に接続してなる半導体装置がある。
2. Description of the Related Art In recent years, packages of semiconductor devices have been tending to be packaged by stacking wiring boards on which semiconductor elements are mounted in response to demands for large capacity, high integration, and thinning. For example, a plurality of wiring boards having a plurality of connection electrodes and leads electrically connected to the connection electrodes are prepared, and a semiconductor element in which the plurality of connection electrodes are electrically connected to the leads of the wiring board is provided. There is a semiconductor device which is mounted on each wiring substrate, and a wiring substrate on which the semiconductor element is mounted is laminated on an element substrate on which external terminals are formed, and the external terminals are electrically connected to connection electrodes of the wiring substrate. .

【0003】[0003]

【発明が解決しようとする課題】このように、特に薄型
化の要求に対しては、素子や集積回路などが形成された
シリコン半導体などのチップが搭載された配線基板から
なる半導体素子の厚さそのものが、例えば、50μm程
度に薄くなり、これら薄型の半導体素子を複数個重ねて
位置合わせや搬送を行うことは、配線基板とチップから
なる半導体素子の個々の反り状態のレベル違いなどによ
り非常に困難であった。本発明は、このような事情によ
りなされたものであり、配線基板とチップからなる薄型
の半導体素子を積層する時の位置合わせや搬送を容易に
行うことができる半導体装置及びその製造方法を提供す
るものである。
As described above, especially for the demand for thinning, the thickness of a semiconductor element formed of a wiring board on which a chip such as a silicon semiconductor on which elements and integrated circuits are formed is mounted. It becomes thin, for example, about 50 μm, and it is extremely difficult to align and transport a plurality of these thin semiconductor elements due to the difference in the level of each warp state of the semiconductor elements consisting of the wiring board and the chip. It was difficult. The present invention has been made in view of such circumstances, and provides a semiconductor device and a method for manufacturing the same, which can easily perform alignment and transport when stacking thin semiconductor elements including a wiring board and a chip. Things.

【0004】[0004]

【課題を解決するための手段】本発明は、半導体チップ
を搭載した配線基板を半導体素子として複数個素子基板
に積層した半導体装置において、前記素子基板に接して
いる第1層の配線基板上のこれ以外の配線基板には切り
欠きが形成され、前記第1層の配線基板上の前記切り欠
きで囲まれた領域は、配線基板保持部として用いられる
ことを特徴としている。積層された配線基板は、第1層
の配線基板に設けられた配線基板保持部に吸着ヘッドの
吸着ノズルで吸着されて搬送される。吸着ヘッドには位
置決めピンを設けたり、位置決めピンに温度センサや荷
重センサを取り付けてこれらの機能を持たせながら積層
時の加工点管理を行うことができる。このように、本発
明は、複数の配線基板を積層する際の位置決め及び搬送
を行う際の手段として、半導体製造装置のXYZ軸を有
する吸着ヘッドに複数の突起を設けている。この複数の
突起は、吸着ノズル機能を有するものであり、また積層
時の加熱温度を測定する為の測温機能もしくは積層時の
加圧を測定する機能を有するものである。個々の突起が
有する機能により、吸着による搬送、温度測定、荷重測
定を実施することが可能となる。
SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device in which a plurality of wiring boards on which a semiconductor chip is mounted are stacked on an element substrate as semiconductor elements. A notch is formed in other wiring boards, and a region surrounded by the notch on the first-layer wiring board is used as a wiring board holding portion. The stacked wiring boards are suctioned by a suction nozzle of a suction head and transported by a wiring board holding portion provided on the first layer wiring board. A positioning pin can be provided on the suction head, or a temperature sensor or a load sensor can be attached to the positioning pin to control these processing points during lamination while providing these functions. As described above, according to the present invention, a plurality of protrusions are provided on the suction head having the XYZ axes of the semiconductor manufacturing apparatus as a means for performing positioning and transport when stacking a plurality of wiring boards. The plurality of protrusions have a suction nozzle function, and also have a temperature measurement function for measuring a heating temperature during lamination or a function for measuring pressure during lamination. The function of each projection makes it possible to perform conveyance by suction, temperature measurement, and load measurement.

【0005】すなわち、本発明の半導体装置は、複数の
接続電極及びこの接続電極に電気的に接続されたリード
とを有する複数の配線基板と、前記配線基板に搭載さ
れ、複数の接続電極が前記配線基板の前記リードに電気
的に接続された少なくとも1つの半導体素子と、前記複
数の配線基板が積層された状態で搭載され、前記配線基
板の前記接続電極に電気的に接続された外部電極を有す
る素子基板とを具備し、前記素子基板に接している第1
層の配線基板上のこの配線基板以外の配線基板には切り
欠きが形成され、前記第1層の配線基板上の前記切り欠
きで囲まれた領域は、配線基板保持部として用いられる
ことを特徴としている。前記複数の配線基板は、矩形状
であり、且つ実質的に全て同じ形状であるようにしても
良い。前記第1層の配線基板以外の配線基板は複数配置
されており前記切り欠きは、各配線基板の同じ領域に形
成されているようにしても良い。前記配線基板にはこの
配線基板の前記接続電極と電気的に接続される前記外部
端子が配置される外部端子用切り欠きが形成されている
ようにしても良い。前記切り欠きは、前記配線基板の向
い合う1対の辺の少なくともいずれか一方に形成され、
前記端子用切り欠きは、前記切り欠きが形成された辺と
隣接する辺に形成されているようにしても良い。
That is, a semiconductor device according to the present invention includes a plurality of wiring boards having a plurality of connection electrodes and leads electrically connected to the connection electrodes, and a plurality of connection electrodes mounted on the wiring board. At least one semiconductor element electrically connected to the lead of the wiring board, and an external electrode mounted on the plurality of wiring boards in a stacked state and electrically connected to the connection electrode of the wiring board. A first substrate in contact with the device substrate.
A notch is formed in a wiring board other than this wiring board on the wiring board of the layer, and a region surrounded by the notch on the wiring board of the first layer is used as a wiring board holding portion. And The plurality of wiring boards may be rectangular and substantially all have the same shape. A plurality of wiring boards other than the first-layer wiring board may be arranged, and the cutout may be formed in the same region of each wiring board. The wiring board may be formed with an external terminal cutout in which the external terminal electrically connected to the connection electrode of the wiring board is formed. The notch is formed on at least one of a pair of opposite sides of the wiring board,
The terminal notch may be formed on a side adjacent to the side on which the notch is formed.

【0006】本発明の半導体装置の製造方法は、複数の
接続電極及びこの接続電極に電気的に接続されたリード
とを有する複数の配線基板に前記リードに電気的に接続
された少なくとも1つの半導体素子を搭載する工程と、
前記配線基板が積層搭載される素子基板に外部端子を形
成する工程と、前記少なくとも1つの半導体素子が搭載
された配線基板の内、前記素子基板に直接接する第1層
の配線基板を除いた配線基板の所定の位置に切り欠きを
形成する工程と、前記第1層の配線基板を最下層にして
前記複数の配線基板を積層する工程と、前記第1層の配
線基板の前記切り欠きに囲まれた領域に吸着ノズルを吸
着させて前記積層された配線基板を搬送し、これを素子
基板に載置する工程と、前記素子基板及びこの素子基板
に積層された前記複数の配線基板とを加熱加圧すること
によって前記外部端子を前記配線基板の接続電極に接続
する工程とを具備したことを特徴としている。
According to a method of manufacturing a semiconductor device of the present invention, at least one semiconductor electrically connected to a lead is connected to a plurality of wiring boards having a plurality of connection electrodes and leads electrically connected to the connection electrodes. Mounting the element,
Forming external terminals on an element substrate on which the wiring substrate is stacked and mounted, and wiring the wiring board on which the at least one semiconductor element is mounted, excluding a first-layer wiring substrate directly in contact with the element substrate; Forming a notch at a predetermined position on the substrate, laminating the plurality of wiring boards with the first-layer wiring board being the lowermost layer, and surrounding the notch in the first-layer wiring board. Transporting the laminated wiring board by adsorbing the suction nozzle to the separated area and mounting the same on the element substrate, and heating the element substrate and the plurality of wiring boards laminated on the element substrate. Connecting the external terminals to the connection electrodes of the wiring board by applying pressure.

【0007】[0007]

【発明の実施の形態】以下、図面を参照して発明の実施
の形態を説明する。まず、図1を参照して半導体装置を
説明する。図1は、半導体装置の断面図及び半導体装置
を構成するチップを搭載した配線基板の断面図である。
半導体装置は、高密度実装化を目的として半導体素子を
積層して用いることが多くなっている。図1(a)に示
すように、チップが搭載された配線基板を用いた積層型
半導体装置は、配線基板1〜4に集積回路などが形成さ
れたチップ11を搭載し、これら配線基板1〜4を積層
して構成されている。配線基板1は、はんだ等からなる
外部端子18が取り付けられた、例えば、エポキシ樹脂
等を材料にした素子基板10に直接搭載される。この第
1層の上に、これら配線基板2〜4を積層して外部端子
18を配線基板1〜4の半円切り欠きの周辺に形成され
た接続電極16に電気的に接続する。この積層型半導体
装置は、例えば、メモリに用いられる。
Embodiments of the present invention will be described below with reference to the drawings. First, a semiconductor device will be described with reference to FIG. FIG. 1 is a cross-sectional view of a semiconductor device and a cross-sectional view of a wiring board on which chips constituting the semiconductor device are mounted.
2. Description of the Related Art In semiconductor devices, semiconductor elements are often stacked and used for high-density mounting. As shown in FIG. 1A, a stacked semiconductor device using a wiring substrate on which a chip is mounted has a chip 11 on which an integrated circuit or the like is formed mounted on wiring substrates 1 to 4 and these wiring substrates 1 to 4. 4 are laminated. The wiring substrate 1 is directly mounted on an element substrate 10 made of, for example, an epoxy resin or the like to which an external terminal 18 made of solder or the like is attached. The wiring boards 2 to 4 are stacked on the first layer, and the external terminals 18 are electrically connected to the connection electrodes 16 formed around the semicircular cutouts of the wiring boards 1 to 4. This stacked semiconductor device is used for, for example, a memory.

【0008】図1(b)は、例えば、積層型半導体装置
を構成する配線基板1の断面図である。配線基板1は、
例えば、25μm厚程度のポリイミドフィルムから構成
されている。配線基板1の第1の面には厚さ20μm程
度のメッキが施された銅箔などからなる複数のリード1
7が形成されている。配線基板1の端部に近い領域には
各リード17に接続された接続電極15が形成されてい
る。配線基板1の第2の面に形成されている接続電極1
6は、裏面のリード17に電気的に接続されている。接
続電極16は、配線基板1に形成された半円切り欠き部
分を介して接続電極15と電気的に接続されている。チ
ップ11は、厚さが50μm程度である。このチップ1
1は、配線基板1の第1の面に搭載される。リード17
の接続電極15が接続されている先端とは反対側の先端
部にチップ11の接続電極(図示しない)上に形成され
た金バンプ14が接合されている。また、配線基板1と
チップ11との間には金バンプ14を含む接続部を被覆
するようにエポキシ樹脂などのアンダーフィル樹脂封止
体13が形成されている。
FIG. 1B is a cross-sectional view of a wiring board 1 constituting a stacked semiconductor device, for example. The wiring board 1
For example, it is made of a polyimide film having a thickness of about 25 μm. A plurality of leads 1 made of plated copper foil or the like having a thickness of about 20 μm are formed on the first surface of the wiring board 1.
7 are formed. A connection electrode 15 connected to each lead 17 is formed in a region near the end of the wiring board 1. Connection electrode 1 formed on second surface of wiring board 1
6 is electrically connected to the lead 17 on the back surface. The connection electrode 16 is electrically connected to the connection electrode 15 via a semicircular notch formed in the wiring board 1. The chip 11 has a thickness of about 50 μm. This chip 1
1 is mounted on the first surface of the wiring board 1. Lead 17
A gold bump 14 formed on a connection electrode (not shown) of the chip 11 is joined to a tip end opposite to the tip to which the connection electrode 15 is connected. Further, an underfill resin sealing body 13 such as an epoxy resin is formed between the wiring board 1 and the chip 11 so as to cover a connection portion including the gold bump 14.

【0009】また、後述するように、配線基板1には配
線基板保持部を設けてあるが、他の配線基板2〜4には
この保持部に相当する領域に本発明の特徴である切り欠
きが形成されている。次に、図2及び図3を参照して半
導体素子を構成するチップ及びチップが搭載された配線
基板の積層された状態を詳細に説明する。図2は、チッ
プが搭載された配線基板の斜視図、図3は、積層された
状態の配線基板の斜視図である。この実施例では半導体
装置として、4つの配線基板を積層する例を示している
が、本発明では、2つ以上ならどのような枚数でも可能
である。
Further, as will be described later, the wiring board 1 is provided with a wiring board holding portion, but the other wiring boards 2 to 4 have cutouts, which are features of the present invention, in areas corresponding to the holding portions. Are formed. Next, referring to FIGS. 2 and 3, a state in which a chip constituting a semiconductor element and a wiring board on which the chip is mounted will be described in detail. FIG. 2 is a perspective view of a wiring board on which a chip is mounted, and FIG. 3 is a perspective view of the wiring board in a stacked state. In this embodiment, an example is shown in which four wiring boards are stacked as a semiconductor device. However, in the present invention, any number of two or more wiring boards can be used.

【0010】配線基板1〜4は、いずれも矩形で同じ形
状を有しており、最下面の配線基板1を第1層として配
線基板2〜3が順次積層されている。配線基板1〜4に
は集積回路などが形成されているチップ11が搭載され
ている。図2及び図3は概略的に記載したのでチップ1
1と配線基板1〜4とを電気的に接続する接続系の記載
を省略している。これら配線基板1〜4には位置決めを
行うための切り欠きが形成されている。切り欠きの形成
方法は、第1層の配線基板1が他のものとは異なってい
る。これは、切り欠き6が第4層の配線基板4から第2
層の配線基板2までに施されているのに対し、最下面と
なる第1層の配線基板1には施されていないところに特
徴がある。切欠き6の形状は、半円状であることが好ま
しいが、位置決め効果が得られれば特に形状を限定する
ものではない。また、切り欠き5が配線基板全部に形成
されている。切り欠き5は、切り欠き6が形成された辺
とは隣接する辺に形成されている。
The wiring boards 1 to 4 are all rectangular and have the same shape, and the wiring boards 2 to 3 are sequentially laminated with the lowermost wiring board 1 as a first layer. A chip 11 on which an integrated circuit or the like is formed is mounted on the wiring boards 1 to 4. Since FIGS. 2 and 3 are schematically described, the chip 1
A description of a connection system for electrically connecting the wiring board 1 to the wiring boards 1 to 4 is omitted. Notches for positioning are formed in these wiring boards 1-4. The method of forming the notch differs from that of the other in the first-layer wiring board 1. This is because the notch 6 is the second
It is characterized in that it is applied to the wiring board 2 of the first layer, but is not applied to the wiring board 1 of the first layer which is the lowermost surface. The shape of the notch 6 is preferably a semicircle, but the shape is not particularly limited as long as a positioning effect can be obtained. Further, the notch 5 is formed on the entire wiring board. The notch 5 is formed on a side adjacent to the side on which the notch 6 is formed.

【0011】切り欠き5、6は、いずれも位置決め用に
使用されるので吸着ヘッドのピンが配置されるが、切り
欠き6に囲まれた第1層の配線基板1の吸着領域12に
は、吸着ヘッドの吸着ノズルが吸着されて配線基板を保
持する。したがって、この切り欠き6は、吸着用切り欠
きとしても用いられる。また切り欠き5は、この部分に
外部端子が形成配置されるので、外部端子用切り欠きと
しても用いられる。次に、図4及び図5を参照して図1
に示される半導体装置の製造方法を説明する。
Since the notches 5 and 6 are both used for positioning, the pins of the suction head are arranged, but the suction area 12 of the first layer wiring board 1 surrounded by the notches 6 has The suction nozzle of the suction head is suctioned to hold the wiring board. Therefore, the notch 6 is also used as a suction notch. The notch 5 is also used as an external terminal notch since the external terminal is formed and arranged in this portion. Next, referring to FIG. 4 and FIG.
The method of manufacturing the semiconductor device shown in FIG.

【0012】図4及び図5は、半導体装置の製造工程断
面図である。まず、積層された配線基板を搭載する素子
基板10を用意する。素子基板10は、例えば、エポキ
シ樹脂などを材料としている。この素子基板10の主面
にはんだペーストを印刷する(図4(a))。次に、印
刷されたはんだペーストをリフローしてはんだボール1
8を形成する(図4(b))。なお、はんだペーストを
使用せず、はんだボールを使用し、リフローによりボー
ルを形成しても良い。次に、積層した配線基板1〜4を
素子基板10に載置する。このときはんだボール18
は、配線基板の切り欠き5に入るように配置する(図4
(c))。その後、素子基板10と積層された配線基板
1〜4とをヒートプレス19により加熱加圧して図1に
示す積層型半導体装置を形成する。はんだボール18
は、各配線基板の切り欠き5に形成されている接続電極
15、16に接続され、外部端子を構成する。
FIG. 4 and FIG. 5 are cross-sectional views showing the manufacturing process of the semiconductor device. First, the element substrate 10 on which the stacked wiring substrates are mounted is prepared. The element substrate 10 is made of, for example, an epoxy resin or the like. A solder paste is printed on the main surface of the element substrate 10 (FIG. 4A). Next, the printed solder paste is reflowed so that solder balls 1
8 (FIG. 4B). Instead of using a solder paste, a ball may be formed by reflow using a solder ball. Next, the laminated wiring substrates 1 to 4 are mounted on the element substrate 10. At this time, solder balls 18
Are arranged so as to enter the notch 5 of the wiring board (FIG. 4).
(C)). Thereafter, the element substrate 10 and the laminated wiring substrates 1 to 4 are heated and pressed by the heat press 19 to form the stacked semiconductor device shown in FIG. Solder ball 18
Are connected to the connection electrodes 15 and 16 formed in the cutouts 5 of the respective wiring boards, and constitute external terminals.

【0013】次に、図6乃至図8を参照して半導体装置
の製造方法を実施する半導体製造装置を説明する。図6
は、チップを搭載した配線基板の供給工程、切り欠き形
成工程、配線基板積層工程、配線基板の素子基板への搭
載工程及び積層された配線基板のプレス工程及び半導体
装置の搬出までを処理する半導体製造装置の概略図であ
る。図6において、チップを搭載した配線基板の供給工
程は、供給装置、切り欠き形成工程は、切断装置、配線
基板積層工程は、積層装置、配線基板の素子基板への搭
載工程は、搬送装置及び積層された配線基板のプレス工
程は加圧装置で行われる。ウェーハ処理により素子、集
積回路などが形成されたチップをウェーハから分離し、
これを配線基板に搭載する。このように形成された複数
の配線基板は、基板トレイ(供給装置)に乗せて半導体
製造装置に搬送する。搬送された基板トレイは、複数の
配線基板を搭載して、金型などの切断装置の近傍に搬送
される。
Next, a semiconductor manufacturing apparatus for implementing the method of manufacturing a semiconductor device will be described with reference to FIGS. FIG.
Is a semiconductor that processes a supply step of a wiring board on which a chip is mounted, a notch formation step, a wiring board laminating step, a mounting step of a wiring board on an element substrate, a pressing step of a laminated wiring board, and a carry-out of a semiconductor device. It is the schematic of a manufacturing apparatus. In FIG. 6, the supply step of the wiring board on which the chip is mounted is a supply apparatus, the notch forming step is a cutting apparatus, the wiring board laminating step is a laminating apparatus, and the mounting step of the wiring board on the element substrate is a transporting apparatus. The pressing step of the stacked wiring boards is performed by a pressing device. Separates the chip on which the elements, integrated circuits, etc. are formed from the wafer by wafer processing,
This is mounted on a wiring board. The plurality of wiring boards thus formed are carried on a substrate tray (supply device) and transported to the semiconductor manufacturing apparatus. The transported substrate tray is loaded with a plurality of wiring boards and transported to a vicinity of a cutting device such as a mold.

【0014】切断装置(金型)では、配線基板1〜4を
並べ金型により、図2に示す形状に切り欠きを形成す
る。配線基板1には、切り欠き5が対向する1対の辺に
半円形状に整列させるように形成される。配線基板2、
3、4には、切り欠き5が対向する1対の辺に半円形状
に整列させるように形成されと共に切り欠き5が形成さ
れた辺とは隣接する辺に切り欠き6が形成される。切り
欠き5、6は、いずれも位置決め用に使用される。ま
た、この切り欠き6は、吸着用切り欠きとしても用いら
れる。切り欠き5は、この部分に外部端子が配置される
ので外部端子用切り欠きとしても用いられる。
In the cutting device (die), the wiring substrates 1 to 4 are arranged, and a notch is formed in the shape shown in FIG. 2 by the die. The notch 5 is formed in the wiring board 1 so as to be aligned in a semicircular shape on a pair of opposing sides. Wiring board 2,
In the portions 3 and 4, the notch 5 is formed so as to be aligned in a semicircular shape on a pair of opposing sides, and the notch 6 is formed on the side adjacent to the side where the notch 5 is formed. The notches 5, 6 are both used for positioning. The notch 6 is also used as a suction notch. The notch 5 is also used as an external terminal notch because the external terminal is disposed in this portion.

【0015】積層装置では、切り欠き加工された配線基
板を順次積層して配線基板の積層体を形成する。第1層
の配線基板1は、最下層に配置され、配線基板2〜4
は、その上に順次積層され、図3に示す前記積層体が形
成される。切り欠き5、6は、どの配線基板も同じ位置
に形成されるので、積層体の切り欠きも重なって形成さ
れる。しかし、第1層の配線基板1には切り欠き6が形
成されていないので、他の配線基板の切り欠きが形成さ
れているされるべき領域は、吸着ノズルが吸着する領域
として用いられる。
In the laminating apparatus, the notched wiring boards are sequentially stacked to form a stacked body of the wiring boards. The wiring board 1 of the first layer is disposed in the lowermost layer, and the wiring boards 2 to 4
Are sequentially laminated thereon to form the laminate shown in FIG. Since the cutouts 5 and 6 are formed at the same position on all the wiring boards, the cutouts of the stacked body are also formed to overlap. However, since the notch 6 is not formed in the wiring board 1 of the first layer, the area where the notch of the other wiring board is to be formed is used as the area where the suction nozzle sucks.

【0016】搬送装置では、積層された配線基板を積層
体の状態で加圧装置まで搬送する。搬送装置としては、
図7に示される位置決めヘッドを用いる。図7は、位置
決めヘッドの側面図及び底面図である。位置決めヘッド
7は、対向する1対の辺に形成された少なくとも2つの
位置決め兼吸着ピン(吸着ノズル)8と複数の位置決め
補助ピン9を有している。また、位置決め補助ピン9の
一部に、温度センサもしくは荷重測定センサ機能を持た
せて積層時の加工点管理を行うことができる。なお、位
置決め兼吸着ピン8の方が位置決め補助ピン9より配線
基板の厚さ分だけピン長さが異なっている。さらに、図
7では位置決め補助ピン9は、10本あるが、本数に関
しては特に限定するものではない。
In the transfer device, the stacked wiring boards are transferred to the pressing device in a state of a stacked body. As a transport device,
The positioning head shown in FIG. 7 is used. FIG. 7 is a side view and a bottom view of the positioning head. The positioning head 7 has at least two positioning and suction pins (suction nozzles) 8 and a plurality of positioning auxiliary pins 9 formed on a pair of opposing sides. Further, a part of the positioning assisting pin 9 can be provided with a temperature sensor or a load measuring sensor function to manage the processing points at the time of lamination. The pin length of the positioning and suction pin 8 is different from that of the positioning assisting pin 9 by the thickness of the wiring board. Further, although there are ten positioning assisting pins 9 in FIG. 7, the number is not particularly limited.

【0017】次に、図8を参照して配線基板の積層体を
搬送する状態を説明する。図8は、配線基板の積層体が
装着された位置決めヘッドの断面図である。配線基板の
積層体は、位置決めヘッド7が下降することによって、
位置決め兼吸着ピンである吸着ノズル8及び位置決め補
助ピン9によって、4個の配線基板1〜4が位置決めさ
れ、吸着ノズル8が積層体の最下面となる第1の配線基
板1と接触し、位置決め兼吸着ピン8内部からのバキュ
ーム20によって、位置決め及び固定が終了すると共
に、積層時には位置決め補助ピン9の一部の温度センサ
又は荷重測定センサにより積層時の加工点管理を行うこ
とが可能となる。以上、実施例では配線基板とチップと
の電気的な接続は、チップの接続電極上のバンプにより
行われていたが、本発明は、このような方法に限定され
ず、例えば、両者の間に異方性導電樹脂フィルムを介在
させ、これに導電路を形成する方法も可能である。異方
性導電樹脂フィルムは、チップと配線基板との間に設け
られるので両者の間の空間を密封する樹脂封止体の役割
りを果たすことになる。
Next, referring to FIG. 8, a description will be given of a state in which the laminate of the wiring boards is transported. FIG. 8 is a cross-sectional view of the positioning head on which the laminate of the wiring boards is mounted. The laminated body of the wiring board is moved down by the positioning head 7,
The four wiring boards 1 to 4 are positioned by the suction nozzle 8 and the positioning auxiliary pins 9 which are positioning and suction pins, and the suction nozzle 8 comes into contact with the first wiring board 1 which is the lowermost surface of the laminated body, and is positioned. The positioning and fixing are completed by the vacuum 20 from the inside of the suction pin 8, and at the time of lamination, it is possible to manage the processing point at the time of lamination by a part of the temperature sensor or the load measuring sensor of the positioning auxiliary pin 9. As described above, in the embodiment, the electrical connection between the wiring board and the chip is performed by the bump on the connection electrode of the chip. However, the present invention is not limited to such a method. A method is also possible in which an anisotropic conductive resin film is interposed and a conductive path is formed in the film. Since the anisotropic conductive resin film is provided between the chip and the wiring board, it plays a role of a resin sealing body that seals a space between the two.

【0018】[0018]

【発明の効果】本発明の半導体装置は、以上の構成によ
り、配線基板とチップからなる薄型の半導体素子を積層
する時の位置合わせや搬送を容易に行うことができる。
また、複数の配線基板を積層する際の位置決め及び搬送
を行う際の手段として、半導体製造装置のXYZ軸を有
する吸着ヘッドに設けた複数の突起は、吸着ノズル機能
を有するものであり、また積層時の加熱温度を測定する
為の測温機能もしくは積層時の加圧を測定する機能を有
するものである。個々の突起が有する機能により、吸着
による搬送、温度測定、荷重測定を実施することが可能
となる。
According to the semiconductor device of the present invention having the above-described structure, positioning and transporting when stacking thin semiconductor elements composed of a wiring board and a chip can be easily performed.
Also, as means for positioning and transporting when stacking a plurality of wiring boards, a plurality of protrusions provided on a suction head having an XYZ axis of a semiconductor manufacturing apparatus have a suction nozzle function, and It has a temperature measurement function for measuring the heating temperature at the time of measurement or a function for measuring pressure during lamination. The function of each projection makes it possible to perform conveyance by suction, temperature measurement, and load measurement.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の断面図及び半導体装置を
構成するチップを搭載した配線基板の断面図。
FIG. 1 is a cross-sectional view of a semiconductor device of the present invention and a cross-sectional view of a wiring board on which a chip constituting the semiconductor device is mounted.

【図2】本発明の半導体装置を構成する積層された配線
基板の斜視図。
FIG. 2 is a perspective view of a stacked wiring board that forms the semiconductor device of the present invention.

【図3】本発明の半導体装置を構成する配線基板の積層
を説明する斜視図。
FIG. 3 is a perspective view illustrating lamination of a wiring substrate included in the semiconductor device of the present invention.

【図4】本発明の半導体装置の製造工程断面図。FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the present invention.

【図5】本発明の半導体装置の製造工程断面図。FIG. 5 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

【図6】本発明の半導体製造装置の概略図。FIG. 6 is a schematic diagram of a semiconductor manufacturing apparatus of the present invention.

【図7】本発明の半導体製造装置を構成する搬送装置の
位置決めヘッドの側面図及び底面図。
FIGS. 7A and 7B are a side view and a bottom view of a positioning head of a transfer device constituting the semiconductor manufacturing apparatus of the present invention.

【図8】図7の位置決めヘッドの配線基板を保持する状
態を説明する断面図。
FIG. 8 is a cross-sectional view illustrating a state of holding the wiring board of the positioning head of FIG. 7;

【符号の説明】[Explanation of symbols]

1、2、3、4・・・配線基板、 5・・・外部端子用
位置決め切り欠き、6・・・吸着用位置決め切り欠き、
7・・・位置決めヘッド、8・・・位置決め兼吸着
ピン(吸着ノズル)、9・・・位置決め補助ピン、
10・・・素子基板、11・・・チップ、 12・・
・吸着領域、13・・・アンダーフィル樹脂封止体、
14・・・金バンプ、15、16・・・接続電極、
17・・・配線、 18・・・外部端子、19・・
・ヒートプレス、 20・・・バキューム。
1, 2, 3, 4 ... wiring board, 5 ... positioning notch for external terminal, 6 ... positioning notch for suction,
7 positioning head, 8 positioning and suction pin (suction nozzle), 9 positioning auxiliary pin,
10 ... element substrate, 11 ... chip, 12 ...
・ Suction area, 13 ・ ・ ・ Underfill resin sealing body,
14 ... gold bump, 15, 16 ... connection electrode,
17 ... wiring, 18 ... external terminal, 19 ...
・ Heat press, 20 ・ ・ ・ Vacuum.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 複数の接続電極及びこの接続電極に電気
的に接続されたリードとを有する複数の配線基板と、 前記配線基板に搭載され、複数の接続電極が前記配線基
板の前記リードに電気的に接続された少なくとも1つの
半導体素子と、 前記複数の配線基板が積層された状態で搭載され、前記
配線基板の前記接続電極に電気的に接続された外部電極
を有する素子基板とを具備し、 前記素子基板に接している第1層の配線基板上のこの配
線基板以外の配線基板には切り欠きが形成され、前記第
1層の配線基板上の前記切り欠きで囲まれた領域は、配
線基板保持部として用いられることを特徴とする半導体
装置。
A wiring board having a plurality of connection electrodes and leads electrically connected to the connection electrodes; and a plurality of connection electrodes mounted on the wiring board, wherein the plurality of connection electrodes are electrically connected to the leads of the wiring board. At least one semiconductor element that is electrically connected, and an element substrate that is mounted in a state where the plurality of wiring boards are stacked and has an external electrode that is electrically connected to the connection electrode of the wiring board. A notch is formed in a wiring board other than this wiring board on the first layer wiring board in contact with the element substrate, and a region surrounded by the notch on the first layer wiring board is A semiconductor device used as a wiring board holding unit.
【請求項2】 前記複数の配線基板は、矩形状であり、
且つ実質的に全て同じ形状であることを特徴とする請求
項1に記載の半導体装置。
2. The method according to claim 1, wherein the plurality of wiring boards have a rectangular shape,
2. The semiconductor device according to claim 1, wherein all the semiconductor devices have substantially the same shape.
【請求項3】 前記第1層の配線基板以外の配線基板は
複数配置されており、前記切り欠きは、各配線基板の同
じ領域に形成されていることを特徴とする請求項2に記
載の半導体装置。
3. The wiring board according to claim 2, wherein a plurality of wiring boards other than the first-layer wiring board are arranged, and the cutouts are formed in the same region of each wiring board. Semiconductor device.
【請求項4】 前記配線基板にはこの配線基板の前記接
続電極と電気的に接続される前記外部端子が配置される
外部端子用切り欠きが形成されていることを特徴とする
請求項1乃至請求項3のいずれかに記載の半導体装置。
4. An external terminal notch for disposing the external terminal electrically connected to the connection electrode of the wiring board is formed in the wiring board. The semiconductor device according to claim 3.
【請求項5】 前記切り欠きは、前記配線基板の向い合
う1対の辺の少なくともいずれか一方に形成され、前記
端子用切り欠きは、前記切り欠きが形成された辺と隣接
する辺に形成されていることを特徴とする請求項2乃至
請求項4のいずれかに記載の半導体装置。
5. The notch is formed on at least one of a pair of opposing sides of the wiring board, and the terminal notch is formed on a side adjacent to the side on which the notch is formed. 5. The semiconductor device according to claim 2, wherein:
【請求項6】 複数の接続電極及びこの接続電極に電気
的に接続されたリードとを有する複数の配線基板に前記
リードに電気的に接続された少なくとも1つの半導体素
子を搭載する工程と、 前記配線基板が積層搭載される素子基板に外部端子を形
成する工程と、 前記少なくとも1つの半導体素子が搭載された配線基板
の内、前記素子基板に直接接する第1層の配線基板を除
いた配線基板の所定の位置に切り欠きを形成する工程
と、 前記第1層の配線基板を最下層にして前記複数の配線基
板を積層する工程と、 前記第1層の配線基板の前記切り欠きに囲まれた領域に
吸着ノズルを吸着させて前記積層された配線基板を搬送
し、これを素子基板に載置する工程と、 前記素子基板及びこの素子基板に積層された前記複数の
配線基板とを加熱加圧することによって前記外部端子を
前記配線基板の接続電極に接続する工程とを具備したこ
とを特徴とする半導体装置の製造方法。
6. mounting at least one semiconductor element electrically connected to the leads on a plurality of wiring boards having a plurality of connection electrodes and leads electrically connected to the connection electrodes; Forming external terminals on an element substrate on which a wiring substrate is stacked and mounted; and a wiring substrate excluding a first-layer wiring substrate directly in contact with the element substrate among the wiring substrates on which the at least one semiconductor element is mounted. Forming a notch at a predetermined position; laminating the plurality of wiring boards with the first-layer wiring board being the lowest layer; and enclosing the notch in the first-layer wiring board. Transporting the laminated wiring substrate by adsorbing the suction nozzle to the region that has been stacked, and placing the substrate on the element substrate; and heating the element substrate and the plurality of wiring substrates laminated on the element substrate by heating. Press Method of manufacturing a semiconductor device is characterized in that; and a step of connecting said external terminal connection electrodes of the wiring board by.
JP2000068285A 2000-03-13 2000-03-13 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3708399B2 (en)

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Application Number Priority Date Filing Date Title
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003133517A (en) * 2001-10-29 2003-05-09 Sharp Corp Substrate for semiconductor device, semiconductor device using the same, and laminated structure
JP2008282895A (en) * 2007-05-09 2008-11-20 Sanae Murakami Semiconductor package
JP2011003715A (en) * 2009-06-18 2011-01-06 Shinko Electric Ind Co Ltd Semiconductor device
WO2012073935A1 (en) * 2010-12-03 2012-06-07 シャープ株式会社 Rear surface electrode-type solar battery cell, solar battery module, solar battery wafer, and solar battery module production method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003133517A (en) * 2001-10-29 2003-05-09 Sharp Corp Substrate for semiconductor device, semiconductor device using the same, and laminated structure
JP2008282895A (en) * 2007-05-09 2008-11-20 Sanae Murakami Semiconductor package
JP2011003715A (en) * 2009-06-18 2011-01-06 Shinko Electric Ind Co Ltd Semiconductor device
WO2012073935A1 (en) * 2010-12-03 2012-06-07 シャープ株式会社 Rear surface electrode-type solar battery cell, solar battery module, solar battery wafer, and solar battery module production method
JP2012119602A (en) * 2010-12-03 2012-06-21 Sharp Corp Back electrode type solar cell, solar cell module, solar cell wafer and method of manufacturing solar cell module

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