JP2002110901A - Laminated semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated semiconductor device of a three-dimensional mounting structure, capable of realizing reduction in thickness of an overall laminated module in the height direction, together with high quality and manufacturing yield, and to provide a method for manufacturing the same. SOLUTION: The method for manufacturing the laminated semiconductor device comprises steps of connecting a connecting land 16 of a first double-sided module 24a to a solder-connecting land 30 of on the surface side of a spacer frame substrate 26 by using the substrate 26, in which the lands 20 are screen printed on both surfaces of a frame-like insulating board 28 as an intermediate connector, when the module 24a in which first and second semiconductor bare chips 20A and 20B are mounted on both surfaces of a first interposer 10a and a second double-sided module 24b, in which third and fourth bare semiconductors 20C and 20D are mounted on both surfaces of a second interposer 10b are laminated, and connecting the land 30 of another surface side of the substrate 26 to the land 16 of the module 24a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked semiconductor device having a three-dimensional mounting structure in which a module having a semiconductor chip mounted on an interposer is stacked on a motherboard in a plurality of stages, and a method for manufacturing the same.

[0002]

2. Description of the Related Art A three-dimensional mounting technique of stacking a plurality of semiconductor chips has been proposed as a high-density mounting method of a semiconductor integrated circuit in order to respond to recent demands for smaller and thinner electronic devices. Is being produced. When three-dimensionally mounting semiconductor chips of the same size, it is general that each semiconductor chip is individually mounted on an interposer, and then these interposers are stacked in a plurality of stages to form a module. In this case, the connection between the interposers stacked in a plurality of stages generally employs a method of connecting the connection lands provided on each interposer with solder balls.

Hereinafter, a method for manufacturing a conventional stacked semiconductor device having a three-dimensional mounting structure will be described with reference to schematic sectional views of FIGS. First, as shown in FIG. 12, a first interposer 10a, which is a rigid thin substrate, is prepared. In the first interposer 10a, wiring layers 14 are respectively formed on both surfaces of an insulating layer 12 made of, for example, polyimide or the like, and an end of the wiring layer 14 is provided with a connection for electrically connecting to another interposer. A land portion 16 is formed.

On one main surface of the first interposer 10a having such a structure, for example, an ACF (Anisot
The first bare semiconductor chip 20A is flip-chip mounted via a ropic conductive film (anisotropic conductive film) 18.

That is, after applying the ACF 18 on one main surface of the first interposer 10a, the first bare semiconductor chip 20A is mounted face down, and the electrode 22 formed on the surface is first Interposer 10a
In contact with the wiring layer 14 formed on one of the main surfaces. Thereafter, the electrodes 22 of the first bare semiconductor chip 20A and the wiring layer 14 of the first interposer 10a are joined by heating and pressing. In this way, the first bare semiconductor chip 20A is flip-chip mounted on one main surface of the first interposer 10a via the ACF 18.

Next, as shown in FIG. 13, the first bare semiconductor chip 20A flips the first interposer 10a flip-chip mounted on one main surface.
Then, as in the case of flip-chip mounting of the first bare semiconductor chip 20A, the first interposer 10
A second bare semiconductor chip 20B is flip-chip mounted on the other main surface of a through the ACF 18.

Thus, as shown in FIG. 14, a first double-sided module 24a in which the first bare semiconductor chip 20A and the second bare semiconductor chip 20B are mounted on both surfaces of the first interposer 10a, respectively. Is prepared.

[0008] Further, as shown in FIG.
2 through 14, the third bare semiconductor chip 2 is formed on both surfaces of the second interposer 10b.
The second double-sided module 24b on which the OC and the fourth bare semiconductor chip 20D are mounted is manufactured.

Next, as shown in FIG. 16, the second bare semiconductor chip 20B of the first double-sided module 24a is
The solder balls 42 are mounted on the connection lands 16 on the side on which is mounted. Then, the solder balls 42 are connected to the connection lands 16 by heating and reflowing.

Next, as shown in FIG. 17, the first double-sided module 24a in which the solder balls 42 are connected to the connection lands 16 is inverted, and the second double-sided module 24a is
b to form a laminate composed of the first double-sided module 24a and the second double-sided module 24b connected to each other via the solder ball 42.

That is, the first double-sided module 24a is
And the solder ball 42 connected to the first double-sided module 24a contacts the connection land 16 on the side of the second double-sided module 24b on which the third bare semiconductor chip 20C is mounted. After that, the connection land portion 16 on the side of the first double-sided module 24a on which the second bare semiconductor chip 20B is mounted and the third bare semiconductor chip 20C of the second double-sided module 24b are heated and reflowed. Is connected via a solder ball 42 to the connection land portion 16 on the side on which is mounted. Thus,
A laminated body including the first double-sided module 24a and the second double-sided module 24b connected to each other via the solder ball 42 is formed.

Subsequently, a laminate composed of the first double-sided module 24a and the second double-sided module 24b connected to each other via the solder ball 42, that is, the first to fourth bare semiconductor chips 20A, 20B, 20C, A four-layer module in which 20Ds are stacked in four layers is mounted on the motherboard.

That is, after a solder 40 is screen-printed on a wiring layer 38 formed on an insulating substrate 36 of a motherboard 34, the second double-sided module 2 is
4b, the connection land 16 on the side on which the fourth bare semiconductor chip 20D is mounted and the wiring layer 3 of the motherboard 34
8 is connected. Then, the solder 40 is heated and reflowed, and the first to fourth bare semiconductor chips 20A, 20B,
A four-layer module in which 20C and 20D are stacked in four layers is mounted on the motherboard. Thus, a stacked semiconductor device having a three-dimensional mounting structure is completed.

[0014]

However, in the above-mentioned conventional method of manufacturing a stacked semiconductor device having a three-dimensional mounting structure, the first bare semiconductor chips are provided on both sides of the first interposer 10a via the solder balls 42. 20A and the first bare semiconductor chip 20B are mounted respectively.
Of the double-sided module 24a and the second interposer 10
b are connected to the second double-sided module 24b on which the third bare semiconductor chip 20C and the fourth bare semiconductor chip 20D are mounted, respectively, and the first to fourth bare semiconductor chips 20A, 20B, 20C, Since the four-layer module is formed by stacking the 20Ds in four layers, the following problem occurs.

(1) The second of the first double-sided module 24a
When the solder balls 42 are mounted on the connection lands 16 on the side on which the bare semiconductor chip 20B is mounted, the solder balls 42 are sucked one by one, and the connection lands 16 of the first interposer 10a are sucked. Since it must be mounted on the upper surface, extremely complicated work requiring special devices and techniques is required, and it has been difficult to reduce the mounting time.

Further, since the size of each solder ball 42 is not always uniform, its mounting accuracy on the connection land portion 16 is not always high. It has been difficult to equalize the distance between the first double-sided module 24a and the second double-sided module 24b with high precision. Therefore,
First to fourth bare semiconductor chips 20A, 20B, 20
There have been problems such as a decrease in the quality and manufacturing yield of a four-layer module in which C and 20D are stacked in four layers.

(2) In order to meet the demand for smaller and thinner electronic equipment, the first to fourth bare semiconductor chips 2
When it is desired to reduce the overall height of the four-layer stacked module in which 0A, 20B, 20C, and 20D are stacked in four layers, there is a method of reducing the overall height by reducing the thickness of each bare semiconductor chip. As long as the solder ball 42 is used as an intermediate connector between the first double-sided module 24a and the second double-sided module 24b, the solder ball 42 needs to have a height of, for example, about 0.35 to 0.4 mm. However, since there is a restriction on the miniaturization, there is a limit to reducing the overall height of the four-layer module even if the thickness of each bare semiconductor chip is reduced. That is, in the existing technology using the solder ball 42 as the intermediate connector, there is a problem that it is difficult to sufficiently cope with a demand for a small and thin electronic device.

Accordingly, the present invention has been made in view of the above-mentioned problems, and has a three-dimensional structure capable of realizing high quality and manufacturing yield and realizing a reduction in the height of the entire laminated module. It is an object of the present invention to provide a stacked semiconductor device having a mounting structure and a method for manufacturing the same.

[0019]

The above objects can be attained by a stacked semiconductor device and a method of manufacturing the same according to the present invention described below. That is, the stacked semiconductor device according to claim 1 is a stacked semiconductor device in which a module in which a semiconductor chip is mounted on an interposer is stacked in a plurality of stages on a motherboard, and the module has connection terminals formed on both surfaces. Are stacked in a plurality of stages via the spacer frame substrate, and the connection portions of the modules stacked in the plurality of stages are connected via connection terminals of the spacer frame substrate.

As described above, in the stacked semiconductor device according to the first aspect, the module in which the semiconductor chip is mounted on the interposer is stacked in a plurality of stages via the spacer frame substrate having connection terminals formed on both surfaces. By doing
That is, when a solder ball is used as a conventional intermediate connector by using a spacer frame substrate having connection terminals formed on both surfaces as an intermediate connector interposed between modules stacked in a plurality of stages. In comparison with the above, since a special and complicated work of adsorbing and mounting the solder balls whose sizes are not necessarily uniform is not required, the connection precision such as equalizing the intervals of the stacked modules in a plurality of stages is improved. Significant improvement is achieved, and the mounting time is easily reduced.

Further, since the thickness of the spacer frame substrate having connection terminals formed on both surfaces can be made much smaller than the height of a solder ball as a conventional intermediate connector, each spacer mounted on a module can be formed. If the thickness of the bare semiconductor chip is reduced, it is easy to reduce the thickness of the entire stacked body of the plurality of modules in the height direction.

In the stacked semiconductor device according to the first aspect, a module having a semiconductor chip mounted on an interposer may include one module on one surface of the interposer.
Although it may be a single-sided module in which a number of semiconductor chips are mounted, it is preferable that the interposer is a double-sided module in which semiconductor chips are mounted on both sides of the interposer.

That is, by adjusting the thickness of the spacer frame substrate as an intermediate connector for connecting a plurality of stages of modules, it is possible to cope with either a single-sided module or a double-sided module. In the case of a module, a stacked semiconductor device with a high mounting density is realized because the number of bare semiconductor chips to be mounted is increased even if the overall height of the stacked body of a plurality of modules is the same.

In the stacked semiconductor device according to the first aspect, it is preferable that the connection terminals of the spacer frame substrate are printed by soldering on both surfaces of the spacer frame substrate. In this case, since the connection terminals are accurately formed on both sides of the spacer frame substrate by solder printing, the connection accuracy between the modules stacked in a plurality of stages is greatly improved compared to the case where the conventional solder balls are mounted. It is easily realized.

Further, since the existing technique of solder printing is used, it is possible to use the existing apparatus as it is without requiring a new apparatus, and to compare it with the conventional case where solder balls are mounted. Since there is no step of applying or washing and removing the flux, an increase in the manufacturing cost is prevented, and the mounting time is significantly reduced.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a stacked semiconductor device in which a module having a semiconductor chip mounted on an interposer is stacked on a motherboard in a plurality of stages. When stacking in a step, a spacer frame substrate having connection terminals formed on both sides is used as an intermediate connector interposed between the modules, and the connection portion of the module is connected to the connection terminal of the spacer frame substrate. Features.

Thus, in the method of manufacturing a stacked semiconductor device according to the fourth aspect, when stacking modules in which semiconductor chips are mounted on an interposer in a plurality of stages, a double-sided intermediate member interposed between the modules is used. By using a spacer frame substrate with connection terminals formed on
Compared to the case of using solder balls as a conventional intermediate connector, a special and cumbersome work of adsorbing and mounting the solder balls whose sizes are not necessarily uniform is not required, so that a plurality of stacked The connection accuracy, such as uniform spacing between modules, is greatly improved, and the mounting time is easily reduced.

Further, since the thickness of the spacer frame substrate having connection terminals formed on both sides can be made much smaller than the height of a solder ball as a conventional intermediate connection body, each spacer mounted on a module can be formed. If the thickness of the bare semiconductor chip is reduced, it is easy to reduce the thickness of the entire stacked body of the plurality of modules in the height direction.

In the method of manufacturing a stacked semiconductor device according to the fourth aspect, the module in which the semiconductor chip is mounted on the interposer may be a single-sided module in which the semiconductor chip is mounted only on the interposer. It is preferable that the interposer is a double-sided module in which semiconductor chips are mounted on both sides of the interposer.

In other words, by adjusting the thickness of the spacer frame substrate as an intermediate connector for connecting a plurality of stages of modules, it is possible to deal with either a single-sided module or a double-sided module. In the case of a module, a stacked semiconductor device with a high mounting density is realized because the number of bare semiconductor chips to be mounted is increased even if the overall height of the stacked body of a plurality of modules is the same.

In the method of manufacturing a stacked semiconductor device according to the fourth aspect, when forming the connection terminals on both surfaces of the spacer frame substrate, it is preferable that the connection terminals are formed by solder printing. In this case, the connection terminals on both sides of the spacer frame substrate are precisely formed by solder printing, so that the connection accuracy between modules stacked in a plurality of stages can be greatly improved as compared with the case where conventional solder balls are mounted. Is realized.

In addition, since the existing technique of solder printing is used, it is possible to use the existing apparatus as it is without needing a new apparatus, and to compare it with the case where a conventional solder ball is mounted. Since there is no step of applying or washing and removing the flux, an increase in the manufacturing cost is prevented, and the mounting time is significantly reduced.

[0033]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing a stacked semiconductor device having a three-dimensional mounting structure according to an embodiment of the present invention. FIGS. 2 to 11 each show a stacked semiconductor device having the three-dimensional mounting structure shown in FIG. FIG. 5 is a schematic cross-sectional view for explaining the manufacturing method of the semiconductor device;

As shown in FIG. 1, in the stacked semiconductor device having a three-dimensional mounting structure according to the present embodiment, for example, an ACF 18 is provided on one main surface of a first interposer 10a which is a rigid thin substrate. , The first bare semiconductor chip 20A is flip-chip mounted.

That is, the first bare semiconductor chip 20A is mounted face down on the one main surface of the first interposer 10a via the ACF 18, and is formed on the surface of the first bare semiconductor chip 20A. An electrode (not shown) is joined to a wiring layer 14 formed on one main surface of an insulating layer 12 made of, for example, polyimide or the like of the first interposer 10a.

Similarly, a second bare semiconductor chip 20B is flip-chip mounted on the other main surface of the first interposer 10a via an ACF 18.

Thus, the first interposer 1
0a, a first bare semiconductor chip 20A and a second bare semiconductor chip 20
A first double-sided module 24a on which B is mounted is formed.

Further, similarly to the first double-sided module 24a, the third bare semiconductor chip 20C is provided on both sides of the second interposer 10b via the ACF 18 respectively.
And a second double-sided module 24b on which the fourth bare semiconductor chip 20D is mounted.

The first double-sided module 24
a and the second double-sided module 24b are stacked via a spacer frame substrate 26 as an intermediate connector, electrically connected to each other, and connected to each other via the spacer frame substrate 26. And a laminated body including the second double-sided module 24b.

That is, the second of the first double-sided module 24a
Connection lands 16 as connection terminals on the side on which the bare semiconductor chip 20B is mounted, and a spacer frame substrate 26
A solder connection land portion 30 screen-printed on one surface side of the frame-shaped insulating substrate 28 is connected via a solder 32. Further, a solder connection land portion 30 screen-printed on the other surface side of the frame-shaped insulating substrate 28 of the spacer frame substrate 26, and a third portion of the second double-sided module 24a.
The connection land portion 16 as a connection terminal on the surface side on which the bare semiconductor chip 20C is mounted is connected via solder 32. Thus, the first double-sided module 24a and the second double-sided module 24a connected to each other via the spacer frame substrate 26
Of the double-sided module 24b.

Here, since the frame-shaped insulating substrate 28 of the spacer frame substrate 26 has a predetermined thickness, the second bare semiconductor chip 20B of the first double-sided module 24a is formed.
And the third mounted on the second double-sided module 24b.
Are housed in a space surrounded by the frame-shaped insulating substrate 28 of the spacer frame substrate 26, and they do not conflict with each other.

Further, a laminate composed of the first double-sided module 24a and the second double-sided module 24b connected to each other via the spacer frame substrate 26, that is, the first to fourth bare semiconductor chips 20A, 20B, 20C, A four-layer module in which 20Ds are stacked in four layers is a motherboard 34.
Has been implemented.

That is, the fourth bare semiconductor chip 2 of the second double-sided module 24b in this four-layer stacked module
The connection lands 16 on the surface side on which the 0D is mounted and the wiring layer 38 formed on the insulating substrate 36 of the motherboard 34 are formed by solder 40 screen-printed on the wiring layer 38.
Are connected to each other. Thus, the first to fourth
Mother module 3 is a four-layer module in which bare semiconductor chips 20A, 20B, 20C, and 20D are stacked in four layers.
4 to constitute a stacked semiconductor device having a three-dimensional mounting structure.

Next, a method of manufacturing the stacked semiconductor device having the three-dimensional mounting structure shown in FIG. 1 will be described with reference to schematic sectional views shown in FIGS. First, as shown in FIG. 2, a first interposer 10a, which is a rigid thin substrate, is prepared.

In the first interposer 10a, wiring layers 14 are formed on both surfaces of an insulating layer 12 made of, for example, polyimide or the like, and an end of the wiring layer 14 is electrically connected to another interposer or the like. A connection land 16 is formed as a connection terminal for connection. Although not shown, the connection lands 16 formed on both surfaces of the insulating layer 12 are electrically connected to each other by a wiring layer penetrating the insulating layer 12.

Then, the first bare semiconductor chip 20 A is flip-chip mounted on one main surface of the first interposer 10 a having such a structure, for example, via the ACF 18.

That is, as shown in FIGS. 2 and 3, the ACF1 is placed on one main surface of the first interposer 10a.
8 is applied, the first bare semiconductor chip 20A is mounted face down, and the first bare semiconductor chip 20A is
The electrode 22 formed on the surface A is brought into contact with the wiring layer 14 formed on one main surface of the first interposer 10a. Thereafter, the electrode 22 of the first bare semiconductor chip 20A and the first interposer 10a are heated and pressed.
To the wiring layer 14. Thus, on one main surface of the first interposer 10a, via the ACF 18,
The first bare semiconductor chip 20A is flip-chip mounted.

Next, as shown in FIG. 4, the first interposer 10a in which the first bare semiconductor chip 20A is flip-chip mounted on one main surface is inverted. Then, in the same manner as the case of flip-chip mounting of the first bare semiconductor chip 20A, the first interposer 10a
A second bare semiconductor chip 20B is flip-chip mounted on the other main surface of the semiconductor chip via the ACF 18.

In this way, as shown in FIG.
A first double-sided module 24a in which a first bare semiconductor chip 20A and a second bare semiconductor chip 20B are respectively mounted on both surfaces of the first interposer 10a is manufactured.

Also, as shown in FIG.
Through a process similar to the process shown in FIG. 5, a second double-sided module 24b in which the third bare semiconductor chip 20C and the fourth bare semiconductor chip 20D are respectively mounted on both surfaces of the second interposer 10b is manufactured. .

Next, as shown in FIG. 7, a rigid spacer frame substrate 26 is prepared as an intermediate connector for laminating and electrically connecting the first double-sided module 24a and the second double-sided module 24b. I do. When manufacturing the spacer frame substrate 26, solder connection lands 30 are formed by screen printing on both surfaces of a frame-shaped insulating substrate 28 having a predetermined thickness forming a space in the center. At this time, although not shown, the frame-shaped insulating substrate 28
The solder connection lands 30 formed on both sides of the substrate are electrically connected to each other by a wiring layer penetrating the frame-shaped insulating substrate 28.

Then, a spacer 32 is provided on the spacer frame substrate 26 as an intermediate connector manufactured in this manner via a solder 32.
The first double-sided module 24a is connected. That is, as shown in FIGS. 7 and 8, after the solder 32 is applied on the solder connection land 30 on one surface side of the spacer frame substrate 26, the first double-sided module 24 is
The connection land portion 16 on the surface on which the second bare semiconductor chip 20B is mounted and the solder connection land portion 30 on one surface side of the spacer frame substrate 26 are connected. Thereafter, the solder 32 is heated and reflowed. Thus, the first double-sided module 2 is mounted on the spacer frame substrate 26 via the solder 32.
4a is connected.

At this time, since the spacer frame substrate 26 has a predetermined thickness, the first double-sided module 24
The second bare semiconductor chip 20B mounted on a
The second bare semiconductor chip 20B is housed in a space surrounded by the spacer frame substrate 26, and the bottom surface of the second bare semiconductor chip 20B protrudes outside the frame of the spacer frame substrate 26, that is, below the plane formed by the bottom surface of the spacer frame substrate 26. Absent.

As shown in FIGS. 9 and 10,
7 and 8, the solder 32 is applied onto the solder connection lands 30 on the other surface of the spacer frame substrate 26, and then the solder 32 is applied on the other surface of the spacer frame substrate 26. Connection land 30 and second double-sided module 24a
The connection land portion 16 on the surface on which the third bare semiconductor chip 20C is mounted is connected via solder 32, and the solder 32 is heated and reflowed. Thus, the second double-sided module 24b is connected to the spacer frame substrate 26 to which the first double-sided module 24a is already connected, and the first double-sided module 24a and the second double-sided module 24a connected to each other via the spacer frame substrate 26 are connected. Of the double-sided module 24b is formed.

At this time, since the spacer frame substrate 26 as an intermediate connector has a predetermined thickness, the third bare semiconductor chip 20C mounted on the second double-sided module 24b is not The second bare semiconductor chip 20B of the first double-sided module 24a that is housed in the space surrounded by the spacer frame substrate 26 and that is housed in the same space does not conflict.

Next, as shown in FIG. 11, a laminate composed of a first double-sided module 24a and a second double-sided module 24b connected to each other via a spacer frame substrate 26, that is, first to fourth bearers Semiconductor chip 20A, 2
A four-layer module in which 0B, 20C, and 20D are stacked in four layers is mounted on the motherboard.

That is, after the solder 40 is screen-printed on the wiring layer 38 formed on the insulating substrate 36 of the motherboard 34, the second double-sided module 2 is
4b, the connection land 16 on the side on which the fourth bare semiconductor chip 20D is mounted and the wiring layer 3 of the motherboard 34
8 is connected. Thereafter, the solder 40 is heated and reflowed, and the first to fourth bare semiconductor chips 20A, 20B,
A four-layer module in which 20C and 20D are stacked in four layers is mounted on the motherboard. Thus, the stacked semiconductor device having the three-dimensional mounting structure shown in FIG. 1 is completed.

As described above, according to the present embodiment, the first
The first bare semiconductor chip 20A and the second bare semiconductor chip 20B are respectively mounted on both surfaces of the interposer 10a, and the third bare semiconductor chip 20 is mounted on both surfaces of the second interposer 10b.
C and a second double-sided module 24b on which the fourth bare semiconductor chip 20D is mounted, respectively, and then, when the first double-sided module 24a and the second double-sided module 24b are stacked, an intermediate connector A rigid spacer frame substrate 26 in which solder connection lands 30 are screen-printed on both surfaces of a frame-shaped insulating substrate 28, respectively.
The connection lands 16 on the side of the first double-sided module 24a on which the second bare semiconductor chip 20B is mounted and the solder connection lands 30 on one side of the spacer frame substrate 26 are soldered 32 And the solder connection land portion 30 on the other surface side of the spacer frame substrate 26 and the second
Third bare semiconductor chip 20 of the double-sided module 24a of FIG.
The solder 3 is connected to the connection land 16 on the surface on which C is mounted.
By connecting via the second, the first stacked layer is compared with the case where a solder ball is used as a conventional intermediate connector.
Double-sided module 24a and second double-sided module 24b
Connection accuracy can be greatly improved, and a step of applying or cleaning and removing the flux is eliminated, so that the mounting time can be greatly reduced. Therefore,
The quality and production yield of the stacked semiconductor device can be significantly improved, and the production cost can be significantly reduced.

The thickness of the rigid spacer frame substrate 26 in which the solder connection lands 30 are screen-printed on both sides of the frame-shaped insulating substrate 28 is, for example, 100 μm.
It is possible to make it much smaller than the case where the height of the solder ball as a conventional intermediate connector is, for example, about 0.35 to 0.4 mm,
If the thicknesses of the first and second bare semiconductor chips 20A and 20B and the third and fourth bare semiconductor chips 20C and 20D mounted on the first double-sided module 24a and the second double-sided module 24b are reduced, , These first
To fourth bare semiconductor chips 20A, 20B, 20C, 2
It is possible to easily reduce the thickness of the entire four-layer stacked module in which 0D is stacked in four layers in the height direction. Therefore,
First to fourth bare semiconductor chips 20A, 20B, 20
The thickness of the stacked semiconductor device in which the C and 20D are mounted three-dimensionally can be reduced, and the electronic device incorporating the stacked semiconductor device can be reduced in size and thickness.

When the spacer frame substrate 26 is manufactured, the solder connection land portion 30 as a connection terminal to be connected to the connection land portion 16 of the first double-sided module 24a or the second double-sided module 24a is frame-shaped insulated. By forming the solder connection lands 30 on both sides of the substrate 28 by screen printing, the solder connection lands 30 can be accurately formed. Significant improvement in connection accuracy between the double-sided module 24a and the second double-sided module 24b can be easily ensured. In addition, since the existing technology of solder printing is used, the existing device can be used as it is without requiring a new device, so that an increase in manufacturing cost can be prevented.

In the above embodiment, the first double-sided module 24a in which the first bare semiconductor chip 20A and the second bare semiconductor chip 20B are respectively mounted on both surfaces of the first interposer 10a, Third bare semiconductor chips 20C on both sides of the interposer 10b.
And a second double-sided module 24b on which the fourth bare semiconductor chip 20D is mounted, respectively. Instead of such a double-sided module, a single-sided module in which the semiconductor chip is mounted on only one side of the interposer is used. Are laminated, and a frame-shaped insulating substrate 2 is used as an intermediate connector at that time.
A rigid spacer frame substrate 26 in which solder connection lands 30 are screen-printed on both surfaces of the substrate 8 may be used. That is, the present invention is applicable to any case by adjusting the thickness of the spacer frame substrate 26 as an intermediate connector regardless of whether the module to be stacked in a plurality of stages is a single-sided module or a double-sided module. It is possible to

[0062]

As described in detail above, according to the stacked semiconductor device and the method of manufacturing the same of the present invention, the following effects can be obtained. That is, according to the stacked semiconductor device of the first aspect, the module in which the semiconductor chip is mounted on the interposer is stacked in a plurality of stages via the spacer frame substrate having the connection terminals formed on both surfaces. That is, when a solder ball is used as a conventional intermediate connector by using a spacer frame substrate having connection terminals formed on both surfaces as an intermediate connector interposed between modules stacked in a plurality of stages. Compared with the above, the connection accuracy between a plurality of stacked modules can be greatly improved, and the mounting time can be easily reduced. Therefore, it is possible to significantly improve the quality and the production yield of the stacked semiconductor device and to reduce the production cost.

Further, the thickness of the spacer frame substrate having connection terminals formed on both sides can be made much smaller than the height of a solder ball as a conventional intermediate connector, so that each of the components mounted on the module can be mounted. If the thickness of the bare semiconductor chip is reduced, it is possible to easily realize a reduction in the height direction of the entire stacked body of a plurality of modules. Therefore, the thickness of the stacked semiconductor device can be reduced, and the electronic device incorporating the stacked semiconductor device can be reduced in size and thickness.

Further, according to the method of manufacturing a stacked semiconductor device according to the fourth aspect, when stacking a plurality of modules having semiconductor chips mounted on the interposer, as an intermediate connector interposed between the modules, By using a spacer frame substrate with connection terminals formed on both sides, the connection accuracy between multiple stacked modules can be greatly improved compared to the case where solder balls are used as conventional intermediate connectors. In addition to that, the mounting time can be easily reduced. Therefore, it is possible to significantly improve the quality and the production yield of the stacked semiconductor device and to reduce the production cost.

Further, since the thickness of the spacer frame substrate having connection terminals formed on both surfaces can be made much smaller than the height of the solder ball as a conventional intermediate connector, each spacer mounted on the module can be formed. If the thickness of the bare semiconductor chip is reduced, it is possible to easily realize a reduction in the height direction of the entire stacked body of a plurality of modules. Therefore, the thickness of the stacked semiconductor device can be reduced, and the electronic device incorporating the stacked semiconductor device can be reduced in size and thickness.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a stacked semiconductor device having a three-dimensional mounting structure according to an embodiment of the present invention.

FIG. 2 is a schematic process cross-sectional view (part 1) for describing the method for manufacturing the stacked semiconductor device having the three-dimensional mounting structure in FIG.

FIG. 3 is a schematic process sectional view (part 2) for describing the method for manufacturing the stacked semiconductor device having the three-dimensional mounting structure in FIG. 1;

FIG. 4 is a schematic process sectional view (part 3) for describing the method for manufacturing the stacked semiconductor device having the three-dimensional mounting structure in FIG.

FIG. 5 is a schematic process sectional view (part 4) for describing the method of manufacturing the stacked semiconductor device having the three-dimensional mounting structure in FIG.

FIG. 6 is a schematic process sectional view (part 5) for describing the method of manufacturing the stacked semiconductor device having the three-dimensional mounting structure in FIG.

FIG. 7 is a schematic process sectional view (part 6) for describing the method of manufacturing the stacked semiconductor device having the three-dimensional mounting structure in FIG.

FIG. 8 is a schematic process sectional view (part 7) for explaining the method for manufacturing the stacked semiconductor device having the three-dimensional mounting structure in FIG. 1;

FIG. 9 is a schematic process sectional view (part 8) for describing the method for manufacturing the stacked semiconductor device having the three-dimensional mounting structure in FIG.

10 is a schematic process sectional view (No. 9) for describing the method for manufacturing the stacked semiconductor device having the three-dimensional mounting structure in FIG.

FIG. 11 is a schematic process sectional view for explaining the method of manufacturing the stacked semiconductor device having the three-dimensional mounting structure in FIG. 1 (part 10)
It is.

FIG. 12 is a schematic process sectional view (part 1) for describing the manufacturing process of the conventional memory module having a three-dimensional mounting structure.

FIG. 13 is a schematic process sectional view (part 2) for describing the manufacturing process of the memory module having the conventional three-dimensional mounting structure.

FIG. 14 is a schematic process sectional view (part 3) for describing the manufacturing process of the memory module having the conventional three-dimensional mounting structure.

FIG. 15 is a schematic process sectional view (part 4) for describing the manufacturing process of the memory module having the conventional three-dimensional mounting structure.

FIG. 16 is a schematic process sectional view (part 5) for describing the manufacturing process of the memory module having the conventional three-dimensional mounting structure.

FIG. 17 is a schematic process sectional view (part 6) for describing the manufacturing process of the memory module having the conventional three-dimensional mounting structure.

[Explanation of symbols]

10a first interposer, 10b first interposer, 12 insulating layer, 14 wiring layer, 16
... Connection land portion, 18 ACF, 20A... First bare semiconductor chip, 20B... Second bare semiconductor chip, 20C... Third bare semiconductor chip, 20D. , 22... Electrodes, 24a.
A double-sided module, 24b... A second double-sided module,
26: spacer frame substrate, 28: frame-shaped insulating substrate, 3
0: solder connection land portion, 32: solder, 34: motherboard, 36: insulating substrate, 38: wiring layer, 40:
... solder, 42 ... solder balls.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shizuichi Miyaji 1st place in the town of Koda-cho, Nita-gun, Aichi Prefecture Chome 7-35 Inside Sony Corporation

Claims (6)

[Claims] 1. A stacked semiconductor device in which a module in which a semiconductor chip is mounted on an interposer is stacked on a motherboard in a plurality of stages, wherein the module is interposed via a spacer frame substrate having connection terminals formed on both surfaces. Wherein the connection portions of the modules stacked in a plurality of stages are connected via the connection terminals of the spacer frame substrate. 2. The stacked semiconductor device according to claim 1, wherein the module is a double-sided module in which semiconductor chips are mounted on both surfaces of an interposer. 3. The stacked semiconductor device according to claim 1, wherein the connection terminals of the spacer frame substrate are printed by soldering on both surfaces of the spacer frame substrate. 4. A method for manufacturing a stacked semiconductor device in which a module having a semiconductor chip mounted on an interposer is stacked on a motherboard in a plurality of stages, wherein the modules are interposed between the modules when the modules are stacked in a plurality of stages. A stacked semiconductor device, wherein a spacer frame substrate having connection terminals formed on both surfaces is used as an intermediate connector, and a connection portion of the module is connected to the connection terminal of the spacer frame substrate. 5. The method of manufacturing a stacked semiconductor device according to claim 4, wherein when mounting the semiconductor chip on the interposer, semiconductor chips are mounted on both surfaces of the interposer, respectively. A method for manufacturing a semiconductor device. 6. The method of manufacturing a stacked semiconductor device according to claim 4, wherein the connection terminals are formed by solder printing when forming the connection terminals on both surfaces of the spacer frame substrate. Production method.