JPH11111914A - Three dimensional memory module - Google Patents

Three dimensional memory module

Info

Publication number
JPH11111914A
JPH11111914A JP9269041A JP26904197A JPH11111914A JP H11111914 A JPH11111914 A JP H11111914A JP 9269041 A JP9269041 A JP 9269041A JP 26904197 A JP26904197 A JP 26904197A JP H11111914 A JPH11111914 A JP H11111914A
Authority
JP
Japan
Prior art keywords
semiconductor memory
memory device
dimensional
conductive spacer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9269041A
Other languages
Japanese (ja)
Other versions
JP2870528B1 (en
Inventor
Takeo Yoshikawa
武夫 吉川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9269041A priority Critical patent/JP2870528B1/en
Application granted granted Critical
Publication of JP2870528B1 publication Critical patent/JP2870528B1/en
Publication of JPH11111914A publication Critical patent/JPH11111914A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/144Stacked arrangements of planar printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/368Assembling printed circuits with other printed circuits parallel to each other

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the number of manufacturing processes and shorten TAT by integrally connecting a plurality of semiconductor memory devices via conductive spacers with anisotropic conductive films. SOLUTION: A conductive spacer structure 3 with anisotropic conductive films is made by adhering anisotropic conductive films 1 on both faces of a conductive spacer 2. A semiconductor memory device 6 is a device, wherein a single semiconductor memory device 4 sealed in a case is mounted on one face of a substrate. A plurality of the semiconductor memory devices 6 are located on both faces of the conductive spacer structure 3 with anisotropic conductive films and then pressurized and heated to be connected electrically to form a three dimensional semiconductor memory device 9. A three dimensional memory module 12 is made by mounting a plurality of the three dimensional memory devices 9 provided with solder bumps 10 as external terminals on a memory module substrate 11.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電話・データ交換
処理制御装置および情報処理制御装置に関し、特にそれ
らの装置の記憶ユニットに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a telephone / data exchange processing control device and an information processing control device, and more particularly to a storage unit of such a device.

【0002】[0002]

【従来の技術】この種の3次元メモリモジュールは従来
3つの技術によって構成されていた。ひとつは、基板に
フリップチップ実装した複数のベア状の半導体メモリデ
バイスを、基板上の電極に設けられた半田バンプ同士を
相互に接続して立体的に積み上げる方法である。もう一
つは、複数のベア状の半導体メモリデバイスを絶縁膜を
介して積層後、各チップの電極パッド間に導電性エポキ
シ樹脂を滴下させながら柱状の導体を形成して相互に接
続する方法がある。もう一つは、ケースに封止された半
導体メモリチップを2枚のメモリモジュール基板に搭載
し、板間コネクタで基板間を接続して2階建て構造とし
た3次元メモリモジュールである。
2. Description of the Related Art A three-dimensional memory module of this type has conventionally been constituted by three techniques. One is a method of three-dimensionally stacking a plurality of bare semiconductor memory devices flip-chip mounted on a substrate by connecting solder bumps provided on electrodes on the substrate to each other. The other method is to stack a plurality of bare semiconductor memory devices via an insulating film and then form a columnar conductor while dropping conductive epoxy resin between the electrode pads of each chip and connect them to each other. is there. The other is a three-dimensional memory module having a two-story structure in which semiconductor memory chips sealed in a case are mounted on two memory module substrates, and the substrates are connected by an inter-plate connector.

【0003】[0003]

【発明が解決しようとする課題】まず基板にフリップチ
ップ実装した複数のベア状の半導体メモリデバイスを、
基板上の電極に設けられた半田バンプ同士を相互に接続
して立体的に積み上げる方法においては、製造TAT
(turn around time)が長いという欠点があった。次に
複数のベア状の半導体メモリデバイスを絶縁膜を介して
積層後、各チップの電極パッド間に導電性エポキシ樹脂
を滴下させながら柱状の導体を形成して相互に接続する
方法においては、柱状導体の製造歩留まりとコストが高
いという欠点があった。また両者ともベア状のチップを
対象とした技術で、チップの良品保証(known good di
e)に問題があった。最後に、ケースに封止された半導
体メモリチップを2枚のメモリモジュール基板に搭載
し、板間コネクタで基板間を接続して2階建て構造とし
た3次元メモリモジュールにおいては、メモリモジュー
ルの形状が大きくなり、従って配線長が長くなることに
よりメモリをドライブできない、あるいは大容量なドラ
イブ回路を必要とする欠点があった。
First, a plurality of bare semiconductor memory devices flip-chip mounted on a substrate are
The method of connecting the solder bumps provided on the electrodes on the substrate to each other and stacking them three-dimensionally involves manufacturing TAT.
(Turn around time) is long. Next, a method in which a plurality of bare semiconductor memory devices are laminated via an insulating film, and a columnar conductor is formed while the conductive epoxy resin is dropped between the electrode pads of each chip to connect to each other, the columnar method is used. There are drawbacks in that the production yield and cost of the conductor are high. In addition, both are technologies targeting bare chips, and guarantee chips with a known good quality.
e) had a problem. Finally, in a three-dimensional memory module having a two-story structure in which a semiconductor memory chip sealed in a case is mounted on two memory module substrates and the substrates are connected by a board-to-board connector, the shape of the memory module is Therefore, there is a disadvantage that the memory cannot be driven due to an increase in the wiring length, or a large-capacity drive circuit is required.

【0004】本発明は、半導体メモリデバイスを高密度
に積層でき製造工程数の少い、歩留まりの良い、立体的
に積層できる3次元メモリモジュールを提供することを
目的とする。
An object of the present invention is to provide a three-dimensional memory module which can stack semiconductor memory devices at a high density, has a small number of manufacturing steps, has a good yield, and can be stacked three-dimensionally.

【0005】[0005]

【課題を解決するための手段】本発明の3次元メモリモ
ジュールは、異方導電フィルムと、内側が中空の基板の
表裏両面にそれぞれ互いに電気的に接続された電極の対
が複数個設けられた導電性スペーサとを備え、異方導電
フィルムが導電性スペーサの表面と裏面の電極にそれぞ
れ接着されてなる異方導電フィルム付きの導電スペーサ
構造体と、ケースに封止された単一の半導体メモリデバ
イスを基板の片面に実装した半導体メモリ装置と、から
なり、導電スペーサ構造体が2個の半導体メモリ装置の
間に介装され、加圧、加熱されて半導体メモリ装置が電
気的に接続された3次元半導体メモリ装置であって、3
次元メモリ装置が、その底面に形成された複数の接続端
子を介してメモリモジュール基板上に実装されている。
A three-dimensional memory module according to the present invention comprises an anisotropic conductive film and a plurality of pairs of electrodes electrically connected to each other on the front and back surfaces of a hollow substrate. A conductive spacer structure having an anisotropic conductive film, comprising a conductive spacer, wherein an anisotropic conductive film is adhered to electrodes on the front and back surfaces of the conductive spacer, respectively, and a single semiconductor memory sealed in a case. And a semiconductor memory device having a device mounted on one side of a substrate, wherein a conductive spacer structure is interposed between the two semiconductor memory devices, and the semiconductor memory device is electrically connected by pressing and heating. A three-dimensional semiconductor memory device, comprising:
A two-dimensional memory device is mounted on a memory module substrate via a plurality of connection terminals formed on a bottom surface thereof.

【0006】そして、ケースに封止された単一の半導体
メモリデバイスを基板の両面に実装した半導体メモリ装
置を用いることができ、又は、ベア状の単一の半導体メ
モリデバイスを基板に実装した半導体メモリ装置を用い
ることもでき、更に、上述の3次元メモリモジュールは
複数個立体的に積層することができる。
[0006] A semiconductor memory device in which a single semiconductor memory device sealed in a case is mounted on both sides of a substrate can be used, or a semiconductor device in which a single bare semiconductor memory device is mounted on a substrate can be used. A memory device can be used, and a plurality of the above-described three-dimensional memory modules can be stacked three-dimensionally.

【0007】本発明によって、 (1)複数の半導体メモリデバイスを異方導電フィルム
付き導電スペーサを介して一括して一体的に接続するた
め製造工程が少ない。 (2)導電スペーサの外形形状において、その内側が中
空状であることによって、半導体メモリデバイスをZ軸
方向に隙間無く積層できる。 (3)また加熱、加圧等の製造条件が比較的ゆるく、又
製造工程も少ないので歩留まりが良好である。 (4)ベア状のメモリチップばかりでなく、市販のケー
スに封止された半導体メモリデバイスに対して本発明を
容易に適用できる。 (5)一般的なSIMMまたはDIMMタイプのメモリ
モジュールにくらべメモリチップを立体的に積層するた
め、容易に大容量のメモリモジュールを実現できる。ま
た高密度実装化によって小さなドライブ回路で駆動で
き、消費電力を減らすことができる。
According to the present invention, (1) a plurality of semiconductor memory devices are collectively and integrally connected via a conductive spacer with an anisotropic conductive film, so that the number of manufacturing steps is small. (2) In the outer shape of the conductive spacer, since the inside is hollow, semiconductor memory devices can be stacked without any gap in the Z-axis direction. (3) The manufacturing conditions such as heating and pressurizing are relatively loose, and the number of manufacturing steps is small, so that the yield is good. (4) The present invention can be easily applied not only to a bare memory chip but also to a semiconductor memory device sealed in a commercially available case. (5) Since memory chips are three-dimensionally stacked as compared with general SIMM or DIMM type memory modules, a large capacity memory module can be easily realized. In addition, high-density mounting enables driving with a small drive circuit, and power consumption can be reduced.

【0008】[0008]

【発明の実施の形態】次に本発明の一実施の形態につき
図面を参照して説明する。図1は、本発明の一構成要素
である矩形状でその内側が中空の異方導電フィルム1で
ある。異方導電フィルム1は、厚さが40μm程度の極
めて薄いフィルムの、接着性のある絶縁テープ内部に金
属粒子あるいは金属皮膜付きプラスチック粒子からなる
導電性粒子101を含むフィルムである。図1に示す異
方導電フィルム1はその内部が中空で矩形状であるが、
この形状は、その内部がベタ状であったり細長いテープ
状であるものを任意に選択して加工して得られる。
Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a rectangular anisotropic conductive film 1 which is a component of the present invention and has a hollow inside. The anisotropic conductive film 1 is a very thin film having a thickness of about 40 μm and a film including conductive particles 101 made of metal particles or plastic particles with a metal film inside an adhesive insulating tape. The inside of the anisotropic conductive film 1 shown in FIG. 1 is hollow and rectangular,
This shape is obtained by arbitrarily selecting and processing a solid or slender tape inside.

【0009】図2に、本発明の一構成要素である導電性
スペーサ2を示す。導電性スペーサ2の板端には、その
表裏面にスルーホール202を介して電気的に接続され
る電極201が複数個配置して形成される。電極の表面
材料は通常金を使用する。本図の導電性スペーサ2の内
側は中空状であるが、これは後述するように半導体デバ
イスを効率よく高密度に積層するために選択したもので
あり、ベタ状にすることも積層するデバイスによっては
選択できる。導電性スペーサ2の材質は通常有機基板が
採用され、その板厚も2mm以下であるが、任意に選択
可能である。
FIG. 2 shows a conductive spacer 2 which is a component of the present invention. At the plate end of the conductive spacer 2, a plurality of electrodes 201 that are electrically connected to the front and back surfaces through through holes 202 are arranged and formed. Gold is usually used as the surface material of the electrode. The inside of the conductive spacer 2 in this figure is hollow, which is selected for efficiently stacking semiconductor devices at high density as described later. Can be selected. The material of the conductive spacer 2 is usually an organic substrate, and the plate thickness is 2 mm or less, but can be arbitrarily selected.

【0010】図3は、本発明の一構成要素で、前記導電
性スペーサ2の両面に前記異方導電フィルム1を接着し
て形成した異方導電フィルム付き導電スペーサ構造体3
である。もともと異方導電フィルムは接着性を持つた
め、単に搭載するだけの簡単な工程でこの異方導電フィ
ルム付き導電スペーサ構造体3を形成できる。この段階
では、異方導電フィルム1は特に導電性スペーサ2の電
極に対しアラインメントする必要性はない。
FIG. 3 shows a component of the present invention, in which a conductive spacer structure 3 with an anisotropic conductive film 1 is formed by bonding the anisotropic conductive film 1 to both surfaces of the conductive spacer 2.
It is. Since the anisotropic conductive film originally has an adhesive property, the conductive spacer structure 3 with the anisotropic conductive film can be formed by a simple process of simply mounting. At this stage, the anisotropic conductive film 1 does not need to be particularly aligned with the electrodes of the conductive spacer 2.

【0011】図4は、本発明の一構成要素で、ケースに
封止された半導体メモリデバイス4一個を、有機系のシ
ングル基板5に実装した半導体メモリ装置6である。シ
ングル基板5とは、半導体メモリデバイス4を1個実装
する基板という理由からこの名称になった。シングル基
板は単にメモリデバイス1個のみ実装するものであるか
ら、デバイスサイズに近い外形サイズと2層の、板厚
0.4mm程度の有機基板で十分である。本半導体メモ
リ装置6の外部電極A7、外部電極B8は、そのシング
ル基板5の板端に位置し、かつシングル基板の両面にス
ルーホール401を介して電気的に接続されている。半
導体メモリ装置6の組み立ては通常のリフロー半田付け
装置で行う。
FIG. 4 shows a semiconductor memory device 6 which is a component of the present invention and in which one semiconductor memory device 4 sealed in a case is mounted on an organic single substrate 5. The single substrate 5 has this name because it is a substrate on which one semiconductor memory device 4 is mounted. Since a single substrate simply mounts only one memory device, an organic substrate having an outer size close to the device size and a two-layer thickness of about 0.4 mm is sufficient. The external electrodes A7 and B8 of the present semiconductor memory device 6 are located at the edge of the single substrate 5 and are electrically connected to both surfaces of the single substrate via through holes 401. The assembly of the semiconductor memory device 6 is performed by a normal reflow soldering device.

【0012】図5は、前記の発明の構成要素を組み合わ
せて3次元半導体メモリ装置9を形成する過程を説明す
るものである。異方導電フィルム付き導電スペーサ構造
体3の両面に、複数の半導体メモリ装置6を位置した
後、アラインメントを行う。アラインメントは、部品搭
載機による認識マークの識別あるいは特定の位置合わせ
治具によって行う。半導体メモリ装置6の外部電極ピッ
チは、ケース封止の半導体メモリデバイス4を使用する
ため通常0.5mmから1.27mmである。そのため
位置合わせに要求される精度は高々±0.1mm程度で
十分である。
FIG. 5 illustrates a process of forming a three-dimensional semiconductor memory device 9 by combining the components of the invention. After a plurality of semiconductor memory devices 6 are positioned on both sides of the conductive spacer structure 3 with an anisotropic conductive film, alignment is performed. The alignment is performed by identifying the recognition mark by the component mounting machine or by using a specific positioning jig. The external electrode pitch of the semiconductor memory device 6 is usually 0.5 mm to 1.27 mm in order to use the case-sealed semiconductor memory device 4. Therefore, the accuracy required for alignment is at most about ± 0.1 mm.

【0013】さてこのようにして位置決めされた3次元
半導体メモリ装置9は、特別の熱圧着装置を使って加圧
と加熱を、異方導電フィルム付き導電スペーサ構造体3
の両面に位置する半導体メモリ装置6から互いに対向す
る方向に印加される。この時の製造条件は、200℃で
20秒間の加熱、および半導体メモリ装置6の単位外部
電極あたり50gの加圧、たとえば50端子の半導体メ
モリデバイス4の場合片側2500gの加圧である。熱
圧着された異方導電フィルム1は、異方導電フィルム付
きスペーサ構造体3の電極とたがいに対向する半導体メ
モリ装置6の外部電極に位置する異方導電フィルム1は
押しつぶされ、押しつぶされることによってフィルム内
部の金属粒子あるいは金属皮膜付きプラスチック粒子は
対向する電極に食い込む形で接触し、その結果電気的接
続をもたらす。
The three-dimensional semiconductor memory device 9 positioned as described above is subjected to pressurization and heating by using a special thermocompression bonding device to apply the pressure to the conductive spacer structure 3 with the anisotropic conductive film.
Are applied in directions opposite to each other from the semiconductor memory devices 6 located on both sides of the semiconductor memory device. The manufacturing conditions at this time are heating at 200 ° C. for 20 seconds and pressurization of 50 g per unit external electrode of the semiconductor memory device 6, for example, 2500 g per side in the case of the semiconductor memory device 4 having 50 terminals. The anisotropically conductive film 1 that has been thermocompression-bonded is crushed by crushing the anisotropically conductive film 1 located on the external electrode of the semiconductor memory device 6 that is opposed to the electrode of the spacer structure 3 with the anisotropically conductive film. The metal particles or metal coated plastic particles inside the film bite into and contact the opposing electrodes, resulting in an electrical connection.

【0014】一方互いに対向する電極のない部分では異
方導電フィルム1は押しつぶされることなく、あるいは
押しつぶされても導電粒子の食い込む電極部がないた
め、したがって電気的導通はおこらない。図6に、この
ようにして製作された3次元半導体メモリ装置9を示
す。半導体メモリ装置間の電気的導通部601を図中の
矢印で示してある。
On the other hand, in the portion where there is no electrode facing each other, the anisotropic conductive film 1 is not crushed, or even if crushed, there is no electrode portion into which the conductive particles bite, so that electrical conduction does not occur. FIG. 6 shows the three-dimensional semiconductor memory device 9 manufactured as described above. The electrical conduction part 601 between the semiconductor memory devices is indicated by an arrow in the figure.

【0015】図7は、3次元半導体メモリ装置9の外部
接続端子として、半田バンプ10を装置底部の電極上に
形成した様子を示す。バンプ状外部端子は、リード状端
子に比べ、高密度に多数の端子を設けられること、半田
のセルフアラインメント機能により半田バンプ10の接
続歩留まりもリード状端子に比べ10倍以上良好である
等の利点を有している。尚、半田バンプ10は、他の形
状の接続端子、例えばクリップ状の端子あるいはろう付
した柱状のピンタイプの端子でも代替できる。
FIG. 7 shows a state in which solder bumps 10 are formed on electrodes at the bottom of the three-dimensional semiconductor memory device 9 as external connection terminals. The bump-shaped external terminal has the advantage that a large number of terminals can be provided at a higher density than the lead-shaped terminal, and the connection yield of the solder bump 10 is at least 10 times better than the lead-shaped terminal due to the self-alignment function of the solder. have. The solder bumps 10 can be replaced with connection terminals of other shapes, for example, clip-shaped terminals or brazed pillar-shaped pin-type terminals.

【0016】図8は、外部端子である半田バンプ10を
具備した複数の3次元半導体メモリ装置9を、メモリモ
ジュール基板11に実装した3次元メモリモジュール1
2を示す。このようにして構成された3次元メモリモジ
ュールは、通常のSIMMあるいはDIMMモジュール
に比べ倍以上のメモリ容量を容易に実現できることは明
らかであろう。
FIG. 8 shows a three-dimensional memory module 1 in which a plurality of three-dimensional semiconductor memory devices 9 having solder bumps 10 as external terminals are mounted on a memory module substrate 11.
2 is shown. It will be apparent that the three-dimensional memory module thus configured can easily realize a memory capacity twice or more that of a normal SIMM or DIMM module.

【0017】本実施の形態では、半導体メモリデバイス
を2段にスタックした場合を例にとり説明したが、さら
に多段にスタッキングしてメモリ容量を増やすことは容
易であることはいうまでもない。また半導体メモリ装置
6は、本実施の形態ではケースに封止された半導体デバ
イスの場合を示したが、ベア状の半導体デバイスをフリ
ップチップ接続して構成する半導体メモリ装置6でも本
発明の効果は何ら変わらないことは明らかである。
In this embodiment, the case where semiconductor memory devices are stacked in two stages has been described as an example. However, it goes without saying that it is easy to increase the memory capacity by stacking in more stages. Although the semiconductor memory device 6 is a semiconductor device sealed in a case in the present embodiment, the effect of the present invention is also achieved in a semiconductor memory device 6 configured by flip-chip connection of a bare semiconductor device. It is clear that nothing has changed.

【0018】[0018]

【発明の効果】以上説明したように本願発明は、以下に
記載するような効果がある。 (1)複数の半導体メモリデバイスを異方導電フィルム
付き導電スペーサを介して一括して一体的に接続するた
め製造工程が少なくTATが早い効果がある。 (2)導電スペーサの外形形状において、その内側が中
空状であることによって、半導体メモリデバイスをZ軸
方向に隙間無く積層でき、高密度化が図れる効果があ
る。 (3)また加熱、加圧等の製造条件が比較的ゆるく、又
製造工程も少ないので歩留まりが良好で、そのため低コ
ストのメモリモジュールを容易に実現できる効果があ
る。 (4)ベア状のメモリチップばかりでなく、市販のケー
スに封止された半導体メモリデバイスに対して本発明を
容易に適用できるため、KGDにかかわる歩留まり不良
によるコストアップ問題を回避できる効果がある。 (5)一般的なSIMM(single in memory module )
またはDIMM(doublein memory module )タイプの
メモリモジュールにくらべメモリチップを立体的に積層
するため、容易に大容量のメモリモジュールを実現でき
る効果がある。 (6)高密度実装によってメモリドライブパワーを小さ
くすることができ、消費電力を削減する効果がある。
As described above, the present invention has the following effects. (1) Since a plurality of semiconductor memory devices are collectively and integrally connected via a conductive spacer with an anisotropic conductive film, the number of manufacturing steps is small and the TAT is fast. (2) In the outer shape of the conductive spacer, since the inside is hollow, the semiconductor memory devices can be stacked without any gap in the Z-axis direction, and there is an effect that the density can be increased. (3) In addition, the manufacturing conditions such as heating and pressurizing are relatively loose, and the number of manufacturing steps is small, so that the yield is good, so that a low-cost memory module can be easily realized. (4) Since the present invention can be easily applied not only to a bare memory chip but also to a semiconductor memory device sealed in a commercially available case, there is an effect of avoiding a cost increase problem due to poor yield related to KGD. . (5) General SIMM (single in memory module)
Alternatively, since memory chips are three-dimensionally stacked as compared with a DIMM (double in memory module) type memory module, there is an effect that a large capacity memory module can be easily realized. (6) The memory drive power can be reduced by high-density mounting, which has the effect of reducing power consumption.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一構成要素である異方導電フィルムの
斜視図である。
FIG. 1 is a perspective view of an anisotropic conductive film which is one component of the present invention.

【図2】本発明の一構成要素である導電性スペーサの斜
視図である。
FIG. 2 is a perspective view of a conductive spacer which is one component of the present invention.

【図3】本発明の一構成要素である異方導電フィルム付
き導電スペーサ構造体の縦断面図である。
FIG. 3 is a longitudinal sectional view of a conductive spacer structure with an anisotropic conductive film which is one component of the present invention.

【図4】本発明の一構成要素である半導体メモリ装置の
縦断面図である。
FIG. 4 is a longitudinal sectional view of a semiconductor memory device which is one component of the present invention.

【図5】本発明の一構成要素である3次元半導体メモリ
装置の形成過程の説明図である。
FIG. 5 is an explanatory diagram of a process of forming a three-dimensional semiconductor memory device which is one component of the present invention.

【図6】本発明の一構成要素である3次元半導体メモリ
装置の縦断面図である。
FIG. 6 is a longitudinal sectional view of a three-dimensional semiconductor memory device which is one component of the present invention.

【図7】本発明の一構成要素である3次元半導体メモリ
装置の外部接続端子形成過程の説明図である。
FIG. 7 is an explanatory diagram of a process of forming external connection terminals of a three-dimensional semiconductor memory device which is a component of the present invention.

【図8】本発明の3次元メモリモジュールの縦断面図で
ある。
FIG. 8 is a longitudinal sectional view of the three-dimensional memory module of the present invention.

【符号の説明】[Explanation of symbols]

1 異方導電フィルム 2 導電性スペーサ 3 異方導電フィルム付き導電スペーサ構造体 4 半導体メモリデバイス 5 シングル基板 6 半導体メモリ装置 7 外部電極A 8 外部電極B 9 3次元半導体メモリ装置 10 半田バンプ 11 メモリモジュール基板 12 3次元メモリモジュール 101 導電性粒子 201 電極 202 スルーホール 401 スルーホール 601 導通部 Reference Signs List 1 anisotropic conductive film 2 conductive spacer 3 conductive spacer structure with anisotropic conductive film 4 semiconductor memory device 5 single substrate 6 semiconductor memory device 7 external electrode A 8 external electrode B 9 three-dimensional semiconductor memory device 10 solder bump 11 memory module Substrate 12 Three-dimensional memory module 101 Conductive particles 201 Electrode 202 Through hole 401 Through hole 601 Conducting part

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 異方導電フィルム(1)と、内側が中空
の基板の表裏両面にそれぞれ互いに電気的に接続された
電極の対が複数個設けられた導電性スペーサ(2)とを
備え、 前記異方導電フィルム(1)が前記導電性スペーサ
(2)の表面と裏面の電極にそれぞれ接着されてなる異
方導電フィルム付きの導電スペーサ構造体(3)と、 ケースに封止された単一の半導体メモリデバイスを基板
の片面に実装した半導体メモリ装置(6)と、からな
り、前記導電スペーサ構造体(3)が2個の前記半導体
メモリ装置(6)の間に介装され、加圧、加熱されて前
記半導体メモリ装置(6)が電気的に接続された3次元
半導体メモリ装置(9)であって、 前記3次元メモリ装置(9)が、その底面に形成された
複数の接続端子を介してメモリモジュール基板(11)
上に実装されてなることを特徴とする3次元メモリモジ
ュール。
An anisotropic conductive film (1), and a conductive spacer (2) provided with a plurality of pairs of electrodes electrically connected to each other on both sides of a substrate having a hollow inside, A conductive spacer structure (3) with an anisotropic conductive film formed by bonding the anisotropic conductive film (1) to electrodes on the front and back surfaces of the conductive spacer (2); A semiconductor memory device (6) in which one semiconductor memory device is mounted on one surface of a substrate, wherein the conductive spacer structure (3) is interposed between the two semiconductor memory devices (6). A three-dimensional semiconductor memory device (9) electrically connected to said semiconductor memory device (6) by pressure and heating, wherein said three-dimensional memory device (9) has a plurality of connections formed on a bottom surface thereof; Memory module via terminal Board (11)
A three-dimensional memory module characterized by being mounted thereon.
【請求項2】 ケースに封止された単一の半導体メモリ
デバイスを基板の両面に実装した半導体メモリ装置から
なることを特徴とする請求項1記載の3次元メモリモジ
ュール。
2. The three-dimensional memory module according to claim 1, comprising a semiconductor memory device in which a single semiconductor memory device sealed in a case is mounted on both sides of a substrate.
【請求項3】 ベア状の単一の半導体メモリデバイスを
基板に実装した半導体メモリ装置からなることを特徴と
する請求項1記載の3次元メモリモジュール。
3. The three-dimensional memory module according to claim 1, comprising a semiconductor memory device in which a single bare semiconductor memory device is mounted on a substrate.
【請求項4】 請求項1記載の3次元メモリ装置を複数
個立体的に積層してなることを特徴とする3次元メモリ
モジュール。
4. A three-dimensional memory module comprising a plurality of the three-dimensional memory devices according to claim 1 stacked three-dimensionally.
【請求項5】 内側が中空の基板の両面に互いに電気的
に接続されて対をなす電極が複数個配置された導電性ス
ペーサの両面に、異方導電フィルムを前記電極に当接さ
せて配置する、異方導電フィルム付きの導電スペーサ構
造体を形成する工程と、 前記導電スペーサ構造体の両面に、複数の外部電極の対
を有し、ケースに封止された単一の半導体メモリ装置
を、前記導電スペーサの電極と前記外部電極が、前記異
方導電フィルムを介して対向するように配置する工程
と、 前記導電スペーサ構造体と、これを挟んで配置された前
記半導体メモリ装置を加熱し、かつ、これら半導体装置
の外側から対向する方向に加圧して半導体装置を互いに
電気的に接続する工程とからなることを特徴とする3次
元半導体メモリ装置の製造方法。
5. An anisotropic conductive film is disposed on both sides of a conductive spacer in which a plurality of pairs of electrodes are electrically connected to each other on both sides of a hollow substrate and disposed on both sides of the substrate. Forming a conductive spacer structure with an anisotropic conductive film; and forming a single semiconductor memory device having a plurality of external electrode pairs on both surfaces of the conductive spacer structure and sealed in a case. Arranging the electrode of the conductive spacer and the external electrode so as to face each other with the anisotropic conductive film interposed therebetween; heating the conductive spacer structure and the semiconductor memory device interposed therebetween; And a step of electrically connecting the semiconductor devices to each other by applying pressure in a direction facing each other from the outside of the semiconductor devices.
JP9269041A 1997-10-01 1997-10-01 3D memory module Expired - Fee Related JP2870528B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9269041A JP2870528B1 (en) 1997-10-01 1997-10-01 3D memory module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9269041A JP2870528B1 (en) 1997-10-01 1997-10-01 3D memory module

Publications (2)

Publication Number Publication Date
JP2870528B1 JP2870528B1 (en) 1999-03-17
JPH11111914A true JPH11111914A (en) 1999-04-23

Family

ID=17466859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9269041A Expired - Fee Related JP2870528B1 (en) 1997-10-01 1997-10-01 3D memory module

Country Status (1)

Country Link
JP (1) JP2870528B1 (en)

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