JPH02198148A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device with a higher mounting density by a method wherein a connector on which a wiring pattern is formed is provided at the position of an outer lead formed by a tape automated bonding(TAB) method and a plurality of semiconductor chips are piled. CONSTITUTION:The connector 9a of a semiconductor chip 15a with a connector on a lowest stage is formed on a substrate 20 made of glass epoxy and having a rear pattern 11a and electrically connected to a wiring pattern 19 formed by Cu-Sn plating or the like with solder through a third connection layer 18. A semiconductor chip 15 with a connector on a second lowest stage is electrically connected to the semiconductor chip 15a with the connector with solder or the like through a second connection layer 14b. By piling and mounting a plurality of film-carriered semiconductor chips like this, a memory capacity which is a result of multiplying the capacity of each chip by the number of chips can be easily obtained with the conventional mounting area. With this constitution, a high density mounting type package can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of a semiconductor device and its manufacturing method, and in particular to the structure of a semiconductor device and its manufacturing method. The present invention relates to a large-capacity multi-chip semiconductor device having a large-capacity multi-chip semiconductor device.

[Prior art]

Semiconductor memory is widely used in information equipment such as large computers, workstations, personal computers, word processors, and facsimile machines.As the performance of these devices continues to improve and the number of products expanded in the future, the semiconductor memory used in these devices will continue to grow. Demand is expected to increase at an accelerating pace.

In contrast, the mounting area occupied by semiconductor memory inside devices that require large-capacity memory is increasing.
This is the biggest factor preventing devices from becoming smaller and lighter. In order to solve this problem, conventional approaches have been to increase the memory capacity per chip by increasing the integration of elements within a chip, mounting packaged semiconductor modules at high density on printed wiring boards, and increasing It has been attempted to increase the density by stacking chips in the thickness direction.

Among these, high-density mounting on printed circuit boards is mainly performed using TAB (a semiconductor device in which a semiconductor chip is connected to the leads of a tape carrier using the tape automated bonding method), which is one of the mounting type semiconductor devices. This is done by arranging a plurality of TABs and connecting the leads of each TAB to the signal wiring on the printed circuit board. Furthermore, methods for stacking a plurality of semiconductor chips in the thickness direction include directly connecting the outer lead portion of each single module to a printed circuit board.

In addition, documents related to these technologies include Japanese Patent Application Laid-Open No. 1986-
194460. JP-A-61-101067° JP-A-62
-195138 is mentioned.

[Problem to be solved by the invention]

As a result of studying the above-mentioned mounting technology, the inventor found the following problems.

First of all, the high integration of on-chip elements has reached a new situation that cannot be solved by extending conventional technology, and requires the development of new technology and production equipment.

Next, in high-density mounting on a printed circuit board, the TABs are mounted one by one on the board, so this TAB
Although AB itself has the advantage of being much smaller and thinner than a semiconductor device in which a semiconductor chip is sealed in a package, there is a problem in that the mounting area becomes large.

Furthermore, in the method of stacking multiple semiconductor chips in the thickness direction, conventionally there is a method of directly connecting each actor lead part of a single module to the mounting board, and a method of connecting each actor lead part of a single module directly to the mounting board, This method used a frame body with wiring formed in accordance with the above. However, there are problems in that the external dimensions become large or the manufacturing process becomes complicated.

An object of the present invention is to provide a semiconductor device with high packaging density.

Another object of the present invention is to provide a package structure that has multiple times the memory capacity for the same mounting area as a conventional package.

A further object of the invention is to obtain the above-mentioned package structure with a simple manufacturing process.

A further object of the present invention is to provide a memory module that can compactly mount a large number of semiconductor chips.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief summary of the invention disclosed in this application to achieve the above object is as follows.

First, the first method is to stack multiple semiconductor chips by interposing a connector with a wiring pattern at the actor lead position of a TAB formed by the conventional TAB (tape automated bonding) method. , it is possible to obtain a semiconductor device having a memory capacity several times larger than that of a conventional TAB. That is, in a plurality of stacked semiconductor chips, terminals that can share signals are stacked so that they are respectively connected using the wiring pattern of the connector. Since the chip selection terminals that cannot be used in common must supply or take out signals to each semiconductor chip separately, the wiring pattern of the connector that corresponds to the chip selection terminal that cannot be used in common is required. Only the seals are different from each other.
Form it so that it does not hit. By doing so, the signal is supplied to all the common terminals of the plurality of semiconductor chips by supplying the signal - times. Then, when a signal is supplied to one chip selection terminal, one of the multiple semiconductor chips is selected.
Only one chip can be selected and used.

Next, the second method is to omit the TAB assembly process,
A connector with a lead configured to achieve the above-mentioned purpose is used. That is, in the first method, instead of the wiring pattern, leads with the same function are formed directly on the connector, and a semiconductor chip on which bank electrodes, which are conventionally used for TAB, are formed is connected to create a TAB with connector. is formed.

Furthermore, as a third method, a square hole is further provided outside the device hole in the conventional TAB method, and a bent base material is set under the actor lead outside the square hole. and,
The lead portion located above the square hole is bent, and the frame base material between the device hole and the square hole and the bent base material are made to face each other and fixed with an adhesive. The frame base material and the folded base material have the same function as the connector described above.

As with the connectors described above, the lead portion includes leads connected to common terminals and leads connected to selection terminals corresponding to each stacked layer.

The above method will be explained using an example in which four 1M bit DRAMs (dynamic random access memories) are stacked. The DRAM has a data input/output terminal, a write enable (WE) terminal, an address terminal, and a CAS
The (column address strobe) terminal corresponds to the above-mentioned common terminal, and the RAS (row address strobe) terminal corresponds to the chip selection terminal. And 8 yen
When selecting, for example, the lowest stage of the layered semiconductor chips, the common terminals are connected by the wiring pattern of the connector, so a signal is supplied to each stage with one signal supply. At the same time, a signal is supplied to the wiring pattern on the board connected to the bottom 1 (As terminal).

The wiring patterns of the connector that lead to the chip selection terminals are formed so that they do not overlap with each other, so unlike the case of common terminals, one signal supply can send signals to terminals on another stage. will not be supplied.

[Effect]

According to the first method described above, since a signal is supplied to one chip selection terminal and a signal is supplied to common terminals at once, the signal supply system is the same as when one conventional TAB is mounted. That means it's good. And in this application, multiple TAB! Since it has an R layer, it is possible to obtain multiple times the memory capacity. Furthermore, the connector is TA
Since it is approximately the same size as B, in other words, it is possible to easily obtain a memory capacity that is an even number times that of stacked chips with a conventional mounting area.

Furthermore, since the lead end of a part of the connector of the TAB with a connector according to the second method is configured in the same way as the wiring pattern section of the first method, a plurality of TABs can be stacked,
The purpose of easily obtaining an even number times the memory capacity of the stacked layers can be achieved.

Further, the TAB with frame base material formed by the third method can obtain the same effects as the above-mentioned first method.

In particular, in the present invention, the memory capacity can be increased by an even number of stacked chips by increasing the mounting area and package thickness of the conventional TAB and the same or slightly thicker.

Furthermore, a package suitable for high-density packaging can be obtained.

Furthermore, since the chip is mounted on the leaded connector, T
The AB assembly process can be omitted.

Furthermore, the manufacturing process using a film carrier tape in the conventional TAB method can be applied, and the memory module device of the present invention can be obtained with a simple process.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

In this application, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

(Example ■) Hereinafter, Example I of the present invention will be described using FIGS. 1 to 44.

First, in FIGS. 1 to 3, a semiconductor chip 1a formed by forming a desired circuit on the main surface of a silicon single crystal substrate is provided with bump electrodes 7a functioning as external terminals. The film carrier tape 2a made of glass epoxy is plated with Cu-8n, Cu
-Solder plating or Cu-Ni/Au
Lead patterns 3a and 4a made of plating are formed, and the gold bumps 7a are electrically connected to the inner lead portions 5a of the lead patterns 3a. The outer lead portion 6a extends to the outside of the semiconductor chip 1a.

As seen in FIGS. 1 and 2, the T A of the present invention
In B, a dummy lead pattern 4a is formed that is not electrically connected to the bumps 7a on the chip.

The upper surface of the semiconductor chip 1a and the side portions of the semiconductor chip 1a including the inner lead portions 5a are coated with resin 8a for protecting the chip and the connecting portions. For example, epoxy resin is used as the resin 8a as the coating material.

Figures 4 and 5 show TABs from Figures 1 to 3.
This connector 9a is inserted between the individual TABs when stacking the TABs. This connector 98 is made of rectangular glass epoxy resin or ceramic, and has a hole in the center for mounting a semiconductor chip. Further, this connector 9a has a front surface pattern 10a formed on its main surface and a back surface pattern lla formed on the opposite surface, and these Cu plated, Cu
Both patterns, which are conductors made of -N i /Au plating, Cu-solder plating, or Cu-8n plating, are electrically connected by a through hole 12a. Furthermore, the corner portion of the connector 93 is provided with an alignment pattern 13a made of a copper pattern.

In the case of a ceramic connector, a pattern made of Mo-Ni/Au plating or W-Ni/Au plating is formed.

6 and 7 show a semiconductor device 15a with a connector for configuring the present invention.

This is a connector 98 shown in FIG. 4 in which the resin-attached TAB shown in FIG. 2 is mounted. The surface pattern 10a of the connector 9a and the outer lead portion 6a are electrically connected by a first connection layer 14a.

FIG. 8 shows an example of the connector 9a, with alignment holes 16a
are formed by penetrating the surface pattern 10a, and are provided at two diagonal positions of the connector 93.

Figure 9 shows a T for mounting on the connector 9a in Figure 8.
In a part of AB, an alignment pattern 17a is provided on the lead pattern 3a.

FIG. 10 shows another example of the connector 93.

Adjacent through holes 12a for connecting the front pattern 10a and the back pattern are formed in a staggered manner. By doing this, the front surface pattern 10a and the back surface pattern lla of the connector 93 are
Each pattern pitch can be narrowed, and the connector can be made smaller.

The film carrier tape 2a used in the present invention is composed of, for example, a polyimide resin film or a glass epoxy material, which is slit to an appropriate width.

The lead pattern 3a can be formed by laminating, for example, copper foil on the film carrier tape and using well-known photoresist technology or etching technology.

The semiconductor chip 1a is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide desired circuit functions.

The bumps 7a are made of gold (Au) pandas, for example.

The resin 8a is mainly made of, for example, a liquid epoxy resin, and is formed by a botting method.

FIGS. 11 to 33 show examples in which a multichip semiconductor device and a multichip semiconductor module are formed using the semiconductor device with a connector.

FIG. 11 (bl represents an example of the bin arrangement using the semiconductor module of FIG. 11 (al) and the corresponding bin functions, and FIG. 11 (C) represents the semiconductor module of FIG. 11 (al). Fig. 12 shows another example of bin arrangement using modules and their corresponding bin functions.

FIG. 14 is an enlarged cross-sectional view of the connecting portions of the semiconductor devices with connectors in the first and second stages from the bottom when the multi-chip semiconductor device of FIG. 12 is mounted on a board. Referring to FIG. 14, the configuration of a multi-chip semiconductor device 23 according to the present invention will be explained.

In FIG. 11, when using IM's D B and AM semiconductor chips, four of the above-mentioned semiconductor devices with connectors 153 to 15d are stacked on a substrate 20 made of glass epoxy material or ceramic on which a wiring pattern 19 is formed. As a whole, a semiconductor module 25 having a capacity of 4M and used particularly for memory is constituted. The board 20 is configured to take out each signal of the semiconductor device with a connector by means of lead-out leads 22 drawn out like, for example, a zigzag in-line package (ZIP).

In FIGS. 12 and 14, the back surface pattern lla of the connector 9a of the connector-equipped semiconductor device 15a at the bottom
Cu is formed on a substrate 20 made of glass epoxy.
-Ni/Au plating, Cu-solder plating, or C
The wiring pattern 19 made of U-8N plating is electrically connected to the third connection layer 18 using solder.

The semiconductor device 15b with a connector in the second tier from the bottom and the semiconductor device 15a with a connector in the bottom tier are electrically connected by a second connection layer 14b using solder or the like. Here, in the case of a ceramic substrate, Ag-Pd paste,
Alternatively, a conductor made of W, Mo-Ni/Au plating is formed.

The semiconductor devices with connectors 15b, 15c, and 15d in the second, third, and fourth tiers stacked from the bottom are the semiconductor devices with connectors 15a (that is, the 12th tier) shown in FIGS. The configuration is the same as that of the semiconductor device with a connector f) at the bottom of the figure, and the semiconductor device with a connector at the bottom in each figure has an "a" after the symbol as described above, and a second
The first row is marked with rbJ, the third row is marked with "C", and the fourth row is marked with rdJ.

Further, in the semiconductor module 25 of this embodiment, a capacitor chip 21 having a function of reducing power supply noise and functioning as a filter is attached on the substrate 20 thereof.

An example (application example 1) using the multi-chip semiconductor device of the present invention will be described with reference to the semiconductor modules of FIGS. 11 to 14, FIGS. 15, 16, and FIG. 11(b).

Figures 15, 16, and 11 (In the semiconductor module 25 with the bl bin arrangement, this constitutes 4MX1 input/output using four IMX1 semiconductor chips)
RAM (Dynamic Random Access Memory) is a 4M memory module in total. Here, RAS (row address strobe) selects a word line, and CAS (column address strobe) selects a column decoder. AO to A9 are address input bins, and WE is a write enable bin. Vcc
.

Vss is a power supply terminal in a broad sense, particularly Vcc is called a power supply voltage terminal, and Vss is called a reference voltage terminal. Din.

Dout is a data input and output terminal.

FIG. 15 is an overall circuit block diagram of the semiconductor module 25 shown in FIG. 11 (BL bin arrangement) described above.

The functions shown in the figure are the same as those described above, and will therefore be omitted.

FIG. 16 shows the RAS of a semiconductor module 25 having a capacity of 4M by stacking semiconductor devices 15a to 15d with connectors.
FIG. 3 is a perspective view showing details of the terminal portion. In the semiconductor devices with connectors 158 to 15d in the same figure, those with the same functions are given the same reference numerals, and as described above, after the reference numerals are raJ to rdJ.
Display with .

FIG. 15 is an example (application example 1) using Example I. Each chip (R, AMO~3) has the capacity of IM, CAS terminal 30, data input terminal (Din) 26
, data output terminal (Dout) 27, WE terminal 28,
Address terminal 29 power supply terminal (Vcc.

Vss) is used in common.

Storage of information (data input) to the semiconductor memory chip and reading of the stored information (data output) are performed in units of addresses set within the chip. Writing information to a certain address requires an address signal specifying the address, a write enable signal permitting writing, and a data signal containing the data to be stored.

First, in FIG. 15, when writing data, a signal specifying the address is sent to the address terminal 29, a data signal to be written to the data input terminal 26, a Low signal to the WE (write enable) terminal 28, and a RAS terminal 31.
By applying a signal to the CAS terminal 30, data is written to the designated address of each chip. When reading data, a signal specifying the address is sent to the address terminal 29, a High signal is sent to the WE terminal 28,
By applying signals to the RAS terminal 31 and the CA8 terminal 30, the data at the specified address is transferred to the data output terminal 2.
Output from 7.

Next, the above operation will be explained using FIGS. 11 to 16.

In FIG. 16, semiconductor devices with connectors 15a to 15
Common terminal pads 43a to 43d and RAS terminal pads 42a to 42d are provided on the upper surfaces of the semiconductor chips 13 to 1d.
(denoted as RASO, RA81, RA82°RAS3) are formed. Moreover, the semiconductor chips 1a~
1d and the corresponding connectors 9a to 9d, common lead wires 458 to 45d are connected to the common terminal pads 43a to 43d, and RAS terminal lead wires are connected to the RAS terminal pads 42a to 42d. 44a to 44d are formed. Furthermore, dummy leads 4a are formed that are not electrically connected to the semiconductor chips 1a to 1d.

Next, in the connectors 9a to 9d, a common terminal pattern 40a is provided on the surface of the connector 9a to connect to the common lead wire 45a and to establish continuity between the upper and lower connectors.
, RAS terminal pattern 35a connected to RAS terminal lead wire 44a; third RAS dedicated pattern 32a connected to dummy lead 4a for filling the gap between connectors;

A pattern 34a is formed. Here, the common terminals are an address terminal, a W1 terminal, and a data input.

These are output terminals (Din, Dout) and power supply terminals.

Further, on the back side of the connector 9a, there is a third pattern on the back side at a position opposite to the third to first RAS exclusive patterns 32a to 34a.
~The first RAS dedicated butter y36a to 38a, the back side As terminal pattern 39a at the position opposite to the RAS terminal pattern 35a, and the back side common terminal hole (turn 41a is the through hole 12a) at the position opposite to the common terminal pattern 40a. are electrically connected.

Next, in addition to the above-mentioned patterns, a connection pattern 46b for connecting the RAS terminal pattern/35b and the first RAS exclusive pattern 34b is formed on the surface of the connector 9b. A back surface connection pattern 47b is formed on the back surface of the connector 9b at the position of the back surface RAS terminal pattern 39a of the connector 9a, and the RAS terminal pattern 35b and the back surface connection pattern 47b are insulated.

Furthermore, the surface of the connector 90 has a RAS terminal pattern 35C and a second RAS terminal pattern in addition to the pattern described for the connector 9a.
A connection pattern 46c for connecting the AS pattern 33C is formed, and a surface dummy pattern 48c is further formed at the position of the first RAS pattern 34a.

On the back surface of the connector 90, a back surface connection pattern 47C is formed at the position of the back surface RAS terminal pattern 39a and the back surface first RAs exclusive pattern 38a of the connector 9a.

Furthermore, the surface of the connector 9d has a RAS terminal pattern 35d and a third R in addition to the pattern described for the connector 9a.
A connection pattern 46d for connecting the As exclusive pattern 32d, and the first . 2nd RAS exclusive putter y34a,
A surface dummy pattern 48d is formed at the position 33a. On the back side of the connector 9d, the connector 9
The back surface RAS terminal pattern 39a and the back surface cylinder 1.a. 2nd R
A back surface connection pattern 47d is formed at the position of the AS exclusive pattern 38a r 39a.

Here, the As terminal patterns 35C, 35d, the front side dummy patterns 48C, 48d, and the back side connection pattern 47c.
, 47d.

The semiconductor module 25 shown in FIGS. 11 to 14 is
A signal is supplied from the outside to the wiring pattern 19 formed on the substrate 20, and the third connection layer 18. Back pattern 11a of connector 9a, through hole 12a9 surface pattern 10
a. Through the first connection layer 14a, the outer lead part 6a,
It passes through the inner lead portion 5a and the bump 7a and is supplied to the elements in the first stage semiconductor chip la. Similarly, the second stage semiconductor chip 1b, the third stage semiconductor chip lc,
The signal is also supplied to the fourth stage semiconductor chip 1d at the same time.

To explain using FIG. 15, taking as an example the operation of writing certain data to a specific address of the semiconductor chip 1a, a signal indicating a "specific address" is sent to the address terminal 29, and a signal for writing is sent to the data input terminal 26. A data signal is applied to the WE (write enable) terminal 28, and a write enable signal is applied to the RAS terminal (
By sending signals to the RASO) 31a and the CAS terminal 30, the address signal, data signal, write enable signal, and CAS signal are made valid only for the semiconductor chip 1a among the four semiconductor chips 1a to 1d, and are valid for the other semiconductor chips 1.
It does not act on b to 1d. That is, the semiconductor chip 1a
Necessary data is written to a specific address, but the other 3
The specific addresses of the unselected semiconductor chips will not change.

For reading data, a read permission signal is applied to the WE terminal 28, and the data stored at a specific address on the semiconductor chip 1a is output to the data output terminal 27 with the other connections being the same as for writing.

In this way, when increasing memory capacity by multiplexing two or more chips, instead of providing a terminal for selecting a chip independently for each chip, all other terminals can be used in common.

Next, the operation shown in FIG. 15 described above will be explained using FIG. 16.

The signal supply path is as described above, and the 16th
In the figure, the common signal terminal, that is, CA in FIG.
S terminal 30. Data input terminal 26゜Data output terminal 27
．． WE terminal 28. Address terminal 29. Vcc and Vss are common terminal pads 43a to 43d and common lead wire 45.
Corresponds to a to 45d. In addition, the RAS terminal 31a (RA
SO) corresponds to the As terminal pad 42a and the As terminal lead wire 44a; the remaining LA8 terminal 31b.

31c, 31d(I(, ASI, RAS2.RAS3)
Also, each of the W terminal pads 42b to 42d and the RAS terminal lease #j! 44b to 44d.

That is, as shown in FIG. 16, the signal supplied to the common terminal is transmitted from the wiring pattern 19 of the board 2o to the back common terminal pattern 41a of the connector 9a.

Through hole 12a, common terminal pattern 40a.

The first stage semiconductor chip 1a passes through the common lead wire 45a.
and then a common lead from the back common terminal pattern 41b of the second stage connector 9b! It is supplied to the semiconductor chip 1b via s45b.

Similarly, each chip is fed a signal simultaneously.

On the other hand, the signal supplied to the As terminal is first
In the case of the RAS terminal pad 42a in the third row, the connector 9a
The back side RAS terminal pattern 39a.

Through yjt-h12a, a signal is supplied through the RAS terminal terminal-turf 38° RASAs terminal lead wire 44a, but the RAS terminal pattern 35b of the second stage connector 9b and the RAS terminal pattern 35a- are electrically Since the semiconductor chip 1b is not connected to the first
The signal supplied to the RAS terminal pad 42a in the third row is desired to be supplied.

Similarly, the second stage As terminal pad 42b is connected to the first As terminal pad 42b on the back side via the first RAS exclusive pattern 38a, the through hole 12a, and the first As exclusive pattern 34a.
Dedicated pattern 38b, through hole 12b, first RAS
Dedicated pattern 34b.

Connection pattern 46b, RAS terminal pattern 35b.

A signal is supplied via the RAS terminal lead wire 44b. Also in this case, the first and third row RAS terminal patterns 35a and 35C are not electrically connected to the second row RAS terminal pattern 35b.

That is, the third and fourth tier chips are similarly patterned so that the KRAS terminals are not connected to each other. In this way, the As terminals are formed electrically independently for each chip.

Third and fourth stage surface dummy patterns 48c to 48
d is not connected to any terminal. 500 is RA8
3 shows an example of a signal path supplied to No. 3.

The connector and substrate used in this embodiment I are made of, for example, glass epoxy material or ceramic.

Furthermore, the pattern formed on the connector is coated with copper plating, solder plating, Ni plating, A u plating, etc.
It is formed by processing such as plating.

The inner walls of the through holes are also formed by copper plating and the same treatment as the pattern described above.

This electrically connects the front surface pattern and the back surface pattern.

Here, the connections between each connector and between the board and the connector are made, for example, by solder (Pb-8n type). In particular, high melting point solder (90Pb) is used between each connector.
108n, approximately 300°C), and low melting point solder (40Pb-608n, approximately 180°C) between the board and connector.
) is used. However, it is not particularly limited to solder, and may include a brazing material whose main component is gold-tin (Au-Sn).

Connections can also be made using gold adhesion, conductive paste (for example, Ag paste), or the like.

By using the connector of Application Example 1 of Example I, it is possible to obtain a package structure having four times the memory capacity as a conventional package with the same mounting area. That is,
The connector of Application Example 1 has a structure that allows you to select a specific semiconductor chip among four semiconductor chips and send a specific signal only to the selected semiconductor chip.Moreover, since it is stacked, the mounting area is small. You can get four times the memory capacity with the same amount. Furthermore, the layout of each chip,
Only the front and back patterns of the connector can be changed to the first pattern without changing the pad arrangement or lead arrangement on the film carrier.
The memory module of the present invention can be obtained simply by forming the memory module to correspond to each of the 4th to 4th tiers. Furthermore, by providing dummy leads, it is possible to prevent gaps from forming between layers when stacking connectors.
Electrical connections between connectors can be reliably realized with high yield.

Furthermore, in this embodiment I, when semiconductor devices with connectors are stacked, the front and back patterns of the connectors are electrically connected through through holes. In this way, the front and back sides of the patterns that use connector through holes are connected, and the front and back sides of patterns that do not use through holes are insulated, so the common terminal can be used as is.
It is configured so that signals can be supplied by selecting only the terminals for selecting the chip. By doing so,
According to the present invention, chips are stacked and mounted at high density, and the stacked chips are individually used to provide more memory & fl.
The objective of obtaining a module with a large t can be achieved.

Next, regarding other application example 2 of Example I, FIGS. 11 to 14, Table 2. This will be explained using FIGS. 17 and 18.

The memory modules shown in FIGS. 17 and 18 have the same external shape as those shown in FIGS. 11 to 14, and the pin arrangement is as shown in Table 2. In this memory module 25, 4
DRAM that constitutes the input and output of MX1, totaling 4M
capacity memory module. RAS terminal 51
, CAS terminal 50°WE (write enable) terminal 52
．． Address terminal 53. Since the power supply terminals Vcc and Vss are the same as those in Application Example 1 described above, their explanation will be omitted.

In FIG. 17, each chip (RAMO to RA
M3) is a 1M capacity tC-1 CAS terminal 50° RAS terminal 51. WE terminal 52. Address terminal 53 and power supply terminal V
cc and Vss are used in common.

First, address terminal 53. RAS terminal 51° CAS terminal 50. At the same time as a signal is applied to the WE terminal 52, a data signal is applied only to the terminal to which data is written among the data input terminals 54a to 54d, and data is written independently to each chip (RAMO to RAM3). For data reading, only the terminal for data reading among the respective data output terminals 558 to 55d is activated, and data is read independently only from a predetermined chip.

In FIG. 18, data input/output terminal pads 56a to 56d on the surfaces of semiconductor chips 49a to 49d.

57a to 57d are RAS terminal pads 42a to 42 on the surfaces of semiconductor chips 13 to 1d in FIG. 16 of Application Example 1 described above.
Corresponds to d. In addition, the data manual output lead wire 59a
~59d, 60a ~60d are As terminal lead wires 44
a to 44d, common terminal pads 58a to 58d are connected to common terminal pads 43a to 43d, and common lead wires 61a to 61 are connected to common terminal pads 43a to 43d.
1b corresponds to common lead wires 458 to 45d. Furthermore, the connectors 62a to 62d have a pattern formed on their surfaces for quick fabrication with the same purpose as in Application Example 1 described above. That is, the common terminal pattern 631
~63d, data input/output cover turns 64a~64d,
65a to 65d1 Connection patterns 66b to 66d1 Data input/output dedicated patterns 67a to 67d, 68a to 68
d68d me putter 769c.

It is 69d. A pattern is similarly formed on the back side. That is, the back side common terminal patterns 708 to 70d, the back side input/output exclusive patterns 71a to 71d, 72a to 7
2d, back side connection putters 773b to 73d.

In this application example 2, the signal supply path is as described above. This is almost the same as Application Example 1, but in Application Example 1, the As terminals 31a to 31d were selected to select the chips for inputting and outputting data, whereas in Application Example 2, each chip 49
A signal for writing data to a to 49d (ie, RAM0 to RAM3) is supplied to each chip, and designated data can be read from each chip.

By using the connector of Application Example 2 of this embodiment,
As in Application Example 1, a package structure having four times the memory capacity as the conventional package can be obtained with the same mounting area. That is, the connector of Application Example 2 can supply signals to each of the four semiconductor chips, and can read data independently from each chip.

Furthermore, the semiconductor module of the present invention can be obtained by only changing the pattern related to data input/output of the connector without changing the pattern on the TAB side.

Next, modified examples of the semiconductor module package used in Application Examples 1 and 2 described above will be explained using FIGS. 19 to 23. The same functions are represented by the same symbols.

Fig. 19 is a sectional view of package modification 1, Fig. 20 is a top view of package modification 1, Fig. 21 is a sectional view of package modification 2, and Fig. 22 is package modification 3.
FIG. 23a) is a sectional view of package modification 4, FIG. 23 (bl is a sectional view of package modification 5,
FIG. 23 (C1 is a sectional view of package modification 6.

First, in FIGS. 19 to 22, the substrate 2 in FIG.
A multi-chip semiconductor device 86 is mounted on a board 82 having the same function as 0, and a chip capacitor 84 is mounted below the multi-chip semiconductor device 86 on the top or bottom surface of the board 82. Furthermore, the multi-chip semiconductor device 86 is covered with a lid member 81. A lead bin 83 for extracting signals is further attached to the substrate 82 to constitute a semiconductor module 80 having the same function as the semiconductor module 25 shown in FIG. 11.

In FIG. 19, the drawer lead bin 83 has the same shape as a so-called DIP (dual in-line package).

FIG. 20 is a top view of FIG. 19, in which, for example, four semiconductor modules 80 are mounted on the substrate 82.

However, the number of semiconductor modules 80 to be mounted is not limited to four, and may be one or more. Furthermore, the 21st
This figure and FIG. 22 are also plan views similar to FIG. 20.

FIG. 21 shows the shape of a gull-wing type lead-out lead of a surface-mount type package, and FIG. 22 shows the shape of a lead-out lead of a J-pend type package.

Next, FIGS. 23(a) to 23(C) show modified examples of the AA' cross section of the semiconductor module in FIG. 11. The multi-chip semiconductor device 86 is mounted on the substrate 82 via leads 85 and an adhesive 87 such as solder.

In the case of mounting the board in Fig. 23(a), the lead 85 has a pull-out lead shape of a so-called gull wing type package, and in the case of mounting the board in Fig. 23(bl), the lead 85 has the shape of a J-pend type package. The mounting lead 85 is in the form of a lead for a pad type package.Furthermore, a chip capacitor 84 is provided at a position below the multi-chip semiconductor device 86 on the upper or lower surface of the substrate 82.

In FIGS. 23(a) to 23(C), the connection between the multichip semiconductor device 86 and the substrate 82 can be mounted to a resilient board by using a lead 85, which allows thermal expansion of the multichip semiconductor device 86 and the substrate 82. Thermal stress caused by the rate difference can be alleviated, which has the effect of improving connection reliability.

Margin below Next, regarding other application example 3 of Example I, i@24
This will be explained with reference to FIGS.

First, in FIG. 24, a multi-chip semiconductor device [
92 is installed. The printed wiring board 91 has board alignment holes 97. A connector terminal 94 is provided. Further, eight multi-chip semiconductor devices 92 are mounted on a printed wiring board 91 to constitute a semiconductor module 95 of application example 3 of the present embodiment I.

The printed wiring board 91 is made of a resin substrate, for example, and can be made into various types depending on the combination K of the base material and bonding material used. As a base material, glass fiber 2
Paper 2 Synthetic fibers are exemplified, and binding materials include:
Examples include epoxy resin, phenol resin, and polyimide resin.

As the resin substrate, an epoxy resin substrate whose base material is glass fiber is preferable.

The formation of the wiring pattern 98 on the flint wiring board 91 is as follows:
This is done using conventional etching or photoresist techniques.

The multi-chip semiconductor device 92 in Application Example 3 is the same as that used in Application Examples 1 and 2 above, and the signal supply path, the stacking method of semiconductor devices with connectors 908 to 90d, and the configuration of connectors 93a to 93d are the same as those used in Application Examples 1 and 2 above. The same thing is used in .

27, 99a to 99h are the circuit blocks of the multi-chip semiconductor device 92 shown in FIG. 24, which are further combined with eight DRAMs (dynamic random access memories) shown in FIG. It is a memory mosier. This semiconductor module is used, for example, in a microcomputer.

In the figure, the WE (write enable) terminal.

Address terminals, data input/output terminals (DQI-8), and power supply terminals (Vcc, Vss) are common terminals.

When the CAS terminal is used as a common terminal, the RAS terminal is used as a terminal for selecting a chip (for example, RAMII-14). On the contrary, when the RAS terminal is used as a common terminal, the CAS terminal is used as a terminal for selecting a chip.

Here, a case where the above-mentioned CA8 terminal is used as a terminal for selecting a chip will be described as an example.

That is, in the semiconductor module of FIG. 27, a signal is applied to the KRAS terminal 100a almost at the same time as signals are applied to the address terminal, WE (write enable) terminal, data input/output terminals (DQ1 to DQ8), and the As terminal. When applied, the chips sharing the signal of the RAS terminal 100a, namely AM11. RAM21. RAM31.
RAM41゜几AM51, RAM61, RAM71
, a signal is supplied to the RAM81. LOW at WE terminal
When a signal is applied, the data input (Din) becomes Hi.
When the gh signal is applied, data output (Dout) is performed.

Furthermore, although this application example 3 shows an example in which the multi-chip semiconductor device 92 is mounted on one side of the printed wiring board 91, it may be mounted on both sides of the board. In this case as well, it is formed in a busy manner as in the case of single-sided mounting.

Furthermore, when mounted on both sides, a semiconductor module with even higher integration and density can be obtained.

Next, another application example 4 of Example I will be explained using FIGS. 28 to 33.

Here, FIG. 33 is a perspective view showing details of each C8 (chip select) terminal portion of the fourth application example.

First, in FIGS. 28 to 30, a multi-chip semiconductor device similar to the multi-chip semiconductor device described in FIGS.
102, and a semiconductor module 105 equipped with a decoder IC 104.

The above multi-chip semiconductor device [102 is 1M bit/S
It consists of four stacked semiconductor devices with connectors 106a to 106d each having a RAM (static random access memory) MOS type or bipolar MO8 type circuit chip mounted on connectors 1032 to 103d.

In FIG. 31, AO to A18 are address input bins;
1100 to 107 are data input/output bins.

V 8 S and (j V CC1ltt source terminal bi/r
W E J OE *C8 is a series of control bins, of which WE is the write enable bin, OE is the out, put enable bin, and C8 is the chip select bin.

In Figure 32, Oi-'C1I100-1107, WE.

Therefore, it is omitted. Further, RAM1 to AM16 are each 1M bit SRAM (static random access memory) integrated circuit chips.

In the figure, address terminals 110a (AQ to A14)
, WE terminal 108. Data input/output terminal 107 (Ilo
Address terminals 110b to 110e (A
l1~A18) and send a signal to the C8 terminal.
Only one chip can be selected to write data.

For reading data, O
A signal is supplied to the E (out enable) terminal, and data is output to the data input/output terminal 107 with the other connections being the same as for writing.

FIG. 33 shows the semiconductor module 105 in application example 4.
The details of the C8 (chip select) terminal portions of the first and second stages of the connector-equipped semiconductor devices 106a to 106d are shown.

In the same figure, 112a is the first stage (lowest stage) C8 (
The chip select terminal pad 1113a is the chip select lead wire 1114a, the chip select terminal pattern 1115a is a pattern exclusively for chip select, and the reference numeral 116b is a connection pattern for connecting the chip select terminal han 114a to the pattern exclusively for chip select.

Connectors 1038, 103 The same pattern as in FIG. 16 of application example 1 is formed on the front and back surfaces, and the terminal to be selected on the chip is not the RAS terminal but the C
A multi-chip semiconductor device similar to Application Example 1 is configured except that S terminals 112a to 112d are used. Furthermore, a signal is supplied to the first-stage connector-equipped semiconductor device 106a.

Application example 1 also supplies signals to the semiconductor devices 106b to 106d with connectors in the second, third, and fourth stages.
Since this is the same route as in Fig. 16, details will be omitted.

In Application Example 4 of Example I, many semiconductor chips can be mounted on the same mounting area as the conventional package. That is, the packaging density of semiconductor devices can be increased. In addition, TAB (Tape Automated)
Since the chips (bonding) are stacked, the thickness of the package can be reduced.

Furthermore, a semiconductor module with several times the capacity can be obtained by only changing part of the pattern of each connector without changing the layout within one chip, the leads of the film carrier, etc.

Next, examples of modified lead shapes of the multi-chip semiconductor device described above are shown in FIGS. 34 to 37.

First, in FIG. 34, (a) shows the outer lead portion 1.
20a to 120d (7): ff nectar 122a to 1
The part between the part where the bonding with the film carrier tape 22d ends and the part where the connection with the film carrier tapes 1218 to 121d starts is bent toward the upper side of the substrate 123. (b) is the first stage and second stage connectors 1228, 122b
FIG.

The connections between the connectors, chips, etc., except for the bent portions of the outer lead portions 120a to 120d, are the same as those shown in FIG. 14, and the above description is included in the description of FIG. 34.

In lead modification 1, by bending the leads upward, it is possible to secure a sufficient area for the one-chip capacitor 124 without changing the thickness of the package. Furthermore, bent outer lead portions 120a to 12
0dK, connector 122a and TAB129a (7
) Difference in thermal expansion coefficient K Thermal stress caused by yaw can be alleviated.

Next, in FIG. 35, outer lead portions 1258 to
125 d17) Film carrier tape 127a from the part where the adhesion with connectors 126a to 126d ends
The area between 127d and 127d ends is the board 12.
8 and from the back side of the connectors 126a to 126d to the front side. Furthermore, the connection portion is similar to that shown in FIG. 34(b), and will be used as part of the explanation.

In this lead modification example 2, TAB129a to 129d
Since the height is approximately the same as the thickness of the connectors 126a to 126d, the package of the multi-chip semiconductor device can be made even thinner, and thermal stress can be greatly alleviated by deforming the leads.

Furthermore, Fig. 36 Kj? Ite, TAB133a ~133
d to the connectors 132a to 132 in the opposite direction to that in FIG.
Equipped with dK. That is, connectors 132a-1
32d remains as is, semiconductor chips 130a to 130d
Mounting is performed with the circuit and bump forming surface facing the substrate 131 side.

In this lead modification example 3, a sufficient area for mounting the chip capacitor 134 on the substrate 131 can be obtained.

FIG. 37 shows an example in which only the lowest lead is modified. The lowermost film carrier 135a carries the semiconductor chip 13.
The circuit and bump forming surface of 8a is mounted facing the substrate 137 side, and furthermore, the outer lead portion 39a of this film carrier 135a is further extended outward from the outer frame of the connectors 140a to 140d, and the extended It is connected to the board 137 at a portion. A holding tape 136 is formed on the side of the extended outer lead portion 141 that is not in contact with the substrate 137. The holding tape 136 connects the lead pattern 142 to the semiconductor chip 138a and prevents variations in the leads when attaching the actor lead portion 139a to the connector 1408. Further, the holding tape is made of the same material as the film carrier tape. For example, polyimide resin, glass epoxy resin material, etc. are used.

In this lower lead modification example, first, since the connecting portion between the substrate 137 and the extended outer lead 141 is located outside the connector portion, the connection can be easily performed. Similarly, since the connection part is visible, it is easy to check whether the connection is good or not. Furthermore, due to the deformation of the extended outer lead 141, the board 14
Thermal stress generated at the connection portion due to the difference in thermal expansion coefficient between No. 1 and TAB can be alleviated, lead variations can be prevented, and a package with higher density packaging can be obtained.

Next, a modification of the lowest connector will be described with reference to FIGS. 38 to 40.

First, in FIG. 38, a front surface pattern 146 made of Cu is formed on the front surface of the connector 145, and a back surface pattern 147 is connected to the front surface pattern 146 through a through hole 148 on the back surface.
5 from the short side to the long side.

In FIG. 39, the connector 145 is the back pattern 1
It is soldered to the board 150 via 47. Also,
When the connector 145 of this connector modification 1 is used, the chip capacitor 149 is provided on the back surface of the board 150.

You can make a back pattern on the back of the connector as shown in Figure 38.

That is, if the back surface pattern for attachment to the board is formed on the back surface at the same pitch as the front surface pattern 146 of the connector 145, the pitch will be narrow and it will be difficult to solder. Therefore, by drawing out the patterns from the short side of the connector 145 to the long side on the back surface, the patterns can be easily soldered together.

In FIG. 40, the bottom of connector 150 is removed. By doing this, the chip capacitor 1491 can be mounted in this empty space, and the pattern pitch on the back side of the connector can be set more freely than on the short side.

Next, an example of forming the multi-chip semiconductor device of this embodiment by deforming the '1' AB lead pattern is shown in FIGS. 41 and 42. An example of forming a chip semiconductor device will be explained using FIG. 43.

First, in FIG. 41, for example, the ninth terminal from DRAM (Dynamic Random Access Memory, which is attached to the board by forming the darn 147),
That is, the FL connected to RAS terminals 151a to 151d
The A8 terminal leads 1111152a to 152d are connected to the RAS terminal pattern 15 in the first stage connector 153a.
4a, and the first in the second stage connector 153b)
1. Similarly, the As-only pattern 155b and the third and fourth stages are connected to the As-only pattern 157dK. Further, the same connectors 153a to 153d can be used without changing the first to fourth stages.

In this modification example (2), by simply changing the chip selection lead of the TAB lead without changing the internal layout of the chip, the lead wires or connectors that share the signal supply path, you can select one of the stacked semiconductor chips. , it is possible to select and operate only a specific chip, and it is possible to obtain a memory module with four times the memory capacity even though the mounting area is the same.

Next, in FIG. 1, a case is illustrated in which the same circuit elements as in Modification I are used, for example. The RAS terminal pads 159a to 159d are connected in advance to the RAS dedicated leads M164, the first AS dedicated leads 160a to d, the second RAS dedicated leads 161a to d, and the third RAS dedicated leads 162a.
d. Connect to the fourth RAS dedicated leads 163a to 163d. In order to individually supply signals to each of the elements in the 1st to 4th stages, 1. First, the 1st stage is the 1st RAS dedicated lead wire 1.
While only 60a is connected, the remaining second to fourth RAS dedicated lead wires 161al, 162a#, and 163a are cut using a laser or the like. Second stage, third stage.

4th stage [Similarly 2nd RAS dedicated IJ-)'Ws151b
.

The remaining dedicated lead wires are cut while leaving only the dedicated lead wire 163d connected.

That is, the modification (2) can achieve the purpose of the present embodiment I. Prepare in advance all lead wires and connectors connected to the internal chip layout and semiconductor chip, and cut the remaining lead wires with a laser etc. until only the necessary lead wires are connected according to the layer to be stacked. The semiconductor module of the present invention can be obtained by performing K.

In addition, in Modification H, the RAS dedicated lead wires 164a to 164dt - the first to fourth RAS dedicated lead wires 160 to 163 are formed in advance without being connected,
When forming each stage, for example, the first stage connector includes a lead wire 164a for RAS and a lead wire 160a for exclusive use of the first RAS.

In the second stage, the RAS dedicated lead wire 164b and the second RAS dedicated lead wire 161b are connected using wire bonding or the like.

In this case as well, four identical lead wires and connectors are prepared in advance for the internal layout of the chip, all the lead wires connected to the TAB chip, and only the necessary lead wires can be connected according to the layer to be stacked.

Next, in FIG. 43, for example, an MO
When using a type 8 circuit element, 1658 to 165d are RA
S terminal pads, 166a-d#: to the first RAS terminal pad y
)” + 1678-d# 168-d and 169a
-d are the second to fourth RAS terminal pads, respectively. Further 170a-d, 171a-dl172a-d and 17
3a to 3d are lead wires dedicated to the first to fourth RAS, respectively.

This modification (2) will be explained using the first stage connector-equipped semiconductor device 174a.

The semiconductor chip 175a has a circuit pattern, pads, etc. formed in advance, and furthermore, a connector 176a and lead wires (the common lead wire and the above-mentioned RASi lead wire) are also formed in advance. Then, a signal is sent through the path of the As terminal pad 165a and the first line. )
tAs terminal pad 165a and first As terminal pad 16
Between 6a and 6a, a master slicing method is used, in which a circuit element is formed on a semiconductor chip on which a polar pattern and a wiring pattern have already been formed, and an insulating film (Sin, etc.) is formed to insulate the circuit element and the pattern. , a wire 177a made of aluminum is formed on the upper surface thereof, and a wire 166a is formed to be connected to this aluminum wiring pattern, thereby making the connection.

In other words, there is a bump ring at the tip of the lead wire 170a! ,
(forming the first RAS terminal pad 166a),
The first RAS dedicated lead 1170a is bonded.

Semiconductor devices with connectors 174b on the second to fourth stages
Similarly, for 174d, AJ wiring is provided from the RAS terminal pads 165b to 165d to the tip of each dedicated lead wire, a bank electrode is formed at the tip, and the dedicated lead wire is bonded.

In modification ①, in order to configure a semiconductor device with connectors at each stage, wiring is only placed in one place on the chip, without changing the circuit elements, electrodes, wiring layout, lead wires, connectors, etc. inside the chip. The purpose of this embodiment I can be achieved.

Furthermore, since the first to fourth RAS terminal pads are formed later on the chip, there is no need to change the wiring within the chip, so the chip size may remain the same as before.

In FIGS. 41 to 43, MO8 consisting of DRAM
Although the description has been made using a type circuit element, the present invention is not limited thereto, and, for example, an SRAM (Static Random Access Memory) MOS type or bipolar MO8 type integrated circuit chip may be used.

Next, a modified example of the connector will be shown.

FIG. 44 is a plan view of a modified example of the connector.

In FIG. 44, the two-side connector 180 has resin-coated TA.
B181 is mounted, and a semiconductor device 182 with a connector is configured.

The two-sided connector 180 is made of, for example, glass epoxy material or ceramic.

By using the two-side connector 180'i shown in FIG. 44, the size of the shorter side of the semiconductor device with the connector can be reduced. In addition, it is easier to process than a frame-shaped connector. Furthermore, when ceramic is used as the connector material, it is easier to process than glass epoxy material and has better heat resistance.

Furthermore, since no thermal stress is generated due to the difference in thermal expansion coefficient between the connector and TAB in the long side direction, the connector and TABlj-
connection reliability can be greatly improved.

[Example ■]

Embodiment 2 of the present invention will be explained using FIG. 45.

FIG. 45(a) is a plan view of the film carrier semiconductor module of Example H, and FIG. 45(b) is a sectional view taken along the line z-z' in FIG. 45(a).

In FIG. 45, a surface pattern is formed on the surface of the leaded connector 200 with the lead pattern 201 extended by the inner lead portion 205''!! , through holes 207 electrically connect the front and back patterns.

Bumps 208 formed on the semiconductor chip 203 are electrically connected to the inner leads 205.

A retention coat 204 is applied to the surface and side surfaces of the semiconductor chip 203 including the connection portions.

To form the connector 200 with leads, a hole into which the semiconductor chip 203 is inserted is punched out in a substrate having a conductive material for a pattern fixed on one side of the base material, and then a conductive material for forming a lead pattern is punched into the hole on the other side. After that, a printed wiring board manufacturing process is used to form a leaded connector 200 with a lead pattern protruding from one end of the base material as shown in FIG. 45.

The connector 200 with leads and the semiconductor chip 203 are bonded using a known inner lead bonding method such as gold-gold or gold-soot. Main lead connector 2
Film carrier semiconductor module 202 using 00
In stacking, the first connecting portion 14 shown in FIG.
a is unstable, which is very advantageous in the assembly process.

[Example 2] Example 2 of the present invention will be described below with reference to FIGS. 46 to 55.

FIG. 46 is a sectional view of a multi-chip semiconductor device 332 according to the present invention, in which four film carrier semiconductor devices 28 shown in FIGS. 47 and 48 are stacked and electrically connected.

FIG. 47 is a sectional view of the film carrier semiconductor device 28 of the present invention in which the outer lead with a base material is bent, and FIG. 48 is a plan view thereof.

First, in FIGS. 47 and 48, the half-wrapped chip 3
02 is formed with a bump 304 and is electrically connected to the inner lead 308 of the film carrier tape 306.

The film carrier tape 306 includes a frame base material 310 and a surface pattern 312 formed on its upper surface, a bent base material 314 and a back surface pattern 3169 formed on its surface, a connection pattern 318 connecting the surface pattern 312 and the back surface pattern 316. There is a fixing layer 320 that fixes the frame base material 310 and the bent base material 314, and the surface of the chip 302 including the inner lead bonding part, the frame base material 310, and the chip 3.
02 side surface is coated with resin 322 to form a film carrier semiconductor device [32B].

In FIG. 48, the inner lead bonding portion is shown with the resin 322 removed to make it easier to see.

In FIG. 46, the same numbers as in FIGS. 47 and 48 indicate the same contents, and four film carrier semiconductor devices t132
The bottom row of B is marked with [a after the number, the second row from the bottom is marked with b, the third row is marked with C, and the fourth row is marked with d. In addition,
The same reference numerals indicate the same contents in the following figures as well.

In FIG. 46, the film carrier semiconductor device fi13
28a to 328d are connected by an interlayer connection layer 330 to form a multichip semiconductor device 332. The multi-chip semiconductor device t332 is connected via a connection layer 338 to a substrate 336 on which a wiring pattern 334 is formed.

FIG. 49 is a sectional view and a plan view showing the manufacturing process of a film carrier semiconductor device according to Example 2 of the present invention.

(a) is an inner lead bonding process for connecting the puncture 304 on the chip 302 and the inner lead 308;
Device hole 341. A nonagonal hole 342 is formed at the bottom of the connection pattern 318. The semiconductor chip 302 is electrically connected to a film carrier tape having a square hole 346 formed in the lower part of the holding lead 344 and an inner lead 308.

ing. (b) is the step of applying resin 322 to the upper surface of the chip part and around the inner lead bonding part (C1 is the step of applying resin 322 to the upper surface of the chip part and around the inner lead bonding part; (C1 is the step of applying resin 322 to the upper surface of the chip part and around the inner lead bonding part; (C1 is the step of applying resin 322 to the top surface of the chip part and the vicinity of the inner lead bonding part; It is done on a standard basis.

50 to 52 are plan views showing a part of the outer lead portion before bending, in which the film carrier tape 306
There are a square hole 342 and a square hole 346, a front surface pattern 312 is formed on the frame wood 310, a back surface pattern 316 is formed on the bent base material 314, and a connection pattern 318 is formed in the square hole 342 part. Also, in Fig. 51, connection pattern 3
A hole 348 is formed in the 18th part.

53 and 54 are cross-sectional views showing the connection pattern 318, and in FIG. 53, the thin portion 350 is
18, and in FIG. 54, it is provided in a part.

Next, the details and operation of each part of the multi-chip semiconductor device and film carrier semiconductor device according to the present invention will be explained.

In FIG. 46, a semiconductor chip 302 is a memory semiconductor chip with a memory element integrated therein, and a substrate 33
Data is written and read by signals supplied from 6.

The flow of electrical signals when writing and reading data is as follows:
First, a signal is supplied from the outside to the wiring pattern 334 on the substrate 336, and is supplied to each terminal of the multi-chip semiconductor devices 328a to 328d through the connection N338. Here, the circuit is constructed so that the electric signal supplied to each terminal effectively acts only on the film carrier semiconductor device selected by the chip select pattern among the film carrier semiconductor devices 328a to 328d, and The carrier semiconductor device is designed not to operate.

Regarding the chip selection method, see the above example! , the method of modification example (Fig. 42) is used.

The structure and manufacturing method of the film carrier semiconductor device FT328 alone will be explained with reference to FIGS. 47, 48, and 49. The film carrier tape 306 has a device hole 344 for attaching the semiconductor chip and the tab 302 to the glass epoxy base material.
Square holes 342 and 344 are punched, copper foil is pasted on the negative side, and the necessary circuit pattern is formed using the already known film carrier chip process.

A film carrier tape 306 is attached to the semiconductor chip 302.
A bank 304 for connecting to the inner lead 308 of the semiconductor device is formed by a known bump forming process.

Inner lead 30 of this film carrier tape 306
8 and the bumps 304 of the semiconductor chip 302 are aligned and connected metallically as shown in FIG. 49(a)K. For joining, a method is used in which a heated heater chip is pressed against the connection part.

Next, as shown in (b), the bonded semiconductor chip 30
2 and the side surface of the semiconductor chip 302 and the frame wood 310
Apply resin 322 to the area where it exists and harden it. resin 3
No. 22 is intended for corrosion resistance and mechanical protection of the inner lead connection portion, and uses an epoxy thermosetting resin, but the material and curing method are not particularly limited.

Next, as shown in (C), (e
) Apply the adhesive 340, and then cut the holding lead 344 and the side surface of the bent base material 314 as shown in (d) and ff.

By this cutting, the bent base material 314 and the back pattern 3 are formed.
In step 16, only the connection pattern 318 is bent along the K side, and the lower surface of the frame wood 310 and the lower surface of the bent base material 314 are made to face each other and fixed with adhesive 310 (h). Then, cut out the shape and adjust it.

The film carrier semiconductor device shown in (h) is completed.

The outer shape cutting is performed based on the sprocket hole 315 of the film carrier tape 306. For this reason, the specific surface pattern 318 is similarly formed with the sprocket hole 315 at the reference pressure.
The dimensional accuracy is very good.

In this Example (2), a glass epoxy material was used for the film carrier tape base material, but the material is not particularly limited to this material.

In FIGS. 50 to 52, the connection pattern 318 corresponds to a portion to be bent, and has a smaller cross-sectional area than the front pattern 312 and the back pattern 316 to make it easier to bend.

In Figs. 50 and 51, the front pattern 312 and the back pattern 316 have the same width, and the connection pattern 318 in Fig. 50 has a narrower width (Q, Fig. 51 has holes) .

In FIG. 52, the connection pattern 318 is made narrower than the front surface pattern 312, and the width of the front surface pattern 312 and the back surface pattern 316 are different. This is to prevent a reduction in the inter-pattern gap due to misalignment during alignment of the first-stage film carrier semiconductor device and the second-stage film carrier semiconductor device stacked thereon.

That is, by providing a difference in width between the front surface pattern 312 and the back surface pattern 316, both patterns will completely overlap even if there is a positional shift of one half of the difference in pattern width.

FIGS. 53 and 54 show other embodiments for reducing the cross-sectional area of the connection pattern 318). Only the connected pattern 318 has a thinner lead float.

Particularly, in FIG. 54, a thin portion 350 is provided near the bending base material 314 to improve bending properties.

In FIG. 47, the bent base material 3 is folded against the frame base material 310.
14 is made narrower, but this is because when a plurality of film carrier semiconductor devices 328 are stacked as shown in FIG. 46, a pattern close to the lower inner lead, for example, the inner lead 308 shown in FIG. Surface pattern 312
Back pattern 316 on the upper row of the diagonal pattern section connecting with
The pressure was applied so as not to overlap with the above.

A plurality of film carrier semiconductor devices 328 formed by the method shown in FIG. 49 are stacked to form a multi-chip semiconductor device 332 shown in FIG. 46. Here, the method of stacking the film carrier semiconductor devices 328 is as follows.
6, each film carrier semiconductor device 328
An interlayer connection layer 330 using solder is provided between them, and the layers are aligned and stacked based on the external shape. Thereafter, the interlayer connection layer 330 is heated to melt the solder and complete the interlayer connection. In addition,
Although four film carrier semiconductor devices 328 are stacked in FIG. 46, the number is not limited to four. Maku,
Although solder is used for the interlayer connection layer 330, it is not limited to K solder, and brazing filler metals, anisotropic conductive adhesives, conductive pastes, etc. whose main components are tin, gold, etc. can also be used.

Next, FIGS. 55 and 56 show another example in which the outer leads of Example 2 are bent.

FIG. 55 is a cross-sectional view of a connector-equipped semiconductor device ft360 having a connector 362 with front and back patterns 364a and b, and FIG. 56 is a cross-sectional view of a connector-equipped semiconductor device 366 having a connector 366 without a pattern.

In FIG. 55, a front surface pattern 364a and a back surface pattern 364b are formed on the connector 362. The front pattern 364a is connected to the outer lead part 363a through the solder layer 365, and the tip of the bent actor lead part 363b is connected to the back pattern 364b through the solder 365.

In FIG. 56, a connector 366 has no front and back patterns formed thereon, and is directly connected to outer lead portions 363a and 363b via an adhesive 367.

As mentioned above, according to the present embodiment (2), a film carrier semiconductor device having double-sided wiring can be formed by a simple process using a film carrier tape having single-sided wiring. Further, since the outer lead portion with the base material is bent, a film carrier tape whose base material thickness is approximately half of the chip thickness can be used, so a conventional film carrier tape manufacturing process can be applied. Furthermore, since the structure is such that a part of the actor lead is directly bent, the surface pattern width can be made sufficiently small, and as a result, the module can be made smaller. Furthermore, since the outer shapes are individually cut from the film carrier tape, the dimensional accuracy between the pattern and the outer shape is good, and alignment can be performed based on the outer shape when laminating film carrier semiconductor devices. Furthermore, since the performance of the film carrier semiconductor device can be completely inspected as a single unit, a multi-chip semiconductor device can be made by combining only non-defective products at this point, resulting in a very high yield.

Next, a manufacturing process of a semiconductor device with a connector according to the present invention will be explained using FIGS. 57 to 63.

First, FIG. 57 is a manufacturing process flow diagram of the semiconductor devices with connectors shown in FIGS. 16, 18, and 33.

In Type A of the same figure, a di-copper pattern is formed on a polyimide resin film tape in the form of a tape using normal etching techniques, and a semiconductor chip is mounted on this pattern by inner lead bonding. Divide T A B into individual TABs. Next to the process, each TAB cuts the excess lead pattern,
Heat each of the four connectors in sets of four to 250℃ using a pulse heat bonder.

Load it for 1 to 2 seconds. (Process■〜■)TA
Divide the connector equipped with B into individual parts and inspect each TAB with the connector (burn-in) and electrical characteristics (Process ■).

(Process ■) Next, the TAB with the connector is laminated and clamped (Process ■), visual inspection is performed (Process ■), and soldered (Process 0) to form a laminated TAB module, that is, the multi-chip semiconductor device of Example ■ is completed.

Since the characteristic test is performed after dividing the connectors, defective products can be removed before stacking, and the yield of stacked TAB modules is improved.

In addition, in Type B of the figure, a case is shown in which burn-in and electrical characteristic inspection are performed at the stage when the laminated TAB module is completed. (Process ◎) FIG. 58 is a manufacturing process flow diagram of the semiconductor device with a connector shown in FIGS. 41 and 43.

In Type A of the figure, a TAB is formed by inner lead bonding of a semiconductor chip to four types of film chips on which different copper wiring patterns are formed.

Alternatively, a TAB formed by inner lead bonding a lead pattern having the shape shown in FIG. 43 to four different types of semiconductor chips is individually divided. (Prosen ■) Next, the excess lead patterns of each TAB are cut off, and each of the four types of TAB is bonded to the same type of connector board using a pulse heat bonder at 250° C. for 1 to 2 seconds.

(■ to ■) Subsequently, the laminated TAB module is completed through the process (■ to 0) explained in FIG. 57.

In addition, the above-mentioned process (■～■) also applies to type B in the same figure.
This is the description of Figure 58.

FIG. 59 is a manufacturing process flow diagram of the semiconductor device with connector shown in FIG. 42.

In Type A of the same figure, four TABs of the same type formed by the normal TAB method were prepared (Process ■), and the prepared TABs were heated at 250°C for 1 to 2 seconds on the same type of connector board.
Second bonding. (Process ■) Next, as shown in FIG. 42, only the necessary lead patterns are left, and the excess lead patterns are cut off using a laser or the like, or only the necessary lead patterns are connected by wire bonding or the like.

(Process ■) Subsequent steps (■ to ■) are the same as the processes (■ to [phase]) explained in FIG. 57 to complete the laminated TAB module.

Also, in type B of the same figure, the above-mentioned process (■~■
) is used as the description in Figure 59.

FIG. 60 is a manufacturing process flow diagram of the semiconductor device with connector shown in FIG. 45.

In type A of the same figure, a semiconductor chip formed through a normal process is prepared, and a pulse heat bomber is used to heat the semiconductor chip at 250°G for 1 hour.
Inner lead bonding is performed for ~2 seconds. (
Process (1) to (2)) Here, the leaded connectors are each formed in the same shape as the front and back surfaces of the connector in FIG. 16 of Example (2), depending on the position where they are stacked.

Subsequently, the subsequent steps (■ to ■) are the same as the processes (■ to 0) explained in FIG. 57 to complete the laminated module.

Also in the same diagram type B, the description in FIG. 60 is made by the above-mentioned process (■ to ◎) in FIG. 57.

FIG. 61 is a semiconductor device with a connector shown in FIG. 45,
As shown in FIG. 43, it is a manufacturing process flow diagram when four types of semiconductor chips (1) ie) are applied.

In type A in the figure, corresponding to each layer to be stacked,
Prepare the four types of semiconductor chips shown in Figure 43, and use a pulse heat bonder to attach the connector with leads to 250°.
Bonding is performed under conditions of C11-2 seconds. (Process ■～■) Next, the following steps (■～■) are the 57th
A laminated module is completed through the same process as the process (■ to 0) explained in the figure.

Also, for type B in the figure, the process (■ to 0) in FIG. 57 described above is used as the description in FIG. 61.

FIG. 62 is a semiconductor device with a connector shown in FIG. 45,
42 is a manufacturing process flow diagram when only necessary lead patterns are connected as shown in FIG. 42.

In the type A shown in the figure, four semiconductor chips and four connectors to which leads are attached in advance are prepared, and each is bonded using a pulse heat bonder at 250° C. for 1 to 2 seconds. (Process ■) Then,
Only the necessary lead patterns are left and the excess lead patterns are cut off using a laser or the like, or only the necessary lead patterns are connected by wire bonding or the like. (Process ■) Subsequent steps (■ to ■) are the same as the processes (■ to [Co., Ltd.]) explained in FIG. 57 to complete the laminated module.

Furthermore, for type B in the same figure, the above-mentioned processes (■ to ■) in FIG. 57 are combined with the description in FIG. 62. ◇ FIG. 63 is a manufacturing process flow diagram of the semiconductor module shown in FIG. 24.

In the single-sided semiconductor module shown in the figure, solder paste is printed on the surface of the printed wiring board.

(Process ■) Next, chip capacitor and Example ■
For the laminated TAB module shown in ~■--Reflow the process as shown in ■). (Process ■) Here, the conditions were 215°C for 30 seconds during paper reflow, and 230°C for 5 seconds during infrared ray 70-.

After passing through an organic solvent to remove slack and cleaning the module (process ①), a single-sided semiconductor module is completed through an external appearance inspection (process ①), burn-in and electrical characteristic inspection (process ②).

In the double-sided semiconductor module shown in the figure, the mounting of the laminated TAB module on the surface of the printed wiring board is common to the processes (■ to ■) for the single-sided semiconductor module. In the case of double-sided mounting, after the solder reflow process (2), solder paste is printed on the back side of the printed wiring board (process (2)), the chip capacitor and the above-described laminated TAB module are mounted (process (2)), and reflow is performed. (Process ■) Next, the double-sided semiconductor module is completed through the above-mentioned cleaning and calibration steps.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

According to the present invention, in a large-capacity memory module using a film carrier-type conductor device, by stacking and mounting a plurality of film carrier semiconductor devices, the number of chips stacked in a conventional mounting area can be increased by multiple times the number of chips stacked in a conventional mounting area. Memory capacity could be easily obtained.

In particular, the technique of the present invention is a technique for obtaining a high-density package that is effective when applied to devices using semiconductor memories whose capacities are becoming larger and larger.

[Brief explanation of the drawing]

FIG. 1 shows the resin 'L' used in the semiconductor device of the present invention.
A plan view of TAB, FIG. 2 is a plan view of AB with resin, FIG. 3 is a sectional view taken along line X-X in FIG. 2, and FIG. 4 is a semiconductor device of the present invention. FIG. 5 is a side view of the connector, FIG. 6 is a plan view of a semiconductor device with a connector, and FIG.
6 is a cross-sectional view along the Y-Y' line, FIG. 8 is a plan view of a connector with one alignment hole, FIG. 9 is an enlarged view of the main part of TAB with an alignment pattern, and FIG. 10 is a , an enlarged view of the main parts of an example of a connector, Fig. 11 (
a) is a plan view of an example of a semiconductor module, section 11 (b) is a plan view of an example of a semiconductor module;
) and (C) are bin layout diagrams, FIG. 12 is a sectional view taken along line AA' in FIG. 11, FIG. 13 is a side view of the semiconductor module in FIG. 11, and FIG. 14 is FIG. 15 is an enlarged cross-sectional view of the main parts of a stacked semiconductor device with connectors; FIG. 15 is an overall circuit block diagram of an example of the semiconductor module of the present invention; FIG. 16 is a main part of the stacked semiconductor device with connectors according to FIG. 15. 17 is an overall circuit block diagram of another example of the semiconductor module of the present invention; FIG. 18 is a perspective view of essential parts of a stacked semiconductor device with a connector according to FIG. 17; FIG. 19 , Fig. 21, Fig. 22, and Fig. 23 (a) to (
C1 is a side view of various package variations when using the semiconductor module of the present invention; FIG. 20 is a plan view of FIG. 19; FIG. 24 is a plan view of an example of the semiconductor module; 26 is a side view of the semiconductor module in FIG. 24, FIG. 27 is an overall circuit block diagram of the semiconductor module in FIG. 24, and FIG. 28 is a cross-sectional view taken along line BB' in FIG. , FIG. 29 is a sectional view taken along the line CC' in FIG. 28, FIG. 30 is a side view of the semiconductor module in FIG. 28, and FIG. 31 is a plan view of the semiconductor module in FIG. 28. FIG. 32 is an overall circuit block diagram of the semiconductor module shown in FIG. 28; FIG. 33 is a perspective view of main parts of a stacked semiconductor device with connectors according to FIG. 28; FIG. 34 (a) and FIGS. 35 to 37) are side views of semiconductor devices with connectors with different lead shapes; FIG. 34(b) is an enlarged side view of the connector connection portion of FIG. 34(a); Fig. 37(b) is a partially enlarged side view of the lowest stage of Fig. 37(a), Fig. 38 is a top view of an example of the lowest stage connector, and Fig. 39 is a connector using the connector of Fig. 38. FIG. 40 is a side view of a semiconductor device with a connector using another example of the lowermost connector. FIGS. 41 to 43 are other examples of stacked semiconductor devices with connectors. 44 is a plan view of an example of a connector, FIGS. 45(a) and 45(b) are a plan view and a side view of another example of a semiconductor device with a connector, and FIG. 46 is a The cross-sectional views of the multi-chip semiconductor device according to the present invention, FIG. M47 and FIG. 48, show the film carrier half. A cross-sectional view and a plan view thereof of a conductor device, (7) Columns from Fig. 49(a) to Fig. 49 are a sectional view and a plan view showing the manufacturing process of a film carrier semiconductor device, and Figs. 50 to 54 show a film carrier semiconductor device. A partially enlarged plan view and a cross-sectional view of the carrier semiconductor device, FIGS. 55 and 56 are cross-sectional views of other examples of the film carrier semiconductor device, and FIGS. 57 to 62 are multi-chip semiconductors of the present invention. The manufacturing process flow diagram of the device, FIG. 63 shows the multi-chip 11(b) which is an example of the present invention, FIG. 7Hc, FIG. ) Figure Figure Figure Figure Figure Figure 45 (a) Figure n1 Figure (l-1) 72 yo (il Figure Figure Figure Figure Figure Figure Figure

Claims (1)

[Claims] 1. A semiconductor chip having a circuit and a plurality of external terminals formed on its main surface; a rectangular connector having a main surface and a back surface for mounting the semiconductor chip; A plurality of conductors formed on the main surface and the back surface of the connector, a through hole that electrically connects the conductors and passes through the connector, and a conductor formed on the external terminal and the main surface of the connector. a plurality of lead patterns for electrically connecting the semiconductor chip and the connector; a film-like tape in contact with the lead pattern and located between the semiconductor chip and the connector; a conductive adhesive for connecting the plurality of lead patterns, and a resin for sealing the main surface of the semiconductor chip, the external terminals, and a part of the lead patterns; A semiconductor device, wherein at least one lead pattern is not electrically connected to the external terminal. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a pattern formed independently at a corner portion of the main surface of the connector. 3. The semiconductor device according to claim 1, wherein the connector is made of glass epoxy material. 4. The semiconductor device according to claim 1, wherein the connector is made of ceramic. 5. The semiconductor device according to claim 1, wherein the plurality of conductors are made of copper patterns. 6. The semiconductor device according to claim 1, wherein the film-like tape is made of polyimide resin. 7. The semiconductor device according to claim 1, wherein the adhesive is solder. 8. The semiconductor device according to claim 1, wherein the resin is an epoxy resin. 9. The semiconductor device according to claim 1, wherein at least two of the connectors are stacked. 10. The semiconductor device according to claim 9, further comprising a substrate on which the stacked connectors are mounted. 11. The semiconductor device according to claim 9, comprising an adhesive for connecting the connectors. 12. The semiconductor device according to claim 11, wherein the adhesive is a high melting point solder. 13. The semiconductor device according to claim 10, further comprising an adhesive for connecting the substrate and the connector. 14. The semiconductor device according to claim 13, wherein the adhesive is a low melting point solder. 15. The semiconductor device according to claim 1, wherein four connectors are stacked. 16. The stacked connectors each have three lead patterns that are not electrically connected to the external terminals.
Claim 1 characterized in that it is individually formed.
The semiconductor device according to item 5. 17. A plurality of semiconductor chips each having a circuit and a plurality of external terminals formed on a main surface; a plurality of rectangular connectors having a main surface and a back surface and for mounting the semiconductor chips; A plurality of conductors formed on the main surface and the back surface, a through hole that electrically connects the conductors and passes through the connector, and a conductor formed on the external terminal and the main surface of the connector. a plurality of lead patterns for electrical connection; a film-like tape in contact with the lead patterns and located between the semiconductor chip and the connector; and a conductive tape formed on the main surface of the lead pattern and the connector. A semiconductor device comprising: a conductive adhesive for connecting to a body; and a resin for sealing a main surface of the semiconductor chip, an external terminal, and a part of the lead patterns, at least among the plurality of lead patterns. One lead pattern is not electrically connected to the external terminal, and furthermore, at least two connectors each carrying the semiconductor chip are stacked, and further, here,
A semiconductor device characterized in that at least one of the external terminals is an independent terminal in each stage, and the remaining external terminals are electrically connected. 18. The semiconductor according to claim 17, wherein at least one set of conductors formed on the front and back surfaces of the stacked connectors other than the bottom one is insulated. Device. 19. The lead pattern connected to an independent terminal of a semiconductor chip mounted on at least one connector stacked on the lowermost connector and the back conductor located on the opposite side of the front conductor are It is not electrically connected to the lead pattern and surface conductor connected to independent terminals of the semiconductor chip mounted on the connector, which is located below and in contact with the connector, and is not electrically connected to the lead pattern and surface conductor that are located below and in contact with the Lead patterns and surface conductors that are adjacent to lead patterns and surface conductors that are connected to independent terminals of semiconductor chips mounted on connectors that are connected to the connector, and that are not electrically connected to these independent external terminals. 18. The semiconductor device according to claim 17, wherein the semiconductor device is electrically connected via a conductive adhesive. 20. The semiconductor device according to claim 17, further comprising a pattern formed independently at a corner portion of the main surface of the connector. 21. The semiconductor device according to claim 17, wherein the connector is made of glass epoxy material. 22. The semiconductor device according to claim 17, wherein the connector is made of ceramic. 23. The semiconductor device according to claim 17, wherein the plurality of conductors are made of copper patterns. 24. The semiconductor device according to claim 17, wherein the film-like tape is made of polyimide resin. 25. The semiconductor device according to claim 17, wherein the adhesive is solder. 26. The semiconductor device according to claim 17, wherein the resin is an epoxy resin. 27. The semiconductor device according to claim 17, further comprising a substrate on which the stacked connectors are mounted. 28. The semiconductor device according to claim 17, further comprising an adhesive for connecting the connectors. 29. The semiconductor device according to claim 28, wherein the adhesive is a high melting point solder. 30. The semiconductor device according to claim 27, further comprising an adhesive for connecting the substrate and the connector. 31. The semiconductor device according to claim 30, wherein the adhesive is a low melting point solder. 32. The semiconductor device according to claim 17, wherein four connectors are stacked. 33. The stacked connectors each have three lead patterns that are not electrically connected to the external terminals.
Claim 3 characterized in that it is individually formed.
2. The semiconductor device according to item 2. 34. A semiconductor chip having a circuit and a plurality of external terminals formed on its main surface; a rectangular connector having a main surface and a back surface for mounting the semiconductor chip; and a rectangular connector formed on the main surface of the connector. and further includes a plurality of lead patterns connected to the external terminals, and a through hole that electrically connects the plurality of conductors formed on the back surface of the connector and the lead patterns and that penetrates the connector. In a semiconductor device made of a resin for sealing a main surface of the semiconductor chip, an external terminal, and a part of a lead pattern, at least one lead pattern among the plurality of lead patterns is electrically connected to the external terminal. A semiconductor device characterized by: 35. The semiconductor device according to claim 34, further comprising a pattern formed independently at a corner portion of the main surface of the connector. 36. The semiconductor device according to claim 34, wherein the connector is made of glass epoxy material. 37. The semiconductor device according to claim 34, wherein the connector is made of ceramic. 38. The semiconductor device according to claim 34, wherein the plurality of conductors are made of copper patterns. 39. The semiconductor device according to claim 34, wherein the resin is an epoxy resin. 40. The semiconductor device according to claim 34, wherein at least two of the connectors are stacked. 41. The semiconductor device according to claim 40, further comprising a substrate on which the stacked connectors are mounted. 42. The semiconductor device according to claim 40, further comprising an adhesive for connecting the connectors. 43. The semiconductor device according to claim 42, wherein the adhesive is a high melting point solder. 44. The semiconductor device according to claim 41, further comprising an adhesive for connecting between the substrate and the connector. 45. The semiconductor device according to claim 44, wherein the adhesive is a low melting point solder. 46. The semiconductor device according to claim 34, wherein four connectors are stacked. 47. The stacked connectors each have three lead patterns that are not electrically connected to the external terminals.
Claim 4 characterized in that it is individually formed.
The semiconductor device according to item 6. 48. A step of preparing a semiconductor chip having a circuit and a plurality of external terminals formed on its main surface; a step of preparing a tape-shaped film tape having a plurality of conductive lead patterns formed on its main surface; A step of inner lead bonding between the terminal and the tip of the lead pattern, a step of dividing the semiconductor chip to which the lead pattern is bonded into individual parts, and a plurality of conductors are formed on the main surface and the back surface, and a plurality of conductors are formed between the conductors. A process of preparing a rectangular connector electrically connected by a through hole, and attaching an outer lead portion of a lead pattern connected to the semiconductor chip to a conductor formed on the main surface of the connector via adhesive. bonding process, and bonding the connector with the semiconductor chip mounted thereon at least two times.
1. A method of manufacturing a semiconductor device, wherein at least one lead pattern among the plurality of lead patterns is not electrically connected to the external terminal. 49. The method of manufacturing a semiconductor device according to claim 48, further comprising the step of mounting the stacked connectors on a substrate via an adhesive. 50. The method of manufacturing a semiconductor device according to claim 48, wherein the connector is made of a glass epoxy material. 51. The method of manufacturing a semiconductor device according to claim 48, wherein the connector is made of ceramic. 52. The method of manufacturing a semiconductor device according to claim 48, wherein the plurality of conductors are made of copper patterns. 53. The method for manufacturing a semiconductor device according to claim 48, wherein the tape-like film tape is made of polyimide resin. 54. The method of manufacturing a semiconductor device according to claim 48, wherein the adhesive is made of solder. 55. The method of manufacturing a semiconductor device according to claim 48, wherein a high melting point solder is present between the connectors. 56. The method of manufacturing a semiconductor device according to claim 49, wherein the adhesive is a low melting point solder.