JP3676197B2 - Semiconductor device and hybrid integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve similar effect as in the adoption of a multilayer substrate, since packaging substrates adopt the multilayer substrate to compose a circuit although there is a hybrid integrated circuit device, where a circuit device is packaged on a printed circuit board, a ceramic substrate, a flexible sheet, or the like. SOLUTION: Insulation covering RF is adopted on the back surface of a semiconductor device 53, and a conductive path 51 is allowed to dent or project, thus extending a wiring 21B on a packaging substrate 10 on the back surface of the semiconductor device, and hence achieving the similar effect as the case, where the packaging substrate is made multilayered equivalently by the conductive path of the semiconductor 53 and metal small-gauge wire.

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device in which a mounting substrate is made smaller by mounting a thin and light semiconductor device on the mounting substrate.
[0002]
[Prior art]
Conventionally, in a hybrid integrated circuit device set in an electronic device, a conductive pattern is formed on, for example, a printed board, a ceramic board, or a metal board, and an active element such as an LSI or a discrete TR, a chip capacitor, a chip A passive element such as a resistor or a coil is mounted and configured. The conductive pattern and the element are electrically connected to realize a circuit having a predetermined function.
[0003]
FIG. 19 shows an example of the circuit. This circuit is an audio circuit, and the elements shown therein are mounted as shown in FIG.
[0004]
In FIG. 20, the outermost rectangular line is the mounting substrate 1 whose surface is insulated at least. And the conductive pattern 2 which consists of Cu is affixed on this. The conductive pattern 2 includes an external extraction electrode 2A, a wiring 2B, a die pad 2C, a bonding pad 2D, an electrode 4 to which the passive element 3 is fixed.
[0005]
On the die pad 2C, a TR, a diode, a composite element, an LSI, or the like is fixed in a bare chip shape via solder. The electrodes on the fixed chip and the bonding pads 2D are electrically connected through the fine metal wires 5A, 5B, and 5C. This metal thin wire is generally classified into small signal and large signal, Au wire 5A consisting of about 40 μmφ is adopted for the small signal portion, and Au wire or Al wire of about 100 to 300 μmφ is adopted for the large signal portion. Yes. In particular, since a large signal has a large wire diameter, 150 μmφ Al wire 5B and 300 μmφ Al wire 5C are selected in consideration of cost.
[0006]
Further, the power TR6 for flowing a large current is fixed to the heat sink 7 on the die pad 2C in order to prevent the temperature of the chip from rising.
[0007]
The wiring 2B is extended to various places in order to use the external extraction electrode 2A, the die pad 2C, the bonding pad 2D, and the electrode 4 as a circuit. In addition, jumping lines 8A and 8B are employed when the wirings intersect due to the position of the chip and the way the wirings extend.
[0008]
[Problems to be solved by the invention]
Recently, a chip having a very small chip size of 0.45 × 0.5 mm and a thickness of 0.25 mm and having a low unit price has been sold. However, when this chip is fixed with solder, the solder rises on the side surface of the chip and short-circuits, so that there is a problem that it cannot be used for a hybrid integrated circuit board.
[0009]
Further, when a package in which a semiconductor element is fixed to a lead frame is mounted on a hybrid integrated circuit board, there is a problem that the size of the hybrid integrated circuit board increases because the size of the package is very large.
[0010]
Further, when a complex circuit is formed on the hybrid integrated circuit board, a multilayer hybrid integrated circuit board is required, but there is a problem that it is difficult to adopt from the viewpoint of cost.
[0011]
As described above, even if trying to reduce the cost by adopting a hybrid integrated circuit board, the cost increases due to the fact that a very small chip cannot be mounted, the assembly process becomes long, and a multilayer board is adopted. There was a problem.
[0012]
[Means for Solving the Problems]
The present invention has been made in view of the problems described above. First, a plurality of conductive paths electrically separated by a separation groove, a semiconductor chip fixed on the conductive path, a semiconductor chip covering the semiconductor chip, and An insulating resin that fills the separation groove between the conductive paths and exposes and supports the back surface of the conductive paths integrally;
The problem is solved by providing an insulating film on the back surface of the conductive path so that a part of the back surface of the conductive path is exposed.
[0013]
Second, a plurality of conductive paths electrically separated by the separation grooves, a semiconductor chip fixed on the conductive paths, and covering the semiconductor chip and filling the separation grooves between the conductive paths, With an insulating resin that exposes the backside of the road and supports it integrally.
A semiconductor device characterized in that the back surface of the conductive path is recessed from the back surface of the insulating resin.
[0014]
Third, the plurality of conductive paths electrically separated by the separation grooves, the semiconductor chip fixed on the conductive paths, the semiconductor chips are covered, and the separation grooves between the conductive paths are filled with the conductive paths. With an insulating resin that exposes the backside of the road and supports it integrally.
The problem is solved by providing the back surface of the conductive path so as to protrude from the back surface of the insulating resin.
[0015]
Fourth, the problem is solved by providing an insulating film on the back surface of the conductive path so that a part of the back surface of the conductive path is exposed.
[0016]
Fifth, the side surface of the conductive path is solved by a curved structure.
[0017]
Sixth, the problem is solved by providing a conductive film on the conductive path.
[0018]
Seventh, the problem is solved by mounting at least one semiconductor chip.
[0019]
Eighth, in addition to the semiconductor chip, an active element and / or a passive element is built in electrically connected to the conductive path, and a circuit is formed including the active element and / or the passive element. It will be solved by.
[0020]
Ninth, the conductive path is made up of Cu, Al, Fe—Ni alloy, Cu—Al laminate, and Al—Cu—Al laminate.
[0021]
Tenth, the conductive film is made of Ni, Au, Ag, or Pd, and is solved by forming eaves.
[0022]
Eleventh, the problem is solved by connecting the conductive film of the conductive path and the electrode on the semiconductor chip with a bonding fine wire or solder.
[0023]
Twelfth, a mounting substrate having at least a surface insulated and having a plurality of electrodes and wirings;
A plurality of conductive paths electrically separated by the separation groove, a semiconductor chip fixed on the conductive path, and the back surface of the conductive path that covers the semiconductor chip and is filled in the separation groove between the conductive paths. Insulating resin that is exposed and supported integrally, and a semiconductor device in which an insulating film is provided on the back surface of the conductive path so that a part of the back surface of the conductive path is exposed,
The problem is solved by fixing the back surface of the conductive path and the electrode through connection means, and extending the wiring under the insulating film.
[0024]
Thirteenth, a mounting substrate having at least a surface insulated and having a plurality of electrodes and wirings;
A plurality of conductive paths electrically separated by the separation groove, a semiconductor chip fixed on the conductive path, and the back surface of the conductive path that covers the semiconductor chip and is filled in the separation groove between the conductive paths. Insulating resin that is exposed and supported integrally, and a semiconductor device provided with the back surface of the conductive path recessed relative to the back surface of the insulating resin,
The problem is solved by fixing the back surface of the conductive path and the electrode through connection means and extending the wiring to the back surface of the semiconductor device.
[0025]
Fourteenth, a mounting substrate having at least a surface insulated and having a plurality of electrodes and wirings;
A plurality of conductive paths electrically separated by the separation groove, a semiconductor chip fixed on the conductive path, and the back surface of the conductive path that covers the semiconductor chip and is filled in the separation groove between the conductive paths. Insulating resin that is exposed and supported integrally, and a semiconductor device provided with the back surface of the conductive path protruding beyond the back surface of the insulating resin,
The problem is solved by fixing the back surface of the conductive path and the electrode through connection means and extending the wiring to the back surface of the semiconductor device.
[0026]
Fifteenth, the problem is solved by providing an insulating film on the back surface of the conductive path so that a part of the back surface of the conductive path is exposed.
[0027]
16th is to solve the problem that the side surface of the conductive path has a curved structure.
[0028]
Seventeenth, the problem is solved by providing a conductive film on the conductive path.
[0029]
Eighteenth, an active element and / or a passive element in addition to the semiconductor chip are built in electrically connected to the conductive path, and a circuit is formed including the active element and / or the passive element. It will be solved by.
[0030]
Nineteenth, the conductive path is made up of a Cu, Al, Fe—Ni alloy, a Cu—Al laminate, and an Al—Cu—Al laminate.
[0031]
20th, The conductive film is made of Ni, Au, Ag, or Pd, and is solved by forming eaves.
[0032]
Twenty-first, the problem is solved by connecting the conductive film of the conductive path and the electrode on the semiconductor chip with a bonding wire or solder.
[0033]
Twenty-second, the connection means is made of a brazing material, a conductive ball, a conductive paste, or an anisotropic conductive resin.
[0034]
[0035]
DETAILED DESCRIPTION OF THE INVENTION
The present invention relates to a thin semiconductor device composed of a semiconductor element, a conductive path, a connecting means, and an insulating resin for sealing, and uses the thin semiconductor device as a mounting substrate. Thus, the present invention relates to a hybrid integrated circuit device capable of reducing the size of the mounting substrate, shortening the manufacturing process of the hybrid integrated circuit device, and reducing the number of layers of the multilayer substrate. First, a semiconductor device will be described below.
[0036]
FIG. 1 shows a thin semiconductor device 53 fixed to a mounting substrate 10. FIG. 2 illustrates three types of the mounting structure of the thin semiconductor device 53. FIG. 3 illustrates a hybrid integrated circuit device 13 in which the thin semiconductor device 53 and circuit elements are mounted on the mounting substrate 10. Further, FIGS. 4 to 9 illustrate a method for manufacturing the semiconductor device, FIGS. 10 to 18 illustrate a semiconductor device formed based on the circuit on the right side, and FIG. The circuit configured on the mounting substrate 10 will be described.
First Embodiment Explaining Semiconductor Device 53A
First, a specific structure of the first semiconductor device 53A will be described with reference to FIG. 9A. The semiconductor device 53A has conductive paths 51A to 51C embedded in an insulating resin 50. A semiconductor chip 52A is fixed on the conductive path 51A, and if necessary, passive elements are provided on the conductive paths 51B and 51C. 52B is fixed. The insulating resin 50 supports the conductive paths 51A to 51C.
[0037]
This structure has three materials: a semiconductor chip 52A, a circuit element 52B composed of passive elements and / or active elements, a plurality of conductive paths 51A, 51B, 51C, and an insulating resin 50 that embeds the conductive paths 51A, 51B, 51C. A separation groove 54 filled with the insulating resin 50 is provided between the conductive paths 51. The conductive paths 51 </ b> A to 51 </ b> C are supported by the insulating resin 50.
[0038]
As the insulating resin, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin or polyphenylene sulfide can be used. As the insulating resin, any resin can be adopted as long as it is a resin that can be hardened using a mold, a resin that can be coated by dipping or coating. Further, as the conductive path 51, a conductive foil mainly made of Cu, a conductive foil mainly made of Al, a conductive foil made of an alloy such as Fe-Ni, an Al-Cu laminated plate, or an Al-Cu-Al The laminated board etc. can be used. In particular, Al—Cu—Al has a strong structure against warping. Of course, other conductive materials are also possible, and in particular, a conductive material that can be etched, a conductive material that evaporates with a laser, or a relatively soft substance that can form the separation groove 54 with a press is preferable.
[0039]
The connection means of the semiconductor element 52A and the circuit element 52B includes a metal thin wire 55A, a conductive ball made of a brazing material, a flat conductive ball, a brazing material 55B such as solder, a conductive paste 55C such as an Ag paste, a conductive film or an anisotropic film. For example, a conductive resin. These connection means are selected depending on the type and mounting form of the semiconductor element and circuit element 52. For example, in the case of a bare semiconductor chip, a thin metal wire 55A is selected for connection between the surface electrode and the conductive path 51B, and in the case of CSP or SMD, a solder ball or solder bump is selected. For the chip resistor and the chip capacitor, the solder 55B is selected. When mounted face down like a CSP, the metal wires do not protrude upward and laterally, and a substantially chip size package is possible.
[0040]
In addition, a conductive coating is used to fix the semiconductor element 52A and the conductive path 51A. Here, at least one conductive film is sufficient.
[0041]
Possible materials for this conductive film are Ag, Au, Pt, Pd, brazing material, etc., which are covered by deposition, plating, sintering or coating under low vacuum or high vacuum such as vapor deposition, sputtering, and CVD. Is done.
[0042]
For example, Ag adheres to Au and also to a brazing material. Therefore, if the Au film is coated on the back surface of the chip, the semiconductor chip can be thermocompression bonded by directly coating the conductive film 51A with the Ag film, Au film, or solder film, and the chip is fixed through a brazing material such as solder. it can. Here, the conductive film may be formed on the uppermost layer of the conductive film laminated in a plurality of layers. For example, on a Cu conductive path 51A, two layers of Ni film and Au film are sequentially deposited, three layers of Ni film, Cu film and solder film are sequentially deposited, Ag film, A Ni film can be formed by sequentially coating two layers. In addition, there are many types of these conductive films and laminated structures, but they are omitted here.
[0043]
In this semiconductor device 53A, since the conductive path 51 is supported by the insulating resin 50 that is a sealing resin, a support substrate for bonding and supporting the conductive paths becomes unnecessary, and the conductive path 51, the element 52, and the insulating resin 50 are eliminated. Consists of. This configuration is a feature of the present invention. Since the conductive path of the conventional circuit device is supported and bonded by a support substrate (printed substrate, ceramic substrate or flexible sheet), or is supported by a lead frame, a configuration that is essentially unnecessary is added. However, this semiconductor device is composed of the minimum necessary elements, can eliminate the need for a support substrate, and has a feature of being thin and inexpensive.
[0044]
In addition to the above-described configuration, the insulating resin 50 that covers the circuit element 52 and is filled in the separation groove 54 between the conductive paths 51 and is integrally supported is provided.
[0045]
The space between the conductive paths 51 becomes a separation groove 54, and the insulating resin 50 is filled therewith, so that there is an advantage that mutual insulation can be achieved.
[0046]
Further, the insulating resin 50 is provided which covers the element 52 and is filled in the separation groove 54 between the conductive paths 51 so as to expose and support the back surface of the conductive path 51 integrally.
[0047]
The point that the back surface of the conductive path is exposed is one of the features of the present invention. The back surface of the conductive path can be used for connection with the outside, and the through hole employed in the printed circuit board employing the support substrate can be eliminated.
[0048]
In addition, when the semiconductor element 52A is directly fixed via a conductive film such as brazing material, Au, or Ag, the back surface of the conductive path 51 is exposed, so that heat generated from the semiconductor element 52A is transmitted via the conductive path 51A. Can be transmitted to the mounting board. In particular, it is effective for a semiconductor chip that can improve characteristics such as an increase in driving current by heat radiation. This is a point of the semiconductor device 53A, which will be described later.
[0049]
Further, the semiconductor device 53A has a structure in which the separation groove 54 and the back surface of the conductive path 51 substantially coincide. This structure is a feature of the present invention. Since no step is provided on the back surface of the conductive path 51, the semiconductor device 53 can be moved horizontally as it is.
[0050]
In the present invention, an insulating coating RF such as a solder resist is applied to realize a multilayer structure with the mounting substrate. Then, by exposing a part of the conductive path 51, the wiring of the mounting substrate 10 is extended to the back surface of the semiconductor device 53A. When the semiconductor device is fixed to the mounting substrate 10, the conductive path 51 and the fine metal wire 55A work as a conventional jumping wire, thereby realizing a multilayer structure. This will be described later.
Second Embodiment Explaining Semiconductor Device 53B
The semiconductor device 53B shown in FIG. 9B is substantially the same except that the back surface structure of the conductive path 51 is different from the semiconductor device 51A shown in FIG. 9A. Here, this different part will be described.
[0051]
As can be seen from the figure, the back surface of the conductive path 51 is recessed from the back surface of the insulating resin 50 (the back surface of the insulating resin 50 filled in the separation groove 54). With this structure, multilayer wiring is possible. Details will be described later.
Third Embodiment Explaining Semiconductor Device 53C
The semiconductor device 53C shown in FIG. 9C differs from the semiconductor devices 51A and 51B shown in FIGS. 9A and 9B in the back surface structure of the conductive path 51, and is otherwise substantially the same. Here, this different part will be described.
[0052]
As can be seen from the figure, the back surface of the conductive path 51 protrudes from the back surface of the insulating resin 50 (the back surface of the insulating resin 50 filled in the separation groove 54). With this structure, multilayer wiring is possible. Details will be described later.
Fourth embodiment for explaining a method of manufacturing semiconductor devices 53A to 53C
Next, a method for manufacturing the semiconductor device 53 will be described with reference to FIGS.
[0053]
First, as shown in FIG. 4, a sheet-like conductive foil 60 is prepared. The conductive foil 60 is selected in consideration of the adhesiveness, bonding property, and plating property of the brazing material. As the material, a conductive foil mainly composed of Cu, a conductive foil mainly composed of Al, or Fe is used. A conductive foil made of an alloy of -Ni, an Al-Cu laminate, an Al-Cu-Al laminate, or the like is employed.
[0054]
The thickness of the conductive foil is preferably about 35 μm to 300 μm in consideration of later etching, and here, a copper foil of 70 μm (2 ounces) is employed. However, it is basically good if it is 300 μm or more and 10 μm or less. As will be described later, it is only necessary that the separation groove 61 shallower than the thickness of the conductive foil 60 can be formed.
[0055]
In addition, the sheet-like conductive foil 60 is prepared by being wound in a roll shape with a predetermined width, and this may be conveyed to each step described later, or a conductive foil cut into a predetermined size is prepared, You may convey to each process mentioned later. (See Figure 4 above)
Subsequently, there is a step of removing the conductive foil 60 excluding at least the region to be the conductive path 51 thinner than the thickness of the conductive foil 60.
[0056]
First, a photoresist (etching resistant mask) PR is formed on the Cu foil 60, and the photoresist PR is patterned so that the conductive foil 60 excluding the region to be the conductive path 51 is exposed (see FIG. 5 above). Then, etching may be performed through the photoresist PR (see FIG. 6 above).
[0057]
The depth of the separation groove 61 formed by etching is, for example, 50 μm, and its side surface is a rough surface, so that the adhesiveness with the insulating resin 50 is improved.
[0058]
Further, the side wall of the separation groove 61 has a different structure depending on the removal method. This removal process can employ wet etching, dry etching, laser evaporation, and dicing. Moreover, you may form with a press. In the case of wet etching, ferric chloride or cupric chloride is mainly used as the etchant, and the conductive foil is dipped in the etchant or showered with the etchant. Here, since wet etching is generally non-anisotropic, the side surface has a curved structure as shown in FIG. 6B.
[0059]
In the case of dry etching, etching can be performed anisotropically or non-anisotropically. At present, it is said that Cu cannot be removed by reactive ion etching, but it can be removed by sputtering. Etching can be anisotropic or non-anisotropic depending on sputtering conditions.
[0060]
Further, in the laser, the separation groove can be formed by direct laser light irradiation. In this case, the side surface of the separation groove 61 is formed to be straight.
[0061]
In dicing, it is impossible to form a complicated bent pattern, but it is possible to form a lattice-like separation groove.
[0062]
In FIG. 6, instead of the photoresist PR, a conductive film resistant to the etching solution may be selectively coated. If the conductive film is selectively deposited on the conductive path, this conductive film becomes an etching protective film, and the separation groove can be etched without employing a resist. Possible materials for this conductive film are Ni, Ag, Au, Pt, Pd, and the like. In addition, these corrosion-resistant conductive films have the feature that they can be used as they are as die pads and bonding pads.
[0063]
For example, the Ag coating adheres to Au and also to the brazing material. Therefore, if the Au coating is coated on the back surface of the chip, the chip can be thermocompression bonded to the Ag coating on the conductive path 51 as it is, and the chip can be fixed via a brazing material such as solder. Further, since an Au fine wire can be adhered to the Ag conductive film, wire bonding is also possible. Accordingly, there is an advantage that these conductive films can be used as they are as die pads and bonding pads. (See Figure 6 above)
Subsequently, as shown in FIG. 7, there is a step of mounting the circuit element 52 by electrically connecting it to the conductive foil 60 in which the separation groove 61 is formed.
[0064]
The circuit element 52 includes a semiconductor element 52A such as a transistor, a diode, and an IC chip, and a passive element 52B such as a chip capacitor and a chip resistor. Although the thickness is increased, face-down type semiconductor elements such as CSP, BGA, and SMD can be mounted.
[0065]
Here, a transistor chip 52A as a bare semiconductor chip is die-bonded to the conductive path 51A, and the emitter electrode and the conductive path 51B and the base electrode and the conductive path 51B are fixed by ball bonding by thermocompression bonding or wedge bonding by ultrasonic waves. It is connected via a thin metal wire 55A. Reference numeral 52B denotes a passive element and / or an active element such as a chip capacitor. Here, a chip capacitor is adopted and is fixed by a brazing material such as solder or a conductive paste 55B. (See Figure 7 above)
Further, as shown in FIG. 8, there is a step of attaching an insulating resin 50 to the conductive foil 60 and the separation groove 61. This can be realized by transfer molding, injection molding, or dipping. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding, and a thermoplastic resin such as polyimide resin or polyphenylene sulfide can be realized by injection molding.
[0066]
In the present embodiment, the thickness of the insulating resin coated on the surface of the conductive foil 60 is adjusted so as to cover about 100 μm from the top of the circuit element. This thickness can be increased or decreased in consideration of strength.
[0067]
The feature of this step is that the conductive foil 60 that becomes the conductive path 51 becomes the support substrate until the insulating resin 50 is coated. For example, in a CSP using a printed board or a flexible sheet, a conductive path is formed by using a support board (printed board or flexible sheet) that is not originally required. In the present invention, the conductive foil 60 serving as a support board is It is a material necessary as a conductive path. Therefore, there is a merit that the work can be performed with the constituent materials omitted as much as possible, and the cost can be reduced.
[0068]
Further, since the separation groove 61 is formed shallower than the thickness of the conductive foil, the conductive foil 60 is not individually separated as the conductive path 51. Accordingly, the sheet-like conductive foil 60 is integrated and can be handled from mounting of circuit elements to dicing, and particularly when molding an insulating resin, it is very easy to carry to the mold and mount to the mold. . Furthermore, since it is molded on a sheet-like Cu foil, there is a merit that no resin burr is generated. (See Figure 8 above)
Subsequently, there is a step of chemically and / or physically removing the back surface of the conductive foil 60 and separating it as the conductive path 51. Here, this removal step is performed by polishing, grinding, etching, laser metal evaporation, or the like.
[0069]
In the experiment, the entire surface is cut by about 30 μm by a polishing apparatus or a grinding apparatus, and the insulating resin 50 is exposed from the separation groove 61. This exposed surface is indicated by a dotted line in FIG. Also, FIG. 9A shows an insulating film RF formed on the back surface of the semiconductor element 53A in order to extend the wiring on the mounting substrate. As a result, the conductive paths 51 having a thickness of about 40 μm are separated.
[0070]
9B, when the insulating resin 50 is exposed and the back surface of the conductive path 51 is recessed from the back surface of the insulating resin 50, the entire surface of the conductive foil 60 may be etched.
[0071]
Furthermore, in the case of FIG. 9C, an etching-resistant mask may be formed on the back surface of the conductive path so that a part of the conductive path is exposed and etched. In this case, the conductive path 51 protrudes from the back surface of the insulating resin 50.
[0072]
In either structure, the back surface of the conductive path 51 is exposed from the insulating resin 50. Then, the separation groove 61 is scraped to become the separation groove 54. (See Figure 9 above)
Finally, a conductive material such as solder is applied to the exposed conductive path 51 if necessary, and the multilayer structure of the mounting substrate is taken into consideration, and if necessary, the back surface of the semiconductor device 53 is coated with an insulating resin. To be completed.
[0073]
When a conductive film is applied to the back surface of the conductive path 51, a conductive film may be formed in advance on the back surface of the conductive foil in FIG. In this case, a portion corresponding to the conductive path may be selectively attached. The deposition method is, for example, plating. The conductive film is preferably made of a material that is resistant to etching. When this conductive film or photoresist is employed, the conductive path 51 can be separated only by etching without polishing, and the structure shown in FIG. 9C can be realized.
[0074]
In this manufacturing method, only the semiconductor chip and the chip capacitor are mounted on the conductive foil 60, but these may be arranged in a matrix form as a unit.
[0075]
Alternatively, a single transistor, diode, IC, or LSI may be mounted as an active element (semiconductor chip) to form a discrete type. (See FIGS. 13-14)
A plurality of active elements may be mounted to form a composite semiconductor device. (See FIGS. 11, 12, and 14)
Furthermore, a hybrid IC type may be configured by mounting a transistor, a diode, an IC or LSI as an active element (semiconductor chip), a chip resistor or a chip capacitor as a passive element, and forming a wiring as a conductive path. (See FIGS. 10, 12, 16, 17, and 18)
And when arrange | positioning at matrix form, after isolate | separating a conductive path, it isolate | separates each with a dicing apparatus.
[0076]
By the above manufacturing method, the flat semiconductor device 53 in which the conductive path 51 is embedded in the insulating resin 50 and the back surface of the insulating resin 50 and the back surface of the conductive path 51 substantially coincide with each other can be realized.
[0077]
This manufacturing method is characterized in that the insulating path 50 can be used as a support substrate and the conductive path 51 can be separated. The insulating resin 50 is a necessary material for embedding the conductive path 51 and does not require an unnecessary support substrate. Therefore, it has the characteristics that it can be manufactured with a minimum amount of material and cost can be reduced. Further, since there is no conductive foil at the dicing line, the blade can be prevented from being clogged. Further, when a package using a ceramic substrate is molded and diced, the blade is severely damaged and worn. However, in the present invention, since only the resin is diced, there is an advantage that the life of the blade can be extended.
[0078]
Note that the thickness of the insulating resin formed above the surface of the conductive path 51 can be adjusted when the insulating resin is attached. Therefore, the thickness of the semiconductor element 53 has a feature that it can be made thicker or thinner, although it depends on the circuit element to be mounted. Here, a semiconductor device in which a 40 μm conductive path 51 and a semiconductor element are embedded in an insulating resin 50 having a thickness of 400 μm is obtained.
Fifth embodiment for explaining the structure of a hybrid integrated circuit device
Next, the hybrid integrated circuit device of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a hybrid integrated circuit device, and FIG. 2 is a cross-sectional view taken along line AA of FIG. A structure in which the semiconductor device 53A in FIG. 9A, the semiconductor device 53B in FIG. 9B, and the semiconductor device 53C in FIG. 9C are fixed to the mounting substrate 10 is shown in FIGS. 2A, 2B, and 2C.
[0079]
First, the mounting substrate 10 will be described. As the mounting board 10 on which the semiconductor device 53 is mounted, a printed board, a ceramic board, a flexible sheet board, or a metal board can be considered. Since the conductive pattern 21 is formed on the surface of the mounting substrate 10, at least the surface of the substrate is insulated in consideration of electrical insulation. Since the printed circuit board, the ceramic substrate, and the flexible sheet substrate are made of an insulating material, the conductive pattern 21 may be formed on the surface as it is. However, in the case of a metal substrate, an insulating material is deposited on at least the surface, and a conductive pattern 21 is deposited thereon. In the present embodiment, the conductive pattern formed on the mounting substrate 10 is referred to as a conductive pattern 21, and the conductive pattern supported by the insulating resin 50 of the semiconductor device 53 is described as a conductive path 51.
[0080]
As can be seen from FIG. 3, the conductive pattern 21 includes a die pad 21A, a wiring 21B, a bonding pad 21C, a chip resistor 23, an electrode 21D for fixing the chip capacitor 24, and an electrode 21E for fixing the semiconductor device 53 (note that Since it is difficult to discriminate in FIG. 3, it is shown in FIG. 1 and FIG. 2), and further, an external connection electrode 21F is provided if necessary. Incidentally, the electrode 21E for fixing the semiconductor device 53 and the wiring 21B integrated therewith are indicated by thick solid lines in FIG.
[0081]
On the other hand, in the semiconductor device 53, the conductive path 51 supported by the insulating resin 50 includes a conductive path 51A to which the semiconductor chip 52A is fixed, a conductive path 51B serving as a bonding pad, and a conductive path 51A and 51B. There is a conductive path 51E to be a wiring provided in.
[0082]
1 indicates a contact portion 24 electrically connected to the electrode 21E on the mounting substrate 10 on the back surface of the semiconductor device 53. The contact portion 24 and the back surface structure shown in FIGS. 2A to 2C allow the wiring 21B of the mounting substrate 10 to extend on the back surface of the semiconductor device 53.
[0083]
Since the structure of the semiconductor device 53 has been described in the first to fourth embodiments, a detailed description thereof will be omitted.
Back surface structure of the semiconductor device 53A shown in FIG. 2A
An insulating coating RF is provided on the back surface of the semiconductor device 53A, and the contact portion 24 is exposed through the insulating coating RF. As can be seen from FIG. 8, the semiconductor device 53 has a structure in which all the conductive paths are originally exposed from the back surface. However, the conductive path 51 can be covered by employing the insulating coating RF.
[0084]
Therefore, the wiring 21 </ b> B formed on the mounting substrate 10 can be extended to the back surface of the semiconductor device 53.
[0085]
The first feature of the present invention resides in that the conductive path 51A sealed with the insulating resin 50 as the semiconductor device 53 and fixed with the semiconductor chip 52A is fixed with the conductive path 21 on the mounting substrate 10.
[0086]
As is clear from the cross-sectional view of FIG. 2, the heat generated in the semiconductor chip 52A is radiated to the conductive path 21E on the mounting substrate 10 through the conductive path 51A. Since the conductive path 21E is a conductive material and excellent in heat conduction, the heat of the semiconductor chip 52A can be transmitted to the mounting substrate 10 side. Further, the heat transmitted to the thin metal wire 55A can also be transmitted to the conductive path through the conductive path 51B having a relatively large size in a rectangular parallelepiped. These conductive paths 21 are integrated with the wiring 21B, and heat is released to the external atmosphere via the wiring 21B. Therefore, the temperature rise of the semiconductor chip 10 can be prevented, and the drive current can be increased as much as the temperature rise of the semiconductor chip can be suppressed.
[0087]
In particular, when the mounting substrate 10 is made of a metal substrate, the heat of the semiconductor chip 52A can be transmitted to the metal substrate via the conductive path 21. This metal substrate functions as a large heat sink and as a heat sink, and can prevent the temperature of the semiconductor chip from rising further than the other mounting substrates described above.
[0088]
In the case of a metal substrate, an insulating material is applied to the surface in consideration of a short circuit between conductive paths, and the material may be inorganic or organic. Here, an epoxy resin, a polyimide resin, or the like is employed. Since this material is formed as thin as 30 to 300 μm, the thermal resistance can be made relatively small, but furthermore, the thermal resistance can be further reduced by mixing fillers such as silica and alumina in the insulating resin. it can.
[0089]
The second feature is the insulating coating RF. By covering the insulating film RF so that the contact portion 24 described above is exposed, the wiring 21B can be extended under the semiconductor device 53A. Therefore, by using the conductive path 51 and the thin metal wire 55A of the semiconductor device 53A, a multilayer wiring structure can be realized, and the wiring on the mounting substrate 10 can be simplified. The conventional hybrid IC shown in FIG. 20 and the hybrid IC shown in FIG. 3 are designed with the same substrate size. Comparing the patterns, the hybrid IC of the present invention has a coarser wiring pattern interval and fewer fine patterns. This is because the conductive path 51 on the semiconductor device 53 side is connected to the conductive pattern 21 on the mounting substrate 10 through the opening of the insulating coating RF, and the others are covered with the insulating coating RF. Since this conductive path can also be formed as a wiring, a crossover is possible, and a multilayer structure is realized together with the fine metal wires. Therefore, if the semiconductor device is prepared in advance in the process of mounting the element on the mounting substrate, the number of crossover bondings employed on the mounting substrate can be reduced. Furthermore, it has a feature that the number of complicated wiring patterns for avoiding crossing can be reduced on the mounting board.
[0090]
Furthermore, the third feature is in the metal fine wire, and has the feature that the bonding process can be reduced. In the hybrid IC of FIG. 20, the wire diameter of the metal thin wire is properly used by dividing into a semiconductor element handling a small signal and a semiconductor element handling a large signal. That is, a thin metal wire for a semiconductor element that handles a small signal is indicated by a thin solid line, and a 40 μm Au wire is adopted. And this Au thin wire is ball bonded. A thin metal wire for a semiconductor element that handles a large signal is indicated by a thick line, and an Al wire of 100 μm to 300 μm is adopted. Here, a 150 μm Al line is used as a jumping line for the gate electrode of the power MOS, and a 300 μm Al line is used as the source electrode of the power MOS, the base of the power transistor, the emitter electrode, and the jumping line. These Al wires are stitch bonded. In addition, you may employ | adopt Au wire instead of Al wire.
[0091]
The present invention is a semiconductor device in which an Au wire is connected to a semiconductor element, an Au wire is connected to a bonding pad, a wiring 51E extending integrally with the bonding pad, and a die pad are integrally sealed with an insulating resin 50. Features the device.
[0092]
By preparing all the semiconductor elements adopting the Au thin metal wires as the semiconductor device 53, there is an advantage that Au bonding on the mounting substrate 10 becomes unnecessary and the bonding process can be reduced. Furthermore, the number of circuit elements including this semiconductor element can be greatly reduced. Conventionally, it has been necessary to prepare three types of bonders by bonding the three types of fine metal wires, and to bond them with the respective bonders. However, the present invention has an advantage that the bonder of Au wires can be omitted. Therefore, the facilities can be simplified, and the mounting substrate can be simply mounted on two types of bonders, and the process can be simplified.
[0093]
In particular, a semiconductor device can be formed as a discrete element, a composite element, or even a hybrid IC. In theory, all circuit elements can be incorporated as a semiconductor device, and can be mounted on a mounting substrate. The number of element sticking can be greatly reduced.
[0094]
The fifth feature is that a small semiconductor element such as 0.45 × 0.5 thickness 0.25 mm can be adopted, and the cost can be reduced.
[0095]
As explained in the conventional example, even when trying to adopt a small chip with low price, in the conventional chip, solder is blown up to the side of the chip in a small chip of 0.45 × 0.5mm and thickness 0.25mm. There was a problem of short circuit.
[0096]
However, in the present invention, an Au coating (for example, a bump) is deposited on the back surface of the semiconductor chip 52A, and the conductive path 51 and the semiconductor chip 52A are fixed through the bump, and the semiconductor device 53 is completed and then fixed to the mounting substrate 10. doing. Therefore, even if the semiconductor device 53 is fixed using solder, the side surface of the semiconductor chip 52A is covered with the insulating resin 50, so that the above-described short circuit problem is eliminated and a small-sized semiconductor chip can be employed. Became.
The back surface structure of the semiconductor device 53B shown in FIG. 2B
The semiconductor device 53B is substantially the same as the semiconductor element 53A of FIG. 2A, and the difference is that the conductive path 51 exposed on the back surface of the semiconductor device 53B is recessed from the insulating resin 50.
[0097]
The feature of the present invention resides in the recess of the conductive path 51. Due to this recess, the conductive path 51 of the semiconductor device 53B and the conductive pattern 21 on the mounting substrate 10 side can have a desired interval. Therefore, like the semiconductor device 53A, the wiring 21B can be extended under the semiconductor device 53B. Therefore, by using the conductive path 51 and the thin metal wire 55A of the semiconductor device 53B, a multilayer wiring structure can be realized, and the wiring on the mounting substrate 10 can be simplified.
[0098]
Note that the insulating film RF may be coated on the back surface as in the semiconductor device 53A.
The back surface structure of the semiconductor device 53C shown in FIG. 2C
The semiconductor device 53C is substantially the same as the semiconductor elements 53A and 53B in FIGS. 2A and 2B, and is different in that the conductive path 51 exposed on the back surface of the semiconductor device 53B protrudes from the insulating resin 50. is there.
[0099]
A feature of the present invention resides in the protrusion of the conductive path 51. This protruding structure can provide a desired interval between the conductive path 51 of the semiconductor device 53C and the conductive pattern 21 on the mounting substrate 10 side. Therefore, like the semiconductor devices 53A and 53B, the wiring 21B can be extended under the semiconductor device 53C. Therefore, by using the conductive path 51 and the thin metal wire 55A of the semiconductor device 53C, a multilayer wiring structure can be realized, and the wiring on the mounting substrate 10 can be simplified.
[0100]
Note that the insulating film RF may be coated on the back surface as in the semiconductor device 53A.
Next, a circuit employed in the present hybrid integrated circuit device and a portion of the circuit configured as a semiconductor device will be described with reference to FIGS.
[0101]
FIG. 19 shows an audio circuit. From the left, an Audio Amp 1ch circuit unit, an Audio Amp 2ch circuit unit, and a switching power supply circuit are surrounded by a thick dashed line.
[0102]
In each circuit portion, a circuit surrounded by a solid line is formed as a semiconductor device. First, in the Audio Amp 1ch circuit portion, three types of semiconductor devices and two semiconductor devices integrated with the 2ch circuit portion are prepared.
[0103]
As shown in FIG. 19, in the first semiconductor device 30A, a current mirror circuit composed of TR1 and TR2 and a differential circuit composed of TR3 and TR4 are integrally formed. This semiconductor device 30A is shown in FIG. Here, four transistor chips of 0.55 × 0.55 × 0.24 mm are adopted and bonded with Au fine wires. The size of the semiconductor device 30A is 2.9 × 2.9 × 0.5 mm.
[0104]
A contact portion indicated by a dotted line is 0.3 mmφ. The numbers shown in the figure are terminal numbers, and B and E indicate a base and an emitter. The same applies to FIG. 11 and subsequent figures.
[0105]
The second semiconductor device 31A is configured by forming a part of the pre-driver circuit with TR6 and D2 in FIG. The pre-driver circuit is composed of TR6, D2, R3, and R8, and drives the output stages TR9 and TR10. This semiconductor device 31A is shown in FIG. 11, and the diode D2 is formed by using a semiconductor chip in which two TRs are constituted by one chip and using a PN junction between the base and the emitter. Here, D2 is a chip size of 0.75 × 0.75 × 0.145 mm, TR6 is a chip size of 0.55 × 0.55 × 0.24 mm, and the outer shape of the semiconductor device 31A is 2.1 × 2. 5 × 0.5 mm.
[0106]
The third semiconductor device 32A constitutes a differential constant current circuit for allowing a stable current to flow through the differential circuit against fluctuations in the power supply voltage, and is constituted by TR5, TR15, and D1 in FIG. D1 is a constant current bias diode of the differential circuit and the pre-driver circuit. This semiconductor device 32A is shown in FIG. 12, TR5 and TR15 have a size of 0.55 × 0.55 × 0.24 mm, and D1 has a size of 0.75 × 0.75 × 0.145 mm. The external shape of 32A is 2.1 × 3.9 × 0.5 mm.
[0107]
The fourth semiconductor device 33A is the temperature compensation transistor TR8 shown in FIG. 19, and compensates the idling current against the temperature fluctuation of the mounting board. This TR8 is composed of the one-chip semiconductor element (0.75 × 0.75 × 0.145) shown in FIG. When this is formed as the semiconductor device 33A, the outer shape is 2.3 × 1.6 × 0.5 mm.
[0108]
In the fifth semiconductor device 34A, two chips of TR7 of a pre-driver constant current circuit constituted by TR7, R6, and R7 of FIG. 19 and TR17 constituting a pre-driver constant current circuit of an Audio Amp 2ch circuit unit are one package. It has become. As shown in FIG. 14, the semiconductor device 34A is composed of two single transistors (0.55 × 0.55 × 0.24 mm), and the outer shape is 2.3 × 3.4 × 0. .5 mm.
[0109]
Note that the two series of semiconductor devices 34A may be individually configured. In this case, the semiconductor device 35 in which only one chip shown in FIG. 15 is sealed is employed. The external shape of the semiconductor device 35 is 2.3 × 1.6 × 0.5 mm.
[0110]
Further, 30B, 31B, and 33B shown in FIG. 19 are the same circuits as 30A, 31A, and 33A, and thus description thereof is omitted.
[0111]
TR9 and TR10 are output stage power transistors, and R1, C1 and C2 are elements for preventing abnormal oscillation.
On the other hand, the switching power supply circuit section shown on the right side of FIG. 19 is a power supply voltage switching circuit composed of TR41, TR51, R41, R43, R51, R53, and a power supply composed of TR43, TR53, R40, R42, R50, R52. A voltage switching comparator, a high-frequency correction circuit composed of diodes D45, D55, C43, and C53, a rectifying diode composed of diodes D42, D43, D52, and D53, and the like.
[0112]
The sixth semiconductor device 36 is a power supply circuit of FIG. 19 in which diodes D42 and D43 and a Zener diode D45 are formed in one package. A semiconductor chip mounted as a semiconductor device is constituted by a TR chip, and diodes D42 and D43 are constituted by a base-collector PN junction. In FIG. 16, TR and Zener diode surrounded by a dotted line are mounted on one chip, and D45 uses the Zener diode of this element. In addition, in order to compensate for the voltage drop due to the temperature rise of the Zener diode, a TR base-emitter diode incorporated together is used.
The outer shape of the TR with a Zener is 0.6 × 0.6 × 0.24, and the outer shapes of the other TRs are 0.35 × 0.35 × 0.24. And the external shape of the package in which these are sealed is 1.9 × 4.4 × 0.5 mm.
[0113]
The seventh semiconductor device 37 is a power supply circuit of FIG. 19 in which diodes D52 and D53 and a Zener diode D55 are formed in one package. In a semiconductor chip mounted as a semiconductor device, transistors corresponding to D53 and D52 are PNP type, and the mounting form is substantially the same although the structure is slightly different.
The eighth semiconductor device 38 of FIG. 18 is obtained by integrating the circuits of FIGS. 16 and 17 and TR43 and TR53 into one package. Note that the outer shape of the package in which these are sealed is 4 × 5.7 × 0.5 mm. The semiconductor device 38 is mounted as the semiconductor device 53 of FIG.
As described above, this semiconductor device can be configured as a discrete type in which one TR is mounted, or a hybrid IC type in which a plurality of TRs are mounted to form a desired circuit. Here, although only TR is configured, a plurality of elements including IC, LSI, system LSI, and passive elements may be mounted. In the experiment, 5 × 5.7 × 0.5 mm is the maximum, but a larger size may be used. Further, this semiconductor device can be used as a semiconductor device in which a semiconductor element is embedded, and an element can be mounted on the back surface.
The semiconductor device mounted on the mounting substrate 10 is shown in FIG. 3, and the wiring pattern is simplified.
[0114]
FIG. 21 illustrates how much the size is reduced by employing the semiconductor device of the present invention. The photograph shown in the figure is the same magnification, and shows a single SMD employing a lead frame from the left, a composite SMD employing a lead frame, and a semiconductor device of the present invention. A single product SMD is molded with one TR, and a composite TR is molded with two TRs. The semiconductor device of the present invention is the semiconductor device 30A shown in FIG. 10, and four TRs are sealed. As is apparent from the figure, the size of the semiconductor device is only slightly larger than that of the composite SMD including the lead frame, even though the element twice that of the composite SMD is sealed. The semiconductor device 35 of FIG. 15 in which one TR is sealed is shown on the rightmost side. As will be understood, a small and thin semiconductor device can be realized by the present invention, which is most suitable for a portable electronic device.
[0115]
【The invention's effect】
As is apparent from the above description, in the present invention, the back surface of the semiconductor device is covered with an insulating resin, the conductive path on the back surface is recessed, or further protruded, so that the mounting substrate is formed on the back surface of the semiconductor device. The provided wiring can be extended. Therefore, a multi-layer structure can be realized by the conductive path, the fine metal wire, and the wiring on the mounting substrate of the semiconductor device. Therefore, an electronic circuit can be configured without using an expensive multilayer substrate as a mounting substrate. Conventionally, a multilayer substrate of 2, 3, 4... Is sometimes used, but the number of layers can be reduced by employing this semiconductor device.
[0116]
In addition, a thin and lightweight circuit device composed of a semiconductor element, a conductive path, and an insulating resin is used, and the conductive path to which the back surface of the semiconductor element is fixed is exposed from the insulating resin. A hybrid integrated circuit device that can be fixed to the conductive path on the mounting substrate side can be provided.
[0117]
Therefore, the heat of the built-in circuit element can be dissipated to the mounting substrate side, and a thin and lighter hybrid integrated circuit device can be provided. ,
Further, since the side surface of the conductive path has a curved structure, even if the entire circuit device generates heat, the conductive path can be prevented from coming off and warping. In addition, since it has an excellent heat dissipation structure as a hybrid integrated circuit device, it is possible to suppress the temperature rise of the circuit device itself, and to prevent the conduction path from coming off and warping. Therefore, it is possible to improve the reliability of the entire hybrid integrated circuit device on which a thin and light circuit device is mounted.
[0118]
Furthermore, if a metal substrate is employed as the mounting substrate, it is possible to provide a hybrid integrated circuit device that can suppress heat generation of the mounted circuit device and allow a drive current to flow.
[Brief description of the drawings]
FIG. 1 illustrates a semiconductor device of the present invention.
FIG. 2 is a cross-sectional view illustrating a semiconductor device of the present invention.
FIG. 3 is a diagram illustrating a hybrid integrated circuit device on which the semiconductor device is mounted.
FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 5 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 6 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 7 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 8 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 9 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 10 is a diagram illustrating a semiconductor device of the present invention.
FIG. 11 illustrates a semiconductor device of the present invention.
FIG. 12 is a diagram illustrating a semiconductor device of the present invention.
FIG. 13 illustrates a semiconductor device of the present invention.
14 is a diagram illustrating a semiconductor device of the present invention. FIG.
FIG. 15 is a diagram illustrating a semiconductor device of the present invention.
FIG 16 illustrates a semiconductor device of the present invention.
FIG 17 illustrates a semiconductor device of the invention.
18 is a diagram illustrating a semiconductor device of the present invention. FIG.
FIG. 19 is a diagram illustrating an example of a circuit mounted on the hybrid integrated circuit device.
FIG. 20 is a diagram illustrating a conventional hybrid integrated circuit device.
FIG. 21 is a diagram comparing a conventional semiconductor device and a semiconductor device of the present invention.
[Explanation of symbols]
10 Mounting board
21 Conductive pattern
21B wiring
53 Semiconductor device

Claims (9)

A semiconductor device is mounted on a mounting substrate having a plurality of electrodes and wirings on the surface, and the electrodes of the mounting substrate and the conductive paths exposed from the back surface of the semiconductor device are electrically connected via connection means. In a hybrid integrated circuit device ,
The semiconductor device includes a plurality of conductive paths, a semiconductor chip electrically connected to the conductive paths, an insulating covering the semiconductor chip and the conductive paths, and exposing and supporting the back surfaces of the conductive paths integrally. A conductive resin, and an insulating film that selectively covers the back surface of the conductive path and the back surface of the insulating resin,
The back surface of the conductive path is formed inside the back surface of the insulating resin, the wiring extends a space formed between the conductive path covered with the insulating film and the mounting substrate, A hybrid integrated circuit device , wherein wiring and the conductive path intersect . The hybrid integrated circuit device according to claim 1 , wherein a side surface of the conductive path has a curved structure. The hybrid integrated circuit device according to claim 1, wherein a conductive film is provided on the conductive path. Wherein the addition to the active element and / or passive elements of the semiconductor chip, the conductive path electrically incorporated the connected and characterized in that the active element and / or the passive elements also include circuit is formed Item 4. A hybrid integrated circuit device according to Item 1 . 2. The hybrid integrated circuit device according to claim 1 , wherein the conductive path is made of a Cu, Al, Fe—Ni alloy, a Cu—Al laminate, or an Al—Cu—Al laminate. 4. The hybrid integrated circuit device according to claim 3 , wherein the conductive film is made of Ni, Au, Ag, or Pd, and has an eaves. 4. The hybrid integrated circuit device according to claim 3 , wherein the conductive film of the conductive path and the semiconductor chip are connected by a thin bonding wire. 2. The hybrid integrated circuit device according to claim 1 , wherein the connecting means is made of a brazing material, a conductive ball, a conductive paste, or an anisotropic conductive resin. The hybrid integrated circuit device according to claim 1 , wherein the conductive path is formed as a wiring formed on the semiconductor device side, and crosses over a wiring provided on the hybrid integrated circuit device side.

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