JP2001352010A - Semiconductor device and hybrid integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve similar effect as in the adoption of a multilayer substrate, since packaging substrates adopt the multilayer substrate to compose a circuit although there is a hybrid integrated circuit device, where a circuit device is packaged on a printed circuit board, a ceramic substrate, a flexible sheet, or the like. SOLUTION: Insulation covering RF is adopted on the back surface of a semiconductor device 53, and a conductive path 51 is allowed to dent or project, thus extending a wiring 21B on a packaging substrate 10 on the back surface of the semiconductor device, and hence achieving the similar effect as the case, where the packaging substrate is made multilayered equivalently by the conductive path of the semiconductor 53 and metal small-gauge wire.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device in which a thin and lightweight semiconductor device is mounted on a mounting substrate to reduce the mounting substrate.

[0002]

2. Description of the Related Art Conventionally, in a hybrid integrated circuit device set in an electronic device, a conductive pattern is formed on, for example, a printed circuit board, a ceramic substrate, or a metal substrate, and an active element such as an LSI or a discrete TR is formed thereon. , A passive element such as a chip capacitor, a chip resistor or a coil is mounted. Then, the conductive pattern and the element are electrically connected to realize a circuit having a predetermined function.

FIG. 19 shows an example of a circuit. This circuit is an audio circuit, and the elements shown here are:
It is implemented as shown in FIG.

[0004] In Fig. 20, the outermost rectangular line is the mounting substrate 1 on which at least the surface is insulated. On top of this, a conductive pattern 2 made of Cu is adhered. The conductive pattern 2 includes an external extraction electrode 2A, a wiring 2B, a die pad 2C, a bonding pad 2D, an electrode 4 for fixing the passive element 3, and the like.

The die pad 2C has a TR, a diode,
A composite element, an LSI, or the like is in a bare chip shape and is fixed via solder. The electrodes on the fixed chip and the bonding pads 2D are connected to the thin metal wires 5A, 5A.
B, 5C are electrically connected. The thin metal wires are generally classified into a small signal and a large signal. The small signal portion employs an Au wire 5A of about 40 μmφ, and the large signal portion employs an Au wire or an Al wire of about 100 to 300 μmφ. I have. In particular, since the large signal has a large wire diameter, the cost is taken into consideration, and the 150 μmφ Al wire 5B
The Al wire 5C of μmφ is selected.

A power TR 6 for flowing a large current is fixed to a heat sink 7 on the die pad 2C in order to prevent a temperature rise of the chip.

The wiring 2B extends to various places in order to make the external extraction electrode 2A, die pad 2C, bonding pad 2D and electrode 4 into circuits. When the wirings cross each other due to the position of the chip and the way the wirings extend, the jumping lines 8A and 8B are adopted.

[0008]

Recently, chips having a very small chip size of 0.45.times.0.5 mm and a thickness of 0.25 mm and having a low unit price have come to be sold. However, when this chip is to be fixed by solder, the solder rises to the side surface of the chip and short-circuits, so that there is a problem that the chip cannot be used for a hybrid integrated circuit board.

When a package in which a semiconductor element is fixed to a lead frame is mounted on a hybrid integrated circuit board, the size of the package is very large, so that there is a problem that the size of the hybrid integrated circuit board becomes large.

Further, when a complex circuit is formed on a hybrid integrated circuit board, a multilayer hybrid integrated circuit board is required.
There was also a problem that it was difficult to adopt from the viewpoint of cost.

As described above, even if an attempt is made to reduce the cost by adopting a hybrid integrated circuit board, the cost rises because a very small chip cannot be mounted, the assembling process is lengthened, and a multilayer board is adopted. There was a problem of inviting.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and firstly, a plurality of conductive paths electrically separated by separation grooves, and a semiconductor chip fixed on the conductive paths. And an insulating resin that covers the semiconductor chip and is filled in the separation groove between the conductive paths and exposes and integrally supports the back surface of the conductive path, and a part of the back surface of the conductive path is exposed. This problem is solved by providing an insulating coating on the back surface of the conductive path.

Second, a plurality of conductive paths electrically separated by the separation grooves, a semiconductor chip fixed on the conductive paths, and a semiconductor chip that covers the semiconductor chips and fills the separation grooves between the conductive paths. An insulating resin that exposes the back surface of the conductive path and integrally supports the conductive path, wherein the back surface of the conductive path is provided so as to be recessed from the back surface of the insulating resin. .

Third, a plurality of conductive paths electrically separated by the separation groove, a semiconductor chip fixed on the conductive path, and a semiconductor chip that covers the semiconductor chip and fills the separation groove between the conductive paths. And an insulating resin that exposes the back surface of the conductive path and integrally supports the conductive path, and the back surface of the conductive path is provided so as to protrude from the back surface of the insulating resin.

Fourth, the problem is solved by providing an insulating coating on the back surface of the conductive path so that a part of the back surface of the conductive path is exposed.

Fifth, the problem can be solved by forming the side surface of the conductive path with a curved structure.

Sixth, the problem is solved by providing a conductive film on the conductive path.

Seventh, the problem is solved by mounting at least one of the semiconductor chips.

Eighth, in addition to the semiconductor chip, an active element and / or a passive element are electrically connected to the conductive path and incorporated therein, and a circuit is formed including the active element and / or the passive element. This will solve the problem.

Ninth, the conductive path is formed of Cu, Al, Fe-
This problem is solved by using a Ni alloy, a laminate of Cu-Al, and a laminate of Al-Cu-Al.

Tenth, the conductive film is made of Ni, Au,
It is made of Ag or Pd, and is solved by forming an eave.

Eleventh, the problem is solved by connecting the conductive film of the conductive path and the electrode on the semiconductor chip with a bonding thin wire or solder.

Twelfth, a mounting substrate having at least a surface insulated and having a plurality of electrodes and wirings, a plurality of conductive paths electrically separated by separation grooves, and a semiconductor chip fixed on the conductive paths. An insulating resin that covers the semiconductor chip and is filled in the separation groove between the conductive paths to expose and support the back surface of the conductive path integrally; and so that a part of the back surface of the conductive path is exposed. A semiconductor device provided with an insulating coating on the back surface of the conductive path, wherein the back surface of the conductive path and the electrode are fixed via connection means, and the wiring extends under the insulating coating. This will solve the problem.

Thirteenth, a mounting substrate having at least a surface insulated and having a plurality of electrodes and wirings, a plurality of conductive paths electrically separated by separation grooves, and a semiconductor chip fixed on the conductive paths. An insulating resin that covers the semiconductor chip and is filled in the separation groove between the conductive paths to expose and support the back surface of the conductive path integrally; and a back surface of the conductive path than a back surface of the insulating resin. Has a semiconductor device provided in a concave shape, the back surface of the conductive path and the electrode are fixed via connecting means, and the wiring is extended on the back surface of the semiconductor device. Things.

Fourteenth, a mounting substrate having at least a surface insulated and having a plurality of electrodes and wirings, a plurality of conductive paths electrically separated by separation grooves, and a semiconductor chip fixed on the conductive paths. An insulating resin that covers the semiconductor chip and is filled in the separation groove between the conductive paths to expose and support the back surface of the conductive path integrally; and a back surface of the conductive path than a back surface of the insulating resin. Has a semiconductor device provided so as to protrude, the back surface of the conductive path and the electrode are fixed via connecting means, and the wiring is extended on the back surface of the semiconductor device. Things.

Fifteenth, the problem is solved by providing an insulating coating on the back surface of the conductive path so that a part of the back surface of the conductive path is exposed.

Sixteenth, the problem is solved by forming the side surface of the conductive path with a curved structure.

Seventeenth, the problem can be solved by providing a conductive film on the conductive path.

Eighteenthly, in addition to the semiconductor chip, an active element and / or a passive element are electrically connected to the conductive path and incorporated therein, and a circuit is formed including the active element and / or the passive element. This will solve the problem.

Nineteenthly, the conductive paths are made of Cu, Al, Fe
The problem is solved by comprising a laminate of -Ni alloy, Cu-Al, and a laminate of Al-Cu-Al.

Twentiethly, the conductive film is made of Ni, Au,
It is made of Ag or Pd, and is solved by forming an eave.

Twenty-first, the problem is solved by connecting the conductive film of the conductive path and the electrode on the semiconductor chip with a bonding thin wire or solder.

Twenty-second, the problem can be solved by forming the connection means from a brazing material, a conductive ball, a conductive paste or an anisotropic conductive resin.

[0034]

[0035]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, a conductive path,
The present invention relates to a thin semiconductor device including a connection means and a minimum necessary amount of insulating resin for sealing, and by adopting the thin semiconductor device as a mounting substrate,
The present invention relates to a hybrid integrated circuit device capable of reducing the size of a mounting substrate, shortening the manufacturing process of the hybrid integrated circuit device, and reducing the number of layers of a multilayer substrate. First, a semiconductor device will be described below.

FIG. 1 shows a thin semiconductor device 53 fixed to a mounting substrate 10. FIG. 2 illustrates three types of mounting structures of the thin semiconductor device 53. FIG. 3 shows this thin semiconductor device 53.
And a circuit element mounted on a mounting substrate 10 to form a hybrid integrated circuit device 13. Furthermore, FIG.
FIG. 9 illustrates a method of manufacturing the semiconductor device, FIGS. 10 to 18 illustrate a semiconductor device formed based on the circuit on the right side, and FIG. FIG. First Embodiment Explaining Semiconductor Device 53A First, a specific structure of the first semiconductor device 53A will be described with reference to FIG. 9A. The semiconductor device 53A has conductive paths 51A to 51C embedded in an insulating resin 50.
A semiconductor chip 52A is fixed on A, and if necessary, a passive element 52B is fixed on the conductive paths 51B and 51C. Then, the conductive paths 51 </ b> A to 51 </ b> A
51C.

This structure comprises a semiconductor chip 52A, a circuit element 52B composed of a passive element and / or an active element, a plurality of conductive paths 51A, 51B, 51C,
A, 51B, and 51C are formed of three materials of insulating resin 50 embedded therein.
Separation grooves 54 filled with zeros are provided. The conductive paths 51A to 51C are supported by the insulating resin 50.

As the insulating resin, a thermosetting resin such as an epoxy resin, or a thermoplastic resin such as a polyimide resin or polyphenylene sulfide can be used. As the insulating resin, any resin can be adopted as long as the resin can be hardened using a mold, or can be coated by dipping or coating. Further, as the conductive path 51, a conductive foil mainly composed of Cu, a conductive foil mainly composed of Al, a conductive foil made of an alloy such as Fe—Ni, a laminate of Al—Cu,
A laminated plate of —Cu—Al or the like can be used. Especially A
l-Cu-Al has a structure resistant to warpage. Of course, other conductive materials are also possible, especially a conductive material that can be etched, a conductive material that evaporates by laser, or a separation groove 5.
4 is preferably a relatively soft material that can be formed by pressing.

The means for connecting the semiconductor element 52A and the circuit element 52B is a thin metal wire 55A, a conductive ball made of a brazing material, a flat conductive ball, a brazing material 55B made of solder or the like, and Ag.
A conductive paste 55C such as a paste, a conductive film or an anisotropic conductive resin is used. These connection means are selected depending on the type of the semiconductor element or the circuit element 52 and the mounting form. For example, in the case of a bare semiconductor chip, the metal thin wire 55A is selected for connection between the surface electrode and the conductive path 51B, and CS
For P and SMD, solder balls and solder bumps are selected. The chip resistor and chip capacitor are solder 55B
Is selected. When mounted in a face-down manner like a CSP, the upward and lateral protrusions of the fine metal wires are eliminated, and a package having a substantially chip size can be realized.

The semiconductor element 52A and the conductive path 51A are fixed by using a conductive film. Here, at least one conductive film is sufficient.

The material considered as the conductive film is A
g, Au, Pt, Pd, brazing material, or the like, and is coated by deposition, plating, sintering, or coating under a low or high vacuum such as evaporation, sputtering, or CVD.

For example, Ag adheres to Au and also to the brazing material. Therefore, if the back surface of the chip is covered with the Au film, the semiconductor chip can be thermocompression bonded by directly covering the conductive path 51A with the Ag film, the Au film, and the solder film, and the chip is fixed via a brazing material such as solder. it can. Here, the conductive film may be formed on the uppermost layer of the conductive film laminated in a plurality of layers. For example, on the conductive path 51A of Cu, two layers of a Ni film and an Au film are sequentially applied, an Ni film, a Cu film, three layers of a solder film are sequentially applied, an Ag film, One in which two layers of the Ni film are sequentially coated can be formed. There are many other types and laminated structures of these conductive films, but they are omitted here.

In the semiconductor device 53A, since the conductive path 51 is supported by the insulating resin 50 as a sealing resin, a support substrate for bonding and supporting the conductive path is not required, and the conductive path 5
1, an element 52 and an insulating resin 50. This configuration is a feature of the present invention. The conductive path of the conventional circuit device is supported and bonded by a support substrate (printed substrate, ceramic substrate or flexible sheet), or is supported by a lead frame, so that a configuration that is originally unnecessary is added. However, this semiconductor device
It consists of the minimum necessary elements, and can eliminate the need for a support substrate.
It has the feature of being thin and inexpensive.

In addition to the above configuration, there is provided an insulating resin 50 which covers the circuit element 52 and is filled in the separation groove 54 between the conductive paths 51 and integrally supported.

A separation groove 54 is formed between the conductive paths 51.
By filling the insulating resin 50 here, there is an advantage that mutual insulation is achieved.

Further, there is provided an insulating resin 50 which covers the element 52 and is filled in the separation groove 54 between the conductive paths 51 to expose the back surface of the conductive path 51 and integrally support the same.

The fact that the back surface of the conductive path is exposed is one of the features of the present invention. The back surface of the conductive path can be used for connection to the outside, and the feature is that the through hole used in the printed circuit board using the support substrate can be eliminated.

Further, the semiconductor element 52A is made of a brazing material, Au,
When directly fixed via a conductive film such as Ag, the back surface of the conductive path 51 is exposed, so that heat generated from the semiconductor element 52A can be transmitted to the mounting substrate via the conductive path 51A. In particular, the present invention is effective for a semiconductor chip capable of improving characteristics such as an increase in drive current due to heat radiation. This is a point of the semiconductor device 53A, which will be described later.

The semiconductor device 53A has a structure in which the separation groove 54 and the back surface of the conductive path 51 are substantially coincident. This structure is a feature of the present invention, and has a feature that the semiconductor device 53 can be horizontally moved as it is because no step is provided on the back surface of the conductive path 51.

In the present invention, an insulating film RF such as a solder resist is applied to realize a multilayer structure with the mounting board. By exposing a part of the conductive path 51, the wiring of the mounting substrate 10 is extended to the back surface of the semiconductor device 53A. When the present semiconductor device is fixed to the mounting substrate 10, the conductive path 51 and the thin metal wire 55A function as conventional jumping wires, realizing a multilayer structure. This will be described later. Second Embodiment Explaining Semiconductor Device 53B Semiconductor Device 53B shown in FIG. 9B
Is different from the semiconductor device 51A shown in FIG. 9A in the back surface structure of the conductive path 51, and is otherwise substantially the same. Here, this different part will be described.

As can be seen from the drawing, the back surface of the conductive path 51 is more concave than the back surface of the insulating resin 50 (the back surface of the insulating resin 50 filled in the separation groove 54). With this structure, multilayer wiring can be realized. Details will be described later. Third Embodiment for Demonstrating Semiconductor Device 53C FIG.
The semiconductor device 53C shown in FIG. 9C is different from the semiconductor devices 51A and 51B shown in FIGS. 9A and 9B in the back surface structure of the conductive path 51, and is otherwise substantially the same. Here, this different part will be described.

As can be seen from the figure, the back surface of the conductive path 51 protrudes from the back surface of the insulating resin 50 (the back surface of the insulating resin 50 filled in the separation groove 54). With this structure, multilayer wiring can be realized. Details will be described later. Fourth Embodiment for Demonstrating Method of Manufacturing Semiconductor Devices 53A to 53C Next, referring to FIGS.
3 will be described.

First, as shown in FIG. 4, a sheet-shaped conductive foil 60 is prepared. The material of the conductive foil 60 is selected in consideration of the adhesion of the brazing material, the bonding property, and the plating property.
As the material, a conductive foil mainly composed of Cu, a conductive foil mainly composed of Al or a conductive foil composed of an alloy of Fe-Ni, a laminated body of Al-Cu, a laminated body of Al-Cu-Al, etc. are adopted. Is done.

The thickness of the conductive foil is preferably about 35 μm to 300 μm in consideration of the later etching.
A 0 μm (2 oz) copper foil was employed. But 300μ
Basically, it is good even if it is more than m or less than 10 μm. As will be described later, it is only necessary that the separation groove 61 shallower than the thickness of the conductive foil 60 can be formed.

The sheet-shaped conductive foil 60 is prepared by being wound into a roll with a predetermined width, and may be conveyed to each step described later, or the conductive foil cut into a predetermined size may be used. It may be prepared and transported to each step described later.
(Refer to FIG. 4 above.) Subsequently, there is a step of removing the conductive foil 60 except for at least a region to become the conductive path 51, with a thickness smaller than the thickness of the conductive foil 60.

First, a photoresist (etching resistant mask) PR is formed on the Cu foil 60, and the photoresist PR is patterned so as to expose the conductive foil 60 excluding the region that becomes the conductive path 51 (see FIG. 5). reference). Then, etching may be performed through the photoresist PR (see FIG. 6).

The depth of the separation groove 61 formed by etching is, for example, 50 μm, and the side surface thereof is rough, so that the adhesiveness with the insulating resin 50 is improved.

The side wall of the separation groove 61 has a different structure depending on the removing method. This removal step can employ wet etching, dry etching, laser evaporation, and dicing. Also, it may be formed by pressing. In the case of wet etching, ferric chloride or cupric chloride is mainly used as an etchant, and the conductive foil is dipped in the etchant or showered with the etchant. Here, wet etching is generally non-anisotropically etched, so the side surface is
As shown in FIG. 6B, a curved structure is obtained.

In the case of dry etching, anisotropy,
Non-anisotropic etching is possible. At present, it is said that it is impossible to remove Cu by reactive ion etching, but it can be removed by sputtering. Further, etching can be performed anisotropically or non-anisotropically depending on sputtering conditions.

In the case of a laser, a separation groove can be formed by directly irradiating a laser beam. In this case, the side surface of the separation groove 61 is formed straight.

In dicing, it is impossible to form a bent complicated pattern, but it is possible to form a lattice-shaped separation groove.

In FIG. 6, a conductive film having corrosion resistance to an etching solution may be selectively coated instead of the photoresist PR. When the conductive film is selectively applied to a portion to be a conductive path, the conductive film serves as an etching protective film, and the separation groove can be etched without employing a resist.
Materials that can be considered as the conductive film include Ni, Ag, and A.
u, Pt or Pd. Moreover, these corrosion-resistant conductive films have a feature that they can be utilized as they are as die pads and bonding pads.

For example, an Ag film adheres to Au and also adheres to a brazing material. Therefore, if the Au film is coated on the back surface of the chip, the chip can be thermocompression-bonded to the Ag film on the conductive path 51 as it is, and the chip can be fixed via a brazing material such as solder. Further, since the Au thin wire can be bonded to the Ag conductive film, wire bonding is also possible. Therefore, there is an advantage that these conductive films can be used as die pads and bonding pads as they are. (The above figure 6
Then, as shown in FIG. 7, the conductive foil 6 on which the separation groove 61 is formed.
There is a step of electrically connecting and mounting the circuit element 52 at 0.

The circuit element 52 is a semiconductor element 52A such as a transistor, a diode, or an IC chip, and a passive element 52B such as a chip capacitor or a chip resistor. Although the thickness is increased, a face-down type semiconductor element such as CSP, BGA, SMD, etc. can also be mounted.

Here, the transistor chip 52A as a bare semiconductor chip is die-bonded to the conductive path 51A, and the emitter electrode and the conductive path 51B, and the base electrode and the conductive path 51B are bonded by thermocompression bonding such as ball bonding or ultrasonic bonding. Are connected via a thin metal wire 55A fixed by the above. Reference numeral 52B denotes a passive element and / or an active element such as a chip capacitor. Here, a chip capacitor is adopted and fixed by a brazing material such as solder or a conductive paste 55B. (Figure 7 above)
Further, as shown in FIG. 8, there is a step of attaching an insulating resin 50 to the conductive foil 60 and the separation groove 61. this is,
Transfer mold, injection mold,
Alternatively, it can be realized by dipping. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding, and a thermoplastic resin such as a polyimide resin and polyphenylene sulfide can be realized by injection molding.

In the present embodiment, the thickness of the insulating resin coated on the surface of the conductive foil 60 is about 1 mm from the top of the circuit element.
It is adjusted so as to cover about 00 μm. This thickness can be increased or reduced in consideration of strength.

The feature of this step is that the conductive foil 60 serving as the conductive path 51 becomes a support substrate until the insulating resin 50 is covered. For example, in a CSP employing a printed board or a flexible sheet, a conductive path is formed by employing a supporting substrate (printed board or flexible sheet) which is not originally required. Is a material necessary for the conductive path. for that reason,
There is an advantage that the operation can be performed while omitting the constituent materials as much as possible, and the cost can be reduced.

Since the separation groove 61 is formed shallower than the thickness of the conductive foil, the conductive foil 60 is not individually separated as the conductive path 51. Therefore, the sheet-shaped conductive foil 60
As a whole, it can handle everything from mounting of circuit elements to dicing, and especially when molding an insulating resin, it has the feature that the work of transporting it to a die and mounting it on a die becomes very easy. Furthermore, since it is molded into a sheet-like Cu foil,
There is also an advantage that resin burrs do not occur. (Refer to FIG. 8 above.) Subsequently, there is a step of chemically and / or physically removing the back surface of the conductive foil 60 and separating it as the conductive path 51. Here, the removing step is performed by polishing, grinding, etching, laser metal evaporation, or the like.

In the experiment, the entire surface was shaved by about 30 μm by a polishing device or a grinding device, and the insulating resin 50 was removed from the separation groove 61.
Is exposed. This exposed surface is indicated by a dotted line in FIG. FIG. 9A shows an example in which an insulating film RF is formed on the back surface of the semiconductor element 53A in order to extend the wiring on the mounting substrate. As a result, the conductive paths 51 having a thickness of about 40 μm are separated.

As shown in FIG. 9B, when employing a structure in which the insulating resin 50 is exposed and the back surface of the conductive path 51 is recessed from the back surface of the insulating resin 50, the conductive foil 60 may be entirely etched.

Further, in the case of FIG. 9C, an etching-resistant mask may be formed on the back surface of the conductive path so that a part of the conductive path is exposed, and etching may be performed. In this case, the conductive path 51
Project from the back surface of the insulating resin 50.

In either structure, the insulating resin 50
, The back surface of the conductive path 51 is exposed. Then, the separation groove 61 is shaved to form the separation groove 54. (See FIG. 9 above.) Finally, a conductive material such as solder is adhered to the exposed conductive path 51 if necessary, and an insulating resin is formed on the back surface of the semiconductor device 53 if necessary in consideration of the multilayer structure of the mounting substrate. To complete the semiconductor device.

When a conductive film is applied to the back surface of the conductive path 51, the conductive film may be formed in advance on the back surface of the conductive foil shown in FIG. In this case, the portion corresponding to the conductive path may be selectively applied. The deposition method is, for example, plating. The conductive film is preferably made of a material having resistance to etching. When the conductive film or the photoresist is used, the conductive path 5 is formed only by etching without polishing.
1 and the structure of FIG. 9C can be realized.

In the present manufacturing method, only the semiconductor chip and the chip capacitor are mounted on the conductive foil 60, but they may be arranged as a unit in a matrix.

A single transistor, diode, IC or LSI may be mounted as an active element (semiconductor chip) to form a discrete type. (See FIGS. 13 and 14.) A plurality of active elements may be mounted to form a composite semiconductor device. (Refer to FIG. 11, FIG. 12, and FIG. 14.) Furthermore, transistors, diodes, ICs or LSIs are mounted as active elements (semiconductor chips), chip resistors and chip capacitors are mounted as passive elements, and wiring is formed as conductive paths. May be configured as a hybrid IC type. (Refer to FIG. 10, FIG. 12, FIG. 16, FIG. 17, FIG. 18, and FIG. 18.) When the conductive paths are separated in a matrix, they are separated individually by a dicing device after the conductive paths are separated.

According to the above manufacturing method, the insulating resin 50
In this case, a flat semiconductor device 53 can be realized in which the conductive path 51 is buried in the substrate and the back surface of the insulating resin 50 and the back surface of the conductive path 51 substantially match.

This manufacturing method has a feature that the conductive path 51 can be separated using the insulating resin 50 as a supporting substrate. The insulating resin 50 is a material necessary as a material for embedding the conductive path 51, and does not require an unnecessary supporting substrate.
Therefore, it has a feature that it can be manufactured with a minimum amount of material and that cost reduction can be realized. Also, since there is no conductive foil at the dicing line, clogging of the blade can be prevented. Furthermore, when a package employing a ceramic substrate is molded and diced, the blade is severely broken and worn. However, in the present invention, since only the resin is diced, there is an advantage that the life of the blade can be extended.

The thickness of the insulating resin formed above the surface of the conductive path 51 can be adjusted when the insulating resin is adhered. Therefore, the thickness of the semiconductor element 53 has a feature that it can be thick or thin, though it depends on the circuit element to be mounted. Here, a semiconductor device is obtained in which a conductive path 51 and a semiconductor element of 40 μm are embedded in an insulating resin 50 of 400 μm thickness. Fifth Embodiment Explaining Structure of Hybrid Integrated Circuit Device Next, a hybrid integrated circuit device of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of the hybrid integrated circuit device, and FIG. 2 is a sectional view taken along line AA of FIG. 2A, 2B, and 2C show a structure in which the semiconductor device 53A of FIG. 9A, the semiconductor device 53B of FIG. 9B, and the semiconductor device 53C of FIG. 9C are fixed to the mounting substrate 10.

First, the mounting board 10 will be described. As the mounting board 10 on which the semiconductor device 53 described above is mounted,
A printed circuit board, a ceramic substrate, a flexible sheet substrate or a metal substrate is conceivable. This mounting board 10
Since the conductive pattern 21 is formed on the surface, at least the surface of the substrate is insulated in consideration of electrical insulation. Since the printed circuit board, the ceramic substrate, and the flexible sheet substrate themselves are made of an insulating material, the conductive pattern 21 may be formed on the surface as it is. However, in the case of a metal substrate, at least the surface is coated with an insulating material, and the conductive pattern 21 is coated thereon. In the present embodiment, the conductive pattern formed on the mounting substrate 10 is referred to as a conductive pattern 21 and the semiconductor device 5
The conductive patterns supported by the third insulating resin 50 are separately described as conductive paths 51.

As can be seen from FIG.
Are die pad 21A, wiring 21B, bonding pad 21C, chip resistor 23, chip capacitor 2
An electrode 21D to which the semiconductor device 53 is fixed, and an electrode 21E to which the semiconductor device 53 is fixed (note that it is difficult to discriminate in FIG. 3 and is shown in FIGS. 1 and 2), and further, an external connection electrode 2 provided as necessary.
1F is provided. The electrode 21E for fixing the semiconductor device 53 and the wiring 21B integrated with the electrode 21E are shown in FIG.
This is indicated by a thick solid line.

On the other hand, in the semiconductor device 53, the conductive path 51 supported by the insulating resin 50 includes a conductive path 51A to which the semiconductor chip 52A is fixed, a conductive path 51B serving as a bonding pad, and a conductive path 51A. There is a conductive path 51E which is a wiring provided integrally with 51B.

The elliptical portion in FIG.
3 shows a contact portion 24 electrically connected to an electrode 21E on the mounting substrate 10 on the back surface of the mounting substrate 3. 2A to 2C, the wiring 21B of the mounting substrate 10 can extend to the back surface of the semiconductor device 53.

Since the structure of the semiconductor device 53 has been described in the first to fourth embodiments, detailed description will be omitted. Back surface structure of semiconductor device 53A shown in FIG. 2A An insulating film RF is provided on the back surface of the present semiconductor device 53A, and the contact portion 24 is exposed through the insulating film RF. This semiconductor device 53 is similar to that of FIG.
As can be seen from the figure, the structure is such that all the conductive paths are originally exposed from the back surface, but by employing the insulating film RF,
The conductive path 51 can be covered.

Therefore, the wiring 2 formed on the mounting substrate 10
1B can be extended to the back surface of the semiconductor device 53.

The first feature of the present invention is that the semiconductor device 53 is sealed in an insulating resin 50 and the conductive path 51A to which the semiconductor chip 52A is fixed is connected to the conductive path 2 on the mounting board 10.
1 and to be fixed.

As is clear from the cross-sectional view of FIG. 2, the heat generated in the semiconductor chip 52A is radiated to the conductive path 21E on the mounting board 10 via the conductive path 51A. Conductive path 2
Since 1E is a conductive material and has excellent heat conduction, the heat of the semiconductor chip 52A can be transmitted to the mounting substrate 10 side. Further, the heat transmitted to the thin metal wire 55A can be transmitted to the conductive path via the relatively large rectangular conductive path 51B. These conductive paths 21 are integrated with the wiring 21B, and heat is released to the outside atmosphere via the wiring 21B. Therefore, the temperature rise of the semiconductor chip 10 can be prevented, and the drive current can be increased by the amount corresponding to the suppression of the temperature rise of the semiconductor chip.

In particular, when the mounting substrate 10 is formed of a metal substrate, the heat of the semiconductor chip 52A can be transmitted to the metal substrate via the conductive path 21. This metal substrate functions as a large heat sink and a heat radiating plate, and can prevent the temperature of the semiconductor chip from rising more than the other mounting substrates described above.

In the case of a metal substrate, an insulating material is applied to the surface in consideration of a short circuit between the conductive paths.
Organic matter can be considered. Here, an epoxy resin, a polyimide resin, or the like is employed. This material is 30-300μ
Since it is formed as thin as m, the thermal resistance can be relatively reduced. However, the thermal resistance can be further reduced by mixing a filler such as silica or alumina into the insulating resin.

The second feature lies in the insulating film RF. By coating the insulating film RF so that the above-mentioned contact portion 24 is exposed, the wiring 21 is formed under the semiconductor device 53A.
B can be extended. Therefore, the semiconductor device 53A
By using the conductive path 51 and the fine metal wire 55A,
A multilayer wiring structure can be realized, and wiring on the mounting board 10 can be simplified. The conventional hybrid IC shown in FIG. 20 and FIG.
Are designed with the same substrate size. When the respective patterns are compared, the hybrid IC of the present invention has a coarser wiring pattern interval and a smaller number of fine patterns. This is because the conductive path 51 on the semiconductor device 53 side is connected to the conductive pattern 21 on the mounting substrate 10 via the opening of the insulating film RF, and the other portions are covered with the insulating film RF. Since the conductive path can be formed as a wiring, crossover is possible, and a multilayer structure is realized together with the thin metal wires. Therefore, if the semiconductor device is prepared in advance in the process of mounting the element on the mounting board, the semiconductor device has a feature that the number of times of crossover bonding adopted on the mounting board can be reduced. Further, it has a feature that a complicated wiring pattern for avoiding intersection can be reduced on the mounting board.

Further, the third feature is that the thin metal wire is used, and has a feature that the number of bonding steps can be reduced. The hybrid IC shown in FIG. 20 is divided into a semiconductor element for handling small signals and a semiconductor element for handling large signals, and uses different diameters of thin metal wires. That is, a thin metal wire for a semiconductor element that handles a small signal is indicated by a thin solid line, and employs a 40 μm Au wire. This Au thin wire is ball-bonded.
A thin metal wire for a semiconductor element that handles a large signal is indicated by a thick line, and an Al wire of 100 μm to 300 μm is employed. Here, a 150 μm Al line is adopted as a jumping line for the gate electrode of the power MOS, and the power MO
A 300 μm Al wire is used as the source electrode of S, the base and the emitter electrode of the power transistor, and the jumping line. These Al wires are stitch-bonded. Note that an Au wire may be used instead of the Al wire.

According to the present invention, the semiconductor element to which the Au line is connected, the bonding pad to which the Au line is connected, the wiring 51E extending integrally with the bonding pad, and the die pad are integrally sealed with the insulating resin 50. Semiconductor device.

By preparing all the semiconductor elements employing the Au thin metal wires as the semiconductor device 53, the bonding of Au on the mounting substrate 10 becomes unnecessary, and the advantage that the bonding step can be reduced can be achieved. Have. Further, the number of mounting of circuit elements including this semiconductor element can be greatly reduced. Conventionally, it has been necessary to prepare three types of bonders by using the three types of thin metal wires and bond them with the respective bonders. However, the present invention has an advantage that the bonder of the Au wire can be omitted. Therefore, the equipment can be simplified, and the mounting substrate can be simply mounted on two types of bonders, and the process can be simplified.

In particular, the semiconductor device may be used as a discrete element, a composite element, or a hybrid IC.
Theoretically, all the circuit elements can be incorporated as a semiconductor device, and the number of fixed elements on the mounting substrate can be greatly reduced.

The fifth feature is that the thickness is 0.45 × 0.5.
Small semiconductor elements such as 25 mm can be adopted,
The cost can be reduced.

As described in the conventional example, even if an attempt is made to adopt a low-cost small chip, the conventional
In a small chip having a size of 0.5 mm and a thickness of 0.25 mm, there is a problem that the solder blows up on the side surface of the chip to cause a short circuit.

However, in the present invention, an Au film (for example, a bump) is applied to the back surface of the semiconductor chip 52A, and the conductive path 51 and the semiconductor chip 52A are fixed via the bump. 10 is fixed. Therefore, even if the present semiconductor device 53 is fixed using solder, since the side surface of the semiconductor chip 52A is covered with the insulating resin 50, the above-described short circuit problem is eliminated, and a small-sized semiconductor chip can be adopted. Became. Back surface structure of semiconductor device 53B shown in FIG. 2B The semiconductor device 53B is substantially the same as the semiconductor element 53A of FIG. 2A, except that the conductive path 51 exposed on the back surface of the semiconductor device 53B is smaller than the insulating resin 50. It is concave.

The feature of the present invention resides in the recess of the conductive path 51. Due to this recess, the conductive path 5 of the semiconductor device 53B is formed.
1 and the conductive pattern 21 on the mounting board 10 side can have a desired interval. Therefore, the semiconductor device 53A
Similarly to the above, the wiring 21B can be extended below the semiconductor device 53B. Therefore, the conductive path 5 of the semiconductor device 53B
1. By using the thin metal wires 55A, a multilayer wiring structure can be realized, and the wiring on the mounting substrate 10 can be simplified.

Incidentally, similarly to the semiconductor device 53A, the back surface may be coated with an insulating film RF. Back surface structure of semiconductor device 53C shown in FIG. 2C This semiconductor device 53C is a semiconductor device 5C shown in FIGS. 2A and 2B.
3A and 53B, except that the conductive path 51 exposed on the back surface of the semiconductor device 53B is made of an insulating resin 50B.
It is a point that is more protruding.

A feature of the present invention resides in the protrusion of the conductive path 51. This protruding structure is formed by the conductive path 51 of the semiconductor device 53C.
A desired space can be provided between the conductive pattern 21 and the conductive pattern 21 on the mounting substrate 10 side. Therefore, the semiconductor devices 53A,
Similarly to 3B, the wiring 21B can extend below the semiconductor device 53C. Therefore, by using the conductive path 51 and the thin metal wire 55A of the semiconductor device 53C, a multilayer wiring structure can be realized, and the wiring on the mounting substrate 10 can be simplified.

Incidentally, similarly to the semiconductor device 53A, the back surface may be coated with an insulating film RF. Next, a circuit adopted in the hybrid integrated circuit device while adopting FIG. 19 and a portion of this circuit configured as a semiconductor device are shown in FIG.
This will be described with reference to FIGS.

FIG. 19 shows an audio circuit, from left to right, an Audio Amp 1ch circuit section and an Audio Am
The p2ch circuit section and the switching power supply circuit are indicated by thick dashed lines.

In each circuit section, a circuit surrounded by a solid line is formed as a semiconductor device. First Au
In the dio Amp 1ch circuit unit, three types of semiconductor devices and two semiconductor devices integrated with the 2ch circuit unit are prepared.

As shown in FIG. 19, the first semiconductor device 30A includes a current mirror circuit including TR1 and TR2 and a current mirror circuit T1.
A differential circuit composed of R3 and TR4 is integrally configured. This semiconductor device 30A is shown in FIG. Here, four transistor chips of 0.55 × 0.55 × 0.24 mm are employed and bonded with Au thin wires. The size of the semiconductor device 30A is 2.9.
× 2.9 × 0.5 mm.

The contact portion shown by the dotted line is 0.3
mmφ. The numbers shown in the figure are terminal numbers,
B and E indicate a base and an emitter. These are shown in FIG.
The same applies to the following.

The second semiconductor device 31A corresponds to the TR shown in FIG.
6. D2 constitutes a part of the pre-driver circuit.
The pre-driver circuit is composed of TR6, D2, R3, and R8, and drives the output stages TR9 and TR10. This semiconductor device 31A is shown in FIG. 11, and the diode D2 is formed using a semiconductor chip having two TRs formed as one chip and utilizing a PN junction between the base and the emitter. Here, D2 is 0.75 × 0.75
× 0.145mm, TR6 is 0.55 × 0.55 ×
The semiconductor device 31A has a chip size of 0.24 mm.
Is 2.1 × 2.5 × 0.5 mm.

The third semiconductor device 32A constitutes a differential constant current circuit for allowing a stable current to flow through the differential circuit in response to fluctuations in the power supply voltage, and includes TR5, TR15, and D1 shown in FIG.
It is composed of D1 is a constant current bias diode of the differential circuit and the pre-driver circuit. This semiconductor device 32A is shown in FIG.
5 is 0.55 × 0.55 × 0.24 mm, D1 is
0.75 × 0.75 × 0.145mm size,
The external shape of the semiconductor device 32A is 2.1 × 3.9 × 0.5 m
m.

The fourth semiconductor device 33A is a temperature compensation transistor TR8 shown in FIG. 19, and compensates for an idling current with respect to a temperature change of a mounting substrate.
This TR8 is composed of the one-chip semiconductor device (0.75 × 0.75 × 0.145) shown in FIG. When this is formed as a semiconductor device 33A, the outer shape becomes 2.
It is 3 × 1.6 × 0.5 mm.

The fifth semiconductor device 34A corresponds to the TR shown in FIG.
This is a package in which two chips, TR7, a pre-driver constant current circuit composed of R7, R6, and R7, and TR17, which constitutes a pre-driver constant current circuit of the Audio Amp 2ch circuit unit, are included in one package. This semiconductor device 34
A is a single transistor (0.
55 × 0.55 × 0.24 mm), and the outer shape is 2.3 × 3.4 × 0.5 mm.

Note that the two semiconductor devices 34A may be individually configured. In this case, a semiconductor device 35 in which only one chip shown in FIG. 15 is sealed is employed. The outer shape of the semiconductor device 35 is 2.3 × 1.6 × 0.5 mm.

Further, 30B, 31B, 33B shown in FIG.
Is the same circuit as 30A, 31A, and 33A, and the description is omitted.

TR9 and TR10 are output stage power transistors, and R1, C1 and C2 are elements for preventing abnormal oscillation. On the other hand, the switching power supply circuit section shown on the right side of FIG. 19 includes TR41, TR51, R41, R43, R5
1, a power supply voltage switching circuit composed of R53, TR4
3, a power supply voltage switching comparator composed of TR53, R40, R42, R50, and R52, a diode D
It comprises a high-frequency correction circuit composed of 45, D55, C43, and C53, a rectifying diode composed of diodes D42, D43, D52, and D53.

The sixth semiconductor device 36 has a configuration in which the diodes D42 and D43 and the Zener diode D45 are formed into one package in the power supply circuit of FIG.
A semiconductor chip mounted as a semiconductor device is constituted by a TR chip, and diodes D42 and D43 are constituted by a PN junction between a base and a collector. In FIG. 16, TR and a Zener diode surrounded by a dotted line are mounted on one chip, and D45 utilizes the Zener diode of this element. Further, in order to compensate for the voltage drop due to the temperature rise of the Zener diode, a diode between the base and the emitter of the TR, which is incorporated together, is used.
The external dimensions of the TR with Zener are 0.6 × 0.6 ×
0.24, other TR dimensions are 0.35 x 0.35 x
0.24. The outer shape of the package in which these are sealed is 1.9 × 4.4 × 0.5 mm.

The seventh semiconductor device 37 has a structure in which the diodes D52 and D53 and the Zener diode D55 are included in one package in the power supply circuit of FIG.
In a semiconductor chip mounted as a semiconductor device, transistors corresponding to D53 and D52 are PNP transistors, and although the structure is slightly different, the mounting form is substantially the same. FIG.
The eighth semiconductor device 38 of FIG. 8 includes the circuits of FIGS. 16 and 17 and TR43 and TR53 in one package. Note that the outer shape of the package in which these are sealed is 4
× 5.7 × 0.5 mm. And this semiconductor device 3
8 is mounted as the semiconductor device 53 of FIG. As described above, the present semiconductor device can be configured as a discrete type in which one TR is mounted or a hybrid IC type in which a plurality of TRs are mounted to form a desired circuit. Here, although only the TR is used, a plurality of elements including an IC, an LSI, a system LSI, and a passive element may be mounted. In the experiment, 5 × 5.7 × 0.5 mm is the maximum, but a larger size may be used. Further, this semiconductor device can be used as a semiconductor device in which a semiconductor element is embedded, and the element can be mounted on the back surface. FIGS. 3A and 3B show the semiconductor devices mounted on the mounting board 10, and the wiring patterns are simplified.

FIG. 21 illustrates how the size is reduced by employing the semiconductor device of the present invention. The photographs shown at the same magnification show a single SMD employing a lead frame, a composite SMD employing a lead frame, and a semiconductor device of the present invention from the left. Single SMD has one TR, composite TR has 2
One TR is molded. The semiconductor device of the present invention is the semiconductor device 30A shown in FIG.
Are sealed. As is clear from the figure, the composite SM
Despite the fact that the element twice as large as D is sealed, the size of the semiconductor device is limited to the composite SM including the lead frame.
It is only slightly larger than D. The semiconductor device 35 of FIG. 15 in which one TR is sealed is shown on the rightmost side. As can be seen from the above, a small and thin semiconductor device can be realized by the present invention, which is most suitable for portable electronic equipment.

[0115]

As is apparent from the above description, according to the present invention, the back surface of the semiconductor device is coated with an insulating resin, the conductive path on the back surface is depressed, and furthermore, the semiconductor device is formed by projecting. The wiring provided on the mounting substrate can be extended on the back surface. Therefore, a multilayer structure can be realized by the conductive paths of the semiconductor device, the fine metal wires, and the wiring on the mounting substrate. Therefore, an electronic circuit can be configured without employing an expensive multilayer board as a mounting board. Conventionally, a multi-layer substrate of 2, 3, 4... May be employed, but by employing this semiconductor device, the number of layers can be reduced.

Further, a thin and light-weight circuit device comprising a semiconductor element, a conductive path and an insulating resin with minimum requirements is employed, and the conductive path to which the back surface of the semiconductor element is fixed is exposed from the insulating resin. Therefore, it is possible to provide a hybrid integrated circuit device that can be fixed to the conductive path on the mounting substrate side.

Therefore, the heat of the built-in circuit elements can be radiated to the mounting substrate side, and a thinner and lighter hybrid integrated circuit device can be provided. Further, since the side surface of the conductive path has a curved structure, the conductive path can be prevented from coming off and warping even when the entire circuit device generates heat. In addition, since the hybrid integrated circuit device has an excellent heat dissipation structure, the temperature rise of the circuit device itself can be suppressed, and furthermore, the disconnection and warpage of the conductive path can be prevented. Therefore, the reliability of the entire hybrid integrated circuit device on which the thin and lightweight circuit device is mounted can be improved.

Furthermore, if a metal substrate is employed as the mounting substrate, heat generation of the mounted circuit device can be suppressed, and a hybrid integrated circuit device capable of supplying a higher drive current can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 3 is a diagram illustrating a hybrid integrated circuit device on which the present semiconductor device is mounted.

FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a diagram illustrating a semiconductor device of the present invention.

FIG. 11 illustrates a semiconductor device of the present invention.

FIG. 12 is a diagram illustrating a semiconductor device of the present invention.

FIG. 13 is a diagram illustrating a semiconductor device of the present invention.

FIG. 14 is a diagram illustrating a semiconductor device of the present invention.

FIG. 15 is a diagram illustrating a semiconductor device of the present invention.

FIG. 16 is a diagram illustrating a semiconductor device of the present invention.

FIG. 17 illustrates a semiconductor device of the present invention.

FIG. 18 is a diagram illustrating a semiconductor device of the present invention.

FIG. 19 is a diagram illustrating an example of a circuit mounted on the hybrid integrated circuit device.

FIG. 20 is a diagram illustrating a conventional hybrid integrated circuit device.

FIG. 21 is a diagram comparing a conventional semiconductor device with a semiconductor device of the present invention.

[Explanation of symbols]

 Reference Signs List 10 mounting board 21 conductive pattern 21B wiring 53 semiconductor device

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 25/04 H01L 25/04 Z 25/18 (72) Inventor Eihisa Maehara 2 Keihanhondori, Moriguchi-shi, Osaka 5-5-5 Sanyo Electric Co., Ltd. (72) Inventor Noriyoshi Sakai 2-5-2-5 Keiyo Hondori, Moriguchi City, Osaka Prefecture (72) Inventor Hitoshi Takagishi Keihan Moriguchi City, Osaka Prefecture 2-5-5 Hondori Sanyo Electric Co., Ltd. (72) Inventor Koji Takahashi 29 Kita-cho, Isesaki-shi, Gunma Kanto Sanyo Electronics Co., Ltd. (72) Inventor Kazuhisa Kusano 29 Kita-cho, Isesaki-shi, Gunma Address Kanto Sanyo Electronics Co., Ltd. F term (reference) 4M109 AA01 BA07 CA05 CA07 CA10 CA21 DA09 DB15 GA02

Claims (22)

[Claims] A plurality of conductive paths electrically separated by a separation groove; a semiconductor chip fixed on the conductive path; a semiconductor chip covering the semiconductor chip and filled in the separation groove between the conductive paths; An insulating resin that exposes the back surface of the conductive path and integrally supports the conductive path, wherein an insulating film is provided on the back surface of the conductive path so that a part of the back surface of the conductive path is exposed. . A plurality of conductive paths electrically separated by a separation groove; a semiconductor chip fixed on the conductive path; and a semiconductor chip that covers the semiconductor chip and is filled in the separation groove between the conductive paths. An insulating resin that exposes and integrally supports the back surface of the conductive path, wherein the back surface of the conductive path is provided so as to be recessed from the back surface of the insulating resin. 3. A plurality of conductive paths electrically separated by a separation groove, a semiconductor chip fixed on the conductive path, a semiconductor chip covering the semiconductor chip, and filled in the separation groove between the conductive paths. An insulating resin that exposes the back surface of the conductive path and integrally supports the conductive path, wherein the back surface of the conductive path is provided so as to protrude from the back surface of the insulating resin. 4. The semiconductor device according to claim 2, wherein an insulating film is provided on the back surface of the conductive path so that a part of the back surface of the conductive path is exposed. 5. The semiconductor device according to claim 1, wherein a side surface of the conductive path has a curved structure. 6. The semiconductor device according to claim 1, wherein a conductive film is provided on the conductive path. 7. The semiconductor device according to claim 1, wherein at least one of the semiconductor chips is mounted. 8. An active element and / or a passive element other than the semiconductor chip is electrically connected to the conductive path to be built therein, and a circuit is formed including the active element and / or the passive element. The semiconductor device according to claim 1, wherein: 9. The conductive path according to claim 1, wherein the conductive path comprises a laminate of Cu, Al, Fe—Ni alloy, Cu—Al, or a laminate of Al—Cu—Al. 2. A semiconductor device according to claim 1. 10. The semiconductor device according to claim 6, wherein the conductive film is made of Ni, Au, Ag, or Pd, and has an eave. 11. The semiconductor device according to claim 6, wherein the conductive film of the conductive path and the electrode on the semiconductor chip are connected by a thin bonding wire or solder. 12. A mounting substrate having at least a surface insulated and having a plurality of electrodes and wirings; a plurality of conductive paths electrically separated by separation grooves; a semiconductor chip fixed on the conductive paths; An insulating resin which covers the semiconductor chip and is filled in the separation groove between the conductive paths and exposes the back surface of the conductive path to integrally support the conductive chip; A semiconductor device having an insulating film provided on the back surface of the path, wherein the back surface of the conductive path and the electrode are fixed via connection means, and the wiring extends below the insulating film. A hybrid integrated circuit device characterized by the above. 13. A mounting substrate having at least a surface insulated and having a plurality of electrodes and wiring; a plurality of conductive paths electrically separated by separation grooves; a semiconductor chip fixed on the conductive paths; An insulating resin that covers the semiconductor chip and is filled in the separation groove between the conductive paths and exposes and integrally supports the back surface of the conductive path; A semiconductor device provided with a concave portion, wherein the back surface of the conductive path and the electrode are fixed via connection means, and the wiring extends to the back surface of the semiconductor device. Integrated circuit device. 14. A mounting substrate having at least a surface insulated and having a plurality of electrodes and wirings; a plurality of conductive paths electrically separated by separation grooves; a semiconductor chip fixed on the conductive paths; An insulating resin that covers the semiconductor chip and is filled in the separation groove between the conductive paths to expose and support the back surface of the conductive path integrally; Wherein the back surface of the conductive path and the electrode are fixed via connection means, and the wiring extends to the back surface of the semiconductor device. Integrated circuit device. 15. The hybrid integrated circuit device according to claim 13, wherein an insulating coating is provided on the back surface of the conductive path so that a part of the back surface of the conductive path is exposed. 16. The hybrid integrated circuit device according to claim 12, wherein a side surface of said conductive path has a curved structure. 17. The hybrid integrated circuit device according to claim 12, wherein a conductive film is provided on said conductive path. 18. An active element and / or a passive element other than the semiconductor chip is electrically connected to the conductive path to be built therein, and a circuit is formed including the active element and / or the passive element. 13. The method according to claim 12, wherein
The hybrid integrated circuit device according to claim 17. 19. The conductive path may be formed of Cu, Al, Fe—Ni.
19. The hybrid integrated circuit device according to claim 12, comprising an alloy, a laminate of Cu-Al, and a laminate of Al-Cu-Al. 20. The hybrid integrated circuit device according to claim 17, wherein the conductive film is made of Ni, Au, Ag, or Pd, and has an eave. 21. The hybrid integrated circuit device according to claim 17, wherein the conductive film of the conductive path and the electrode on the semiconductor chip are connected by a bonding thin wire or solder. 22. The hybrid integrated circuit device according to claim 12, wherein said connection means is made of a brazing material, a conductive ball, a conductive paste, or an anisotropic conductive resin.