JP3626475B2 - Time division processing type code processing circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a time division processing type code processing circuit used for encoding and decoding when transmitting a plurality of information signals at the same time. For example, the present invention relates to a multipoint or a plurality of transmission signals at a plurality of transmission rates. It can be used for a high-speed wireless communication apparatus and a broadband satellite communication apparatus that simultaneously perform digital transmission using a carrier.
[0002]
[Prior art]
For example, when multiple independent signals are simultaneously digitally transmitted using multiple carriers, for example, the information is transmitted after encoding on the transmission side for the purpose of compressing the amount of information, and the information is encoded on the reception side. The original information is reproduced by decoding the received information.
[0003]
Moreover, the transmission rates of a plurality of independent signals to be transmitted are not necessarily the same.
Therefore, when this type of digital signal transmission is performed, encoding has conventionally been performed using a circuit as shown in FIG. In the example of FIG. 7, it is assumed that five independent signals are input to the five input terminals.
[0004]
The signal input to each input terminal is input to one pre-assigned encoding circuit and processed. Each encoding circuit encodes an input signal in accordance with an encoding type and an encoding rate designated by the control circuit, and outputs a processing result to one output terminal assigned in advance. Therefore, it is necessary to provide the same number of independent encoding circuits as the number of signals to be transmitted or the number of input terminals.
[0005]
On the other hand, the reception side conventionally decodes the received signal using a circuit as shown in FIG. In the example of FIG. 8, it is assumed that five encoded received signals are input to five input terminals, respectively.
The received signal input to each input terminal is input to one decoding circuit assigned in advance and processed. Each decoding circuit decodes the input received signal according to the decoding type and decoding rate designated by the control circuit, and outputs the processing result to one output terminal assigned in advance. Therefore, it is necessary to provide the same number of independent decoding circuits as the number of signals to be received or the number of input terminals.
[0006]
[Problems to be solved by the invention]
When encoding and decoding signals using the conventional circuit as described above, the same number of independent encoding circuits and decoding circuits as the number of signals to be transmitted must be provided.
Therefore, for example, multi-carrier / multi-rate transmission that processes signals of several hundred channels simultaneously, or as shown in the document “Science Technical Report SAT 2001-63 Multi-carrier / multi-rate modem with channel aggregation function: Tanabe et al” When used in applications, there is a high possibility that the circuit scale and power consumption of the apparatus will be enormous for encoding and decoding, and there is a problem in practicality.
[0007]
An object of the present invention is to provide a time division processing type code processing circuit suitable for simultaneously transmitting a plurality of independent signals having different transmission rates and the like.
[0008]
[Means for Solving the Problems]
The time division processing type code processing circuit according to claim 1 is a time division processing type code processing circuit which simultaneously inputs a plurality of information signals independent from each other and outputs a signal subjected to encoding processing. A time slot generating means for outputting a time slot as a timing signal, and a parallel-serial conversion of a plurality of information signals input in parallel, and sequentially assigning each information signal appearing sequentially to each time slot of the timing signal. Serial conversion means, and time division encoding processing means for sequentially encoding each information signal output from the parallel serial conversion means for each time slot, the time division encoding processing means, Signal processing control means for outputting a control signal relating to code processing of the assigned information signal for each time slot generated by the time slot generating means; Each time slot generated by the time slot generating means encodes an assigned information signal according to an instruction of a control signal output from the signal processing control means, and the encoding processing means includes each information When the signal is encoded by time division, the internal signal storage means for temporarily storing the internal signal used by the encoding processing means in the encoding process, and the internal signal storage means for each time slot A storage control means for controlling writing and reading of the internal signal;In the encoding processing means, the calculation result or intermediate result of the encoding for the first signal part in a certain information signal is stored as an internal signal by writing to the internal signal storage means by the storage control means. When the second signal portion of the information signal is encoded, the stored internal signal is read from the internal signal storage means by the storage control means and used for calculation.It is characterized by that.
[0009]
According to the first aspect, since a plurality of input signals are converted from parallel to serial and sequentially processed according to the arrangement of the time slots, it is not necessary to provide a large number of elements for performing the encoding process.
However, in the actual encoding process, encoding calculation is not performed for the signal portion at each time point of the signal that appears sequentially in time series, but encoding for the first signal portion that appears at a certain time point, for example. It is necessary to perform the calculation by combining the calculation result or the intermediate result with the contents of the second signal portion that appears at the next time point.
[0010]
However, if a plurality of input information signals are parallel-serial converted and sequentially assigned to each time slot, each signal is temporally separated, so that it is necessary for calculation of the encoding process of the second signal portion. The calculation result or intermediate result of the encoding for the first signal part to be performed will be lost.
Therefore, in claim 1, when the encoding result or intermediate result of the first signal portion is temporarily stored in the internal signal storage means as an internal signal, and the second signal portion is encoded. Read and use for calculation. Thereby, even when processing is performed for each time slot, correct encoding processing can be performed.
[0011]
Accordingly, in claim 1, even when the number of signals to be processed increases, it is not necessary to increase the number of circuits for executing the encoding process, and the increase in circuit scale can be suppressed.
The time-division processing type code processing circuit according to claim 2 is the storage control means according to claim 1, wherein the internal signal is written into the internal signal storage means at the timing of one time slot, and at the timing of the next time slot. Reading out the signal required when encoding the information signal from the internal signal storage means.Features.
That is,Regarding the operation of the storage control means, the internal signal corresponding to the information signal processed at the timing of one time slot is written into the internal signal storage means, and the information signal is encoded at the timing of the next time slot. Read out the signals required for the internal signal storage meansIs.
[0012]
The time-division processing type code processing circuit according to claim 3 is the storage control means according to claim 1, wherein a signal required for encoding the information signal at the timing of one time slot is the internal signal. Read from the storage means, perform the encoding process in the encoding processing means, and write the result to the internal signal storage meansIt is characterized by that.
That is,A signal required for encoding an information signal to be processed at the timing of one time slot is read from the internal signal storage means, encoded at the same timing, and the internal signal is written to the internal signal storage means at the same timing. Control asTo do.
Claim4Claim 1To any one of claims 3 to 4In the time division processing type code processing circuit, the signal processing control means outputs encoding information and a coding rate as the control signal, and is applied to a plurality of input information signals. When a plurality of encoding rates to be used are mixed, or when the transmission speeds of a plurality of input information signals are a plurality of types, or when a plurality of types of encoding are applied to a plurality of input information signals, The parallel-serial conversion means changes the number of time slots assigned to an information signal input per unit time according to at least one of the coding rate, transmission rate, and coding type. To do.
[0013]
Claim4Since the coding type and coding rate can be switched for each time slot, the coding type and coding rate can be switched independently for each signal to be processed.
Also, for example, when encoding multiple signals with different transmission rates, the amount of information per unit time differs for each signal, but the encoding processing capacity is determined according to the signal with the largest amount of information per unit time. Must. However, since the amount of information per time slot can be reduced by allocating a plurality of time slots to a signal having a large amount of information per unit time, for example, the amount of information to be processed per unit time is averaged. be able to.
[0014]
Further, even when the encoding type and the encoding rate are different for each signal, the encoding can be realized with the minimum necessary processing capability by controlling the time slot assignment.
Claim5Claim 1To any one of claims 3 to 4In the time division processing type code processing circuit, a plurality of encoded information signals corresponding to a plurality of input information signals are obtained by separating each time slot of the signal output from the time division encoding processing means and performing serial-parallel conversion. Further, a serial-parallel conversion means for generating is provided.
[0015]
Claim5Since the encoded signal is output after being converted into a parallel signal, the present invention can be applied without changing the conventional apparatus.
Claim6The time-division processing type code processing circuit is a time-division processing type code processing circuit that outputs a signal obtained by decoding an encoded information signal, and timings a predetermined series of time slots. Time slot generating means for outputting as signals, time division processing decoding means for sequentially decoding each information signal assigned to each time slot and sequentially inputted for each time slot, and the time division processing decoding Means for separating and serial-parallel converting each time slot of the information signal output from the means, and simultaneously outputting a plurality of information signals, and the time division processing decoding means includes the time slot For each time slot generated by the generating means, signal processing control means for outputting a control signal relating to decoding processing of the assigned signal, and for each time slot Decoding processing means for decoding the assigned signal according to an instruction of a control signal from the signal processing control means, and when the decoding processing means decodes each information signal in a time division manner, Internal signal storage means for temporarily storing internal signals used in the decoding process of the decoding processing means, and storage control means for controlling writing and reading of the internal signals to and from the internal signal storage means for each time slot AndIn the decoding processing means, the calculation result or intermediate result of decoding for the first signal portion in a certain information signal is stored as an internal signal by writing to the internal signal storage means by the storage control means,
When the second signal portion of the information signal is decoded, the stored internal signal is read from the internal signal storage means by the storage control means and used for calculation.It is characterized by that.
[0016]
Claim6Is assumed that a plurality of encoded signals (received signals) are input as serial signals. Claim6In, a plurality of signals input as serial signals are extracted for each time slot and decoded, so that it is not necessary to provide many elements for performing the decoding process.
However, in the actual decoding process, the decoding of the first signal portion that appears at a certain time point is not performed for the signal portion at each time point of the signal that appears sequentially in time series. It is necessary to perform the calculation by combining the calculation result or the intermediate result with the contents of the second signal portion that appears at the next time point.
[0017]
However, since the plurality of input information signals are temporally separated for each time slot, the decoding calculation result for the first signal portion required for the calculation of the decoding processing of the second signal portion Or intermediate results will be lost.
Therefore, the claim6, The decoding calculation result or intermediate result for the first signal portion is temporarily stored in the internal signal storage means as an internal signal, and is read out and used for calculation when the second signal portion is decoded. . Thereby, even when processing is performed for each time slot, correct decoding processing can be performed.
[0018]
Therefore, the claims6Then, even when the number of signals to be processed increases, it is not necessary to increase the number of circuits for executing the decoding process, and the increase in circuit scale can be suppressed.
The time division processing type code processing circuit according to claim 7 is the storage control means according to claim 6, wherein the internal signal is written to the internal signal storage means at the timing of one time slot, and at the timing of the next time slot. The signal required for decoding the information signal is read from the internal signal storage means.
That is,Regarding the operation of the storage control means, the internal signal corresponding to the information signal processed at the timing of one time slot is written into the internal signal storage means, and the information signal is decoded at the timing of the next time slot. Control to read out the signal required for the internal signal storage meansThe
[0019]
The time division processing type code processing circuit according to claim 8 is the storage control means according to claim 6, wherein the signal required for decoding the information signal at the timing of one time slot is the internal signal. Reading from the storage means, performing the decoding process in the decoding processing means, and writing the result into the internal signal storage means
That is,A signal necessary for decoding an information signal to be processed at the timing of one time slot is read from the internal signal storage means, decoded at the same timing, and the internal signal is written to the internal signal storage means at the same timing. Control asTo do.
Claim9Claims9. Any one of claims 6 to 8In the time division processing type code processing circuit, the signal processing control means outputs information indicating the type of coding and the coding rate as the control signal, and when there are a plurality of coding rates to be applied, or information When a plurality of signal transmission rates are mixed, or when there are a plurality of types of decoding, the serial-to-parallel conversion means, according to at least one of the coding rate, transmission rate, and decoding type, It is characterized in that the number of time slots assigned to a signal input per unit time is changed.
[0020]
Claim9Since the coding type and coding rate can be switched for each time slot, the decoding type and coding rate can be switched independently for each signal to be processed and the decoding process can be performed independently.
For example, when decoding multiple signals with different transmission speeds, the amount of information per unit time differs for each signal, but the coding processing capacity is determined according to the signal with the largest amount of information per unit time. Must. However, since the amount of information per time slot can be reduced by allocating a plurality of time slots to a signal having a large amount of information per unit time, for example, the amount of information to be processed per unit time is averaged. be able to. The same applies when the encoding type and the encoding rate differ for each signal.
[0021]
Claim10Claims9. Any one of claims 6 to 8In the time division processing type code processing circuit, a plurality of independently encoded information signals are simultaneously input from a plurality of input terminals, and the plurality of information signals are parallel-serial converted in accordance with the time slot assignment. A parallel-serial conversion unit is further provided, and a serial signal output from the parallel-serial conversion unit is input to the time division processing decoding unit.
[0022]
Claim10Since the received signal encoded as in the conventional apparatus is input as a parallel signal, the present invention can be applied as it is without changing the conventional apparatus.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
One embodiment of a time division processing type code processing circuit of the present invention will be described with reference to FIGS. This form is claimed in claim 1.FromClaim4Corresponding to
[0024]
FIG. 1 is a block diagram showing the configuration of a time division processing type code processing circuit of this embodiment. FIG. 2 is a time chart showing an operation example of the time division processing type code processing circuit of this embodiment. FIG. 3 is a schematic diagram showing an operation example of the parallel-serial conversion circuit.
In this embodiment, the time slot generation means, parallel-serial conversion means, time division encoding processing means, signal processing control means, encoding processing means, internal signal storage means and storage control means of claim 1 are respectively connected to the control circuit 13, This corresponds to the parallel-serial conversion circuit 12, the encoding circuit 14, the control circuit 13, the encoding circuit 14, the memory circuit 15, and the memory control circuit 21.
[0025]
As shown in FIG. 1, the time division processing type code processing circuit of this embodiment includes an input terminal 10, a buffer 11, a parallel-serial conversion circuit 12, a control circuit 13, an encoding circuit 14, a memory circuit 15, and an output terminal 16. ing.
The memory circuit 15 includes a memory control circuit 21, a memory 22, an input buffer 23, and an output buffer 24.
[0026]
In this embodiment, since it is assumed that five independent digital signals are input from the outside and encoded, five input terminals 10 are provided. Five input terminals 10 (A), 10 (B), 10 (C), 10 (D) and 10 (E) are respectively connected to buffers 11 (A), 11 (B), 11 (C) and 11 (D ) And 11 (E) and connected to the inputs (A to E) of the parallel-serial converter circuit 12.
[0027]
This time division processing type code processing circuit converts five signals SG1A, SG1B, SG1C, SG1D and SG1E, which are independently input to five input terminals 10, into one serial signal SG2 by the parallel-serial conversion circuit 12. Convert.
The serial signal SG2 is divided into time slots having a constant period, and information of a certain period of any one of the five input signals SG1A, SG1B, SG1C, SG1D, and SG1E is assigned to each time slot.
[0028]
That is, in the signal SG2, signals input to the input terminals 10 (A) to 10 (E) are time-multiplexed at a rate corresponding to their bit rate.
However, since it is necessary to process signals simultaneously input from a maximum of five systems of input terminals 10 in a time division manner, the internal signal of the encoding circuit 14 is stored in the memory 22 using the control signal C2 output from the control circuit 13. Writing and reading data from the memory 22 are used in the encoding circuit 14.
[0029]
The time division processing type code processing circuit of FIG. 1 operates in synchronization with an operation clock (pulse signal having a constant cycle) CLK generated internally by the control circuit 13. In addition, the switching timing of the time slot is determined by the division ratio of the operation clock. For example, the frequency division ratio is 1 when the switching timing of the operation clock and the time slot is synchronized, and the frequency division ratio is 2 when the time slot changes once in 2 clocks.
[0030]
The control circuit 13 outputs a control signal C <b> 1 to the parallel / serial conversion circuit 12. The control signal C1 is a number that identifies one of the input terminals 10 (or the buffer 11), and is updated at the time slot switching timing.
Therefore, the parallel-serial conversion circuit 12 takes out a signal from the specific buffer 11 specified by the control signal C1 every time the time slot is switched, and outputs it to one time slot of the signal SG2.
[0031]
For example, in each time slot, as shown in FIG. 2, (A), (E), (A), (B), (C), (D), (A), (E), (A), (B ), (C), (D),... Are input as the control signal C1, SG1A, SG1E, SG1A, SG1B, SG1C, SG1D, SG1A, SG1E, respectively, in each time slot of the signal SG2. SG1A, SG1B, SG1C, SG1D,... Appear.
[0032]
In addition, when the transmission speeds of a plurality of signals input to each input terminal 10 are different, the amounts of information input per unit time are different from each other. , SG1E are assigned in order, which causes a problem because the amount of information changes for each time slot.
Therefore, the control circuit 13 controls the control signal C1, and automatically assigns the number of time slots assigned to each series of signals (SG1A to SG1E) according to the transmission rate of each signal, the type of encoding, and the encoding rate. change.
[0033]
A specific example shown in FIG. 3 will be described. Note that numbers 1, 2, 3, 4, and 5 surrounded by circles in FIG. 3 correspond to the signals SG1A, SG1B, SG1C, SG1D, and SG1E, respectively.
In the example of FIG. 3A, the first signal (SG1A) is input by an amount of information of 2 units and the second signal (SG1B) is an information amount of 1 unit during five periods of the time slot. The third signal (SG1C) is input by an amount of information of one unit, and the fifth signal (SG1E) is input by an amount of information of one unit. That is, the transmission speed of the first signal (SG1A) is twice that of the other signals.
[0034]
Therefore, a uniform information amount can be assigned to each time slot by sequentially assigning signals of numbers 1, 2, 3, 1, and 5 to each time slot of the output signal SG2. Also, all input signals can be assigned to time slots of output signals.
Similarly, in the example of FIG. 3B, the first signal (SG1A) is input by the amount of information of 3 units and the second signal (SG1B) is 2 units during the five periods of the time slot. Only the amount of information is entered. Therefore, a uniform amount of information can be assigned to each time slot by sequentially assigning signals of numbers 1, 2, 1, 2 and 1 to each time slot of the output signal SG2.
[0035]
Similarly, in the example of FIG. 3C, the first signal (SG1A) is input by an amount of information of 5 units during 5 periods of the time slot. Accordingly, a uniform amount of information can be assigned to each time slot by sequentially assigning signals of numbers 1, 1, 1, 1, 1 to each time slot of the output signal SG2.
The control circuit 13 outputs a control signal C3 to the encoding circuit 14. This control signal C3 is a signal indicating a number for identifying one of the input terminals 10 (or the buffer 11), a coding rate for the corresponding signal, and a coding type, and is synchronized with the switching timing of the time slot. Updated.
[0036]
Further, the control circuit 13 outputs a control signal C2 to the memory circuit 15. The control signal C2 includes information on the read address and the write address, and is updated in synchronization with the switching timing of the time slot.
In the memory circuit 15, the following operation is performed under the control of the memory control circuit 21. That is, in synchronization with the switching timing of each time slot, data is read from the designated first address (read address of the control signal C2) on the memory 22 and written to the output buffer 24, and at the same time, The contents held in the input buffer 23 are written to the designated second address (write address of the control signal C2).
[0037]
The encoding circuit 14 takes in the information of the signal SG2 from the output of the parallel-serial conversion circuit 12 at a timing synchronized with the operation clock CLK, and simultaneously takes in and expands the data output from the output buffer 24 of the memory circuit 15. Performs arithmetic processing for conversion.
In addition, when the coding rate and the coding type are specified by the control signal C3 input from the control circuit 13, the coding circuit 14 switches the content of the calculation according to the content of the control signal C3.
[0038]
The encoding circuit 14 outputs the result of the operation, that is, the encoded signal SG2 to the output terminal 16 as the signal SG3. At the same time, the encoding circuit 14 outputs internal data (data necessary for calculation of the next appearing signal) to the input buffer 23 of the memory circuit 15.
The signals appearing at the five input terminals 10 (A) to 10 (E) are separated for each time slot, and each signal is discontinuous in time, but is required for calculation in the encoding circuit 14. Since the internal signal is temporarily stored in the memory 22 and read and used at a necessary timing, the encoding circuit 14 can perform encoding independently for each input signal.
[0039]
(Second Embodiment)
Another embodiment of the time division processing type code processing circuit of the present invention will be described with reference to FIG. This form is claimed5Corresponding to
FIG. 4 is a block diagram showing the configuration of the time division processing type code processing circuit of this embodiment. This form is a modification of the first embodiment. 4, elements corresponding to those in FIG. 1 are denoted by the same reference numerals. The following description is omitted for the same parts as those of the first embodiment.
[0040]
In this form, the claims5The serial / parallel conversion means corresponds to the serial / parallel conversion circuit 31.
As shown in FIG. 4, in this embodiment, a serial-parallel conversion circuit 31 is connected to the output of the encoding circuit 14, and an output terminal 33 is connected to each output of the serial-parallel conversion circuit 31 via a buffer 32.
The serial / parallel conversion circuit 31 performs the reverse operation of the parallel / serial conversion circuit 12. That is, the time-multiplexed signal SG3 is separated for each time slot and output to each designated output terminal (buffer 32).
[0041]
The control signal C4 output from the control circuit 13 is a number that identifies one of the output terminals 33 (or the buffer 32), and is updated in synchronization with the switching timing of the time slot.
Therefore, the signal SG3 is separated for each time slot, written in the buffer 32 of the system specified by the control signal C4, and output to any one of the output terminals 33.
[0042]
By giving a read signal to each of the five buffers 32 (A) to 32 (E) at a unique timing, it is possible to take out signals having independent transmission rates from the five output terminals 33 (A) to 33 (E). it can.
(Third embodiment)
Another embodiment of the time division processing type code processing circuit of the present invention will be described with reference to FIG. FIG. 5 is a block diagram showing the configuration of the time division processing type code processing circuit of this embodiment. This form is claimedFrom 6Claim9Corresponding to
[0043]
In this form, the claims6Time slot generating means, time division processing decoding means, serial-parallel conversion means, signal processing control means, decoding processing means, internal signal storage means and storage control means are respectively a control circuit 43, a decoding circuit 42, and a serial parallel processing. This corresponds to the conversion circuit 45, the control circuit 43, the decryption circuit 42, the memory 52, and the memory control circuit 51.
The time division processing type code processing circuit shown in FIG. 5 is used to receive and decode the serial signal encoded by the time division processing type code processing circuit of FIG.
[0044]
As shown in FIG. 5, the time division processing type code processing circuit of this embodiment includes an input terminal 41, a decoding circuit 42, a control circuit 43, a memory circuit 44, a serial-parallel conversion circuit 45, a buffer 46, and an output terminal 47. ing.
The memory circuit 44 includes a memory control circuit 51, a memory 52, an input buffer 53, and an output buffer 54.
[0045]
In this embodiment, since it is assumed that a signal obtained by time-multiplexing five signals is received, five buffers 46 and five output terminals 47 are provided.
Each component of the time division processing type code processing circuit shown in FIG. 5 operates in synchronization with an operation clock CLK having a constant cycle generated by the control circuit 43. Further, the control circuit 43 generates a time slot having a constant period synchronized with the operation clock CLK.
[0046]
The signal input to the input terminal 41 is divided for each time slot having a fixed period in synchronization with the operation clock CLK.
The control signal C21 output from the control circuit 43 includes a signal for specifying the signal in each time slot of the signal input to the input terminal 41, and information on the decoding type and decoding rate. . This control signal C21 is updated in synchronization with switching of each time slot.
[0047]
Further, the control signal C22 output from the control circuit 43 includes information on a write address and a read address. This control signal C22 is updated in synchronization with switching of each time slot.
The control signal C23 output from the control circuit 43 includes a number indicating the output destination (buffer 46 or output terminal 47) of the signal for each time slot. This control signal C23 is updated in synchronization with switching of each time slot.
[0048]
In the memory circuit 44, the following operation is performed under the control of the memory control circuit 51. That is, in synchronization with the switching timing of each time slot, data is read from the designated first address (read address of the control signal C22) on the memory 52 and written to the output buffer 54, and at the same time, The contents held in the input buffer 53 are written to the designated second address (write address of the control signal C22).
[0049]
The decryption circuit 42 captures signal information from the input terminal 41 at the timing synchronized with the operation clock CLK, and simultaneously captures and expands data output from the output buffer 54 of the memory circuit 44 to perform an operation for decryption. Process.
[0050]
When the decoding rate and the decoding type are specified by the control signal C21 input from the control circuit 43, the decoding circuit 42 switches the calculation contents according to the contents of the control signal C21.
The decoding circuit 42 outputs the operation result, that is, the decoded signal, to the serial / parallel conversion circuit 45. At the same time, the decoding circuit 42 writes internal data (data necessary for the calculation of the next appearing signal) to the input buffer 53 of the memory circuit 44.
[0051]
The serial / parallel conversion circuit 45 assigns each time slot of the signal to the output system (any buffer 46) designated by the control signal C23 output from the control circuit 43, and selectively selects the buffer 46 (A) for each time slot. A signal is output to .about.46 (E). Therefore, the signal output from the decoding circuit 42 as a serial signal is serial / parallel converted by the serial / parallel conversion circuit 45 and output to the buffers 46 (A) to 46 (E) as a parallel signal.
[0052]
By giving a read signal to each of the five buffers 46 (A) to 46 (E) at a unique timing, it is possible to extract independent transmission rate signals from the five output terminals 47 (A) to 47 (E). it can.
(Fourth embodiment)
Another embodiment of the time division processing type code processing circuit of the present invention will be described with reference to FIG. This form is claimed10Corresponding to
[0053]
FIG. 6 is a block diagram showing the configuration of the time division processing type code processing circuit of this embodiment. This form is a modification of the third embodiment. In FIG. 6, elements corresponding to those in FIG. 5 are denoted by the same reference numerals. The following description is omitted for the same parts as those of the first embodiment.
In this form, the claims10The parallel / serial conversion means corresponds to the parallel / serial conversion circuit 63.
[0054]
As shown in FIG. 6, in this embodiment, five input terminals 61 are provided, and each input terminal 61 is connected to an input of the parallel-serial conversion circuit 63 via a buffer 62.
The parallel-serial conversion circuit 63 selectively inputs one of five signals from one of the five buffers 62 at the timing of each time slot in accordance with the control signal C24 output from the control circuit 43. 42 is output to the input.
[0055]
That is, in the time division processing type code processing circuit shown in FIG. 6, five independent signals are input as reception signals from the input terminal 61, converted into serial signals by the parallel-serial conversion circuit 63, and then input to the decoding circuit 42. give. The operation of the parallel-serial conversion circuit 63 is the same as that of the parallel-serial conversion circuit 12 described above.
[0056]
【The invention's effect】
As described above, the apparatus according to the present invention parallelizes the input signal for each bit rate even when the bit rate is different for each of a plurality of existing signals, or when the coding method and coding rate are different. By having an encoding circuit and a memory interface that are serially converted and controlled by a control circuit, a circuit configuration with reduced circuit scale and power consumption can be realized. This can be particularly effective in communication systems that handle several hundred channels simultaneously.
[0057]
Further, the apparatus of the present invention can be expected to have the same effect as described above even when the bit rate of a signal to be decoded is different for each signal, or when the decoding method and the decoding rate are different. Furthermore, the apparatus of the present invention can be applied to a case where a satellite communication line is efficiently used by a plurality of transmission stations, or a case where communication is performed in which the bandwidth and the number of carriers are changed in a programmable manner.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a time division processing type code processing circuit according to a first embodiment;
FIG. 2 is a time chart showing an operation example of the time division processing type code processing circuit according to the first embodiment;
FIG. 3 is a schematic diagram showing an operation example of the parallel-serial conversion circuit.
FIG. 4 is a block diagram illustrating a configuration of a time division processing type code processing circuit according to a second embodiment;
FIG. 5 is a block diagram illustrating a configuration of a time division processing type code processing circuit according to a third embodiment;
FIG. 6 is a block diagram illustrating a configuration of a time division processing type code processing circuit according to a fourth embodiment;
FIG. 7 is a block diagram illustrating a configuration example of a conventional encoding circuit.
FIG. 8 is a block diagram illustrating a configuration example of a conventional decoding circuit.
[Explanation of symbols]
10 Input terminal
11 Buffer
12 Parallel to serial converter
13 Control circuit
14 Coding circuit
15 Memory circuit
16 output terminals
21 Memory control circuit
22 memory
23 Input buffer
24 Output buffer
31 Series-parallel conversion circuit
32 buffers
33 Output terminal
41 Input terminal
42 Decoding circuit
43 Control circuit
44 Memory circuit
45 Series-parallel conversion circuit
46 buffers
47 Output terminal
51 Memory control circuit
52 memory
53 Input buffer
54 Output buffer
61 Input terminal
62 buffers
63 Parallel to serial converter

Claims (10)

A time-division processing type code processing circuit for simultaneously inputting a plurality of information signals independent of each other and outputting an encoded signal,
Time slot generating means for outputting a predetermined time slot as a timing signal;
Parallel-serial conversion means for parallel-serial conversion of a plurality of information signals input in parallel, and sequentially assigning each information signal that appears continuously to each time slot of the timing signal;
The time division coding processing means for sequentially coding each information signal output from the parallel-serial conversion means for each time slot, and the time division coding processing means,
Signal processing control means for outputting a control signal relating to code processing of the assigned information signal for each time slot generated by the time slot generating means;
Encoding processing means for encoding an assigned information signal according to an instruction of a control signal output from the signal processing control means for each time slot generated by the time slot generating means;
An internal signal storage means for temporarily storing an internal signal used in the encoding process by the encoding processing means when the encoding processing means encodes each information signal in a time division manner;
Storage control means for controlling writing and reading of the internal signal to and from the internal signal storage means for each time slot ;
In the encoding processing means,
The calculation result or intermediate result of encoding for the first signal portion in a certain information signal is stored as an internal signal by writing to the internal signal storage means by the storage control means,
The time-division processing characterized in that when the second signal portion of the information signal is encoded, the stored internal signal is read from the internal signal storage means by the storage control means and used for calculation. Type code processing circuit. In the storage control means,
The internal signal is written into the internal signal storage means at the timing of one time slot, and the signal required for encoding the information signal is read out from the internal signal storage means at the timing of the next time slot.
Division processing type code processing circuit when the claim 1, wherein a. In the storage control means,
At the timing of one time slot, a signal required for encoding the information signal is read from the internal signal storage means, encoded by the encoding processing means, and the result is obtained as the internal signal. The time division processing type code processing circuit according to claim 1, wherein the time division processing type code processing circuit is written in the storage means . In the time division processing type code processing circuit according to any one of claims 1 to 3,
The signal processing control means outputs information indicating a coding type and a coding rate as the control signal,
When a plurality of coding rates used in encoding applied to a plurality of input information signals are mixed, or when there are a plurality of types of transmission speeds of a plurality of input information signals, or for a plurality of input information signals On the other hand, when applying a plurality of types of encoding, the parallel-to-serial conversion means performs an information signal input in unit time according to at least one of the encoding rate, the transmission rate, and the encoding type. The time division processing type code processing circuit is characterized in that the number of time slots to be allocated is changed . In the time division processing type code processing circuit according to any one of claims 1 to 3 ,
Serial-parallel conversion means for separating each time slot of the signal output from the time-division encoding processing means and performing serial-parallel conversion to generate a plurality of encoded information signals corresponding to the plurality of input information signals
Division processing type code processing circuit when said further providing the. A time-division processing type code processing circuit that outputs a signal obtained by decoding an encoded information signal,
Time slot generating means for outputting a predetermined time slot as a timing signal;
Time division processing decoding means for sequentially decoding each information signal assigned to each time slot and sequentially input for each time slot;
Serial-parallel conversion means for separating and serial-parallel converting each time slot of the information signal output from the time-division processing decoding means, and outputting a plurality of information signals simultaneously;
And the time division process decoding means includes:
Signal processing control means for outputting a control signal related to decoding processing of the assigned signal for each time slot generated by the time slot generating means;
Decoding processing means for decoding a signal assigned to each time slot in accordance with an instruction of a control signal from the signal processing control means;
An internal signal storage means for temporarily storing an internal signal used in the decoding process of the decoding processing means when the decoding processing means decodes each information signal in a time division manner;
Storage control means for controlling writing and reading of the internal signal to and from the internal signal storage means for each time slot;
In the decryption processing means,
The calculation result or intermediate result of decoding for the first signal part in an information signal is stored as an internal signal by writing to the internal signal storage means by the storage control means,
The time division , wherein when the second signal portion of the certain information signal is decoded, the stored internal signal is read from the internal signal storage means by the storage control means and used for calculation. Processing type code processing circuit. In the storage control means,
The internal signal is written into the internal signal storage means at the timing of one time slot, and the signal required for decoding the information signal is read out from the internal signal storage means at the timing of the next time slot.
The time division processing type code processing circuit according to claim 6. In the storage control means,
At the timing of one time slot, a signal required for decoding the information signal is read from the internal signal storage means, the decoding processing means performs decoding processing, and the result is obtained as the internal signal. Write to storage
The time division processing type code processing circuit according to claim 6. In the time division processing type code processing circuit according to any one of claims 6 to 8,
The signal processing control means outputs information indicating a coding type and a coding rate as the control signal,
When a plurality of coding rates to be applied are mixed, when a plurality of information signal transmission rates are mixed, or when there are a plurality of types of decoding, the serial-to-parallel conversion means includes the coding rate and the transmission rate. And a time division processing type code processing circuit, wherein the number of time slots allocated to a signal input per unit time is changed according to at least one of decoding types. In the time division processing type code processing circuit according to any one of claims 6 to 8,
Parallel-serial conversion means for simultaneously inputting a plurality of independent encoded information signals from a plurality of input terminals and performing parallel-serial conversion of the plurality of information signals according to the allocation of the time slots
And a serial signal output from the parallel-serial conversion means is input to the time-division processing decoding means.

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