JP2004080146A - Time division processing type encoding processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a time division processing type encoding processing circuit proper to the case when a plurality of different and independent signals with different transmission rates or the like are simultaneously transmitted. <P>SOLUTION: The time division processing type encoding processing circuit is provided with: a time slot generating means 13; a parallel serial conversion means 12 applying parallel serial conversion to a plurality of information signals received as parallel signals and assigning the result to each time slot; and a time division encoding processing means 14. The time division encoding processing means 14 is provided with: a signal processing control means 13 for outputting an encoding processing control signal by each time slot; an encoding processing means 14 performing encoding by each time slot; an internal signal storage means 22 for temporarily storing an internal signal used by the encoding processing means 14 for the encoding; and a storage control means 21 for controlling write / read of the internal signal, and the internal signal corresponding to the information signal processed in one time slot is written in the internal signal storage means 22 and the signal required to encode the information signal in the succeeding timing is read from the internal signal storage means 22. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a time-division processing type code processing circuit used for performing encoding and decoding when simultaneously transmitting a plurality of information signals, for example, a multi-point or a plurality of transmission signals at a plurality of transmission speeds to a plurality of transmission signals. It can be used for high-speed wireless communication devices and broadband satellite communication devices that perform digital transmission simultaneously using carriers.
[0002]
[Prior art]
For example, when multiple independent signals are simultaneously digitally transmitted using multiple carriers, information is transmitted after encoding is performed on the transmission side for the purpose of, for example, compressing the amount of information, and is encoded on the reception side. The original information is reproduced by decoding the obtained information.
[0003]
In addition, a plurality of independent signals to be transmitted do not always have the same transmission speed.
Therefore, when performing this type of digital signal transmission, encoding has conventionally been performed using a circuit as shown in FIG. In the example of FIG. 7, it is assumed that five independent signals are input to five input terminals.
[0004]
The signal input to each input terminal is input to one pre-assigned encoding circuit and processed. Each encoding circuit encodes an input signal according to an encoding type and an encoding rate specified by the control circuit, and outputs a processing result to one output terminal assigned in advance. Therefore, it is necessary to provide the same number of independent coding circuits as the number of signals to be transmitted or the number of input terminals.
[0005]
On the other hand, the receiving side has conventionally used a circuit as shown in FIG. 8 to decode a received signal. In the example of FIG. 8, it is assumed that five encoded reception signals are input to five input terminals, respectively.
The received signal input to each input terminal is input to one decoding circuit assigned in advance and processed. Each decoding circuit performs a decoding process on an input received signal according to a decoding type and a decoding rate designated by the control circuit, and outputs a processing result to one output terminal assigned in advance. Therefore, it is necessary to provide the same number of independent decoding circuits as the number of signals to be received or the number of input terminals.
[0006]
[Problems to be solved by the invention]
When encoding and decoding signals using the conventional circuits as described above, it is necessary to provide the same number of independent encoding circuits and decoding circuits as the number of signals to be transmitted.
Therefore, for example, multi-carrier / multi-rate transmission for simultaneously processing signals of several hundred channels, or a multi-carrier / multi-rate modem with a channel aggregation function: Tanabe et al. When used in applications, the circuit scale and power consumption of the device for encoding and decoding are likely to be enormous, and there is a problem in practicality.
[0007]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a time-division processing type code processing circuit suitable for simultaneously transmitting a plurality of independent signals having different transmission speeds and the like.
[0008]
[Means for Solving the Problems]
The time-division processing type code processing circuit according to claim 1 is a time-division processing type code processing circuit that simultaneously inputs a plurality of information signals independent of each other and outputs an encoded signal. A time slot generating means for outputting a time slot as a timing signal, and a parallel / serial conversion of a plurality of information signals input in parallel, and sequentially assigning each information signal appearing successively to each time slot of the timing signal. Serial conversion means, and a time-division encoding processing means for sequentially encoding each information signal output from the parallel-serial conversion means for each time slot, and the time-division encoding processing means, For each time slot generated by the time slot generating means, a signal processing control means for outputting a control signal relating to code processing of the assigned information signal, Encoding processing means for encoding the assigned information signal in accordance with a control signal output from the signal processing control means for each time slot generated by the time slot generating means; When encoding a signal in a time-division manner, the encoding processing means temporarily stores an internal signal used in the encoding processing, and an internal signal storage means for temporarily storing the internal signal used for the encoding processing. Storage control means for controlling writing and reading of the internal signal.
[0009]
According to the first aspect, since a plurality of input signals are converted from parallel to serial and processed sequentially according to the arrangement of time slots, there is no need to provide a large number of elements for performing encoding processing.
However, in the actual encoding processing, the encoding calculation is not performed independently on the signal portions at each time point of the signal appearing sequentially in time series. For example, the encoding for the first signal portion appearing at a certain time point is performed. It is necessary to perform the calculation by combining the calculation result or the intermediate result with the content of the second signal portion appearing at the next time.
[0010]
However, if a plurality of input information signals are parallel-to-serial converted and sequentially assigned to each time slot, the respective signals are temporally separated, which is necessary in the calculation of the encoding process of the second signal portion. The calculation result or intermediate result of the encoding for the first signal portion to be performed will be lost.
Therefore, in claim 1, when the calculation result or the intermediate result of the encoding for the first signal portion is temporarily stored as an internal signal in the internal signal storage means, and when the second signal portion is encoded, Read it out and use it for calculation. As a result, even when processing is performed for each time slot, correct encoding processing can be performed.
[0011]
Therefore, according to the first aspect, even when the number of signals to be processed increases, it is not necessary to increase the number of circuits for executing the encoding process, and it is possible to suppress an increase in circuit size.
In the operation of the storage control means, the internal signal corresponding to the information signal processed at the timing of one time slot is written into the internal signal storage means, and the information signal is encoded at the timing of the next time slot. It is sufficient to read out a signal required for the operation from the internal signal storage means.
[0012]
Further, a signal required when encoding an information signal to be processed at a timing of one time slot is read from the internal signal storage means, encoded at the same timing, and the internal signal is stored at the same timing. May be controlled so as to be written.
According to a second aspect of the present invention, in the time-division processing type code processing circuit according to the first aspect, the signal processing control unit outputs, as the control signal, information indicating an encoding type and an encoding rate. When a plurality of coding rates used in coding applied to an information signal are mixed, or when a plurality of input information signals have a plurality of transmission speeds, or when a plurality of input information signals have a plurality of When coding is applied, the parallel / serial conversion unit may determine a time slot to be assigned to an information signal input in a unit time according to at least one of the coding rate, the transmission rate, and the type of coding. The number is changed.
[0013]
According to the second aspect, since the type of coding and the coding rate can be switched for each time slot, it is possible to switch the coding type and the coding rate for each signal to be processed and perform independent coding processing. it can.
Also, for example, when encoding a plurality of signals having different transmission rates, the amount of information per unit time differs for each signal, but the encoding processing capacity is determined according to the signal having the largest amount of information per unit time. Must. However, for example, by allocating a plurality of extra time slots to a signal having a large amount of information per unit time, the amount of information per time slot can be reduced, so that the amount of information to be processed per unit time is averaged. be able to.
[0014]
In addition, even when the coding type and the coding rate are different for each signal, by controlling the allocation of the time slots, the coding can be realized with the minimum necessary processing capacity.
According to a third aspect of the present invention, in the time-division processing type code processing circuit of the first aspect, each time slot of the signal output by the time-division encoding processing means is separated and subjected to serial / parallel conversion, and is converted into a plurality of input information signals. A serial-parallel converter for generating a plurality of corresponding encoded information signals is further provided.
[0015]
According to the third aspect, the encoded signal is converted into a parallel signal and then output, so that the present invention can be applied without changing the conventional device.
The time-division processing type code processing circuit according to claim 4 is a time-division processing type code processing circuit that outputs a signal obtained by decoding a coded input information signal. A time slot generating means for outputting a slot as a timing signal; a time division processing decoding means for sequentially decoding each information signal allocated to each of the time slots and sequentially inputted for each time slot; A serial-to-parallel conversion unit that separates each time slot of the information signal output from the processing decoding unit and performs serial-to-parallel conversion, and outputs a plurality of information signals simultaneously, and the time-division processing decoding unit includes: Signal processing control means for outputting a control signal relating to decoding processing of the assigned signal for each time slot generated by the time slot generation means; Decoding means for decoding the signals assigned to the signals in accordance with an instruction of a control signal from the signal processing control means; and a decoding processing means for decoding each information signal by time division. An internal signal storage unit for temporarily storing an internal signal used in the decoding processing of the decoding processing unit; and a storage for controlling writing and reading of the internal signal to and from the internal signal storage unit for each time slot. Control means is provided.
[0016]
Claim 4 assumes that a plurality of encoded signals (received signals) are input as serial signals. According to the fourth aspect, since a plurality of signals input as serial signals are extracted for each time slot and each of them is subjected to decoding processing, it is not necessary to provide a large number of elements for performing decoding processing.
However, in the actual decoding processing, the decoding calculation is not performed independently on the signal portions at each time point of the signal sequentially appearing in time series. For example, the decoding on the first signal portion appearing at a certain time point is performed. It is necessary to perform the calculation by combining the calculation result or the intermediate result with the content of the second signal portion appearing at the next time.
[0017]
However, since a plurality of input information signals are temporally separated for each time slot, the calculation result of the decoding for the first signal portion required for the calculation of the decoding process for the second signal portion Alternatively, intermediate results will be lost.
Therefore, in claim 4, when the calculation result or the intermediate result of decoding of the first signal portion is temporarily stored as an internal signal in the internal signal storage means, and when the second signal portion is decoded, Read it out and use it for calculation. As a result, a correct decoding process can be performed even when the process is performed for each time slot.
[0018]
Therefore, according to the fourth aspect, even when the number of signals to be processed increases, it is not necessary to increase the number of circuits that execute the decoding processing, and it is possible to suppress an increase in circuit scale.
In the operation of the storage control means, the internal signal corresponding to the information signal processed at the timing of one time slot is written into the internal signal storage means, and the information signal is decoded at the timing of the next time slot. In such a case, it is sufficient to perform control so that a signal required at the time of reading is read out from the internal signal storage means.
[0019]
Also, a signal required when decoding an information signal to be processed at one time slot timing is read from the internal signal storage means, decoded at the same timing, and the internal signal is stored at the same timing. May be controlled so as to be written.
According to a fifth aspect of the present invention, in the time-division processing type code processing circuit according to the fourth aspect, the signal processing control means outputs, as the control signal, information indicating a coding type and a coding rate, and applies a coding rate to be applied. When a plurality of data signals coexist, or when a plurality of information signal transmission speeds coexist, or when there are a plurality of types of decoding, the serial-parallel conversion unit performs the coding rate, the transmission speed, and the type of decoding. The number of time slots assigned to signals input per unit time is changed according to at least one of the following.
[0020]
According to the fifth aspect, since the type of coding and the coding rate can be switched for each time slot, the decoding type and the coding rate can be switched for each signal to be processed to perform independent decoding processing. it can.
Also, for example, when decoding a plurality of signals having different transmission rates, the amount of information per unit time differs for each signal, but the encoding processing capacity is determined according to the signal having the largest amount of information per unit time. Must. However, for example, by allocating a plurality of extra time slots to a signal having a large amount of information per unit time, the amount of information per time slot can be reduced, so that the amount of information to be processed per unit time is averaged. be able to. The same applies to the case where the coding type and coding rate are different for each signal.
[0021]
According to a sixth aspect of the present invention, in the time-division processing type code processing circuit of the fourth aspect, a plurality of independently encoded information signals are simultaneously input from a plurality of input terminals, and the plurality of information signals are input in response to the time slot allocation. Parallel-to-serial conversion means for parallel-to-serial conversion of the information signal is input to the time-division processing decoding means.
[0022]
In the sixth aspect, the received signal that has been subjected to the encoding process in the same manner as the conventional apparatus is input as a parallel signal, so that the present invention can be applied without any change to the conventional apparatus.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
(First Embodiment)
One embodiment of the time-division processing type code processing circuit of the present invention will be described with reference to FIGS. This embodiment corresponds to claims 1 and 2.
[0024]
FIG. 1 is a block diagram showing a configuration of a time-division processing type code processing circuit of this embodiment. FIG. 2 is a time chart showing an operation example of the time-division processing type code processing circuit of this embodiment. FIG. 3 is a schematic diagram showing an operation example of the parallel / serial conversion circuit.
In this embodiment, the time slot generating means, the parallel / serial conversion means, the time-division encoding processing means, the signal processing control means, the encoding processing means, the internal signal storage means and the storage control means of the first embodiment are respectively composed of a control circuit 13, It corresponds to the parallel-to-serial conversion circuit 12, the encoding circuit 14, the control circuit 13, the encoding circuit 14, the memory circuit 15, and the memory control circuit 21.
[0025]
As shown in FIG. 1, the time-division processing type code processing circuit of this embodiment includes an input terminal 10, a buffer 11, a parallel / serial conversion circuit 12, a control circuit 13, a coding circuit 14, a memory circuit 15, and an output terminal 16. ing.
The memory circuit 15 includes a memory control circuit 21, a memory 22, an input buffer 23, and an output buffer 24.
[0026]
In this embodiment, since it is assumed that five independent digital signals are input from outside and encoded, five input terminals 10 are provided. Buffers 11 (A), 11 (B), 11 (C), 11 (D) are respectively connected to five input terminals 10 (A), 10 (B), 10 (C), 10 (D) and 10 (E). ) And 11 (E) are connected to the inputs (A to E) of the parallel / serial conversion circuit 12.
[0027]
The time-division processing type code processing circuit converts the five-system signals SG1A, SG1B, SG1C, SG1D, and SG1E, which are independently input to the five input terminals 10, into one serial signal SG2 by the parallel-serial conversion circuit 12. Convert.
The serial signal SG2 is divided into time slots having a constant period, and information of one of five input signals SG1A, SG1B, SG1C, SG1D, and SG1E is assigned to each time slot.
[0028]
That is, in the signal SG2, signals input to the input terminals 10 (A) to 10 (E) are time-multiplexed at a rate corresponding to their bit rates.
However, since signals simultaneously input from the input terminals 10 of up to five systems need to be processed in a time-division manner, the internal signal of the encoding circuit 14 is stored in the memory 22 using the control signal C2 output from the control circuit 13. Writing is performed and data read from the memory 22 is used in the encoding circuit 14.
[0029]
1 operates in synchronization with an operation clock (pulse signal having a constant cycle) CLK generated internally by the control circuit 13. The timing of switching the time slot is determined by the frequency division ratio of the operation clock. For example, the division ratio is 1 when the operation clock and the time slot switching timing are synchronized, and the division ratio is 2 when the time slot changes once with two clocks.
[0030]
The control circuit 13 outputs a control signal C1 to the parallel / serial conversion circuit 12. The control signal C1 is a number for specifying any one of the input terminals 10 (or the buffer 11), and is updated at the timing of switching the time slot.
Therefore, each time the time slot is switched, the parallel / serial conversion circuit 12 takes out the signal from the specific buffer 11 specified by the control signal C1, and outputs the signal to one time slot of the signal SG2.
[0031]
For example, in each time slot, as shown in FIG. 2, (A), (E), (A), (B), (C), (D), (A), (E), (A), (B) ), (C), (D),... Are input as control signals C1, SG1A, SG1E, SG1A, SG1B, SG1C, SG1D, SG1A, SG1E, SG1A, SG1B, SG1C, SG1D,... Appear.
[0032]
If the transmission rates of the plurality of signals input to the input terminals 10 are different, the amounts of information input per unit time are different from each other. Therefore, the signals SG1A, SG1B, SG1C, and SG1D are assigned to each time slot of the signal SG2. , SG1E in order, there is a problem because the amount of information changes for each time slot.
Therefore, the control circuit 13 controls the control signal C1 and automatically determines the number of time slots to be allocated to the signals of each stream (SG1A to SG1E) according to the transmission speed of each signal, the type of coding, and the coding rate. change.
[0033]
A specific example shown in FIG. 3 will be described. The numbers 1, 2, 3, 4, and 5 encircled in FIG. 3 correspond to the signals SG1A, SG1B, SG1C, SG1D, and SG1E, respectively.
In the example of FIG. 3A, the first signal (SG1A) is input by two units of information in five periods of the time slot, and the second signal (SG1B) is input by one unit of information. The third signal (SG1C) is input by one unit of information amount, and the fifth signal (SG1E) is input by one unit of information amount. That is, the transmission speed of the first signal (SG1A) is twice that of the other signals.
[0034]
Therefore, by sequentially assigning signals of numbers 1, 2, 3, 1, and 5 to each time slot of the output signal SG2, a uniform amount of information can be assigned to each time slot. Also, all the input signals can be assigned to the time slots of the output signal.
Similarly, in the example of FIG. 3B, the first signal (SG1A) is input by the amount of information of three units during the five periods of the time slot, and the second signal (SG1B) is input by two units of information. Only the amount of information has been entered. Therefore, by sequentially allocating signals of numbers 1, 2, 1, 2, and 1 to each time slot of the output signal SG2, a uniform amount of information can be allocated to each time slot.
[0035]
Similarly, in the example of FIG. 3 (c), the first signal (SG1A) is input by five units of information amount during five periods of the time slot. Therefore, by sequentially allocating signals of numbers 1, 1, 1, 1, 1 to each time slot of the output signal SG2, a uniform amount of information can be allocated to each time slot.
Further, the control circuit 13 outputs a control signal C3 to the encoding circuit 14. The control signal C3 is a signal indicating a number for specifying one of the input terminals 10 (or the buffer 11) and a coding rate and a type of coding for the corresponding signal, and is synchronized with a time slot switching timing. Be updated.
[0036]
Further, the control circuit 13 outputs a control signal C2 to the memory circuit 15. The control signal C2 includes information on the read address and the write address, and is updated in synchronization with the time slot switching timing.
The following operations are performed inside the memory circuit 15 under the control of the memory control circuit 21. That is, in synchronization with the switching timing of each time slot, data is read from the specified first address (the read address of the control signal C2) on the memory 22 and written to the output buffer 24, and at the same time, The content held in the input buffer 23 is written to the specified second address (write address of the control signal C2).
[0037]
The encoding circuit 14 takes in the information of the signal SG2 from the output of the parallel-to-serial conversion circuit 12 at the timing synchronized with the operation clock CLK, and at the same time, takes in and outputs the data output from the output buffer 24 of the memory circuit 15, and Perform arithmetic processing for conversion.
When the coding rate and the type of coding are specified by the control signal C3 input from the control circuit 13, the coding circuit 14 switches the content of the operation according to the content of the control signal C3.
[0038]
The encoding circuit 14 outputs the result of the operation, that is, the encoded signal SG2 to the output terminal 16 as the signal SG3. At the same time, the encoding circuit 14 outputs internal data (data necessary for calculating the next signal) to the input buffer 23 of the memory circuit 15.
The signals appearing at the five input terminals 10 (A) to 10 (E) are separated for each time slot, and the signals are discontinuous in time. Since the internal signal is temporarily stored in the memory 22 and read out and used at a necessary timing, the encoding circuit 14 can perform encoding independently for each input signal.
[0039]
(Second embodiment)
Another embodiment of the time-division processing type code processing circuit of the present invention will be described with reference to FIG. This embodiment corresponds to claim 3.
FIG. 4 is a block diagram showing a configuration of the time-division processing type code processing circuit of this embodiment. This embodiment is a modification of the first embodiment. 4, elements corresponding to those in FIG. 1 are denoted by the same reference numerals. For the same parts as those in the first embodiment, the following description is omitted.
[0040]
In this embodiment, the serial-parallel conversion means in claim 3 corresponds to the serial-parallel conversion circuit 31. As shown in FIG. 4, in this embodiment, a serial-to-parallel conversion circuit 31 is connected to the output of the encoding circuit 14, and an output terminal 33 is connected to each output of the serial-to-parallel conversion circuit 31 via a buffer 32.
The serial-parallel conversion circuit 31 performs the reverse operation of the parallel-serial conversion circuit 12. That is, the time-multiplexed signal SG3 is separated for each time slot and output to the designated output terminal (buffer 32).
[0041]
The control signal C4 output from the control circuit 13 is a number for specifying one of the output terminals 33 (or the buffer 32), and is updated in synchronization with the time slot switching timing.
Therefore, the signal SG3 is separated for each time slot, written into the buffer 32 of the system specified by the control signal C4, and output to one of the output terminals 33.
[0042]
By giving a read signal to each of the five buffers 32 (A) to 32 (E) at a unique timing, signals with independent transmission rates can be extracted from the five output terminals 33 (A) to 33 (E). it can.
(Third embodiment)
Another embodiment of the time-division processing type code processing circuit of the present invention will be described with reference to FIG. FIG. 5 is a block diagram showing a configuration of a time-division processing type code processing circuit of this embodiment. This embodiment corresponds to claims 4 and 5.
[0043]
In this embodiment, the time slot generating means, the time-division processing decoding means, the serial-parallel conversion means, the signal processing control means, the decoding processing means, the internal signal storage means and the storage control means of the present invention comprise a control circuit 43, It corresponds to the decoding circuit 42, the serial / parallel conversion circuit 45, the control circuit 43, the decoding circuit 42, the memory 52, and the memory control circuit 51.
The time-division processing type code processing circuit shown in FIG. 5 is used to receive and decode serial signals encoded by the time-division processing type code processing circuit of FIG.
[0044]
The time-division processing type code processing circuit of this embodiment includes an input terminal 41, a decoding circuit 42, a control circuit 43, a memory circuit 44, a serial-parallel conversion circuit 45, a buffer 46, and an output terminal 47, as shown in FIG. ing.
The memory circuit 44 includes a memory control circuit 51, a memory 52, an input buffer 53, and an output buffer 54.
[0045]
In this embodiment, it is assumed that a signal obtained by time-multiplexing signals of five systems is received. Therefore, five buffers 46 and five output terminals 47 are provided.
Each component of the time-division processing type code processing circuit shown in FIG. 5 operates in synchronization with an operation clock CLK whose cycle generated by the control circuit 43 is constant. Further, the control circuit 43 generates a time slot having a constant cycle synchronized with the operation clock CLK.
[0046]
The signal input to the input terminal 41 is divided into time slots having a constant cycle in synchronization with the operation clock CLK.
The control signal C21 output by the control circuit 43 includes a signal for specifying the signal of each time slot of the signal input to the input terminal 41, and information on the type of decoding and the decoding rate. . This control signal C21 is updated in synchronization with the switching of each time slot.
[0047]
The control signal C22 output from the control circuit 43 includes information on the write address and the read address. This control signal C22 is updated in synchronization with the switching of each time slot.
The control signal C23 output from the control circuit 43 includes a number indicating the output destination (buffer 46 or output terminal 47) of the signal for each time slot. This control signal C23 is updated in synchronization with the switching of each time slot.
[0048]
In the memory circuit 44, the following operation is performed under the control of the memory control circuit 51. That is, in synchronization with the switching timing of each time slot, data is read from the designated first address (read address of the control signal C22) on the memory 52 and written to the output buffer 54, and at the same time, The contents held in the input buffer 53 are written to the specified second address (the write address of the control signal C22).
[0049]
The decoding circuit 42 fetches signal information from the input terminal 41 at the timing synchronized with the operation clock CLK, and at the same time fetches and expands data output from the output buffer 54 of the memory circuit 44 to perform an operation for decoding. Perform processing.
[0050]
When the decoding rate and the type of decoding are specified by the control signal C21 input from the control circuit 43, the decoding circuit 42 switches the content of the operation according to the content of the control signal C21.
The decoding circuit 42 outputs the result of the operation, that is, the decoded signal to the serial-parallel conversion circuit 45. At the same time, the decoding circuit 42 writes the internal data (data necessary for the operation of the next signal) into the input buffer 53 of the memory circuit 44.
[0051]
The serial-parallel conversion circuit 45 assigns each time slot of the signal to an output system (any buffer 46) specified by the control signal C23 output from the control circuit 43, and selectively allocates the buffer 46 (A) for each time slot. To (E). Therefore, the signal output from the decoding circuit 42 as a serial signal is subjected to serial-parallel conversion by the serial-parallel conversion circuit 45 and output to the buffers 46 (A) to 46 (E) as parallel signals.
[0052]
By providing readout signals to the five buffers 46 (A) to 46 (E) at their own timings, signals with independent transmission rates can be extracted from the five output terminals 47 (A) to 47 (E). it can.
(Fourth embodiment)
Another embodiment of the time-division processing type code processing circuit of the present invention will be described with reference to FIG. This embodiment corresponds to claim 6.
[0053]
FIG. 6 is a block diagram showing the configuration of the time-division processing type code processing circuit of this embodiment. This embodiment is a modification of the third embodiment. 6, elements corresponding to those in FIG. 5 are denoted by the same reference numerals. For the same parts as those in the first embodiment, the following description is omitted.
In this embodiment, the parallel / serial conversion means of claim 6 corresponds to the parallel / serial conversion circuit 63.
[0054]
As shown in FIG. 6, in this embodiment, five input terminals 61 are provided, and each input terminal 61 is connected to an input of a parallel-to-serial conversion circuit 63 via a buffer 62.
The parallel / serial conversion circuit 63 selectively inputs one of the five signals from one of the five buffers 62 at the timing of each time slot according to the control signal C24 output from the control circuit 43, and Output to 42 inputs.
[0055]
That is, in the time-division processing type code processing circuit shown in FIG. 6, five independent signals are input from the input terminal 61 as reception signals, converted into serial signals by the parallel / serial conversion circuit 63, and then transmitted to the decoding circuit 42. give. The operation of the parallel-serial conversion circuit 63 is the same as the operation of the parallel-serial conversion circuit 12 described above.
[0056]
【The invention's effect】
As described above, the apparatus of the present invention arranges an input signal for each signal bit rate even when the bit rate differs for each of a plurality of existing signals or when the encoding method and the encoding rate differ. By having an encoding circuit and a memory interface controlled by the control circuit after serial conversion, a circuit configuration with reduced circuit scale and power consumption can be realized. This is particularly effective in a communication system that handles several hundred channels simultaneously.
[0057]
Further, the apparatus of the present invention can expect the same effects as above even when the bit rate of the signal to be decoded differs for each signal, or when the decoding method and the decoding rate are different. Further, the device of the present invention can be applied to a case where a satellite communication line is efficiently used by a plurality of transmitting stations, or a case where communication is performed in which the bandwidth or the number of carriers is changed in a programmable manner.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a time-division processing type code processing circuit according to a first embodiment.
FIG. 2 is a time chart illustrating an operation example of the time-division processing type code processing circuit according to the first embodiment;
FIG. 3 is a schematic diagram illustrating an operation example of a parallel-to-serial conversion circuit.
FIG. 4 is a block diagram illustrating a configuration of a time-division processing type code processing circuit according to a second embodiment.
FIG. 5 is a block diagram illustrating a configuration of a time-division processing type code processing circuit according to a third embodiment.
FIG. 6 is a block diagram illustrating a configuration of a time-division processing type code processing circuit according to a fourth embodiment.
FIG. 7 is a block diagram illustrating a configuration example of a conventional encoding circuit.
FIG. 8 is a block diagram illustrating a configuration example of a conventional decoding circuit.
[Explanation of symbols]
10 Input terminal
11 buffer
12. Parallel-to-serial conversion circuit
13 Control circuit
14 Encoding circuit
15 Memory circuit
16 output terminals
21 Memory control circuit
22 memory
23 Input buffer
24 Output buffer
31 Series-parallel conversion circuit
32 buffers
33 output terminal
41 input terminal
42 Decoding circuit
43 Control circuit
44 Memory Circuit
45 Series-parallel conversion circuit
46 buffers
47 output terminal
51 Memory control circuit
52 memory
53 input buffer
54 Output buffer
61 Input terminal
62 buffers
63 Parallel-to-serial conversion circuit

Claims (6)

A time-division processing type code processing circuit that simultaneously inputs a plurality of information signals independent of each other and outputs an encoded signal,
Time slot generating means for outputting a predetermined sequence of time slots as a timing signal,
Parallel-to-serial conversion of a plurality of information signals input in parallel, parallel-serial conversion means for sequentially assigning each information signal that appears continuously to each time slot of the timing signal,
Along with providing time-division encoding processing means for sequentially encoding each information signal output from the parallel-serial conversion means for each time slot, the time-division encoding processing means includes:
For each time slot generated by the time slot generating means, a signal processing control means for outputting a control signal related to code processing of the assigned information signal,
Encoding processing means for encoding the assigned information signal according to an instruction of a control signal output from the signal processing control means, for each time slot generated by the time slot generation means,
When the encoding processing unit encodes each information signal in a time-division manner, an internal signal storage unit that temporarily stores an internal signal used by the encoding processing unit in the encoding process,
A time-division processing type code processing circuit, comprising: a storage control means for controlling writing and reading of the internal signal to and from the internal signal storage means for each of the time slots. The time-division processing type code processing circuit according to claim 1,
The signal processing control unit outputs, as the control signal, information indicating a coding type and a coding rate,
When a plurality of coding rates used in coding applied to a plurality of input information signals are mixed, or when transmission rates of a plurality of input information signals are plural types, or when a plurality of input information signals When a plurality of types of coding are applied to the information signal, the parallel-to-serial conversion unit converts the information signal input per unit time according to at least one of the coding rate, the transmission speed, and the type of coding. A time-division processing type code processing circuit, wherein the number of time slots to be allocated is changed. The time-division processing type code processing circuit according to claim 1,
Further provided is a serial-parallel conversion means for separating each time slot of the signal output by the time-division encoding processing means and performing serial-parallel conversion to generate a plurality of encoded information signals corresponding to the plurality of input information signals. A time-division processing type code processing circuit. A time-division processing type code processing circuit that outputs a signal obtained by decoding a coded input information signal,
Time slot generating means for outputting a predetermined sequence of time slots as a timing signal,
Time-division processing decoding means for sequentially decoding each information signal allocated to each time slot and sequentially input for each time slot,
Serial-parallel conversion means for separating and serial-to-parallel converting each time slot of the information signal output from the time-division processing decoding means, and outputting a plurality of information signals simultaneously; In
For each time slot generated by the time slot generating means, a signal processing control means for outputting a control signal related to decoding processing of the assigned signal,
Decoding processing means for decoding a signal assigned to each time slot in accordance with an instruction of a control signal from the signal processing control means;
When the decoding unit decodes each information signal in a time-division manner, an internal signal storage unit that temporarily stores an internal signal used in the decoding process of the decoding unit,
A time-division processing type code processing circuit, comprising: a storage control means for controlling writing and reading of the internal signal to and from the internal signal storage means for each of the time slots. The time-division processing type code processing circuit according to claim 4,
The signal processing control unit outputs, as the control signal, information indicating a coding type and a coding rate,
When a plurality of coding rates to be applied coexist, or when a plurality of information signal transmission rates coexist, or when there are a plurality of types of decoding, the serial / parallel conversion means performs the coding rate and transmission rate processing. A time-division processing type code processing circuit, wherein the number of time slots allocated to a signal input per unit time is changed in accordance with at least one of decoding types. The time-division processing type code processing circuit according to claim 4,
Parallel-serial conversion means for simultaneously inputting a plurality of independently encoded information signals from a plurality of input terminals and parallel-to-serial conversion of the plurality of information signals in accordance with the time slot allocation; A time-division processing type code processing circuit, wherein a serial signal output from the serial conversion means is input to the time-division processing decoding means.

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