JPH10232265A - Semiconductor test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a circuit in a small scale by providing a bit counter and an output control part common in one PE(pin electronics) board, and providing a mapping register and a comparator in every channel. SOLUTION: One PE board PE1 is constituted of a bit counter 20, an output control part 90 and eight-channel serial normal reading circuits 100a-100m. A one-channel serial normal reading circuit 100a is constituted of a mapping register 30, a comparator 40 and a memory 50. With regard to the comparator 40, a bit position signal 21 from the bit counter 20 is received to one input end, the comparison output data of the mapping register 30 is received to the other input end, and only when they coincide with each other, a bit position accordance signal 41 is output. The circuit can be made small scale and a small space can be made in the PE board of a semiconductor test device in which hundreds channels are mounted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read system for performing normalization conversion to an arbitrary binary code array and reading when reading data from a memory of many channels.

[0002]

2. Description of the Related Art FIG. 5 is a conceptual diagram showing the connection of a main part for converting a plurality of memories in a plurality of PE boards into a predetermined binary code array and reading the same from a plurality of memories in the PE board of FIG. A description will be given with reference to a block diagram of a main part which is sequentially read and a diagram for explaining a conversion output from each memory of FIG. 7 into a predetermined binary code array.

Here, a brief background explanation will be given with reference to FIG.
By performing the DUT test, each memory 5
The data of the DUT test result or the data of the PASS / FAIL determination result are sequentially stored at the same address of 0 respectively. For example, a DUT (device under test) is a 20-bit AD converter, and a device in which binary code data is output in parallel from 20 pins of the DUT will be described. In this case, the test result is 20
Bit data is stored in each of the corresponding memories 50 in a distributed manner for each bit. In order to normalize and read the distributed and stored data into the original 20-bit weighted binary code and read it, as shown in FIG.
Multiple channels CH1 to C distributedly stored in PEn
It is necessary to load 1-bit data of a channel required in H8 onto a predetermined bit line on a 32-bit parallel bus 550 so as to become a weighted binary code. By the way, since the output pins and pin positions of the DUT vary depending on the type, it is necessary to provide a normalization conversion means which can be flexibly assigned to these on the PE board circuit side. Here, the normalization conversion is to restore and read the original binary code in which the bits are weighted.

As shown in FIGS. 5 and 6, a main part of the prior art is composed of PE boards PE1 to PEn and an address bus 5 as shown in FIG.
10, a parallel bus 550, and a controller 500. The controller 500 supplies all address signals by supplying an address bus 510 as an address signal, a parallel bus 550 as a bidirectional data bus, and other control signals.
Individual channels 600a-6 of E board PE1-PEn
It controls various writing and reading of 00m.

[0005] As shown in FIG. 6, the internal structure of one PE1 board includes a plurality of individual channels 600a to 600m.
Consists of The internal configuration of the main part of one individual channel 600a includes a mapping register 30, a memory 50,
It comprises an N decoder 70 and a bus driver 75. The memory 50 is used for storing DUT test result data as described in the background section above, and is connected to the pins of the DUT in a one-to-one correspondence, so that the memory 50 is stored as data dispersed in one bit for each DUT pin. ing.

The mapping register 30 can be set from the controller 500 and is a register for allocating bit positions on N-bit length code data and a setting register for enabling data bus output. Here, the N-bit length may be used in accordance with the data length of the DUT, or may be 32 bits, 16 bits, or 8 bits in accordance with the data bus of the CPU, the CPU memory, or the length of the operation register. . Here, assuming that N = 32 bits is set, 5 bits are used for the bit position assignment register. The mapping register 30 for each individual channel 600a-600m is:
Different predetermined decode setting values are set in advance in the allocation register so as to be at bit positions corresponding to the weights of the binary codes output from the DUT.

[0007] The decoder 70 outputs an output enable signal for enabling a tri-state output terminal of any bit of the 32-bit bus driver. For example, upon receiving a 5-bit decode setting value from the mapping register 30, 32 enable signals decoded to 5 to 32 bits are supplied to each output enable terminal of the bus driver 75. However, when the output enable setting of the mapping register 30 is OFF, all bits of the bus driver 75 are OFF. Further, one-bit read data 51 from the memory 50 is connected and supplied to all input terminals of the bus driver 75. As a result, the data can be read on an arbitrary bit line on a 32-bit data bus. As described above, an arbitrary individual channel 600 having several hundred channels
Of the memory 50, the data can be read out as parallel data obtained by normalizing and converting a desired channel into a binary code array having a desired weight and OR-added to 32 bits. As described above, the circuit is directly converted into a binary code array by a normalization, read out, and variably set.

The storage in the memory 50 is performed during a device test, and a high-speed real-time operation is required. On the other hand, reading of the contents of the memory 50 is performed every time the device test or each test item is completed, and high-speed operation is not required. For this reason, the memory 50 is stored in software via the data bus.
Read the contents and execute.

As described above, it is not preferable to provide the decoder 70 and the bus driver 75 for each of the individual channels 600 having several hundred channels, because the circuit scale and power consumption increase. Also, there is a practical difficulty in terms of mounting space in a semiconductor test apparatus, particularly a PE board, which requires high-density mounting.

[0010]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a read operation for normalizing and converting a multi-channel memory into a predetermined binary code array.
It is an object of the present invention to realize memory reading of an individual channel by a serial method capable of relatively reducing the circuit scale.

[0011]

FIGS. 2 and 3 show a solution according to the present invention. First, in order to solve the above problem, in the configuration of the present invention, all the PE boards PE1
To the serial transmission bus 250 connected to the PE
In reading the contents of the memory 50 of all the channels in the boards PE1 to PEn, means for arbitrarily assigning the read bit position on the code data having a predetermined N-bit length to each memory 50 circuit of each channel; A means for outputting a serial array normalized to a predetermined weighted binary code on a serial transmission bus, and a means for reading the normalized serial data. As a result, DUs are stored in a plurality of PEs of the semiconductor test apparatus.
A plurality of memories 5 for storing T measurement results for each DUT pin
0, which realizes a read operation for normalizing conversion to a predetermined binary code array by a serial method in reading memory contents.

FIG. 1, FIG. 2, FIG. 3, and FIG. 4 show a solution according to the present invention. Second, in order to solve the above-mentioned problem, in the configuration of the present invention, all the PE boards PE1
, A dedicated serial transmission bus 250 connected to PEN to serially read and transmit the contents of all memories 50;
A bit counter 20 that generates bit position information of a predetermined N-bit serial output string for each PE board, and (A) allocates a bit position on N-bit length code data to each memory 50 circuit of each channel A mapping register 30 for setting and output enable setting to the serial bus; and (B) receiving an output signal of the bit counter 20 and an output signal of the mapping register 30,
A comparator 40 is provided for detecting whether it is a timing to serially output 0 contents. If any output signal of the comparator 40 of each channel is present for each PE board,
The contents read from the memories 50 of the E boards PE1 to PEn are synchronized with the clock timing and the serial transmission bus 250
An output control unit 90 for receiving the serial data from each PE board, converting the received serial data into parallel data and outputting the parallel data, and a dedicated serial via the serial / parallel converter 200. The configuration means is a controller 500 that reads serial data on the transmission bus 250. Thus, the plurality of PEs of the semiconductor test apparatus have the plurality of memories 50 for storing the measurement results of the DUT for each DUT pin, and read out the contents of the memory to the controller 500 side from the memory of a large number of channels into a predetermined binary code array. The reading for normalization conversion can be realized by a relatively small-scale circuit using a serial method.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

FIG. 1 is a block diagram of a main part of a single PE board shown in FIG. 1 for serially reading from a plurality of memories in a predetermined binary code arrangement order in a single PE board; FIG. 3 is a conceptual diagram of a main part connection for converting into an array and serially reading, an operation explanatory diagram of serial reading in FIG. 3, and a block diagram of another main part for serial reading in one PE board in FIG. explain. Here, it is assumed that the memory 50 of M = 8 channels is provided in one PE board, and the serial output length is assumed to be N = 32 bits.

The overall structure of the present invention is as shown in FIG.
PE boards PE1 to PEn, an address bus 510,
Serial / parallel converter 200, serial transmission bus 250, parallel bus 550, controller 500
And With this configuration, the address bus 510, the parallel bus 550, and the controller 500 are the same as those in the related art. Further, the parallel bus 550 is not used for normalized reading from the multiple memories 50.

The serial transmission bus 250 is a dedicated bus controlled by the controller 500 and connected to all the PE boards, for normalizing the contents of all the memories 50 as desired and reading them out serially. Specifically, as shown in FIG.
It comprises a reference serial clock 201, one serial bus 205, and a data enable signal 202 for synchronization and output control. Further, as shown in FIG.
At the time of reading, the address bus 510 is used in conjunction with the operation. At this time, the address signal 511 continuously supplies the same address in one read cycle period, and after reading, supplies the next desired address and repeats the read operation in the same manner. It should be noted that another serial transmission bus for supplying a desired serial bus control signal corresponding to the circuit on the PE board side may be used.

As shown in FIG. 1, the main configuration of one PE board according to the present invention is a single bit counter 20.
, One output control unit 90, and eight serialized normalization read circuits 100a to 100m. The internal configuration of the main part of the one-channel serial normalization read circuit 100a includes a mapping register 30, a comparator 40, and a memory 50. In this configuration, the mapping register 30 and the memory 50 in each channel are the same as the conventional one.

The bit counter 20 is for generating bit position information of a predetermined N-bit serial output string, and supplies the bit position information to an 8-channel serial normalization read circuit.
Specifically, it is a 5-bit counter, and is a binary counter that receives the serial clock 201 from the controller 500, counts the serial clock 201, and outputs a bit position signal 21 of a serial output string having a length of N = 32 bits. . still,
This counter may be an N-ary counter. The bit counter 20 is initialized and cleared in response to the data enable signal 202 from the controller 500 side. Since the number of output signals of the bit counter 20 is a small number, for example, about five, this function can be implemented by the controller 5 if desired.
00, and may be supplied to all PE boards in a bus format.

The comparator 40 in each channel detects whether or not it is time to perform serial output from its own channel. More specifically, the bit position signal 21 from the bit counter 20 is received at one input terminal of the comparator, and the comparison output data 31 of the mapping register 30 is received at the other input terminal. The bit position match signal 41 is output only in the cycle. However, the output of the bit position match signal 41 is enabled only when the serial bus output enable setting of the mapping register 30 is ON.

The output terminal of the memory 50 of each channel is wired-OR connected, and the bit position coincidence signal 41 output from the comparator 40 is connected to the output enable terminal of this memory element, and this signal is valid. Only in the case of, the memory contents are output from the tri-state output terminal of the OR connection. As a result, the read data 51 is output only from the memory at the timing to be serially output. Note that, for example, the lower 16 address signals in the address bus 510 from the controller 500 are connected to the address input terminals of the memories of all the PE boards at the time of serial reading, as in the conventional case. Here, the storage capacity of the memory 50 is 64K
It is assumed that the memory device is an I / O separated terminal type memory device having a × 1 bit configuration.

The output control unit 90 synchronizes the contents of the memory with the clock timing at the timing of serial output from the board, and
Is output to Specifically, eight comparators 40
, If there is a bit position match signal 41 in any of
The read data 51 from the output terminal of the memory 50 connected to the R is transmitted onto the serial bus 205. This example is shown in CHn0, CHn1 to CHn30, and CHn31 shown in FIG. As shown in FIG. 1, the internal circuit includes an 8-input OR gate 97, a 2-input NAND gate 98, and a tri-state driver 99. An eight-input OR gate 97 OR-adds the eight bit position coincidence signals 41, and a gate 98 outputs the data enable signal 20 from the controller 500 side.
Turn on tri-state driver 99 only when 2 is valid
Then, the read data 51 is sent out onto the serial bus 205.

The serial / parallel converter 200 is shown in FIG.
As shown in (1), serial data is converted into parallel data and output. Specifically, as shown in FIG. 3, a 32-bit serial data stream 210 on the serial bus 205 is received, and the 32-bit parallel data 288 is received.
And supplies it to the controller 500.
This function may be incorporated in the controller 500 if desired.

The controller 500 according to the present invention is for normalizing a serial bus to a predetermined binary code and controlling readout. Specifically, in the memories 50 having a plurality of PE boards, the mapping register 30 is set in advance so that any memory 50 is normalized.
The serial transmission bus 250 is controlled to read and control as parallel data normalized to a predetermined 32-bit binary code via the serial / parallel converter 200.

With the above-described structure, the contents of the memory 50 of an arbitrary channel having several hundred channels are normalized to a binary code array allocated to a desired bit position in 32 bits for a desired channel as in the conventional case. It can be read as converted parallel data.

According to the configuration of the present invention, a common bit counter 20 and an output control unit 90 are provided in one PE board, and a mapping register 30 and a comparator 40 are provided for each channel. This circuit has the advantage that the circuit scale can be made much smaller than before. This has the effect of reducing the space and achieving lower cost on a PE board of a semiconductor test apparatus that requires several hundred channels and requires high-density mounting.

As described above, according to the present invention, the serial transmission bus 250 connected to all the PE boards PE1 to PEn
Means for arbitrarily assigning a read bit position on code data having a predetermined N-bit length to each memory 50 circuit of each channel in reading contents of memories 50 of all channels in all PE boards PE1 to PEn. This is realized by means for outputting the contents of the memory 50 on a serial transmission bus in a serial array obtained by normalizing and converting the contents of the memory 50 into a binary code having a predetermined weight, and means for reading the normalized serial data.

Although the specific configuration example of the serial normalization read circuit and the output control section 90 in the above embodiment has been described on the assumption that the memory element is of an I / O separated terminal type,
In the case of the / O common terminal type memory element, the read data 51 of the memory 50 is AND gated with the bit position match signal 41 by the configuration shown in FIG. And the circuit configuration of driving the serial bus 205 by the bus driver 95 of an open collector type driver element can be similarly implemented.

[0028]

According to the present invention, the following effects can be obtained from the above description. This can be realized by providing a common bit counter 20 and output control unit 90 within one PE board, and providing a mapping register 30 and a comparator 40 for each channel. As a result, there is an advantage that the circuit scale can be made much smaller than before.
This is highly effective in that it can be implemented in a small space and at a lower cost on a PE board of a semiconductor test apparatus which is mounted with several hundred channels and requires high-density mounting.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a single PE board according to the present invention, which reads serially from a plurality of memories in a predetermined binary code arrangement order.

FIG. 2 is a conceptual diagram of a main part connection according to the present invention, in which a plurality of memories in a plurality of PE boards are converted into a predetermined binary code array and serially read out.

FIG. 3 is an explanatory diagram of an operation of serial reading according to the present invention.

FIG. 4 is a block diagram of another main part of the present invention for serially reading data on one PE board.

FIG. 5 is a conventional connection diagram of a main part, which converts a plurality of memories in a plurality of PE boards into a predetermined binary code array and serially reads them.

FIG. 6 is a block diagram of a main part of the related art for reading from a plurality of memories in a PE board in a predetermined binary code arrangement order.

FIG. 7 is a diagram illustrating a conventional conversion output from each memory to a predetermined binary code array.

[Explanation of symbols]

 PE1 to PEn PE board 20 bit counter 30 mapping register 40 comparator 50 memory 70 decoder 75 bus driver 90 output control unit 92 AND gate 94 OR gate 95 bus driver 97 8 input OR gate 98 2 input NAND gate 99 tristate driver 100a １００100 m Serial normalization read circuit 200 Serial / parallel converter 205 Serial bus 250 Serial transmission bus 500 Controller 510 Address bus 550 Parallel bus

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[Procedure amendment]

[Submission date] May 19, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

The mapping register 30 can be set from the controller 500 and is a register for allocating bit positions on N-bit length code data and a setting register for enabling data bus output. Here, the N bit length may be used according to the data length of the DUT, or may be 32 bits, 16 bits, or 8 bits according to the length of the CPU data bus, CPU memory, or arithmetic register. is there. Here, assuming that N = 32 bits is set, 5 bits are used for the bit position assignment register. The mapping register 30 for each individual channel 600a-600m is:
Different predetermined decode setting values are set in advance in the allocation register so as to be at bit positions corresponding to the weights of the binary codes output from the DUT.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

The storage in the memory 50 is performed during a device test, and a high-speed real-time operation is required. On the other hand, reading of the contents of the memory 50 is performed every time the device test or each test item is completed, and high-speed operation is not required. Therefore, the controller reads out and executes the contents of the memory 50 via the data bus.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

FIG. 1, FIG. 2, FIG. 3, and FIG. 4 show a solution according to the present invention. Second, in order to solve the above-mentioned problem, in the configuration of the present invention, all the PE boards PE1
, A dedicated serial transmission bus 250 connected to PEN to serially read and transmit the contents of all memories 50;
A bit counter 20 that generates bit position information of a predetermined N-bit serial output string for each PE board, and (A) allocates a bit position on N-bit length code data to each memory 50 circuit of each channel Mapping for setting and output enable setting to serial transmission bus
A register 40, and (B) a comparator 40 which receives the output signal of the bit counter 20 and the output signal of the mapping register 30 and detects whether or not it is time to serially output the contents of the memory 50. When there is an output signal from any one of the comparators 40 of each channel, the output control unit outputs the contents read from the memories 50 of the PE boards PE1 to PEn to the serial transmission bus 250 in synchronization with the clock timing. 90, a serial / parallel converter 200 that receives the serial data output from each PE board, converts it into parallel data, and outputs the parallel data.
The controller 500 reads out serial data on a dedicated serial transmission bus 250 via the serial / parallel converter 200. This allows
DU measurement results of DUT in multiple PEs of semiconductor test equipment
A plurality of memories 50 are stored for each T pin, and when reading the contents of the memory to the controller 500 side, the reading for normalizing conversion from the memory of many channels to a predetermined binary code array is performed by a relatively small-scale circuit serial method. Reading can be realized.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction contents]

The serial transmission bus 250 is a dedicated bus controlled by the controller 500 and connected to all the PE boards, for normalizing the contents of all the memories 50 as desired and reading them out serially. Specifically, as shown in FIG.
Reference serial clock 201 and one serial
It comprises a transmission bus 205 and a data enable signal 202 for synchronization and output control. As shown in FIG. 3, when reading the memory 50, the address bus 510 is used in conjunction with the operation. At this time, the address signal 511 is 1
The same address is continuously supplied during the read cycle period. After reading, the next desired address is supplied and the read operation is repeated in the same manner. It should be noted that another serial transmission bus for supplying a desired serial bus control signal corresponding to the circuit on the PE board side may be used.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction contents]

The output control unit 90 synchronizes the contents of the memory with the clock timing at the timing of serial output from the board, and
Is output to Specifically, eight comparators 40
, If there is a bit position match signal 41 in any of
The read data 51 from the output terminal of the memory 50 connected to the R is transmitted onto the serial transmission bus 205. This example is shown in CHn0, CHn1 to CHn30, and CHn31 shown in FIG. As shown in FIG. 1, the internal circuit includes an 8-input OR gate 97, a 2-input NAND gate 98, and a tri-state driver 99. An 8-input OR gate 97 OR-adds the eight bit position coincidence signals 41, and a gate 98 only outputs the tristate driver 99 when the data enable signal 202 from the controller 500 is valid.
Is turned on to read out the read data 5 on the serial transmission bus 205.
Send 1

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0022

[Correction method] Change

[Correction contents]

The serial / parallel converter 200 is shown in FIG.
As shown in (1), serial data is converted into parallel data and output. Specifically, as shown in FIG. 3, a 32-bit serial data stream 210 on the serial transmission bus 205 is
It is converted to 88 and supplied to the controller 500. Note that this function can be included in the controller 500 if desired.
May be stored.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0027

[Correction method] Change

[Correction contents]

Although the specific configuration example of the serial normalization read circuit and the output control section 90 in the above embodiment has been described on the assumption that the memory element is of an I / O separated terminal type,
In the case of the / O common terminal type memory element, the read data 51 of the memory 50 is AND gated with the bit position match signal 41 by the configuration shown in FIG. , And a circuit configuration in which the serial transmission bus 205 is driven by the bus driver 95 of an open collector type driver element can be similarly implemented.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] Explanation of sign

[Correction method] Change

[Correction contents]

[Description of Signs] PE1 to PEn PE board 20 bit counter 30 mapping register 40 comparator 50 memory 70 decoder 75 bus driver 90 output control unit 92 AND gate 94 OR gate 95 bus driver 97 8 input OR gate 98 two input NAND gate 99 Tri-state driver 100a-100m Serial normalization read circuit 200 Serial / parallel converter 205 Serial transmission bus 250 Serial transmission bus 500 Controller 510 Address bus 550 Parallel bus

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction contents]

The bit counter 20 is for generating bit position information of a predetermined N-bit serial output string, and supplies the bit position information to an 8-channel serial normalization read circuit.
Specifically, it is a 5-bit counter, and is a binary counter that receives the serial clock 201 from the controller 500, counts the serial clock 201, and outputs a bit position signal 21 of a serial output string having a length of N = 32 bits. . still,
This counter may be an N-ary counter. The bit counter 20 is initialized and cleared in response to the data enable signal 202 from the controller 500 side. Since the number of output signals of the bit counter 20 is a small number, for example, about five, this function can be implemented by the controller 5 if desired.
A built in 00, it may be supplied to all the PE board bus format.

[Procedure amendment 11]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG.

[Procedure amendment 12]

[Document name to be amended] Drawing

[Correction target item name] Figure 2

[Correction method] Change

[Correction contents]

FIG. 2

[Procedure amendment 13]

[Document name to be amended] Drawing

[Correction target item name] Figure 3

[Correction method] Change

[Correction contents]

FIG. 3

[Procedure amendment 14]

[Document name to be amended] Drawing

[Correction target item name] Fig. 4

[Correction method] Change

[Correction contents]

FIG. 4

Claims (2)

[Claims] 1. A semiconductor test apparatus having a plurality of memories for storing measurement results of a DUT (device under test) in a plurality of PEs (pin electronics) of the semiconductor test apparatus, and connected to all PE boards when reading the contents of the memory. A serial transmission bus, a means for arbitrarily assigning a read bit position for each memory circuit of each channel, a means for outputting the assigned memory contents to the serial transmission bus, and a means for reading the normalized serial data. A semiconductor test apparatus comprising: 2. A semiconductor test apparatus comprising: a plurality of PEs each having a plurality of memories for storing measurement results of a DUT in a plurality of PEs; in reading out the contents of the memory to a controller, the memories are connected to all the PE boards to store the contents of the entire memory; A dedicated serial transmission bus for serially reading and transmitting the data, a bit counter for generating bit position allocation information of a predetermined N-bit serial output string for each PE board, and (A) N for each channel memory circuit. Receiving a mapping register for setting a bit position on bit-length code data and setting an output enable to the serial bus; and (B) receiving an output signal of the bit counter and an output signal of the mapping register. And a comparator for detecting whether or not it is time to serially output the contents of the memory. When an output signal is present in any of the comparators of the channel, an output control unit that reads the memory content of the PE board and outputs the content to the serial transmission bus in synchronization with a clock timing. In response to the output serial data,
A serial-to-parallel converter that converts and outputs parallel data, and a controller that reads serial data on the serial transmission bus via the serial-to-parallel converter; apparatus.