JP3508547B2 - Si wafer etching method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Si wafer etching method suitable for forming a Si diaphragm such as a semiconductor pressure sensor or a semiconductor acceleration sensor.

[0002]

2. Description of the Related Art An example of a method for forming a Si diaphragm such as a semiconductor pressure sensor or a semiconductor acceleration sensor is shown in FIG.
And FIG. 43. In the case of this method, first, as shown in FIG. 42, a gauge (strain gauge) 2 having a predetermined shape is formed on the lower surface of the Si wafer 1, and an etching mask 3 made of SiO ₂ or SiN film is formed on the upper surface of the Si wafer 1. Form. Then, as shown in FIG.
The lower surface side of the i-wafer 1 is attached to the ceramic substrate 5 via a protective material 4 such as wax. As a result, the lower surface side of the Si wafer 1 is protected.

Then, as shown in FIG. 43, the Si wafer 1 and the ceramic substrate 5 are stored in a container 6 and an anisotropic etching liquid 7 made of, for example, an aqueous KOH solution is used.
It is soaked in and configured to perform chemical etching. In this case, after setting a plurality of Si wafers 1 (and the ceramic substrate 5) in the carrier 8,
The entire carrier 8 is immersed in the anisotropic etching liquid 7.

When the Si wafer 1 is dipped in the anisotropic etching solution 7, as shown by a chain double-dashed line in FIG.
The etching surface corresponding to the opening 3a of the etching mask 3 is melted to form the recess 9. The bottom portion of the recess 9 becomes the diaphragm 9a. Here, since the etching with the anisotropic etching solution 7 is anisotropic etching, the end portions 9b and 9b of the diaphragm 9a become corner portions. And thus, the diaphragm 9
If the end portions 9b and 9b of a are corner portions, the diaphragm 9a
However, there is a drawback in that the pressure resistance of is low.

Therefore, in the conventional structure, the recess 9 is formed.
The Si wafer 1 on which is formed is dipped in an isotropic etching solution composed of, for example, an acid-based etching solution to perform isotropic etching on the inner surface of the recess 9 to round the end of the diaphragm 9a. .

[0006]

However, since the isotropic etching process executed in the above conventional structure is a diffusion-controlled reaction, it is difficult to control the reaction. Further, the acid-based isotropic etching solution had a large change with time in composition. Therefore, there is a problem in that the depth dimension of the recess 9 formed in the Si wafer 1, that is, the thickness dimension of the formed Si diaphragm 9a varies considerably. Further, in the above-described conventional configuration, there are problems that the inner bottom surface of the recess 9, that is, the surface of the Si diaphragm 9a is considerably roughened, and that the dimension D1 of the diaphragm shown in FIG. 17 varies. This is because the surface of the Si wafer 1 whose crystal orientation is (110) (hereinafter, referred to as (110) surface) is anisotropic etching liquid 7
This is because the impurities such as metal ions (for example, Pb) contained in the anisotropic etching solution in a trace amount are adsorbed on the etching surface of the Si wafer 1 and the etching rate is changed by the masking action during the etching by.

Therefore, an object of the present invention is to improve the accuracy of the depth dimension of the recess while allowing the end portion of the inner bottom of the recess formed when the Si wafer is anisotropically etched to be rounded. A method of etching a Si wafer is provided. Another object of the present invention is to improve the smoothness of the inner bottom surface of the recess formed when the Si wafer is etched and the accuracy of the recess size.
An i-wafer etching method is provided.

[0008]

According to a first aspect of the present invention, after performing the first step of anisotropically etching a Si wafer to a predetermined depth, a positive voltage for anodizing is applied to the Si wafer. Then, the second step of performing isotropic etching while anodizing the etching surface that appeared in the first step is performed. In this case, the corners of the inner bottom edge of the recess of the Si wafer produced by the anisotropic etching in the first step are rounded by the anodic oxidation in the second step, that is, isotropic etching. Then, the isotropic etching reaction by anodic oxidation is reaction-controlled, not diffusion-controlled. In addition, since etching proceeds very slowly as compared with the anisotropic etching of the first step, that is, the etching rate is very small, etching control is easy. For this reason,
It is possible to prevent variations in the thickness of the diaphragm as much as possible.

According to the second aspect of the present invention, in the first step, the Si wafer is anisotropically etched while applying a voltage to the Si wafer such that anisotropic etching is possible. According to this method, the potential of the etching surface of the Si wafer is shifted in the positive direction, and the potential difference from the metal ions that are more noble than Si is reduced, so that impurities such as metal ions are less likely to be adsorbed on the etching surface. Therefore, even if the etching surface is the (110) surface, the etching surface becomes smooth, the smoothness of the inner bottom surface of the recess is improved, and at the same time, the dimensional variation of the diaphragm can be suppressed.

According to the third aspect of the present invention, the anisotropic etching solution is KOH, and the temperature of the anisotropic etching solution is set to a high temperature of 80 ° C. or higher in the second step. When a positive voltage for anodic oxidation is applied and the Si wafer is anodized and isotropically etched, the etching rate becomes high. As a result, it is possible to reduce the time required for rounding the inner bottom end of the recess.

According to the invention of claim 4, in the first step,
Since the Si wafer is anisotropically etched while applying a positive voltage to the P layer of the PN-bonded Si wafer so as to be anisotropically etched, the etching surface becomes smooth and the inner bottom surface of the recess is improved in smoothness. At the same time, dimensional variations of the diaphragm can be suppressed. Then, in this case, after performing the first step, the application of the positive voltage to the P layer of the Si wafer is stopped, and the positive voltage for anodization is applied to the N layer of the Si wafer to cause the vicinity of the PN junction layer. Then, the anodizing step of anodizing the Si wafer was performed. According to this method, Si is formed near the PN junction layer by the anodization.
Since the etching of the wafer is automatically stopped, the accuracy of the diaphragm thickness can be increased. Further, in the case of the above method, after performing the anodizing step, in the second step, the application of the positive voltage to the N layer of the Si wafer is stopped and
A positive voltage for anodic oxidation was applied to the P layer of the wafer so that the Si wafer was isotropically etched. As a result, it is possible to round the corners of the inner bottom end of the recess of the Si wafer caused by the anisotropic etching in the first step, and to prevent variations in the thickness of the diaphragm as much as possible. Even when a voltage is applied to the PN junction in the second step for anodic oxidation, it has the effect of rounding the corners appearing at the ends of the inner bottom of the Si wafer recess.
Only the vicinity of the joint can be rounded, and it cannot be sufficiently rounded. Therefore, by performing a step of applying a voltage for anodic oxidation to the P layer, the corners can be sufficiently rounded as in the first aspect.

Also in the fifth aspect, similarly to the fourth aspect, the diaphragm thickness can be accurately controlled by applying the voltage for anodic oxidation to the PN junction, and the voltage for anodic oxidation is applied to the P layer. Thus, the corners appearing at the inner bottom edge of the Si wafer recess can be sufficiently rounded.

According to the sixth aspect of the invention, since the resistors are connected in series to the Si wafer to apply the voltage, the voltage applied when the anisotropic wafer is anisotropically etched is applied to the Si wafer. The range of the applied voltage is widened and the voltage control becomes easy. In the case of this configuration, when the resistance value of the resistor is changed according to the type of the Si wafer and the etching process as in the invention of claim 7, the voltage control can be more easily performed.

Further, in the invention of claim 8, when the voltage is applied to the Si wafer, the voltage applied to the Si wafer is adjusted so that the current flowing through the Si wafer has a predetermined value. As a result, voltage control becomes easy and the required voltage can be applied accurately.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment in which the present invention is applied to a structure for forming a Si diaphragm such as a semiconductor pressure sensor or a semiconductor acceleration sensor will be described below with reference to FIGS.
This will be described with reference to 1. First, S used in this embodiment
The i-wafer will be briefly described with reference to FIG. In FIG. 10, the Si wafer 11 is composed of a P-type silicon wafer (for example, having a specific resistance of 10 to 20 Ω · cm), and the lower surface, which is one surface of the Si wafer 11, is, for example, CV.
An N-type Si layer (N epi layer) 61 is formed by D. Then, the N-type Si layer 61 is formed with a gauge 62 made of P ^{+ in} a predetermined shape, and a P ⁺ isolation layer 63 is formed. On the lower surface of the P ⁺ isolation layer 63, for example, an Al-made power feeding electrode 64 that is substantially in a lattice shape as a whole is formed. Power is supplied from the electrode 64 to the P-type Si layer which is the etching surface through the P ⁺ isolation layer 63.

On the upper surface, which is the other surface of the Si wafer 11, an etching mask 12 made of, for example, SiO ₂ or SiN film is formed. The Si wafer 1
As 1, the N-type silicon wafer and the P-type silicon wafer (without the N layer) can be used in addition to the P-type silicon wafer (with the N layer). These wafers are etched to a predetermined depth from the original thickness to form a diaphragm.

Then, similarly to the conventional structure (see FIG. 43), the right side surface of the Si wafer 11 is attached to, for example, a ceramic substrate via a protective material such as wax. The protective material and the ceramic substrate are not shown in FIG. As a result, the right side surface of the Si wafer 11 is protected.

Then, as shown in FIG. 2, the Si wafer 11 (and the ceramic substrate) thus formed is stored in a container 13, and an anisotropic etching solution 1 made of, for example, KOH is used.
Etching is carried out by immersing in 4. in this case,
The Si wafer 11 (the power supply electrode 64 thereof) is connected in advance to the positive terminal 15 a of the variable power supply circuit 15 via the current detector 16. In addition, the negative terminal 1 of the variable power supply circuit 15
The Pt electrode 17 connected to 5b is previously immersed in the anisotropic etching liquid 14 in the container 13. The variable power supply circuit 15 is, for example, a minute DC voltage V of about 0 to 0.2V.
1 and a DC voltage V2 of, for example, 0.6 V or more can be output.

Further, the variable power supply circuit 15 and the Si wafer 11
The current detector 16 provided between the Si wafer 1 and the
1. Detecting the magnitude of the current flowing in the circuit composed of the anisotropic etching liquid 14 and the Pt electrode 16, the detection signal is given to the control device 18. The control device 18 has a function of controlling the etching process as a whole, and changes the value of the DC voltage output from the variable power supply circuit 15 by giving a command signal to the variable power supply circuit 15, and The output of the DC voltage can be stopped (disconnected).

Further, the controller 18 is constructed so as to control the temperature of the anisotropic etching liquid 14 in the container 13. Specifically, while the container 13 is housed in the oil bath, the control device 18 controls the energization of the heater of the oil bath and the temperature of the silicon oil stored in the oil bath (or the inside of the container 13). The temperature of the anisotropic etching liquid 14) is detected. Thereby, the control device 18 sets the temperature of the anisotropic etching liquid 14 in the container 13 to a desired temperature within a temperature range of about 70 to 120 ° C. with an accuracy of about ± 2 to 3 ° C., for example. Is possible.

Next, referring also to FIGS. 1 and 3 to 9,
An etching method for etching the Si wafer 11 will be specifically described. First, as shown in FIG. 2, for example, a P-type Si wafer 11 is dipped in an anisotropic etching liquid 14 made of a KOH aqueous solution having a liquid temperature of, for example, 110 ° C. and a concentration of 32 wt%, and the controller 13 The etching control operation is started. Then, the control device 13
Gives a command signal to the variable power supply circuit 15 to cause the variable power supply circuit 15 to output a minute DC voltage V1. As a result, the minute DC voltage V1 is applied to the Si wafer 11, and in this applied state, the process of anisotropically etching the Si wafer 11 proceeds. That is, the Si wafer 1
The etching surface corresponding to the opening 12a of the etching mask 12 of No. 1 is dissolved by the anisotropic etching liquid 14 to form the recess 19.

Here, the minute DC voltage V1 applied to the Si wafer 11 is a positive voltage that allows anisotropic etching,
For example, it is 0.1 V, which will be described later in detail. Then, as described above, the step of anisotropically etching the Si wafer 11 (hereinafter referred to as the first step) is configured to be executed by the control device 18 for a predetermined time, for example, about 30 minutes. The length of the predetermined time for performing the first step may be appropriately set based on the depth dimension of the recess 19 to be formed and the etching rate of the anisotropic etching liquid 14.

Here, the etch rate of the anisotropic etching liquid 14 changes depending on the type of liquid, the temperature of the liquid, the concentration of the liquid, and the magnitude of the positive voltage applied to the Si wafer 11. Specifically, when the anisotropic etching liquid 14 is KOH, the liquid temperature is 110 ° C., and the concentration is 32 wt%, the etching rate of the anisotropic etching liquid 14 is
It changes as shown in FIG. 7 according to the positive voltage applied to the Si wafer 11. It can be seen from FIG. 7 that if the applied positive voltage is a minute DC voltage of about 0 to 0.2 V, the etching rate is sufficiently high and the anisotropic etching proceeds promptly. On the other hand, it can be seen from FIG. 7 that when the applied positive voltage is a DC voltage of 0.6 V or more, the etching rate becomes very small and the etching almost stops. The reason why the etching rate becomes very small is that the etched surface of the Si wafer 11 is anodized by the application of the DC voltage of 0.6 V or more.

By the execution of the first step, as shown in FIG.
As shown in FIG. 5, the recess 19 is formed in the Si wafer 11. In this case, since the concave portion 19 is formed by anisotropic etching, the shape of the end portion 19b of the inner bottom portion 19a of the concave portion 19 is a corner portion. The inner bottom portion 19 of the recess 19 is
The a becomes the diaphragm 20.

After that, the controller 18 controls the variable power supply circuit 15
To the variable power supply circuit 15, for example, 3.
A DC voltage V2 of 0 V is output. As a result, the DC voltage V2 is applied to the Si wafer 11,
The etched surface of the Si wafer 11 is anodized. In this case, the DC voltage V2 corresponds to a positive voltage for anodic oxidation.

Here, by applying the DC voltage V2,
When the etching surface of the Si wafer 11 is anodized, the etching is almost stopped, but in reality, as shown in FIG. 7, the etching rate is very small (the etching rate of the first step is less than the etching rate). Etching proceeds only about 1/50). The reason why the etching progresses in this way is, as shown in FIGS. 6A, 6B, and 6C, the operation of anodizing the etched surface of the Si wafer 11 and the anodized oxide film (SiO ₂ ). Since the operation of melting 11a progresses at the same time, as a result, the Si wafer 1
The surface of 1 (etching surface) is etched at a fairly slow rate.

The above etching is isotropic etching while the Si wafer 11 is immersed in the anisotropic etching liquid 14. This is because the dissolution of the oxide film (SiO ₂ ) 11a does not depend on the plane orientation of the Si wafer 11. The thickness of the oxide film 11a is, for example, 20 to 30 Å.

Further, in this embodiment, as described above, Si
The process of performing isotropic etching while the anodized surface of the wafer 11 is anodized (hereinafter referred to as the second process) is performed for, for example, about 10 minutes. As a result, as shown by the hatched area in FIG. 4, the process of isotropic etching of the inner surface of the recess 19 progresses, and as shown in FIG. 5, the shape of the end 19b of the inner bottom 19a of the recess 19 is increased. Is rounded. In this case, even if the etching rate of the isotropic etching is a considerably small value, it is sufficient to round the shape of the end portion 19b of the inner bottom portion 19a of the recess 19 for about 10 minutes.

The time for performing the second step is not limited to the above 10 minutes, but the type of anisotropic etching solution 14, the temperature of the solution, the positive voltage V2 applied to the Si wafer 11, and the like. It may be set appropriately according to the value of Specifically, the Si wafer 11 is a P type, the anisotropic etching liquid 14 is a KOH aqueous solution, and the liquid temperature thereof is, for example, 11.
When the temperature is 0 ° C. and the concentration is 32 wt%, the rounding amount of the end portion 19 b of the inner bottom portion 19 a of the recess 19 and the Si wafer 11
It has been confirmed by an experiment that the relationship between the application time of the positive voltage V2 applied to the Si wafer 11 (that is, the anodic oxidation time) and the value of the positive voltage V2 applied to the Si wafer 11 is as shown in FIG.

In FIG. 8, the straight line A1 is the positive voltage V2.
Is 1.0 V, and the straight line A2 has a positive voltage V2 of 2.
This is the case of 0V, and the straight line A3 is the case where the positive voltage V2 is 3.0V. If the Si wafer 11 is of N type,
It hardly changes with the positive voltage V2, and becomes almost only the straight line A1.

Further, the positive voltage V applied to the Si wafer 11
When 2 is 3.0 V, for example, the inner bottom portion 19 of the recess 19 is
The amount of rounding of the end portion 19b of a, the temperature of the anisotropic etching liquid 14, and the application time of the positive voltage V2 (that is, anodization time)
It was confirmed by an experiment that the relationship with the relationship between and is as shown in FIG. In FIG. 9, the straight line B1 indicates that the liquid temperature is 80 ° C.
The straight line B2 is the case where the liquid temperature is 100 ° C., and the straight line B3 is the case where the liquid temperature is 110 ° C.

After that, when the execution of the second step is completed, the Si wafer 11 is subjected to S
The i-wafer 11 is pulled out of the anisotropic etching solution 14 and the Si wafer 11 is washed with water. This allows Si
The process of forming the concave portion 19, that is, the diaphragm 20 on the wafer 11 is completed.

According to this embodiment having such a configuration, the first
When the concave portion 19 is formed by anisotropically etching the Si wafer 11 in the step of 1., a corner portion is generated at the end portion 19b of the inner bottom portion 19a of the concave portion 19. This corner portion is different from that of the second step. It is rounded by performing anodization, i.e. isotropic etching. By this rounding process,
The pressure resistance strength of the diaphragm 20 of the manufactured Si wafer 11 becomes sufficiently high. The isotropic etching by the anodic oxidation in the second step proceeds much more slowly than the anisotropic etching in the first step, so that the etching control is easy. Therefore, it is possible to prevent variations in the depth dimension of the recess 19, that is, the thickness dimension of the diaphragm 20, as much as possible.

Further, in the above embodiment, in the first step of anisotropically etching the Si wafer 11 to a predetermined depth, while applying a minute positive voltage V1 to the Si wafer 11 that is anisotropically etchable. , The Si wafer 11 is anisotropically etched. In this case, the Si wafer 1
Since the potential of the etched surface of No. 1 shifts to the positive direction and the potential difference with the metal ion which is more noble than Si becomes smaller, it becomes difficult to adsorb impurities such as metal (for example, Pb) on the etched surface. Therefore, according to the above embodiment, even if the etching surface of the Si wafer 11 is the (110) surface, the etching surface becomes smooth, and the smoothness of the inner bottom surface 19a of the recess 19 is further improved. In addition, variations in dimensions are reduced.

In the above embodiment, the current flowing through the Si wafer 11 is detected by the current detector 17, and the initial current density of the etching surface, that is, the value obtained by dividing the initial etching current by the area to be etched is 0. .10 to 0.15
The voltage V applied to the Si wafer 11 by the controller 18 and the variable power supply circuit 15 so as to be about mA / mm ^2.
The size of 1 is adjusted. Here, FIG. 11 shows the relationship between the voltage and the initial current density of the etching surface when a positive voltage is applied to the P-type Si wafer 11. In the case of the above-described embodiment, as described above, when the magnitude of the voltage V1 applied to the Si wafer 11 is adjusted, Rz indicating the degree of smoothness (unevenness) of the surface of the inner bottom portion 19a of the recess 19 is about 0.
It became 2 μm or less. In the case of performing normal anisotropic etching in which a voltage is not applied to the etching surface, the degree of smoothness of the inner bottom surface 19a of the concave portion 19, that is, Rz indicating the surface roughness.
Is about 1.0 μm, and it can be seen that the smoothness is considerably improved in this example.

Furthermore, in the above embodiment, the anisotropic etching liquid 14 was KOH, and the temperature of the anisotropic etching liquid 14 was set high, for example, 110 ° C. in the second step. Positive voltage V for anodic oxidation
When 2 is applied and the Si wafer 11 is anodically etched while being isotropically etched, the etching rate becomes high. As a result, it is possible to shorten the time required for rounding the end portion 19b of the inner bottom portion 19a of the recess 19.

Incidentally, in the above-mentioned embodiment, in the first step, the minute positive voltage V1 is applied to the Si wafer 11 such that anisotropic etching is possible. However, instead of this, a minute positive voltage V1 is applied. The anisotropic etching may be performed without applying the positive voltage V1, that is, without applying any voltage. In the case of this configuration, the smoothness of the inner bottom surface of the recess 19 is somewhat deteriorated, but the rounding process is sufficiently performed.

Further, in the case of the above embodiment, the liquid temperature of the anisotropic etching liquid 14 may be unstable at the initial stage of the first step. In such a case, the etching may not be controlled accurately. So the first
In the initial stage of the process of 1.
A positive voltage of 0 V or more is applied to anodize the etching surface to stop the etching. After that, when the liquid temperature of the anisotropic etching solution 14 becomes stable, the application of the positive voltage is stopped and It is preferable to apply a minute positive voltage that allows anisotropic etching.

FIG. 12 shows a second embodiment of the present invention. The same parts as those in the first embodiment are designated by the same reference numerals. In the second embodiment, when etching the Si wafer 11, the etching device 21 shown in FIG. 12 is used. The etching device 2
1 includes a base 22, a cylindrical frame 23, and a lid 24, and these members are made of a material having a high insulating property, such as tetrafluoroethylene resin, and having excellent heat insulation and corrosion resistance. ing. The space between the base 22 and the frame body 23 and the space between the frame body 23 and the lid body 24 are liquid-tightly sealed by O-rings 25 and 26. Therefore, the base body 22, the frame body 23 and the lid body are sealed. An airtight container is composed of 24. The anisotropic etching liquid 14 can be stored in this closed container.

The Si wafer 11 is arranged on the upper surface 22a of the base 22.
The upper surface (etching surface) of 1 is the anisotropic etching liquid 1
4 is configured to contact. Upper surface 2 of base 22
An annular negative pressure chamber forming recess 27 is provided on the outer peripheral portion of 2a. The recess 27 for forming the negative pressure chamber is closed by a ring-shaped packing 28. This packing 28
Are fixed by sandwiching the outer peripheral edge of the Si wafer 11.
The inside of the negative pressure chamber forming recess 27 is evacuated by a vacuum pump to suck the packing 28 and fix the Si wafer 11.

In the negative pressure chamber forming recess 27, for example, two anode electrodes 29 and 30 are provided. The tip portions of these anode electrodes 29, 30 are in contact with and connected to the Si wafer 11. The base ends of the anode electrodes 29 and 30 are
It is connected to the positive terminal 15a of the variable power supply circuit 15.

A supply passage 31 is formed in the lid 24, and the anisotropic etching liquid 14 is supplied into the frame 23 (closed container) through the valve 32 and the supply passage 31. Has been done. Furthermore, pure water is used for valve 3
3 and the supply passage 31 into the frame 23, and the nitrogen gas is supplied into the frame 23 through the valve 34 and the supply passage 31. still,
The etching liquid 14 and the like in the frame 23 (closed container) is configured to be discharged to the outside through a discharge passage 36 formed in the pipe 35 and the lid 24 by a pump or the like.

On the other hand, the rod-shaped cathode electrode 37 is arranged so as to penetrate the lid body 24 and extend to the vicinity of the bottom in the closed container. The base end of the cathode electrode 37 is connected to the negative terminal 15b of the variable power supply circuit 15 via the current detector 16. Further, a heater 38 for heating the etching liquid and the like and a temperature sensor 39 for detecting the temperature of the etching liquid and the like are arranged in the closed container. The heater 38 is configured to be energized by a temperature controller 40, and the temperature controller 40 is configured to receive a temperature detection signal output from the temperature sensor 39. This allows the temperature controller 4
0 has a configuration in which the temperature of the etching liquid or the like in the closed container can be set to a desired temperature (for example, 110 ° C.).

A stirring blade 41 for stirring the etching liquid and the like is arranged in the closed container, and the stirring blade 41 is driven to rotate by a motor 42 arranged above the lid 24. Is configured. Furthermore, the control device 1
8 is configured to drive and control the variable power supply circuit 15, the valves 32, 33, 34, the temperature controller 40, and the motor 42.

Then, when the Si wafer 11 is etched by using the etching apparatus 21 having such a structure, the first step and the second step described in the first embodiment are sequentially executed. ing. Therefore, the second
Also in this embodiment, it is possible to obtain the same effect as that of the first embodiment. In particular, according to the second embodiment, the temperature of the etching solution can be controlled with high accuracy, and the etching solution can be discharged and the Si wafer 11 can be washed with water quickly, so that the etching control can be made more stable and highly accurate. Can be run to.

Further, in the second embodiment, the Si wafer 11
Is mounted on the upper surface of the base 22 of the etching apparatus 21 and is fixed by sandwiching the outer peripheral edge portion of the Si wafer 11 by the ring member 28, unlike the first embodiment. It is possible to eliminate the work of attaching the to the ceramic substrate or the like.

13 to 28 are views showing a third embodiment of the present invention. The same parts as those in the first embodiment are designated by the same reference numerals. The third embodiment is an embodiment in which the Si wafer 43 having a PN junction is electrochemically etched as shown in FIG. This Si wafer 4
3 is a P-type silicon substrate (hereinafter,
N-type Si is formed on the lower surface of the P layer 44 by, for example, CVD.
A layer (hereinafter referred to as N layer) 45 is formed, and P is formed by thermal diffusion.
^{The +} layer 65 is doped and separated into a plurality of N layers 45. A P layer electrode 46 communicating with the P layer 44 is formed on the lower surface of the Si wafer 43, and an N layer 45 is formed.
An N-layer electrode 47 that communicates with is formed. An insulating layer 66 made of, for example, an oxide film is formed between the N layer electrode 47 and the P ⁺ layer 65. Further, a gauge 62 having a predetermined shape is formed on the lower surface of (the N layer 45 of) the Si wafer 43.

Then, the Si wafer 43 having such a configuration is used.
An etching mask 12 made of, for example, a SiN film is formed on the upper surface of the. Further, the lower surface of the Si wafer 43 is attached to, for example, a ceramic substrate via a protective material such as wax to protect the right side surface of the Si wafer 43.

Further, as shown in FIG. 13, the anisotropic etching solution 1 made of, for example, KOH stored in the container 13 is used for the Si wafer 43 (and the ceramic substrate).
Etching is carried out by immersing in 4. in this case,
The P layer 44 (of the P layer electrode 46) of the Si wafer 43 is connected to the positive terminal 15a of the variable power supply circuit 15 via the relay 48, and the N layer 45 (of the N layer electrode 47) of the Si wafer 43 is connected. Is connected to the positive terminal 15a of the variable power supply circuit 15 via the relay 49. In addition, the variable power supply circuit 1
5 is connected to the negative terminal 15b of the Pt electrode 17 in the container 13
It is immersed in the anisotropic etching liquid 14 therein. The two relays 48 and 49 are configured to be on / off controlled by the control device 18.

Further, the control device 18 is constructed so as to control the temperature of the anisotropic etching liquid 14 in the container 13 as in the first embodiment. That is, the container 13 is stored in the oil bath, and the control device 18
Controls the energization of the heater of the oil bath and detects the temperature of silicon oil in the oil bath (and thus the temperature of the anisotropic etching liquid 14 in the container 13).

Next, FIGS. 14, 15, and 17 to 2
8, an etching method for etching the Si wafer 43 having the PN junction will be specifically described. First, as shown in FIG. 13, the Si wafer 43 is immersed in the anisotropic etching liquid 14 composed of a 32 wt% KOH aqueous solution having a liquid temperature of 110 ° C. in the container 13, and the etching control operation of the control device 13 is performed. Let it start.
Then, the control device 13 causes the relay 48 on the P layer electrode 46 side.
Is turned on, the relay 49 on the N-layer electrode 47 side is turned off, and a command signal is given to the variable power supply circuit 15 so that the variable power supply circuit 15 outputs a small DC voltage V1 (for example, 0.15).
V) is output.

As a result, the minute DC voltage V1 is
The voltage is applied to the P layer 44 of the wafer 43, and in this applied state, the process of anisotropically etching the left surface (etching surface) of the P layer 44 of the Si wafer 43 in FIG. 13 proceeds. In this case, the etching surface of the P layer 44 of the Si wafer 43 corresponding to the opening 12 a of the etching mask 12 is dissolved by the anisotropic etching liquid 14 to form the recess 50.

Here, the minute DC voltage V1 applied to the P layer 44 of the Si wafer 43 is a positive voltage that allows anisotropic etching. Then, as described above, the Si wafer 4
The step of anisotropically etching 3 (hereinafter referred to as the first step) is configured to be executed by the control device 18 for a predetermined time, for example, about 30 minutes. The length of time for performing the first step may be appropriately set based on the depth dimension of the recess 50 to be formed and the etch rate of the anisotropic etching liquid 14.

By the execution of the first step, as shown in FIG.
3 and FIG. 18, the P layer 44 of the Si wafer 43
A recess 50 is formed in the. In this case, since the recess 50 is formed by anisotropic etching, the inner bottom portion 5 of the recess 50 is
The shape of the end portion 50b of 0a is a corner portion. The inner bottom portion 50a of the recess 50 serves as the diaphragm 20. The application state of the minute positive voltage V1 in the first step is shown in the graph from time T0 to time T1 in FIG.
Current flowing in the P layer 44 of the Si wafer 43 (current detector 1
(Current detection value by 6) from time T0 to time T1 in FIG.
Shown in the graph up to.

After this, at the time T1 when the first step is completed,
That is, when the etching progresses to the vicinity of the PN junction layer of the Si wafer 43, the control device 18 turns off the relay 48 on the P layer electrode 46 side and turns on the relay 49 on the N layer electrode 47 side. A command signal is given to the variable power supply circuit 15 so that the variable power supply circuit 15 outputs a DC voltage V2 (for example, 3.0 V) as a positive voltage for anodic oxidation. As a result, the DC voltage V2 is applied to the N layer 45 of the Si wafer 43. By this voltage application, the etching progresses to the vicinity of the PN junction layer of the Si wafer 43, and the etching surface is anodized in the same manner as in the normal (well-known) electrochemical etching, and the etching is stopped there.

In this case, the etching surface (diaphragm surface) of the Si wafer 43 is applied by applying the DC voltage V2.
Is anodized, the etching is almost stopped, but in reality, the etching rate is very small. However, in the case of the present embodiment, the time of the step of applying the DC voltage V2 is about 5 minutes (time t2 from time T1 to time T2 in FIGS. 14 and 15), so etching is almost stopped. There is. At this time, since a voltage is applied to the N layer 45, the etching surface (diaphragm surface) in the vicinity of the PN junction between the N layer 45 and the P layer 44 is anodized, but the side surface of the etching surface is the anode. Not oxidized. Therefore, the corners of the recess formed by etching are not sufficiently anodized. Therefore, this process alone cannot sufficiently round the entire end of the recess (end of the diaphragm). The process of anodizing the etched surface of the Si wafer 43 is hereinafter referred to as an anodizing process.

Next, at the time point T when the anodizing step is completed,
At 2, the control device 18 turns on the relay 48 on the side of the P layer electrode 46, turns off the relay 49 on the side of the N layer electrode 47, and further gives a command signal to the variable power supply circuit 15 so that the variable power supply circuit 15 DC voltage V as a positive voltage for anodic oxidation
3 (for example, 3.5V) is output. As a result, the DC voltage V3 is applied to the P layer 44 of the Si wafer 43. By this voltage application, similarly to the second step of the first embodiment, the etching surface (diaphragm surface and side wall portion) of the Si wafer 43 is anodized, and the isotropic etching is very slow (first step).
Although it is about 1/50 of the etch rate at the time of the process), it progresses.

In this embodiment, as described above, S
The step of performing isotropic etching while the anodized surface of the i-wafer 43 is anodized (hereinafter referred to as the second step) is performed for about 5 minutes, for example. As a result, the process of isotropically etching the inner surface of the recess 50 of the Si wafer 43 progresses, and the shape of the end 50b of the inner bottom 50a of the recess 50 is rounded. In this case, even if the etching rate of the isotropic etching is a considerably small value, it is sufficient to round the end 50b of the inner bottom 50a of the recess 50 for about 5 minutes. Where the second
The time for executing the step is not limited to the above 5 minutes, and is set appropriately according to the type of the anisotropic etching solution 14, the temperature of the solution, the value of the positive voltage V3 applied to the Si wafer 43, and the like. Just do it.

After that, when the execution of the second step is completed (at time T3), the Si wafer 43 is subjected to the anisotropic etching liquid 14 with the positive voltage V3 being applied.
The Si wafer 43 is pulled up from the inside and washed with water. This completes the process of forming the recess 50, that is, the diaphragm 20, on the Si wafer 43.

According to the third embodiment having such a configuration,
In the first step of anisotropically etching the Si wafer 43 having a PN junction to a predetermined depth, the Si wafer 43
The Si wafer 43 is configured to be anisotropically etched while applying a small positive voltage V1 to the extent that anisotropic etching is possible. In this structure, the potential of the etching surface of the Si wafer 43 shifts in the noble direction, and the potential difference with the metal ions more noble than Si becomes smaller, so that impurities such as metal (for example, Pb) are less likely to be adsorbed to the etching surface. Become. Therefore, even if the etching surface of the Si wafer 43 is the (110) surface, the etching surface becomes smooth, and the smoothness of the inner bottom surface 19a of the recess 19 can be further improved.

FIG. 24 shows a graph obtained by measuring the relationship between the initial current density flowing through the Si wafer 43 and Rz representing the smoothness of the etched surface (surface roughness). In FIG. 24, black dots represent measured points of the surface roughness Rz, and a curve connecting the black dots represents a relationship between the initial current density and the surface roughness Rz. In addition, in FIG. 24, the white circles indicate the actual measurement points of the occurrence frequency of the micropyramid,
A curve connecting these white circles is a graph showing the relationship between the initial current density and the occurrence frequency of micropyramids.

In the third embodiment, the initial current density was 0.13 mA / mm ² , and the surface roughness Rz of the etched surface was about 0.1 μm. Here, in the case of performing the conventional electrochemical etching in which the voltage is not applied to the etching surface (P layer 44), the surface roughness Rz of the etching surface is about 1.0 μm, and the third embodiment is smoother. The sex has improved considerably. Note that the graph of FIG. 24 is an experimental example when a 32 wt% KOH aqueous solution at 110 ° C. is used as the anisotropic etching liquid 14.

FIG. 25 shows the state of point A in FIG. 24, that is, the etching surface when the initial current density is 0 (when no voltage is applied). Further, B in FIG.
FIG. 26 shows the points, that is, the state of the etched surface when the initial current density is 0.10 mA / mm ² . Furthermore, FIG.
Point C in 4, that is, the initial current density is approximately 0.15 m
The state of the etched surface in the case of A / mm ² is shown in FIG. FIG. 28 shows the state of the etched surface at point D in FIG. 24, that is, when the initial current density is approximately 0.24 mA / mm ² . Incidentally, these FIG. 25, FIG. 26 and FIG.
FIG. 7 and FIG. 28 are diagrams showing a photograph of the etched surface.

The graph of FIG. 24 and the graphs of FIGS.
From FIG. 27, it is clearly seen that when the initial current density is higher than 0.10 mA / mm ² , the smoothness of the etching surface is improved. On the other hand, the initial current density is 0.18 mA /
When it is larger than about mm ² , as shown in FIG. 28, a micropyramid 67 having a rhombus cross-sectional shape starts to be generated on the etching surface, and the initial current density is 0.20 m.
From A / mm ² or more, micropyramids 67 are frequently generated. The number of micropyramids 67 having a size (for example, the length of the longer diagonal of the rhombus) of 20 μm or more per 1 mm ² is defined as the occurrence frequency of the micropyramids 67, and the occurrence frequency is measured. The graph of FIG. 24 was obtained. From the graph of FIG. 24, it is well understood that when the initial current density is increased, the micropyramids 67 are generated and the quality is deteriorated. Therefore, the initial current density is 0.10 mA / mm ² ~
About 0.20 mA / mm ² , preferably 0.12 mA
/ ^Mm When 2 is set to ～0.18MA / mm ^2, it is found that the most quality is improved. Micro Pyramid 6
The surface roughness Rz of the etching surface when 7 occurs indicates the surface roughness of the portion of the etching surface where the micro pyramid 67 is not present. When etching is performed so that micropyramids are generated, the micropyramids can be eliminated by performing etching thereafter under the condition that micropyramids are not generated.

On the other hand, in the third embodiment, the Si wafer 43 has a small positive voltage V1 that is anisotropically etched.
As a result, the variation in the dimensions of the manufactured diaphragm 20 (dimensions indicated by D1 in FIG. 17) could be significantly reduced. Specifically, the dimensional variation of the diaphragm manufactured by the electrochemical etching of the conventional configuration is about ± 30 μm, while the dimensional variation of the diaphragm 20 manufactured by the third embodiment is ± 10 μm. It became a degree. Here, the reason why the variation in the dimension D1 of the diaphragm is reduced will be briefly described.

First, the recess 5 formed in the Si wafer 43.
17 is a front view of the concave portion 50, and FIG.
A sectional view taken along the line is shown in FIG. 17 and 18 above
In, the bottom surface portion 50a of the recess 50 is the (110) surface, the upper and lower end side slopes 50c, 50c are the (100) surfaces, and the left and right end side slopes 50d, 50d are the (111) surfaces.

In the case of the conventional electrochemical etching, only a positive voltage of, for example, 1.0 V or more is applied to the N layer 45 of the Si wafer 43, so that the PN junction is reverse biased and the P layer 44 is formed. Anisotropy etching proceeds with no voltage applied to the substrate. In this case, since the potential of the etching surface of the Si wafer 43 does not shift, impurities such as metal (for example, Pb) are likely to be adsorbed on the etching surface, and the etching rate may change.
This change in the etching rate changes depending on the concentration of Pb in the anisotropic etching liquid 14, the plane orientation of the etching surface, the liquid temperature in the anisotropic etching liquid 14, and the like.

Specifically, the etching rate changes as shown in FIG. 19 depending on the concentration of Pb in the anisotropic etching liquid 14. In FIG. 19, a curve P1 shows the case where the plane orientation is the (110) plane, and a curve P2 has the plane orientation (10).
The case of the (0) plane is shown. In this case, the anisotropic etching solution 14 is a 32 wt% KOH aqueous solution at 110 ° C., for example.

Then, when the ratio of the etch rate of the (100) plane to the etch rate of the (110) plane is calculated,
It becomes like the graph of FIG. That is, it can be seen that the ratio of the etching rates of the above two surfaces varies considerably depending on the concentration of Pb in the anisotropic etching liquid 14. Then, when the ratio of the etch rates of the two surfaces changes, as shown in FIG. 18, the amount of progress of etching of the (100) surface and the (110) surface changes considerably. Etching of the (110) plane is performed near the PN junction interface (actually, 2 to 5
The etching depth is almost constant, and the etching depth is almost constant. Therefore, the formed diaphragm 2
There is a drawback that the dimension D1 of 0 varies about ± 30 μm.

In particular, it was found that the ratio of the etch rates of the above two surfaces, which varies depending on the concentration of Pb in the anisotropic etching solution 14, is strongly influenced by the temperature of the anisotropic etching solution 14. FIG. 21 shows an example of the fluctuation due to the liquid temperature. In FIG. 21, the curve Q1 has a Pb concentration of 1
The curve Q2 shows the case of 5 ppb and the concentration of Pb is 130.
The case of ppb is shown. It can be seen from FIG. 21 that the higher the liquid temperature of the anisotropic etching liquid 14, the greater the variation in the ratio of the etch rates of the two surfaces due to the Pb concentration in the anisotropic etching liquid 14. Therefore, in the case of the conventional configuration, when the temperature of the anisotropic etching liquid 14 is increased, there is a drawback that the variation of the dimension D1 of the diaphragm is further increased.

According to the above-described conventional electrochemical etching, when the etching reaches the vicinity of the PN junction layer, the etching surface is anodized and the etching is automatically stopped. Therefore, the depth of the concave portion, that is, the diaphragm. The thickness dimension can be formed with high precision.

In contrast to the above-described conventional electrochemical etching, the Si wafer 4 is used in the third embodiment.
The P layer of 3 has a predetermined depth (10 to 20 μ from the PN junction interface).
Anisotropic etching is performed up to a region near the P layer by about m.
In the process of S, while applying a minute positive voltage V1 to the P layer to the extent that anisotropic etching can be performed on the Si wafer 43, S
The i-wafer 43 was configured to be anisotropically etched.
In this case, the potential of the etching surface of the Si wafer 43 shifts in the positive direction, so that impurities such as metal (for example, Pb) are less likely to be adsorbed on the etching surface. For this reason,
The etch rate of the (100) surface of the Si wafer 43 and (11
As shown in the graph of FIG. 22, the ratio of the (0) plane to the etch rate is almost constant regardless of the concentration of Pb in the anisotropic etching liquid 14. As a result, the variation in the dimension D1 of the diaphragm 20 manufactured according to the third embodiment is reduced to about ± 10 μm. Also, the surface accuracy is improved. The graph of FIG. 22 shows that the anisotropic etching liquid 14 is, for example, 32 wt% KOH at 110 ° C.
The voltage applied to the P layer 44 is set to, for example, 0.1 by using an aqueous solution.
V, and the current density of the current flowing through the Si wafer 43 is 0.
It was set to 13 mA / mm ² .

Here, the above 32 wt% KOH at 110 ° C.
The relationship between the ratio of the etch rate of the (100) plane to the etch rate of the (110) plane and the current density of the current flowing through the Si wafer 43 was measured in the case where the anisotropic etching solution 14 made of an aqueous solution was used. The graph is shown in FIG.
In FIG. 23, the curve R1 has a Pb concentration of 130 pp.
b, and R2 shows the case where the Pb concentration is 15 ppb. From FIG. 23, when the initial current density is 0 mA / mm ² (when no voltage is applied),
It can be seen that the ratio of the above etching rates becomes large. Further, when the initial current density is higher than 0.18 mA / mm ² , there is a problem that micropyramids are generated on the etching surface. Therefore, in the third embodiment, the initial current density is 0.10 mA / mm ² or more and 0.1 or more.
The magnitude of the voltage V1 applied to the P layer 44 of the Si wafer 43 is adjusted by the controller 18 and the variable power supply circuit 15 so as to be 8 mA / mm ² or less.

In the third embodiment, the time T1 at which the first process is completed, that is, near the PN junction layer of the Si wafer 43 (a region near the P layer from the PN junction interface by about 10 to 20 μm). When the etching progressed, the voltage application to the P layer 44 was stopped and the DC voltage V2 was applied to the N layer 45 as a positive voltage for anodic oxidation. This voltage V
By applying 2, the etching proceeds to the vicinity of the etching PN junction layer of the Si wafer 43, and the etching surface (diaphragm surface) is anodized in the same manner as normal electrochemical etching, and the etching stops automatically. To do. Therefore, the depth dimension of the recess 50, that is, the thickness dimension of the diaphragm 20 can be formed with high accuracy.

Further, in the third embodiment, at the time T2 when the anodizing process is completed, the voltage application to the N layer 45 is stopped and the DC voltage V3 is applied to the P layer 44 as a positive voltage for anodizing.
(For example, 3.5 V) is applied. By applying this voltage V3, the etching surface (diaphragm surface and side wall portion) of the Si wafer 43 is anodized in the same manner as in the second step of the first embodiment, and isotropic etching is slow. It will progress. As a result, the process of isotropically etching the inner bottom portion 50a of the recess 50 of the Si wafer 43 progresses, and the shape of the end 50b of the inner bottom portion 50a of the recess 50 is rounded. As a result, the pressure resistance of the diaphragm 20 increases.

FIG. 29 shows a fourth embodiment of the present invention. The same parts as those in the second and third embodiments are designated by the same reference numerals. In the fourth embodiment, when etching the Si wafer 43 having the PN junction, the process shown in FIG.
The etching device 21 shown in FIG.
The etching apparatus 21 is substantially the same as the etching apparatus shown in FIG. 12, except for the following points.

That is, the tip portion of one of the two anode electrodes 29, 30 is connected to the P layer 4 of the Si wafer 43.
4 and the tip of the other anode electrode 30 is connected to the N layer 45 of the Si wafer 43. The base end of the one anode electrode 29 is connected to the positive terminal 15a of the variable power supply circuit 15 via the relay 48, and the other anode electrode 3 is connected.
The base end of 0 is connected to the positive terminal 15a of the variable power supply circuit 15 via the relay 49.

The structure of the fourth embodiment other than the above is the same as that of the second or third embodiment.
Therefore, also in the above-mentioned fourth embodiment, the second or third
It is possible to obtain substantially the same effect as that of the embodiment.

30 to 41 show a fifth embodiment of the present invention. The same parts as those in the first to fourth embodiments are designated by the same reference numerals. First, the problem solved by the fifth embodiment will be described. First mentioned above
In the first embodiment, in the first step of anisotropically etching the Si wafer 11 to a predetermined depth, a small positive voltage V1 that is anisotropically etchable to the Si wafer 11 is used.
Is applied, the Si wafer 11 is anisotropically etched. As a result, impurities such as a metal (for example, Pb) contained in the etching liquid are less likely to be adsorbed on the etching surface, so that the etching surface of the Si wafer 11 becomes (1
Even with the 10) surface, the etched surface becomes smooth, the inner bottom surface 19a of the recess 19 is improved in smoothness, and the dimensional variation is reduced.

Here, the voltage V applied to the Si wafer 11 is
If the Si wafer 11 is P-type Si, the size of 1 is
The voltage was as small as 0 to 0.2 V, and the applied voltage had to be controlled within this small voltage range. For this reason, in the case of the first embodiment, a system for precisely controlling the voltage for applying the minute positive voltage V1 to the extent that anisotropic etching is possible is required.

When the Si wafer 11 is N-type Si, the voltage V1 applied to the Si wafer 11 is a negative voltage and the voltage range is about -0.2 to -0.05V. I understood. Here, the experimental results of the etching characteristics of the N-type Si wafer with respect to the applied voltage are shown in FIGS. 31 (a) and 31 (b). 31A is a characteristic diagram showing the relationship between the applied voltage and the current density, and FIG. 31B is a characteristic diagram showing the relationship between the applied voltage and the etch rate. Therefore, when the Si wafer 11 is N-type Si, there is a problem that the accuracy of voltage control must be further improved.

In order to solve such a problem, the inventor of the present invention invented an etching method constituted as in the fifth embodiment. In the fifth embodiment, a resistor is connected in series to the Si wafer to apply a voltage. Specifically, the etching device 21 as shown in FIG. 33 was used. This etching device 21 has substantially the same basic configuration as the etching device 21 of the second embodiment shown in FIG. 12, except for the following points.

That is, a resistance connection switching circuit 71 is provided between the base ends of the anode electrodes 29 and 30 and the positive terminal 15a of the variable power supply circuit 15, and both terminals 15 of the variable power supply circuit 15 are provided.
a and 15b, resistance connection switching circuit 71, and cathode electrode 37
And a voltage polarity switching circuit 72 is provided between and. First, the resistance connection switching circuit 71 is configured by connecting in parallel a series circuit in which a switching element 73 including a transistor and a relay and a resistor 74 are connected in series, and a switching element 75 including a transistor and a relay. The two switching elements 73 and 75 are configured to be on / off controlled by the control device 18.
The resistor 74 has a resistance of 20Ω, for example.

In the case of this structure, when the switching element 73 is turned on and the switching element 75 is turned off,
The resistor 74 is configured to be connected in series to the Si wafer 11. Further, when the switching element 73 is turned off and the switching element 75 is turned on, the resistor 74 is not connected to the Si wafer 11.

On the other hand, the voltage polarity switching circuit 72 is composed of four switching elements 76 including transistors and relays,
77, 78, 79 are connected as shown in FIG. In the case of this configuration, the switching elements 76 and 79 are turned on and the switching elements 77 and 7 are turned on.
When 8 is turned off, a positive voltage is applied to the Si wafer 11. When the switching elements 76 and 79 are turned off and the switching elements 77 and 78 are turned on, S
A negative voltage is applied to the i-wafer 11.

The N-type Si wafer 11 is etched by using the etching apparatus 21 having the above-described structure. Here, the N-type Si wafer 11 will be briefly described with reference to FIG. As shown in FIG. 30, N-type S
On the lower surface of the i-wafer 11, a gauge 62 having a predetermined shape is formed, and for example, an Al-made power supply electrode 64 which is substantially in a lattice shape as a whole is formed. And N
An etching mask 12 made of, for example, SiO ₂ or SiN film is formed on the other surface of the mold Si wafer 11.

Now, the N-type Si wafer 11 is shown in FIG.
The etching operation when etching is performed using the etching apparatus 21 shown in FIG. Si wafer 11
Is immersed in an alkaline etching solution facing the Pt electrode, and when a voltage is applied, anisotropic etching proceeds when the voltage is a predetermined value or less, and when the voltage is a predetermined value or more, Si is anodized. Here, when Si is anodized, an oxide film is formed on Si and the oxide film is slightly etched by alkali, so that a very gentle isotropic etching proceeds.

On the other hand, when a very small voltage is applied,
Although anisotropic etching basically progresses, the etching surface is smoothed and the etching rate ratio of each surface changes as compared with the case where no voltage is applied. Further, when a predetermined voltage is applied, a trace amount of metal impurities (P
It is possible to eliminate the variation in the etch rate of the (100) plane and the (110) plane due to (b) or the like. However, when the applied voltage increases, micropyramids are likely to occur on the etched surface, and finally the anisotropy disappears and Si is anodized.

Here, the liquid temperature is 110 ° C. and the concentration is 3
Anisotropic etching solution 1 consisting of 2 wt% KOH aqueous solution
4 is an etching surface when a voltage is applied to the N-type Si wafer 11 without using the resistor 74, that is, with the switching element 73 turned off and the switching element 75 turned on. When the initial current density and the etch rate of the (110) plane were measured, the etching characteristic diagram as shown in FIG. 31 was obtained. The N-type Si wafer 11
The specific resistance was 0.6 to 1.2 Ω · cm.

The etching characteristics vary depending on the etching conditions, the type of the wafer (impurity species and concentration), and the resistance in the power supply circuit system including various contact resistances.
In this case, for example, when the same type of wafer is used and the same etching mask pattern is used, the variation factor of the etching characteristics depends on the resistance in the power feeding circuit. However, under the same initial current density when there is no resistance and when the resistance is 20Ω, the etching characteristics such as the etching rate become constant.

Therefore, it can be said that the etching characteristics in the voltage region where the voltage and the current change substantially linearly depend on the initial current (density) of the etching surface, but if the current at the initial etching is controlled, the repeatability of etching is secured. be able to. Therefore, it is necessary to control the initial etching current density, that is, a value obtained by dividing the current value by the area to be etched.

Here, the roughness of the etched surface with respect to the initial current density, that is, the roughness of the (110) surface is as shown in the graph of FIG. Incidentally, point A in FIG. 34, that is,
FIG. 35 shows the state of the etched surface when the initial current density is 0 (when no voltage is applied). Then, at point B in FIG. 34, that is, the initial current density is approximately 0.07 mA / m.
The state of the etched surface in the case of m ² is shown in FIG. Further, FIG. 37 shows the state of the etching surface at point C in FIG. 34, that is, when the initial current density is approximately 0.14 mA / mm ² . Further, FIG. 38 shows the state of the etched surface at point D in FIG. 34, that is, when the initial current density is approximately 0.24 mA / mm ² . These FIG. 35, FIG. 36, and FIG.
FIG. 7 and FIG. 38 are diagrams showing a photograph of the etched surface.

The frequency of occurrence of micropyramids on the etched surface with respect to the initial current density is as shown in the graph of FIG. Furthermore, for the initial current density (10
The etch rate ratio between the (0) plane and the (110) plane is as shown in the graph of FIG.

From FIG. 34, FIG. 39 and FIG. 40 described above, in order to form a smooth diaphragm in which dimensional variation due to the influence of trace metal impurities such as Pb contained in the etching solution is reduced, It can be seen that the initial current density of 1 may be controlled so as to be set within the range of 0.07 to 0.17 mA / mm ² . Then, in the case where etching is performed in a state where the resistance of the power feeding circuit is small, that is, in a state where the resistor 74 is not connected, in order to obtain the current density in the above range, as shown in FIG.
It is necessary to apply a negative voltage of 2) to (-0.05) V.

However, in other etching steps,
In some cases, it is necessary to apply a large positive voltage as compared with the above-mentioned considerably small negative voltage. For example, when the silicon is anodized to stop the etching until the temperature of the etching solution stabilizes at the initial stage of etching or to round the diaphragm end after etching, a positive voltage of, for example, about 1 to 3 V is applied. Need to let. In such a case, it is necessary to switch the polarity of the voltage and to apply a negative voltage of a considerably small value within the above range when applying a negative voltage. Therefore, control the current density to be constant in each case. Causes a fairly difficult voltage control.

Therefore, a resistor 74 of 20Ω is provided in the feeding circuit.
By providing the above, the voltage can be controlled only by the positive voltage. Here, the anisotropic etching solution 14 composed of a KOH aqueous solution having a liquid temperature of, for example, 110 ° C. and a concentration of 32 wt% is used to connect the resistor 74, that is, the switching element 73 is turned on and the switching element 75 is turned off. In this state, when a voltage is applied to the N-type Si wafer 11, the initial current density and the etch rate of the (110) plane, which is the etching plane, are measured. As shown in FIG. An etching characteristic diagram was obtained. As the N-type Si wafer 11, one having a specific resistance of 0.6 to 1.2 Ω · cm was used. Also, FIG.
In FIG. 2, the etching characteristic indicated by the white circles and the curve connecting the white circles is the case where the resistor 74 is not connected.

From FIG. 32 (a), when the resistor 74 is connected, the initial current density of the etching surface is 0.07.
The applied voltage range for setting within an appropriate range of 0.17 mA / mm ² is 0.2 to 1.0 V as it shifts to the positive potential side and widens. Therefore, this applied voltage range is the same positive voltage as the applied voltage in the case of anodic oxidation, and is a wide voltage range in which voltage control is relatively easy.

On the other hand, when silicon is anodized in order to stop the etching until the temperature of the etching solution is stabilized at the initial stage of etching or to round the end of the diaphragm after etching, the resistor 7 is used.
The smaller the resistance value of 4 is, the smaller the applied voltage can be. Therefore, in such a case, the total applied voltage range can be reduced by switching the circuit so that the resistance value of the resistor 74 to be connected is reduced or the resistor 74 is not connected. Therefore, the voltage controllability is improved accordingly.

Next, a method of controlling the initial current density will be described. When etching is performed by applying a minute voltage, the current (density) at the time of etching gradually changes as the shape of the diaphragm changes as the etching progresses. At the initial stage of etching, only the (110) plane is of interest, so the current becomes almost constant depending on the applied voltage.
However, since the current also varies depending on the contact resistance and the impurity concentration of the silicon substrate, the applied voltage may be adjusted so that the initial current density (actually, the current value) becomes a predetermined value.

For example, the etching apparatus 21 shown in FIG.
When using, the heated etching solution is put in the frame body 23 which is a processing tank, and it takes several minutes after the etching is started until the solution temperature reaches a target value (for example, 110 ° C.).
During this period, for example, when a resistor is not connected (without a resistor), a voltage of about 1 V is applied so that the etching does not proceed. Then, when the liquid temperature reaches the target value and stabilizes, the resistor 74 of 20Ω is connected and the applied voltage is set to 0.
The current flowing in the power feeding circuit is monitored (detected) at 2 to 1 V, and the current density is within a suitable range (0.0).
The voltage is controlled so as to be 7 to 0.17 mA / mm ² ).

When the etching apparatus 21 is used, there are uncontrollable fluctuation factors such as the resistivity (specific resistance) of the Si wafer 11 itself and the contact resistance between the Si wafer 11 and the power supply electrodes 29 and 30. Therefore, as described above, when the voltage is applied at the initial stage of etching, the current is measured, and then the applied voltage is finely adjusted so that the current becomes a predetermined value (appropriate range), the controllability becomes high.

Next, etching conditions for forming a diaphragm having a thickness of 30 μm using an N-type Si wafer 11 having an original thickness of 300 μm will be described. First, without connecting the resistor 74, a first voltage of 1 V, for example, is applied for 10 minutes, and the Si wafer 11 is anodized until the temperature of the etching solution becomes stable. Thereafter, the resistance connection switching circuit 71 is switched to connect the resistor 74, and a voltage of, for example, 1 V is applied to monitor the value of the current flowing through the Si wafer 11, and the current density is, for example, 0.14 mA / mm. ^The applied voltage is finely adjusted to be ² . Then, etching is continued at this voltage for 29 minutes, for example.

After that, water is injected into the frame body 23 which is an etching tank to dilute and cool the etching solution to complete the etching. Here, in order to round the diaphragm end portion, the resistor 74 is not connected (without resistance) before water is injected, and the first voltage (for example, 1
V) may be applied. When etching is performed under such conditions, the etched surface is smooth (surface roughness Rz is 0.2 or less), and a diaphragm having a small dimensional variation (± 10 μm or less) can be stably formed (manufactured). it can.

On the other hand, when the P-type Si wafer 11 is etched, the resistor 74 need not be connected when anisotropically etching the Si wafer 11 in the first step. This is because the P-type S has a specific resistance of 10 to 20 Ω · cm.
In the case of the i-wafer 11, when the etching characteristic with respect to the applied voltage is experimentally obtained under the condition of no resistance, FIG.
The graphs are as shown in (a) and (b). Therefore, even if there is no resistance, a suitable applied voltage is -0.1 to 0.
Since it is 2V, the positive voltage region is sufficiently included in this voltage range. Therefore, it is not necessary to apply a negative voltage,
That is, since it is not necessary to switch the voltage polarity, the resistor 7
It is possible to control the voltage even if 4 is not connected.

Even in the case of the P-type Si wafer, as in the case of the N-type Si wafer, when the Si wafer 11 is anisotropically etched in the first step, etching is performed so as to connect the resistor 74. You may control. Also in this configuration, when the resistor 74 is connected, the appropriate voltage range is widened (shifts to the positive voltage side and widens), and thus the controllability is improved accordingly.

In the above embodiment, the resistance connection switching circuit 7
Although it is configured to switch whether or not the resistor 74 is connected in the first example, the present invention is not limited to this, and a plurality of resistors may be switchably connectable. And
It is also a preferable configuration to change the resistance value of the resistor connected in series to the Si wafer 11 to a desired value.

[Brief description of drawings]

FIG. 1 shows a first embodiment of the present invention, in which Si
Time chart of voltage applied to wafer

FIG. 2 is a vertical sectional side view of the etching apparatus.

FIG. 3 is a partial vertical sectional side view of a Si wafer.

FIG. 4 is a partial vertical sectional side view of a Si wafer.

FIG. 5 is a partial vertical sectional side view of a Si wafer.

FIG. 6 illustrates S for explaining isotropic etching by anodic oxidation.
Side view of a partial vertical section of an i-wafer

FIG. 7 is a diagram showing a relationship between an etch rate and an applied voltage.

FIG. 8 is a diagram showing the relationship between the rounding amount of the end of the diaphragm, the anodic oxidation time, and the applied voltage.

FIG. 9 is a diagram showing the relationship between the rounding amount of the end of the diaphragm, the anodizing time, and the liquid temperature.

FIG. 10 is a vertical sectional side view of a Si wafer.

FIG. 11 is a characteristic diagram showing the relationship between the voltage when a positive voltage is applied to a P-type Si wafer and the initial current density of the etched surface.

FIG. 12 is a vertical sectional side view of an etching apparatus showing a second embodiment of the present invention.

FIG. 13 is a view corresponding to FIG. 2 showing a third embodiment of the present invention.

FIG. 14 is a view equivalent to FIG.

FIG. 15 is a time chart showing changes in detected current.

FIG. 16 is a vertical sectional side view of a Si wafer.

FIG. 17 is a front view of a recess (diaphragm).

FIG. 18 is a vertical sectional side view of a recess (diaphragm).

FIG. 19 is a graph showing the relationship between the etch rate, the Pb concentration, and the surface orientation of the Si wafer.

FIG. 20 is a graph showing the relationship between the etch rate ratio and the Pb concentration.

FIG. 21 is a graph showing the relationship between the etch rate ratio, the liquid temperature, and the Pb concentration.

FIG. 22 is a graph showing the relationship between the etch rate ratio and the Pb concentration.

FIG. 23 is a graph showing the relationship between the etch rate ratio and the current density.

FIG. 24 is a graph showing the relationship between the roughness of the etched surface and the initial current density, and the relationship between the micropyramid generation frequency and the initial current density.

FIG. 25 is a diagram showing a state of an etched surface.

FIG. 26 is a diagram showing a state of an etching surface.

FIG. 27 is a diagram showing a state of an etched surface.

FIG. 28 is a diagram showing a state of an etched surface.

FIG. 29 is a view corresponding to FIG. 12, showing a fourth embodiment of the present invention.

FIG. 30 is a vertical sectional side view of a Si wafer showing a fifth embodiment of the present invention.

FIG. 31 is a characteristic diagram showing an etching characteristic of an N-type Si wafer, (a) is a characteristic diagram showing a relationship between an applied voltage and a current density, and (b) is a characteristic showing a relationship between an applied voltage and an etch rate. Figure

FIG. 32 is a characteristic diagram showing etching characteristics of an N-type Si wafer depending on the presence or absence of resistance.

FIG. 33 is a view corresponding to FIG. 12.

FIG. 34 is a graph showing the relationship between the roughness of the etched surface of an N-type Si wafer and the initial current density.

FIG. 35 is a diagram showing a state of an etching surface.

FIG. 36 is a diagram showing a state of an etching surface.

FIG. 37 is a diagram showing a state of an etched surface.

FIG. 38 is a diagram showing a state of an etched surface.

FIG. 39 is a graph showing the relationship between the occurrence frequency of micropyramids of an N-type Si wafer and the initial current density.

FIG. 40 is a graph showing the relationship between the initial current density of an N-type Si wafer and the etch rate ratio.

FIG. 41 is a characteristic diagram showing etching characteristics of a P-type Si wafer.

42 is a view corresponding to FIG. 16 showing the conventional configuration.

FIG. 43 is a vertical sectional side view of the etching apparatus.

[Explanation of reference numerals] 11 is a Si wafer, 12 is an etching mask, 14 is an anisotropic etching solution, 15 is a variable power supply circuit, 16 is a Pt electrode, 17 is a current detector, 18 is a controller, 19 is a recess,
20 is a diaphragm, 21 is an etching device, 22 is a base, 23 is a frame, 24 is a lid, 29 and 30 are anode electrodes,
37 is a cathode electrode, 42 is a motor, 43 is a Si wafer, 4
Reference numeral 4 is a P layer, 45 N layer, 46 is a P layer electrode, 47 is an N layer electrode, 48 and 49 are relays, 50 is a recess, and 74 is a resistor.

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Toshinao Taniguchi, 1-1, Showamachi, Kariya city, Aichi Prefecture, Denso Co., Ltd. (72) Inventor, Takeshi Fukada, 1-1, Showamachi, Kariya city, Aichi prefecture, Denso company ( 72) Inventor Motoki Ito 1-1, Showa-cho, Kariya City, Aichi Prefecture DENSO CORPORATION (56) References JP-A 1-291429 (JP, A) JP-A 61-30038 (JP, A) JP-A Sho 60-154575 (JP, A) JP 61-137330 (JP, A) JP 4-132224 (JP, A) JP 9-153479 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/306 H01L 21/3063 H01L 21/308

Claims (8)

(57) [Claims] 1. An etching method in which a Si wafer is immersed in an anisotropic etching solution to etch a desired portion of the Si wafer, the first step of anisotropically etching the Si wafer to a predetermined depth, After performing the first step, a voltage is applied to the Si wafer so that the voltage for anodic oxidation is applied to the entire etched surface appearing in the first step, and the etched surface is isotropically etched. And a second step of: 2. The Si wafer according to claim 1, wherein in the first step, the Si wafer is anisotropically etched while applying a voltage to the Si wafer such that anisotropic etching is possible. Wafer etching method. 3. The anisotropic etching solution is KOH, and the temperature of the anisotropic etching solution is set to a high temperature of 80 ° C. or higher in the second step. 2. The method for etching a Si wafer according to 2. 4. The PN-bonded Si as the Si wafer
In a configuration using a wafer, in the first step, the Si wafer is anisotropically etched while applying a positive voltage to the P layer of the Si wafer such that anisotropic etching is possible. Then, the application of the positive voltage to the P layer of the Si wafer is stopped and a positive voltage for anodizing is applied to the N layer of the Si wafer to anodize the Si wafer in the vicinity of the PN junction layer. An anodic oxidation step of oxidizing is performed, and after performing the anodization step, in the second step, the application of the positive voltage to the N layer of the Si wafer is stopped and the P layer of the Si wafer is anodized. 4. The method for etching a Si wafer according to claim 1, wherein the Si wafer is isotropically etched by applying a positive voltage for oxidation. 5. An etching method for immersing a PN-bonded Si wafer in an anisotropic etching solution to etch a desired portion of the Si wafer, wherein the P layer is anisotropically etched to near the PN junction layer. After performing this step, a positive voltage for anodic oxidation is applied to the N layer of the Si wafer so that the Si layer nears the PN junction layer.
A step of anodizing the wafer, and after performing this step, stopping the application of the positive voltage to the N layer of the Si wafer and the P of the Si wafer.
A Si wafer comprising: a step of applying a positive voltage for anodizing to the layer to perform the anisotropic etching; and a step of isotropically etching the etching surface exposed by the step of anodizing. Etching method. 6. The method of etching a Si wafer according to claim 2, wherein a resistor is connected in series to the Si wafer to apply a voltage. 7. The method of etching a Si wafer according to claim 6, wherein the resistance value of the resistor is changed according to the type of the Si wafer and the etching process. 8. The voltage applied to the Si wafer is adjusted so that the current flowing through the Si wafer has a predetermined value when the voltage is applied to the Si wafer. A method for etching a Si wafer as described above.