JPH11111675A - Silicon wafer etching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an etching method of high thickness precision at a diaphragm in a wafer surface by reducing the variations in etching amount at center part and outer peripheral part of a wafer. SOLUTION: A process in which, either to with a silicon wafer 3 submerged in an etching liquid, a voltage is to be applied or a voltage for etching is to be advanced is applied for etching from one surface of the silicon wafer 3, so that a recessed part 4 is formed in part region of the silicon wafer 3, and a process where, before and after theis process, the silicon wafer 3 is applied with a positive voltage with the silicon wafer 3 submerged in the etching liquid like wise for anode-oxidation of a silicon, are provided. BY canceling the tendency of etching amount distribution in a wafer surface in each process, the etching amount is controlled in the surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for etching a silicon wafer, and more particularly, to a method suitable for use as an etching method for forming a thin portion in a semiconductor pressure sensor or a semiconductor acceleration sensor.

[0002]

2. Description of the Related Art As a method of repeatedly etching a silicon wafer with high precision, there is a method of controlling a positive voltage applied to a surface to be etched of the wafer (Japanese Patent Laid-Open No. Hei 8-2645).
04 publication). Specifically, as shown in FIG. 22, after forming a mask material 61 on a silicon wafer 60, as shown in FIG. 23, the mask material 61 is immersed in an alkaline etching solution such as KOH,
A positive voltage is applied to the surface to be etched at the beginning and end of etching when the liquid temperature is unstable, and silicon is anodically oxidized to form the recess 62. In this way, a predetermined amount of silicon can be repeatedly and accurately etched with a stable solution temperature while eliminating the variation factor of the etching amount (thickness).

[0003]

However, the distribution of the etching amount in the wafer surface depends on the temperature distribution of the etching solution on the wafer surface, so that there is a problem that the etching amount varies between the central portion and the outer peripheral portion of the wafer. There is. In particular, when etching is performed at a high temperature, the variation in the amount of etching increases according to the liquid temperature distribution.

An object of the present invention is to provide an etching method capable of reducing the variation in the etching amount between the central portion and the outer peripheral portion of the wafer and increasing the thickness accuracy of the thin portion in the plane of the wafer. .

[0005]

According to the first aspect of the present invention, no voltage is applied in a state where the silicon wafer is immersed in the etching solution, or a voltage is applied so that the etching proceeds. A step of forming a recess in a partial region of the silicon wafer by etching from one surface of the wafer, and applying a positive voltage to the silicon wafer in a state where the silicon wafer is immersed in an etching solution at least before or after the step. By offsetting the tendency of the etching amount distribution in the wafer surface in each step with the step of applying and anodizing silicon,
The amount of etching in the plane is controlled.

More specifically, as described in claim 2, when performing anodic oxidation, the power supply electrode is arranged only on the outer peripheral portion of the silicon wafer. Further, as described in claim 3, the stirring strength of the etching solution for etching,
At least one of the applied voltage and the anodic oxidation time at the time of anodic oxidation is adjusted.

That is, as shown in FIGS. 14 and 15, the power supply electrode 70 is arranged on the outer peripheral portion of the wafer and the power supply electrode 72 is arranged around the chip forming area 71 so that one pressure is uniformly applied to the entire surface of the wafer. As shown in FIG. 16, the etching amount distribution in the wafer surface during anodization is flat, and as shown in FIG. 17, the etching amount in the wafer surface during etching (except during anodization). Has a small outer peripheral portion, and as a result, as shown in FIG. 18, the total etching amount in the wafer surface is smaller at the outer peripheral portion.
On the other hand, for example, when the power supply electrode 9 is arranged only on the outer peripheral portion of the wafer as shown in FIGS. 6 and 7 and a voltage is applied only on the outer peripheral portion of the wafer, as shown in FIG. The amount of etching in the outer part increases,
As shown in FIG. 20, the amount of etching in the wafer surface at the time of etching (excluding the time of anodic oxidation) is small in the outer peripheral portion, and as a result, as shown in FIG. 21, the distribution of the total etching amount in the wafer surface Becomes flat.

Focusing on the fact that the etching rate changes depending on the applied voltage when silicon is anodized in this manner, the power supply method is designed so that the applied voltage differs between the central portion and the outer peripheral portion of the wafer during the anodizing. In addition, the variation of the etching amount is offset by devising the stirring strength of the etching solution, the applied voltage at the time of anodic oxidation, the anodic oxidation time, and the like. As a result, the variation in the etching amount between the central portion and the outer peripheral portion of the wafer is reduced, and the accuracy of the thickness of the thin portion in the wafer surface can be increased.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. This embodiment is embodied in a semiconductor pressure sensor using a piezoresistive layer.

FIG. 1 shows a cross section of a semiconductor pressure sensor.
An N-type epitaxial layer 2 having a thickness of 10 μm is formed on one surface of a P-type silicon substrate 1 having a (110) plane orientation, and a semiconductor substrate 3 is formed by this stacked body. The P-type silicon substrate 1 is formed with a concave portion 4 that is open on one surface, and a thin portion 5 is formed on the bottom surface 4 a of the concave portion 4. The thin portion 5 becomes a sensor diaphragm. The recess 4 is formed by etching.

In FIG. 1, a P ⁺ -type impurity diffusion layer 6 is formed in an N-type epitaxial layer 2, and this P ⁺ -type impurity diffusion layer 6 serves as a piezo resistor for sensing strain. A silicon oxide film 7 is formed on the surface of N-type epitaxial layer 2. P ⁺ -type impurity diffusion layer 6 is electrically led out to the surface side of silicon oxide film 7 by aluminum wiring 8.

FIG. 2 is a schematic view of an etching apparatus for forming a thin portion (diaphragm) 5 on a semiconductor substrate 3 in a wafer state. The etching apparatus has a base 14, a cylindrical frame 15, and a lid 16, and these members are made of tetrafluoroethylene resin or the like, and have high insulation properties and excellent heat insulation and corrosion resistance. . On the base 14, the lower opening end of the frame 15 is disposed in a state that it can be held in a liquid-tight state by an O-ring 17. Installed in a dense state. The base 14, the frame 15, and the lid 16 form a closed container, in which a 32 wt% KOH aqueous solution 19 as an alkali anisotropic etching solution can be placed.

An upper surface 14a of the base 14 is a smooth substrate mounting surface, and the semiconductor substrate 3 in a wafer state to be etched is arranged on the upper surface 14a. At this time, the P-type silicon substrate 1 of the silicon wafer (semiconductor substrate 3) faces upward and the surface of the P-type silicon substrate 1 is 32 wt%.
It is in contact with KOH aqueous solution 19. The power supply electrode 9 (see FIG. 1) of the silicon wafer (semiconductor substrate 3) is
4 is in close contact with the upper surface 14a.

Upper surface (substrate mounting surface) 14 of base 14
A concave portion 20 for forming a negative pressure chamber is provided in an annular shape on the outer peripheral portion of a. A ring-shaped packing 21 is fixed to the lower surface of the frame body 15, and the packing 21 is attached to the negative pressure chamber forming recess 20 while sandwiching the outer peripheral edge of the silicon wafer (semiconductor substrate 3).
The opening is closed. Then, by evacuating the inside of the negative pressure chamber forming recess 20 by a vacuum pump or the like (not shown), the packing 21 is sucked and the silicon wafer 3 is immovably fixed. In this manner, the masking of the etched surface at the outer peripheral edge of the silicon wafer 3 is performed by the packing 21. Further, the base 14 and the frame 15 are suction-fixed by the evacuation.

As shown in FIG. 3, a passage 23 is formed in the base 14 so as to communicate an upper surface (substrate mounting surface) 14a thereof with the concave portion 20 for forming a negative pressure chamber.
4 are arranged. One end of the anode electrode 24 is connected to a pin 26 by a nut 25 in the negative pressure chamber forming recess 20. The pin 26 is exposed to the outside of the base 14 by the communication hole 27, and hermetically sealed by an O-ring 28. The tip of the anode electrode 24 protrudes from the upper surface 14a of the base 14 by a distance L when there is no silicon wafer (semiconductor substrate 3), and when the silicon wafer 3 is disposed on the upper surface 14a of the base 14, Figure 3
As shown by the two-dot chain line. Thus, the anode electrode 2
4 contacts the power supply electrode 9 (see FIG. 1) of the silicon wafer 3 with a constant contact pressure, so that a voltage can be applied to the silicon wafer (semiconductor substrate 3).

In FIG. 2, the lid 16 is provided with a supply passage 29 extending to the inside of the frame 15, and a 32 wt% KOH aqueous solution is passed through the valve 30 through the supply passage 29 to the valve 3.
Pure water can be supplied through 1 and nitrogen gas can be supplied through a valve 32. The lid 16 is provided with a discharge passage 33 communicating the inside and the outside, and one end of the discharge passage 33 is opened at the bottom of the frame 15 by a pipe 34. The KOH aqueous solution 19, pure water and the like in the frame 15 can be discharged through the pipe 34 and the discharge passage 33.

A bar-shaped cathode electrode 35 is disposed so as to penetrate the lid 16, and hermetically sealed by an O-ring 36. This cathode electrode 35 is 32 wt% in the frame 15.
The KOH aqueous solution 19 extends to a predetermined depth. Between the cathode electrode 35 and the anode electrode 24, a DC power supply 37, an ammeter 38, and a contact 39 are connected in series. Then, a voltage is applied to the cathode electrode 35 and the anode electrode 24 by the DC power supply 37 by closing the contact 39. At this time, the ammeter 38
From the silicon wafer (semiconductor substrate 3) to the cathode electrode 3
5 is detected.

A heater 40 is disposed so as to penetrate the lid 16, and the O-ring 41 maintains airtightness. When the heater 40 is energized, the heater 40 generates heat and the temperature of the 32 wt% KOH aqueous solution 19 can be raised. The temperature sensor 42 is arranged so as to penetrate the lid 16, and the O-ring 43 keeps airtight. The temperature of the KOH aqueous solution 19 is detected by the temperature sensor 42. The temperature controller 44 is a temperature sensor 42
Monitoring the temperature of the KOH aqueous solution 19 by the heater 40
Is controlled to keep the temperature of the KOH aqueous solution 19 at 110 ° C.

A stirring blade 45 is disposed in the frame 15, and the stirring blade 45 rotates via a coupling 47 by a motor 46 attached to the lid 16 to stir the KOH aqueous solution 19. The stirring blade 45 is kept airtight by an O-ring 48.

The main controller 49 includes a start switch 5
The start of etching is detected by a signal from 0, and the energizing current is detected by a signal from the ammeter 38.
Further, the main controller 49 includes a contact 39, a motor 4
6. The drive of the temperature controller 44 and the valves 30, 31, and 32 is controlled. Main controller 4
Reference numeral 9 mainly includes a microcomputer.

Next, a method of manufacturing the semiconductor pressure sensor will be described. FIG. 4 is an explanatory view of the steps of the etching process, and FIG. 5 shows the state of voltage application. The manufacturing process will be described with reference to FIGS.

First, a P-type silicon substrate (silicon wafer) 1 of (110) plane in FIG. 22 is prepared. This wafer has a specific resistance of 10 to 20 Ω · cm. An N-type epitaxial layer 2 is grown on one surface of the P-type silicon substrate (silicon wafer) 1, and a power supply electrode (metal film) 9 is provided on the outer peripheral portion of the surface of the N-type epitaxial layer 2 via a P ⁺ layer. Form. At this time, as shown in FIGS. 6 and 7, the power supply electrode 9 is formed only on the outer peripheral portion (the portion where no element is provided) of the surface (circuit surface) of the silicon wafer (semiconductor substrate 3). (2Ω or less). Further, the resistance of the silicon substrate 1 between the central portion and the outer peripheral portion of the silicon wafer 3 is set to about 10 to 100Ω. That is, a dummy chip area is formed in the center of the silicon wafer 3, and the voltage measuring electrodes 9a are formed in the dummy chip area.
Is formed, and the resistance between the center and the outer peripheral portion of the P-type silicon substrate 1 is measured by applying a probe to the voltage measurement electrode 9a and the power supply electrode 9. The voltage measuring electrode 9a
(Dummy chip area) may be at least one (one location).

Further, a mask material 10 (see FIG. 1) is arranged in a predetermined region on the surface of the P-type silicon substrate 1. As the mask material 10, a silicon nitride film (SiN) is used. Thus, a silicon wafer (semiconductor substrate 3) before etching is prepared. A large number of recesses 4 are formed in the silicon wafer 3 for each chip formation region by the subsequent processing.

Then, the silicon wafer 3 is set in the etching apparatus shown in FIG. 2 (timing t1 in FIG. 4). At this time, the back surface (etched surface) of the wafer is directed upward, and power can be supplied from two to four peripheral portions of the wafer. That is, as shown in FIG. 2, the silicon wafer 3 is disposed on the upper surface 14 a of the base 14, the inside of the negative pressure chamber forming recess 20 is evacuated, and the silicon wafer 3 is fixed by the packing 21.

When the start switch 50 is turned on from this state, the main controller 49 switches the contact 39 shown in FIG.
Is closed to start voltage application (timing at t2 in FIG. 4). Subsequently, the main controller 49 opens the valve 30 in FIG. 2 while applying a positive voltage to the P-type silicon wafer 1, and transfers a KOH aqueous solution (etching solution) heated in advance to a predetermined temperature to the processing bath (FIG. 4 at t3). That is, as shown in FIG. 8, the etchant preheated in the preheating tank is put into the container of FIG. As a result, the liquid temperature of the KOH aqueous solution 19 decreases in the early stage of the etching, and the degree thereof slightly changes for each processing (for each wafer). However, in the initial stage of the etching, a positive voltage is applied to the silicon wafer 3 and the anodic oxidation is performed. Therefore, as shown in FIG. 5, the progress of the etching during that time (the anodizing period T1 in FIG. 5) is suppressed. In this period T1, the etched surface is anodically oxidized. However, as shown in FIG. 19, the effective voltage is higher at the outer peripheral portion of the wafer on which the power supply electrode 9 is disposed than at the central portion, and the outer peripheral portion of the wafer is different from other central portions. Etching proceeds from the site.

Thereafter, the main controller 49 keeps this state for a predetermined time (T1 in FIG. 4) until the liquid temperature is stabilized. Then, when the predetermined time T1 has elapsed (timing at t4 in FIGS. 4 and 5), the main controller 49 opens the contact 39 in FIG. 2 and ends the voltage application. When the voltage application is completed, the silicon is etched. At this time, the heat from the heater 40 is hardly transmitted to the outer peripheral portion of the silicon wafer 3, and as shown in FIG. 20, the temperature of the etchant is lower in the outer peripheral portion than in the central portion of the wafer, and is lower than that in the central portion of the wafer. Etching progresses slowly. That is, as shown in FIG. 2, the packing 21 (sealant) is pressed against the outer periphery of the silicon wafer 3, and the heat generated by the heater 40 escapes through the packing 21 (sealant). The progress of etching is slower than in the center.

Although no voltage is applied during the etching period T2, the present invention is not limited to this, and the voltage may be applied such that etching proceeds, and etching may be performed from one surface of the silicon wafer 3.

Next, the main controller 49 will be described with reference to FIGS.
The contact 39 in FIG. 2 is closed at the timing t5 to start the voltage application, and the contact 39 is opened at the timing t7 in FIG. 4 to end the voltage application. The initial stage of this voltage application, that is, FIG.
Is anodized in a period T3 between t5 and t6.

At time t6 in FIG. 4, the main controller 49 opens the valve 31 in FIG. 2 and injects pure water. That is, pure water is injected into the tank in a state where silicon is anodized, and the KOH aqueous solution (etching solution) 19 is diluted and cooled. Then, as described above, when the voltage application is stopped at the timing of t7 in FIG. 4 and the etching is completed, the silicon wafer 3 in which the thickness of each diaphragm in the wafer surface has a desired value is obtained.

In these processes, when the uniform power supply method using the power supply electrodes 70 and 72 shown in FIG. 15 is used, the distribution of the etching amount on the silicon wafer is uniform in the anodizing step and the outer peripheral portion in the etching step. The amount of etch tends to be small. In contrast, FIGS.
When the power supply method is adopted, the etching amount distribution tends to be opposite in each step of anodic oxidation and etching. Therefore, by setting the anodic oxidation conditions (applied voltage and time) and the rotation speed of the stirring blade that can offset the etching amount distribution, In addition, a variation in etching amount can be reduced, and an accurate diaphragm can be formed.

The condition setting for canceling the distribution of the etching amount will be described in detail below. FIG. 9 shows the relationship between the applied voltage and the etching rate, and the etching rate differs depending on the applied voltage. In the region where the voltage is 1 volt or more, S
i is anodized and the etch rate drops significantly,
It increases little by little as the voltage rises.

FIG. 10 shows various positions in the wafer surface when the anodic oxidation time is changed when P-type silicon having a specific resistance of 10 to 20 Ω · cm is employed using the power supply system of FIGS. 3 shows the measurement results of the etching amount of the sample. The anodizing times are 10 minutes, 15 minutes and 20 minutes.

FIG. 11 shows the respective positions in the wafer surface when the anodic oxidation voltage is changed when the power supply system shown in FIGS. 6 and 7 is employed and P-type silicon having a specific resistance of 10 to 20 Ω · cm is used. 3 shows the measurement results of the etching amount of the sample. Anodizing voltages are 5 volts, 7 volts, and 9 volts.

From FIGS. 10 and 11, it can be seen that the amount of etching at the time of anodic oxidation varies depending on the time and voltage of anodic oxidation, but the tendency that the amount of etching at the outer peripheral portion of the wafer is large does not change. This is because the resistance inside the wafer is large, so that a voltage drop occurs in the central portion with respect to the outer peripheral portion of the wafer close to the power supply electrode 9, and as shown in FIG. Due to becoming smaller.

FIG. 12 shows the variation in the rotation speed of the stirring blade 45 when the power supply method shown in FIGS. 6 and 7 is used and P-type silicon having a specific resistance of 10 to 20 Ω · cm is used. The measurement results of the etching amount at each position are shown. This figure 1
From FIG. 2, it can be seen that the amount of etching in the wafer surface varies depending on the number of rotations of the stirring blade 45, but the tendency that the amount of etching in the outer peripheral portion of the wafer is small at any number of rotations does not change.

As described above, since these tendencies regarding the anodizing time, the anodizing voltage, and the etching amount distribution depending on the number of rotations of the stirring blade 45 are reproducible, the etching in the wafer surface is determined by the combination of the anodizing conditions and the stirring conditions. It is possible to make the quantity (thickness) distribution more uniform.

The following is a summary of these matters. When a voltage is uniformly applied to the entire surface of the wafer as shown in FIGS. 14 and 15, as shown in FIG. 16, the distribution of the etching amount in the wafer surface during anodization is flat,
As shown in FIG. 17, the amount of etching in the wafer surface at the time of etching (excluding the time of anodic oxidation) is small in the outer peripheral portion. As a result, as shown in FIG. The outer circumference is small. On the other hand, when a voltage is applied only to the outer peripheral portion of the wafer as in the present example shown in FIGS. 6 and 7, the amount of etching in the wafer surface at the time of anodic oxidation increases in the outer peripheral portion, as shown in FIG.
As shown in FIG. 20, the amount of etching in the wafer surface at the time of etching (excluding the time of anodic oxidation) is small in the outer peripheral portion, and as a result, as shown in FIG. 21, the distribution of the total etching amount in the wafer surface Becomes flat.

Hereinafter, description will be made with reference to specific numerical values.
The anodizing voltage was 9 volts, the time T1 (see FIG. 4) was 15 minutes, the etching time T2 was 29 minutes, the anodizing time T3 at the end was 3 minutes, and the rotation speed of the stirring blade was 300 rpm.
By controlling the anodic oxidation voltage / time and the rotation speed of the stirring blade during etching, the etching amount distribution can be made flat. Note that T3 has almost no effect on the progress of etching.

Here, 32 wt% K is used as an etching solution.
The liquid temperature was adjusted to 110 ± 0.1 ° C. using OH. FIG. 13 shows an etching amount distribution of each diaphragm in the wafer when a silicon wafer having an original thickness of 300 μm is etched under the above conditions. In FIG. 13, the present embodiment is shown by a solid line, and a broken line shows a comparative example using the equal power feeding method of FIGS. In the comparative example shown by the broken line, the anodic oxidation voltage was 5 volts, the anodic oxidation time was 15 minutes, the etching time was 29 minutes, and the number of revolutions of the stirring was 300 rpm. In the present embodiment shown by the solid line, the anodic oxidation voltage is 9 volts, the anodic oxidation time is 15 minutes, the etching time is 29 minutes, and the number of rotations for stirring is 300 rpm.

FIG. 13 shows that the etching amount distribution of the present embodiment is flatter than that of the comparative example. As a result, in this embodiment, the variation in the etching amount can be suppressed to ± 1 μm or less.

In the case of FIG. 13, the etching amount distribution in the wafer surface is flattened by changing only the anodic oxidation voltage. However, only the anodic oxidation time is changed, By changing only the number of rotations, or changing two of the anodizing voltage, the anodizing time, and the number of rotations of the stirring blade 45, or changing all three factors, the flatness of the etching amount distribution in the wafer surface is obtained. May be achieved.

As described above, this embodiment has the following features. (A) A part of the silicon wafer 3 is etched by applying a voltage such that the etching proceeds, or not by applying a voltage in a state where the silicon wafer 3 is immersed in the etching solution. A step of forming a concave portion 4 in the region and a step of applying a positive voltage to the silicon wafer 3 while immersing the silicon wafer 3 in an etching solution at least one of before and after the step to anodize silicon. The in-plane etching amount is controlled by canceling the tendency of the in-plane etching amount distribution in each step.
As a result, the variation in the etching amount between the central portion and the outer peripheral portion of the wafer is reduced, and the accuracy of the thickness of the thin portion in the wafer surface can be increased.

More specifically, at the time of anodic oxidation, in order to cause a difference in applied voltage between the central portion and the outer peripheral portion of the wafer,
The power supply electrode 9 is arranged only on the outer peripheral portion of the silicon wafer to offset the variation in the etching amount at the time of etching.

The amount of etching (thickness) in the wafer surface
Is caused by the liquid temperature distribution on the wafer at the time of etching, and therefore, at least one of the rotation speed of the stirring blade for etching (the stirring strength of the etching solution), the applied voltage at the time of anodic oxidation, and the etching time. Is adjusted, the amount of etching in the wafer surface can be made more uniform.

In the above description, the case where the diaphragm of the semiconductor pressure sensor is formed has been described.
It can be used when a thin portion (beam portion) of a semiconductor acceleration sensor is formed.

In the above description, the P layer is etched on a silicon wafer having a PN junction. However, an electrode leading to the surface to be etched is provided on a silicon wafer having no PN junction, and silicon is etched through the electrode. The present invention may be applied to a case where etching is performed by applying a positive voltage to an etching surface of a wafer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor pressure sensor according to an embodiment.

FIG. 2 is a schematic diagram of an etching apparatus.

FIG. 3 is a partially enlarged view of an etching apparatus.

FIG. 4 is a process chart for explaining an etching operation.

FIG. 5 is a time chart for explaining an etching operation.

FIG. 6 is a plan view of a silicon wafer.

FIG. 7 is a sectional view taken along the line AA of FIG. 6;

FIG. 8 is a diagram illustrating an etching operation.

FIG. 9 is a diagram showing a relationship between an applied voltage and an etching rate.

FIG. 10 is a distribution diagram of an etching amount.

FIG. 11 is a distribution diagram of an etching amount.

FIG. 12 is a distribution diagram of an etching amount.

FIG. 13 is an etching distribution diagram in a wafer surface.

FIG. 14 is a plan view of a silicon wafer.

FIG. 15 is a sectional view taken along line BB of FIG. 14;

FIG. 16 is an etching distribution diagram in a wafer surface.

FIG. 17 is an etching distribution diagram in a wafer surface.

FIG. 18 is an etching distribution diagram in a wafer surface.

FIG. 19 is an etching distribution diagram in a wafer surface.

FIG. 20 is an etching distribution diagram in a wafer surface.

FIG. 21 is an etching distribution diagram in a wafer surface.

FIG. 22 is a cross-sectional view illustrating etching.

FIG. 23 is a cross-sectional view illustrating etching.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P type silicon substrate, 2 ... N type epitaxial layer, 3
... Semiconductor substrate (silicon wafer), 4 ... Recess, 19 ... K
OH aqueous solution

Claims (3)

[Claims] 1. A method in which a voltage is not applied in a state where a silicon wafer is immersed in an etching solution, or a voltage that allows the etching to proceed is applied to perform etching from one surface of the silicon wafer and a partial area of the silicon wafer is applied. Forming a concave portion in the silicon wafer, and applying a positive voltage to the silicon wafer in a state where the silicon wafer is immersed in an etching solution at least one of before and after the step to anodize the silicon The method of etching a silicon wafer, wherein the in-plane etching amount is controlled by canceling out the tendency of the in-plane etching amount distribution in each step. 2. The method for etching a silicon wafer according to claim 1, wherein a power supply electrode is arranged only on an outer peripheral portion of the silicon wafer when performing anodic oxidation. 3. The silicon wafer according to claim 2, wherein at least one of a stirring strength of an etching solution for etching, an applied voltage at the time of anodic oxidation, and an anodic oxidation time is adjusted. Etching method.