JP3506036B2 - Silicon wafer etching method - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for etching a silicon wafer for producing a diaphragm or the like used in a semiconductor pressure sensor, an acceleration sensor, or the like.

[0002]

2. Description of the Related Art A diaphragm 15 of a semiconductor pressure sensor 10 as shown in FIG. 3 described later can be produced by etching a silicon wafer 1 as shown in FIGS. 1 and 2 described later. As will be described later with reference to FIG. 1, the P layer 11 and the N layer 12 are integrated by a PN junction.
A silicon wafer 1 in which a partial region on the layer 11 side is provided with an etching mask 110 is prepared, and a positive voltage is applied to the N layer 12 side while the silicon wafer 1 is immersed in an etching solution 19 as shown in FIG. Apply.

As a result, the region of the P layer 11 without the etching mask 110 is dissolved and removed, and finally anodic oxidation occurs near the PN junction, a silicon oxide film is formed, and the dissolution of the P layer 11 is almost stopped. To do. At this point, water is added to the etching solution 19 to stop the etching. Then, the silicon wafer 1 is taken out from the etching solution 19 and washed with water.

From the above, as shown in FIG. 3 described later,
Etching mask 110 for P layer 11 of silicon wafer 1
It is possible to form a recess by removing a region without a gap up to the vicinity of the N layer 12. This recess becomes the diaphragm 15.
According to this etching method, a diaphragm having a desired shape and a desired thickness can be easily manufactured with high accuracy.

[0005]

However, in the conventional etching method, as shown in FIG. 35, the voltage applied to the N layer 12 leaks to the P layer 11 side, a leak current 9 is generated, and the vicinity of the surface of the P layer 11 is generated. May be anodized.
Such a leak current 9 is generated, for example, when the Al wiring leading to the N layer is short-circuited with the Al wiring leading to the P layer of the integrated circuit due to a photo defect. In this case, there is a problem that the etching is delayed or the etching does not proceed particularly in the portion where the leak current 9 is generated (in the above-described example, the chip in which the short circuit has occurred or the chip in the vicinity thereof).

Due to a partial etching delay, for example, when manufacturing a diaphragm, the thickness and size vary. For example, when the conventional etching process is applied to the diaphragm of the semiconductor pressure sensor as described above, There have been problems that the precision of the etching process is reduced and the production yield due to the etching process is reduced. This problem chronically occurs for several percent. Also,
Taking the above-mentioned production of the diaphragm as an example, the defective thickness of the diaphragm due to insufficient etching may reach about 50% of the total diaphragm depending on the silicon wafer, which is also a factor of high cost.

As a measure against this problem, a voltage is applied to the silicon wafer before etching to measure the presence or absence and the magnitude of the leak current, and the silicon wafer in which a defect may occur may be excluded as a defective product (Japanese Patent Laid-Open No. Hei 10 (1999) -242242). 3-20977
8), a method of identifying a leak current generating portion and stopping power supply thereto (Japanese Patent Laid-Open No. 8-181278) has been conventionally devised.

However, these methods require a pre-inspection of the silicon wafer before etching, which may increase the number of steps and the cost. In the latter case, since no voltage is applied to the leak current generating portion, the etching proceeds even while the other portions are anodized and the etching is stopped, and the N layer is dissolved and the N layer is removed. When it is a thin film, there is a concern that the N layer may have holes.

The present invention has been made in view of the above conventional problems, and it is possible to omit the preliminary inspection of the silicon wafer, it is difficult to cause etching variations due to the leak current, and the processing cost is low. There is an object to provide a method for etching a silicon wafer.

[0010]

According to a first aspect of the present invention, there is provided a silicon wafer comprising a P layer and an N layer which are integrated by a PN junction, and an etching mask is applied to a partial region of the P layer side. In a method of etching a silicon wafer, which is prepared, a positive voltage is applied to the N layer side in a state where the silicon wafer is immersed in an etching solution to remove a predetermined amount of a region of the P layer of the silicon wafer without an etching mask. ， The above silicon wafer is immersed in the etching solution
Then, a positive voltage is applied to the N layer to flow from the N layer to the P layer.
Since the initial current is measured, the presence / absence of leakage current from the N layer to the P layer is determined, and an etching sheet prepared in advance is
Select one of the cans based on the initial current value
Then, based on the etching sequence selected above,
It is possible to start the etching process on the silicon wafer.
And a method for etching a silicon wafer.

The operation of the present invention will be described. In the etching method according to the present invention, the presence or absence of a leak current is determined at the beginning of etching, and the subsequent etching sequence is changed according to the determination result. Therefore, the preliminary inspection before etching the silicon wafer can be omitted.
The presence or absence of the leak current is determined by applying a positive voltage to the N layer.
It is judged by the initial current flowing at the start of etching.
Also, because the etching sequence is changed,
Since the silicon wafer can be reliably etched regardless of the state of the leak current, variations in processing accuracy due to insufficient etching due to the leak current are unlikely to occur.

Further, since the etching sequence according to the state of the silicon wafer can be performed, the number of silicon wafers to be excluded as defective products is reduced, which is economical and has a high yield, and thus the cost is low. Can be realized.

As described above, according to the present invention, there is provided a method for etching a silicon wafer, in which a preliminary inspection of the silicon wafer can be omitted, variation in etching caused by a leak current is unlikely to occur, and the processing cost is low. can do.

Further, by using the etching method according to the present invention, a silicon diagram used for a semiconductor pressure sensor (see Embodiment 1), an acceleration sensor, etc. can be manufactured. In addition, the etching method according to the present invention can be applied to the manufacture of a three-dimensional structure using silicon.

Further, the etching is generated by applying a positive voltage to the N layer side while the silicon wafer is immersed in the etching solution. Therefore, the initial etching is a short period from the start of etching, and is a period in which the silicon is hardly dissolved by the etching solution.

For example, 1 to 2 seconds after the positive voltage is applied to the silicon wafer and the current starts to flow is preferable (T0 according to the first embodiment described later). If the leak current is judged in less than 1 second, the current is unstable,
Measurement error may increase. If the etching is performed after 2 seconds, a difference in etching amount may occur between the leaked portion and the non-leaked portion, resulting in non-uniform etching.

Further, according to the present invention, any ordinary PN junction wafer can be etched. As the usable etching solution, an aqueous solution of KOH, tetramethylammonium hydroxide, hydrazine or the like can be used.

[0018] In the present invention, the presence or absence of the leakage current, it determines the initial current flowing at the start of etching by applying a positive voltage to the N layer. By the way, since a positive voltage is also applied to the P layer at the leak current generation portion, anodic oxidation occurs immediately after the start of etching. If there is no leak current, the PN junction is reverse-biased.
Almost no current flows to the silicon wafer. Since the current that flows during anodization depends on the area of the silicon wafer, the presence or absence of leak current can be determined from the initial current.

Further, even in the case of the anodized silicon wafer of the leak current generating portion, if the voltage application is immediately stopped, the etching proceeds. Therefore, the judgment based on the initial current does not affect the etching quality. As described above, the presence / absence of a leak current can be determined without adversely affecting the subsequent etching sequence.

Next, as in the invention described in claim 2 ,
In the etching sequence when the initial current is less than the predetermined value, the positive voltage is continuously applied to the N layer side as it is, the peak point of the current is detected, and then water is injected into the etching solution after the elapse of a predetermined time. However, it is preferable to terminate the etching. Since a silicon wafer whose initial current is less than a predetermined value has no leak current, etching can be completed by performing the same etching sequence as in the conventional technique.

By the way, when a positive voltage is applied to the N layer side of a silicon wafer having a PN junction in an etching solution to etch the P layer, a voltage drop due to the PN reverse bias causes a drop in the P layer, which is the etching surface. No voltage is applied, so etching progresses (silicon wafer melts).
At this time, almost no current flows.

After that, when the etching progresses to the vicinity of the PN junction (more specifically, the end portion of the PN depletion layer on the P layer side), the voltage drop disappears at this portion, and anodic oxidation of silicon occurs. Due to this anodic oxidation, the current suddenly increases and reaches a peak and then stabilizes. After waiting until such a state occurs (this is "waiting for the lapse of a predetermined time" above), water is added to terminate the etching as described above. Since the etching liquid is diluted and cooled when water is added, the etching can be surely stopped without further progressing the etching.

A predetermined value, which is a reference for determining the initial current, is a value generated when a silicon wafer having no leak current is etched by a conventional etching method. It is preferable to set the peak value to 1/20 or less. If this value deviates from the above range, there is a possibility that the etching becomes non-uniform due to the influence of the leak current and the quality of the etching process deteriorates. For example, when it is used for processing a diaphragm, a diaphragm having an uneven thickness may be manufactured.

Further, "Wait for a lapse of a predetermined time" is mentioned, but this time cannot be unconditionally specified because it changes depending on the type of etching solution, temperature and the like. For example, K
When using OH and etching at a temperature of 110 ° C,
It is preferably 2 to 6 minutes. As a result, uniform etching can be reliably performed. If this value is less than 2 minutes, the etching may be non-uniform. Further, if it exceeds 6 minutes, excessive etching may occur. Taking the processing of the diaphragm described later as an example, the unevenness of the etching causes a large variation in the thickness of the diaphragm, and excessive etching causes the sidewalls of the recesses to be excessively etched to obtain the desired shape. It can be difficult.

Next, as in the invention of claim 3, the etching sequence when the initial current is not less than the predetermined value, stop the application of positive voltage to the N-layer side, or leakage current is generated The etching is the fastest in the step of etching the P layer by applying a positive voltage to the N layer side to a size that does not cause anodic oxidation of the P layer in the leak generation portion, and in the portion of the silicon wafer where no leak has occurred. When the etching of the portion is completed and the etching reaches the vicinity of the PN interface, it is preferable to apply a positive voltage to the N layer side for a predetermined time and then inject water into the etching solution to complete the etching.

By stopping the application of the positive voltage to the N layer side with respect to the silicon wafer whose initial current is equal to or more than the predetermined value, no voltage is applied to the P layer side, so that the etching of the P layer can proceed. Alternatively, by setting the magnitude of the positive voltage applied to the N layer side to such an extent that the P layer does not undergo anodic oxidation, etching in the P layer can proceed.

If a positive voltage is not applied to the N layer after that, the etching progresses to the N layer, the thickness of the silicon wafer varies, and the N layer is penetrated by the etching. To prevent this phenomenon, N
A positive voltage is applied to the layer side for a predetermined time to stop the etching of the P layer. As described above, by controlling the positive voltage applied to the N layer, uniform etching can be performed even on a silicon wafer in which a leak current is generated.

The predetermined value of the initial current is the same as in claim 4 described above. Further, in the etching sequence according to the present invention, after the etching tip at the portion with the highest etching rate reaches the vicinity of the PN interface (the interface between the P layer and the N layer, which is substantially synonymous with the PN junction), the N layer is reached. A positive voltage is applied, but it is preferable that the timing of this application is such that, when the voltage is continuously applied to the N layer, the portion of the unleaked portion with the fastest etching reaches the PN interface and the current starts to rapidly increase.
Further, although “after applying a positive voltage to the N layer side for a predetermined time” is mentioned, the timing of the predetermined time in this case will be described later.

According to the invention of claim 4 , the positive voltage is applied to the N layer side for a predetermined period of time by applying a pulse voltage at regular time intervals and by anodic oxidation of an unleaked portion where no leak current occurs. It is preferable to detect by monitoring the current surge point. When positive voltage is turned on / off, that is, pulsed, anodic oxidation becomes possible,
It becomes impossible. That is, etching and anodic oxidation are switched instantaneously according to the pulse application cycle.

If anodic oxidation occurs, the current also increases accordingly. Further, when the etching tip of the unleaked portion reaches the vicinity of the PN interface, anodic oxidation occurs. Therefore, by monitoring this, the current sudden increase point is detected, and the voltage is switched at this timing to generate the leakage current. It is possible to prevent the etching from completely stopping at the portion to be etched, and to stop the etching by detecting that the etching tip of the non-leak portion has come near the PN interface.

Next, as in the fifth aspect of the invention, it is preferable that the determination of the leak current and the etching sequence corresponding to the determination result are performed in the same apparatus. As a result, the cost for etching can be reduced.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1 An etching method according to an embodiment of the present invention will be described with reference to FIGS. To explain the outline of this example, as shown in FIG. 1, this example is composed of a P layer 11 and an N layer 12 which are integrated by a PN junction, and an etching mask 110 is provided in a partial region on the P layer 11 side. The processed silicon wafer 1 is prepared, and as shown in FIG. 2, a positive voltage is applied to the N layer 12 side while the silicon wafer 1 is immersed in the etching solution 19 to etch the P layer 11 of the silicon wafer 1. In removing a predetermined amount of the region without 110, the presence or absence of a leak current from the N layer 12 to the P layer 11 is determined at the initial stage of etching, and the silicon wafer 1 is processed by two different etching sequences based on this determination. And perform etching.

The presence or absence of this leak current is determined by the N layer 12
Judgment is made by applying a positive voltage to the initial current flowing at the start of etching. In the etching sequence when the initial current is less than the predetermined value, that is, when there is no leakage current, the positive voltage is continuously applied to the N layer 12 side,
After detecting the peak point of the electric current, water is injected into the etching solution 19 after waiting a predetermined time, and the etching is finished.

Further, in the etching sequence when the initial current is equal to or higher than the predetermined value, the positive voltage application to the N layer 12 side is stopped, or the positive voltage to the extent that the P layer 11 is not anodized is applied to the N layer 12 side. Applied to the N layer 12 side at the step of etching the P layer 11 and at the time when the etching tip of the fastest etching portion of the silicon wafer 1 where no leak occurs reaches the PN interface. After applying a positive voltage to the etching solution for a predetermined time, water is injected into the etching solution 19 to terminate the etching.

The details will be described below. First, in the etching method according to this example, the diaphragm 15 of the semiconductor pressure sensor 10 using the following piezoresistive layer is manufactured.
As shown in FIG. 3, an N type epitaxial layer which is the N layer 12 is laminated on one surface of the P type silicon substrate which is the P layer 11, and a recess 151 is formed in the P layer 11.
The thin portion formed on the bottom surface 150 of the diaphragm 1 is the diaphragm 15
Becomes The thickness of the N layer is 10.5 μm, which is substantially the same as the thickness D of the diaphragm 15 as shown in FIG. In addition,
The thickness of the entire silicon wafer 1 is 300 μm. The P-type silicon substrate has a crystal orientation (110)
Was used (the crystal orientation is (100)
It is also possible to use silicon).

As shown in FIG. 3, a P + type impurity layer 163 is partially laminated on the N layer 12, and this serves as a piezoresistor for sensing strain. A silicon oxide film 161 is laminated on the surface of the N layer 12. The P + type impurity layer 163 is formed on the aluminum wiring 162 by the silicon oxide film 161.
Is electrically drawn to the surface side of. An etching mask 110 made of SiN is provided on a part of the surface of the P layer. Although not shown, a metal film (aluminum) communicating with the N layer 12 is formed on the silicon wafer 1,
It is configured so that a positive voltage can be applied.

The semiconductor pressure sensor 10 is manufactured as follows. As shown in FIG. 1, first, an N layer 12 is grown on one surface of the P layer 11 by CVD (chemical vapor deposition) to form a P + type impurity layer 163, a silicon oxide film 161, and an aluminum wiring 162. . Next, the diaphragm 15 to be obtained on the surface of the P layer 11
An etching mask 110 made of a silicon nitride film is formed in accordance with the shape of. A semiconductor pressure sensor 10 having a diaphragm 15 can be obtained by anisotropically etching such a silicon wafer 1 by applying a positive voltage in an etching solution 19 (KOH) as shown in FIG. .

Next, the outline of the etching apparatus 3 used in this example will be described with reference to FIG. The etching apparatus 3 is composed of a base 314 made of a material having a high insulating property, such as tetrafluoroethylene resin, and having excellent heat insulation and corrosion resistance, a cylindrical frame 315, and a lid 316. A frame 315 is provided on the base 314.
The open end of the lower surface of O is arranged in a liquid-tight state by the O-ring 317. The lid 316 is arranged in a liquid-tight state by an O-ring 318 at the open end of the upper surface of the frame 315. This base 314,
The processing tank 31 is configured by the frame body 315 and the lid body 316,
The etching solution 19 for anisotropic etching of the alkali and the silicon wafer 1 are introduced into the processing bath 31.

The silicon wafer 1 is set with the surface on which the aluminum wiring 162 and the like are provided on the upper surface of the base 314 facing the processing tank as the bottom and the surface on which the diaphragm 15 is formed as the top. The positive voltage is applied to the N layer 12 by the power supply device 36 connected via the terminal 361, the Pt electrode 372 arranged so as to face the silicon wafer 1, and the circuit 360. In addition, the circuit 360 has an ammeter 36
3 and the contact 365 are connected. In addition, the Pt electrode 37
The tip of No. 2 is placed in the etching liquid 19 in the processing bath 31.

Further, the base 314, the frame 315, the lid 31
Outside of 6, a nitrogen gas tank 376 and a pure water tank 37
4. An etching liquid tank 372 is provided, and the introduction / stop of the processing bath 31 can be controlled by the valves 371, 372 and 373. A temperature sensor 370 connected to a temperature controller 37 and a heater 371 are arranged in the processing bath 31. Also,
A stirring blade 381 connected to a motor 38 is arranged in the processing tank 31. A control device 39 such as the power supply device 36, the temperature controller 37, and the motor 38 is provided.

The etching method of this embodiment will be described with reference to the flow charts of FIGS. 5 to 7 and the diagrams of FIGS. 8 to 15. Here, an etching sequence in which the positive voltage applied is constant and the positive voltage is turned on and off will be described. 8 and 12 are diagrams showing the relationship between the elapsed time from the start of etching and the positive voltage applied to the silicon wafer 1 from the power supply device 36, and FIGS. 9 and 13 show the elapsed time and the ammeter 363. It is a diagram which shows the relationship with the electric current which flows into the measured circuit 360.

250 ml of a 32% KOH aqueous solution was pumped up from the etching liquid tank 372 in an amount necessary for etching one silicon wafer and introduced into a preliminary tank (not shown), where the temperature was adjusted to 110 ° C. To do.

Next, as shown in step 411 of FIG. 5, the power supply device 36 is operated, the contact 365 is closed, and a positive voltage is applied to the silicon wafer 1. In this state, the valve 371 is operated, the etching liquid 19 is introduced into the processing tank 31 in which the silicon wafer 1 is set, and etching is started. (Initial current monitor) Next, as shown in step 412, waiting for the lapse of time T0 from the start of etching, after that, as shown in step 413, the initial current I0 is measured,
The difference from the judgment value I ′ of the presence / absence of leakage current is calculated.

(1) In the case of no leak current If the difference is positive, it is considered that there is no leak current, and the same etching sequence as the conventional one is carried out as shown in step 441 and subsequent steps in FIG. Change of positive voltage in this case,
Changes in current are shown in FIGS. (Etching) That is, the positive voltage is continuously applied to the N layer 12 side as it is. As shown in step 441, the time T
After 1 lapse of time, the current In is measured. Then, step 44
As shown in FIG. 3, the currents In + 1 and In are obtained every time T21.
Measure +2 etc. As shown in FIG. 9, the current gradually increases. (Anodic oxidation) However, the current reaches a peak point (corresponding to In + 3 in Fig. 9) at some point, and then a rapid current drop occurs for a very short time, and then the current increases again. The situation of the increase is gentle. As shown in step 444, the measurement point immediately before the difference between the current values measured every time T21 becomes negative is regarded as the current peak point (corresponding to In + 3 in FIG. 9), and step 44
As shown in 5, wait for the time T3 to elapse from the current peak point. (Washing) After that, as shown in step 446, the valve 373 is opened and pure water is injected into the processing bath 31. As a result, the etching solution 19 is cooled and the concentration thereof is reduced, so that the current is rapidly reduced and the etching is stopped. As shown in step 447, the elapse of time T4 is waited, then the injection of pure water is stopped, and the etched silicon wafer is taken out from the processing bath 31 as shown in step 448. Thereby, the semiconductor pressure sensor 10 having the diaphragm 15 is obtained.

The distribution of the diaphragm thickness D in the lateral direction of the obtained semiconductor pressure sensor 10 was evaluated. As shown in FIG. 11, measurement was performed between A and B in a line segment L connecting both ends of the silicon wafer 1. This measuring method will be described. As shown in FIG. 34, which will be described later, an infrared light irradiator 5 is provided on the N layer side of the silicon wafer 1, and infrared light is irradiated toward the diaphragm 15 from here. The reflected light reflected by the surface 51 on the N layer side and the surface 5 transmitted through the N layer
The interference situation of the reflected light reflected at 2 was measured. The diaphragm thickness D was obtained from this measurement result and is shown in FIG.

In the figure, the diaphragm position 1 is the point A in FIG. 11, which is the leftmost diaphragm on the line L, and the position 29 is the rightmost diaphragm point B on the line L.
Pointing to. As can be seen from the figure, the diaphragm thickness D on the silicon wafer 1 was substantially the same between A and B. That is, it was found that a diaphragm having a uniform thickness was obtained.

(2) When there is a leakage current When the difference between I0 and I'is 0 or more, it is considered that there is a leakage current. Changes in positive voltage and current in this case are shown in FIG.
It is FIG. Then, the etching sequence as shown in FIGS. 5 and 6 is performed. (Etching) As shown in step 414 in FIG. 5, the contact 365 is opened, the positive voltage applied to the N layer 12 side is turned off, and the time T1 elapses as shown in step 415.

(Current Change Monitor) The contact 365 is closed as shown in step 416. As shown in step 417, after T200, the current In flowing through the circuit 360 is measured as shown in step 418. Step 4 of FIG.
As shown in FIG. 19, the contact 365 is opened immediately after the measurement is completed.

Next, after the time T20 has elapsed as shown in step 420, the contact 365 is closed again as shown in step 421. As shown in step 422, the time T
After 200 hours, as shown in step 423, the current In
Measure +1. Repeat this operation for In + 1 and In
When the difference between and is greater than Ik, the next step 42
Move to 4 or later.

The voltage is continuously applied, and as the time T21 elapses, the current Im, I is impressed as shown in steps 424 to 427.
Measure m + 1. Then, the difference from the previous current value is obtained (Im + 1-Im), and the time when this becomes negative is regarded as the current peak point (Im + 2 is the current peak point in FIG. 13), and from this point, step 428 is shown. As shown in FIG.

(Washing) As shown in step 429, the valve 373 is opened and pure water is injected into the processing bath 31. This causes the current to decrease sharply. As shown in step 430, the elapse of time T4 is waited, and as shown in step 431, the injection of pure water is stopped, the contact 365 is opened, and the etching is stopped. Thus, the semiconductor pressure sensor 10 having the diaphragm 15 was obtained.

The distribution of the thickness D of the diaphragm 15 in this semiconductor pressure sensor 10 was measured in the same manner as described above, and FIG.
It was described in 4. When this is compared with a silicon wafer of the same lot (leakage current is generated at the same location. The leak generation portion is reference numeral C in FIG. 11) in the conventional etching shown in FIG. It was found that a diaphragm with a uniform thickness was obtained by significantly reducing In this example, after measuring the initial current,
Although the positive voltage was turned off during the time T1, the positive voltage (for example, 0 to 0.
Similar results could be obtained by applying 1 V).

Here, a guideline for setting values of the respective parameters in the above-mentioned etching sequence will be described. The time T0 is 1 to 2 seconds after the current starts to flow, and the time T1 is the 14th time obtained by dividing the time at which the current reaches the peak when the rate is the fastest into 15 equal parts, taking into consideration variations in the etching rate of the P layer. (For example, if the earliest peak arrival time is 33 minutes, 30.8 minutes). This is to detect the timing at which the fastest etching portion in the unleaked portion reaches the vicinity of the PN interface.

I'is set to 1/20 or less of the current during anodic oxidation as a standard. This is the initial current that becomes the threshold value for determining the presence or absence of leakage current. Since Ik depends on the silicon wafer or the like used, it cannot be determined in a general way. However, the peak current Ip of anodic oxidation in a silicon wafer having no leak current is applied, and 0.001 × Ip (mA / sec) is used as a standard. It is preferable to determine Ik by actually examining the relationship between the change in current and the thickness of the diaphragm with reference to this standard.

Time T20 is about 4 to 20 seconds and time T20
It is preferably 4 times or more than 0 (1 to 2 seconds). However, if the etching rate is large, note that if the time T20 is increased, the detection of the timing at which the etching of the non-leakage portion reaches the vicinity of the PN interface is delayed, the thickness cannot be corrected sufficiently, and the etching accuracy decreases. is necessary. Further, the time T21 is about 2 to 10 seconds, and the time T3 is 2
Approximately 6 minutes and time T4 is approximately 2-5 minutes.

Then, each set value in the etching method according to this example is as follows: the applied positive voltage is 4 V, the time T0 is 2 seconds,
I'is 1.5 mA, time T1 is 30.8 minutes, time T20
0 is 1 second, time T20 is 8 seconds, time T21 is 2 seconds, Ik
Was 0.035 mA / sec. Further, I0 when it was considered that there was a leak current was 15 mA.

For comparison, a silicon wafer considered to have a leak current (a silicon wafer having a leak generating portion at the same location in the same lot as described above) is
Applying the etching sequence without leak current described in (1), the diaphragm thickness of the obtained semiconductor pressure sensor was measured and described in FIG. 15 and 16 show the relationship between the applied positive voltage and the elapsed time and the relationship between the current and the elapsed time in this case. As is known from FIG. 17, the diaphragm thickness near the 5th to 10th positions from the left end A is very large, and as described above, the thickness of the silicon wafer used in this example is 300 μm. It was found that a leak current was generated at the indicated portion C) and etching was almost stopped.

The function and effect of this example will be described. In the etching method of this example, the etching sequence is different depending on the presence or absence of leak current. Specifically, when there is no leak current, a positive voltage is applied to the N layer 12 as in the conventional method, and etching is advanced. If there is a leak current, the application of the positive voltage is stopped and the etching proceeds. As a result, as shown in FIGS. 10 and 14, the semiconductor pressure sensor 10 having the diaphragm 15 having a uniform thickness can be obtained regardless of the presence or absence of leak current. In addition, it is possible to minimize variations in processing accuracy due to insufficient etching caused by leak current.

Further, in the etching method of this example, the presence / absence of a leak current is determined by measuring the initial current after the start of etching, so that it is not necessary to separately provide a preliminary inspection. Further, the silicon wafer 1 having a leak current in the preliminary inspection was conventionally treated as a defective product, but the method according to this example can be processed as the semiconductor pressure sensor 10, so that the yield can be increased. it can. As a result, the cost for etching can be reduced.

In addition, the etching method of this example uses a single etching apparatus to perform a process corresponding to a conventional pre-inspection (determination of presence / absence of leak current), a silicon wafer having a leak current, and a silicon wafer 1 having no leak current. An etching sequence can be performed. Therefore, the number of manufacturing steps can be reduced, and the cost can be reduced.

As described above, according to the present embodiment, the silicon wafer etching method can be provided in which the preliminary inspection of the silicon wafer can be omitted, the variation of the etching caused by the leak current hardly occurs, and the processing cost is low. can do.

Embodiment 2 As shown in Steps 421 to 430 of FIG. 6 of Embodiment 1, etching is completed at the fastest etching portion in the silicon wafer where no leak occurs, and etching is performed at the PN interface. When reaching the vicinity, a positive voltage is applied to the N layer side for a predetermined time. In this example, in order to verify the validity of the timing of applying the positive voltage to the N layer,
The following test was conducted.

A silicon wafer (leakage generating portion at the same position on the wafer) and an etching apparatus similar to those of the first embodiment were prepared, and the following etching was performed on them. As in the first embodiment, as shown in FIG. 18, the application of the positive voltage to the N layer side was turned off to start etching, and 30 minutes after the start of etching, the positive voltage was applied again. The state of the current at this time is shown in FIG. A current is generated at the same time as the positive voltage is applied, and it rises sharply and reaches its peak. Once decreased from the peak, then gradually increased,
And as the etching stops with the addition of pure water,
The current suddenly drops to zero.

The thickness of the diaphragm thus obtained was measured in the same manner as in Embodiment 1 (see FIG. 11), and FIG.
0. According to this, the thickness of the portion where the leakage current occurred was larger than the other portions. From this, it was confirmed that it is necessary to further increase the non-application time of the positive voltage from the start of etching to more than 30 minutes in order to bring the thickness of this portion closer to the thickness of other portions.

Further, the same silicon wafer as that of the first embodiment (the leak generating portion is located at the same position on the wafer) and the etching apparatus were prepared, and the following etching was performed on the same. As in the first embodiment, as shown in FIG. 21, the application of the positive voltage to the N layer side was turned off to start the etching, and 33 minutes after the etching was started, the positive voltage was applied again.

The state of the current at this time is shown in FIG. The current rapidly increases with the application of a positive voltage, but before the sudden increase, that is, 33 minutes after the start of etching, the rapid increase point of the current, the midpoint (1/2) between the peak and the rapid increase point of the current, and the diaphragm thickness at the peak, At each point of time, water was poured into the treatment tank to dilute the etching solution, and after cooling, the silicon wafer was taken out, washed with water and dried, and the measurement was carried out by the method as shown in Embodiment 1 and FIG. The results are shown in FIG.

By the way, since the thickness of the N layer of the silicon wafer used is 10.5 μm, if the diaphragm thickness is 10.5 μm, the etching has just reached the interface of the PN junction. Moreover, when a reverse voltage is applied to a semiconductor having a PN junction, a depletion layer with few carriers is formed around the PN junction. The depletion layer of the silicon wafer used in this example is in the range shown by the diagonal lines in the figure.

As a result, it was found that the current started to increase rapidly when the etching tip of the fastest progressing portion reached the end portion on the P layer side of the depletion layer. Therefore, it was found that the positive voltage is preferably applied to the N layer at a point where the current starts to increase rapidly when the voltage is continuously applied to the N layer.

Embodiment 3 As shown in Steps 421 to 430 in FIG. 6 of Embodiment 1, the etching of the portion of the silicon wafer where the leak has not occurred and the etching progresses the fastest is completed, and the etching is PN. When it reaches near the interface,
A positive voltage is applied to the N layer side for a predetermined time, but in this example, the following test was performed in order to verify the optimization of the positive voltage applied to the N layer.

In the silicon wafer according to the first embodiment, the P layer is composed of a P type silicon substrate and the N layer is composed of an N type epitaxial layer (silicon). For these materials, the relationship between the etching rate and applied voltage was determined as shown below. Prepare P-type and N-type silicon substrate wafers with the same impurity concentration and use Al for power supply.
Wiring is provided. On the other hand, the etching rate was determined from the amount of silicon dissolved and the etching time when a voltage of -0.5 to 1.0 V was applied, and the results are shown in FIGS. 24 and 23.

From the figure, the etching rate of silicon changes drastically at a boundary of around 0.5 V for P-type silicon and around 0.3 V for N-type silicon. A positive voltage of 0.3 V or more is used to anodize N-type silicon, a positive voltage of 0.5 V or more is used to anodize P-type silicon, and the etching rate of P-type silicon is not applied ( (Corresponding to −0.5 V in FIG. 22), the level is 0 to 0.1.
It was found that a positive voltage of V should be applied.

Embodiment 4 This embodiment will be described below in order to confirm the validity of timing detection of applying a positive voltage to the N layer side for a predetermined time, as shown in step 416 of FIG. 5 of Embodiment 1. Such a test was conducted. The same silicon wafer as that of the first embodiment (the leak generating portion is located at the same position on the wafer) and an etching apparatus were prepared, and the following three types of etching were performed on the same.

In the same etching as in Embodiment 1, after the etching was started, the positive voltage was continuously applied to the N layer side (always applied). Further, 30 minutes after the start of etching, a positive voltage was applied to the N layer side. Further, as in the method described in Embodiment 1, a positive voltage was applied when the etching tip of the fastest etching portion reached near the PN interface.

The thickness of each diaphragm thus obtained was measured in the same manner as in Embodiment 1 (see FIG. 11) and is shown in FIG. According to this, it was found that the thickness of the portion where the leakage current occurred becomes thinner as the application of the positive voltage is delayed, and is the same as the thickness of other portions. As a result, it has been found that even in the case of a silicon wafer having a leak current, if the method according to the first embodiment is used for etching, it is possible to manufacture a diaphragm having a higher yield than the conventional one.

Embodiment 5 In this embodiment, as shown in step 413 in FIG. 5 of Embodiment 1, the threshold value of the initial current used for determining the presence / absence of a leak current from the N layer to the P layer at the initial etching stage. The following test was performed on the.

A silicon wafer (a silicon wafer with or without leak and a leak generation part unknown) and an etching apparatus similar to those of the first embodiment were prepared, and the following test was performed on this. Etching is started in the same manner as in Embodiment 1, but as shown in FIG. 27 (a typical example of a silicon wafer with and without leak current is described), a positive voltage to the N layer side of the silicon wafer is applied. The application was continued. Then, the initial current due to the application of the positive voltage is measured, and thereafter, the current is as shown in FIG.
As known from 8, it does not change.

After that, it rises sharply and reaches a peak. The current once decreases from the peak, then gradually rises, and etching stops with the addition of pure water, so that the current rapidly becomes zero. In such etching, the relationship between the ratio of the initial current of each silicon wafer (with or without leak current) to the magnitude of the peak current when there is no leak current, the diaphragm thickness of each silicon wafer, and the NG ratio were obtained. .

Here, the ratio of the initial current to the current at the peak is plotted on the horizontal axis and the diaphragm thickness is plotted on the vertical axis, as shown in FIG. The case where the ratio of the initial current and the current at the peak is 0 means that the initial current flows very little (the ratio is less than 1/200).

As is known from the figure, the larger the current ratio, the higher the thickness NG ratio of the diaphragm. Here, the thickness NG ratio means that the diaphragm thickness is 1
It is the occurrence rate of those exceeding the range of 3 + -2 μm. From the above, it was found that in the case of the conventional method of continuously applying the voltage, the NG ratio increases as the current ratio increases.

Example 6 of the Embodiment In this example, steps 416 to 423 of FIG.
When the positive voltage is applied to the N layer side by pulse application as shown in FIG. 5, the following test was conducted for its validity. The same silicon wafer as that of the first embodiment (the leak generating portion is located at the same position on the wafer) and the etching apparatus were prepared, and the change in the diaphragm thickness of the leak generating portion of the silicon wafer due to the applied voltage was measured in real time. .

When the P layer was etched without applying a voltage to the N layer and the thickness of the silicon became 16.0 μm, as shown in FIG.
As shown in 0, a voltage of 4 V was applied for 5 seconds, the voltage was turned off, and etching was performed for 10 seconds. After that, again for 5 seconds,
FIG. 31 shows the change over time in the diaphragm thickness corresponding to the voltage when a voltage of 4 V was applied.

Similarly, as shown in FIG. 32, when the thickness of silicon reaches 24.5 μm, a voltage of 4 V is applied for 15 seconds, a voltage of 0.1 V is applied for 10 seconds, the silicon is etched, and again, FIG. 33 shows the changes over time in the diaphragm thickness corresponding to the voltage when a voltage of 4 V was applied for 5 seconds and the silicon was anodized.

As shown in FIG. 34, the diaphragm thickness is measured by providing an infrared light irradiator 5 on the N layer side of the silicon wafer 1 and irradiating the diaphragm 15 with infrared light. Then, the interference state of the reflected light reflected by the surface 51 on the N layer side and the reflected light transmitted by the N layer and reflected by the surface 52 was measured. From this result, the diaphragm thickness between 51 and 52, that is, the diaphragm thickness could be obtained.

From the above measurement results, it was found that anodic oxidation and dissolution were instantaneously repeated by turning on / off or switching the positive voltage. In other words, it was found that the silicon wafer etching can be controlled by turning on and off the positive voltage.

[Brief description of drawings]

FIG. 1 is an explanatory cross-sectional view of a silicon wafer according to a first embodiment.

FIG. 2 is an explanatory diagram of a silicon wafer etching method according to the first embodiment.

FIG. 3 is an explanatory cross-sectional view of a semiconductor pressure sensor according to the first embodiment.

FIG. 4 is an explanatory diagram showing a structure of an etching apparatus according to the first embodiment.

FIG. 5 is an explanatory diagram showing a flowchart of an etching sequence in the first embodiment.

FIG. 6 is an explanatory diagram showing a continuation of the flowchart of FIG. 5 of the etching sequence in the first embodiment.

FIG. 7 is an explanatory diagram showing a continuation of the flowchart of FIG. 5 of the etching sequence in the first embodiment.

FIG. 8 is a diagram showing a relationship between a positive voltage and an elapsed time in an etching sequence for a silicon wafer having no leak current in the first embodiment.

FIG. 9 is a diagram showing a relationship between current and elapsed time in an etching sequence for a silicon wafer having no leakage current according to the first embodiment.

FIG. 10 is a diagram showing the relationship between diaphragm thickness and diaphragm position according to the etching sequences shown in FIGS. 8 and 9.

FIG. 11 is a plan view showing measurement positions of the diaphragm thickness in the first embodiment.

FIG. 12 is a diagram showing a relationship between a positive voltage and an elapsed time in an etching sequence for a silicon wafer having a leak current according to the first embodiment.

FIG. 13 is a diagram showing a relationship between current and elapsed time in an etching sequence for a silicon wafer having a leak current according to the first embodiment.

FIG. 14 is a diagram showing the relationship between diaphragm thickness and diaphragm position according to the etching sequences shown in FIGS. 12 and 13;

FIG. 15 is a diagram showing a relationship between a positive voltage and an elapsed time in an etching sequence for a silicon wafer having a leak current as a comparative example in the first embodiment.

FIG. 16 is a diagram showing a relationship between a current and an elapsed time in an etching sequence for a silicon wafer having a leakage current as a comparative example in the first embodiment.

FIG. 17 is a diagram showing the relationship between diaphragm thickness and diaphragm position according to the etching sequences shown in FIGS. 15 and 16.

FIG. 18 is a diagram showing a relationship between a positive voltage applied to a silicon wafer and time according to the second embodiment.

FIG. 19 is a diagram showing a relationship between current and time in the etching according to FIG. 18 according to the second embodiment.

FIG. 20 is a diagram showing the relationship between diaphragm thickness and diaphragm position according to the etching sequence of FIGS. 18 and 19 according to the second embodiment.

FIG. 21 is a diagram showing a relationship between a positive voltage applied to a silicon wafer and time according to the second embodiment.

FIG. 22 is a diagram showing a relation between current and time in the etching according to FIG. 21 according to the second embodiment.

FIG. 23 is a diagrammatic view showing the relationship between the change in current, the diaphragm thickness, the diaphragm position, and the position of the depletion layer according to the etching sequence of FIGS. 21 and 22, according to the second embodiment.

FIG. 24 is a diagram showing the relationship between the applied voltage and the etching rate for P-type silicon according to the third embodiment.

FIG. 25 is a diagram showing a relationship between an applied voltage and an etching rate for N-type silicon according to the third embodiment.

FIG. 26 is a diagram showing the relationship between the positive voltage application timing, diaphragm thickness, and diaphragm position according to the fourth embodiment.

FIG. 27 is a diagram showing a relationship between a positive voltage applied to a silicon wafer and time according to the fifth embodiment.

FIG. 28 is a diagram showing a relationship between current and time in the etching according to FIG. 27 according to the fifth embodiment.

FIG. 29 is a diagram showing the relationship between the current ratio and the thickness NG ratio according to the fifth embodiment.

FIG. 30 is a diagram showing a relationship between positive voltage and time according to the sixth embodiment.

FIG. 31 is a diagram showing the relationship between the diaphragm thickness and time when etching is performed by applying the voltage applied to FIG. 30 according to the sixth embodiment.

FIG. 32 is a diagram showing a relationship between positive voltage and time according to the sixth embodiment.

FIG. 33 is a diagram showing the relationship between the diaphragm thickness and time when etching is performed by applying the voltage applied to FIG. 32 according to the sixth embodiment.

FIG. 34 is an explanatory view showing a method for measuring the diaphragm thickness according to the sixth embodiment.

FIG. 35 is an explanatory diagram showing a state when a leak current is generated in the conventional silicon wafer etching method.

[Explanation of symbols]

1. ． ． Silicon wafer, 11. ． ． P layer, 12. ． ． N layer, 110. ． ． Etching mask,

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-3-209778 (JP, A) JP-A-6-104244 (JP, A) JP-A-9-92843 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 21/306 H01L 21/3063 H01L 21/308

Claims (5)

(57) [Claims] 1. A silicon wafer comprising a P layer and an N layer integrated by a PN junction and having an etching mask in a partial region on the P layer side is prepared, and the silicon wafer is used as an etching solution. a positive voltage is applied to the N layer side in a state dipped in the etching method for a silicon wafer to remove a predetermined amount of area without etching mask P layer of the silicon wafer, the etching initial etching solution the silicon wafer
Immerse in the N layer, apply a positive voltage to the N layer, and
From measuring the initial current flowing to Luo P layer, and determining the presence or absence of leakage current to the P layer from the N layer, one of the previously prepared etch sequence Tsuoue
The selection is made based on the initial current value, and the system is selected based on the selected etching sequence.
A method for etching a silicon wafer, which comprises starting an etching process for a recon wafer. 2. The etching sequence according to claim 1, wherein when the initial current is less than a predetermined value, a positive voltage is continuously applied to the N layer side as it is, and a predetermined time after the peak point of the current is detected. A method for etching a silicon wafer, characterized in that water is injected into an etching solution after a certain period of time to finish the etching. 3. The etching sequence according to claim 1, wherein the initial current is equal to or more than a predetermined value, the positive voltage application to the N layer side is stopped, or P is generated at a leak generating portion where a leak current is generated. The process of applying a positive voltage to the N layer side so that the layer does not anodize and etching the P layer, and the etching of the fastest etching part in the silicon wafer where no leak occurs Then
A method for etching a silicon wafer, characterized in that, when the etching reaches the vicinity of the PN interface, a positive voltage is applied to the N layer side for a predetermined time and then water is injected into the etching solution to terminate the etching. 4. The positive voltage is applied to the N layer side for a predetermined period of time according to claim 3, wherein a voltage is pulsed at regular time intervals, and a rapid current increase due to anodic oxidation of a non-leak portion where no leak current occurs. A method for etching a silicon wafer, characterized by detecting by monitoring points. 5. The method according to any one of claims 1 to 4 ,
The method for etching a silicon wafer, wherein the determination of the leak current and the etching sequence corresponding to the determination result are performed in the same apparatus.