JP3496523B2 - Semiconductor device, evaluation method thereof, and method of manufacturing semiconductor element - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method for evaluating the same, and a method for manufacturing a semiconductor element, and more particularly, to a minute defect generated when a storage node electrode of the semiconductor element is formed.
TEG (Test Element) capable of detecting foreign matter
And a method for evaluating the semiconductor device and a method for manufacturing a semiconductor element.

[0002]

2. Description of the Related Art As semiconductor devices become highly integrated, the area occupied by memory cells is decreasing. However, in a device having a capacitor such as a DRAM, it is necessary to ensure that the capacitance of the capacitor has a certain value or more in order to suppress a soft error due to α particles. In order to solve this, the shape of the storage node electrode (lower electrode) forming the capacitor is three-dimensionally three-dimensionally formed, and the interval between them is becoming extremely narrow. Therefore, the size of the defect / foreign matter that causes the current leakage between the storage node electrodes has become extremely small, and it has become difficult to detect the defect / foreign matter inspection apparatus using light such as a laser.

Therefore, conventionally, there is no effective inspection method for such minute defects and foreign matters, and even if a large amount of minute foreign matters is generated due to an apparatus abnormality or the like, the damaged wafer ends all wafer processes. Since the abnormality cannot be detected until the reliability test after the dicing / assembling and the burn-in is performed, it takes several months from the occurrence of the abnormality to the countermeasure.

As a method of detecting defects / foreign substances that cause a leak failure between such storage node electrodes, there is a method disclosed in, for example, Japanese Patent Laid-Open No. 9-45875. This is TE side by side with the product chips on the edge of the wafer.
By providing a G (Test Element Group) region, forming a wiring-shaped storage node dummy electrode having the same spacing as that between the storage node electrodes in the memory cell, and measuring the leak current value therebetween. This is a method of monitoring the occurrence of leak defects.

As a method of evaluating the insulation in the direction horizontal to the wafer, for example, there is a method disclosed in Japanese Patent Laid-Open No. 9-213762. In this method, a pair of conductive patterns are formed in a comb-like shape with a space between them, and the current flowing between them is measured to evaluate the insulation between the wirings.

[0006]

In the conventional semiconductor device as described above, the shape of the storage node dummy electrode is different from that of the storage node electrode in the memory cell. There is a problem that the defect situation cannot be accurately reproduced.

Further, in the former case of the prior art described above, since the TEG region on the product wafer is used, the effective area is extremely small and it is impossible to manage the minute fluctuation of the process.
Since the probe needle is brought into contact with the pad during the process, the probe mark may cause problems such as film peeling and foreign matter generation in the subsequent process.

Further, in the method of evaluating a semiconductor device using the conventional semiconductor device as described above, the memory of the semiconductor element is
There is a problem that the defect situation in the cell cannot be accurately reproduced, and it is not possible to correctly manage minute defects and foreign matter between the storage node electrodes.

The present invention has been made to solve the above problems, and by providing a storage node electrode pattern (storage node dummy electrode) similar to that of an actual product on the entire surface of a wafer, The present invention provides a semiconductor device that can accurately reproduce a defective state in a cell.

Further, by applying a stress to this semiconductor device under a high temperature and a high electric field to perform a leak test, the process control around the storage node electrode formation can be performed, and a quick feedback for an abnormality can be performed. Is provided.

The present invention also provides a method of manufacturing a semiconductor device, which evaluates a manufacturing process of a storage node electrode of a semiconductor device according to a result of a leak test in the method of evaluating a semiconductor device.

[0012]

A semiconductor device according to the present invention includes a semiconductor wafer, a first conductive portion and a second conductive portion formed on the semiconductor wafer, and the first and second conductive portions. At least a pair of storage node dummy electrode connecting contacts formed on a semiconductor wafer on which parts are formed
An insulating film hole and at least a pair of voltage application contact hole is provided, the storage node da
The Mie electrode connecting contact holes are formed so as to extend upward and are arranged close to each other at a predetermined interval, and one is connected to the first conductive portion and the other is connected to the second conductive portion. In addition , in the product actually produced
At least a pair of scan simulating the that storage node electrode
Storage node dummy electrode (storage node dummy
Electrode) and the voltage applying contact hole, and one of the first electrode
And a pair of voltage applying electrodes connected to the second conductive portion and the other connected to the second conductive portion.

Here, the storage node dummy electrode is a model of a storage node electrode in a product (semiconductor element) actually manufactured in a line to be managed, and the shape of the storage node dummy electrode is Usually, it has the same shape as the storage node electrode of the semiconductor element. Further, the above-mentioned predetermined interval between the storage node and the dummy electrode is set to an interval at which a leak test and evaluation can be performed, and is usually the same as or smaller than the interval between the storage node electrodes of the semiconductor element. Keep it.

The cross-sectional shape of the storage node / dummy electrode may be a bale, a cylinder, a cylinder, or a fin. Further, the first conductive portion and the second conductive portion may be formed of a wiring layer or a wiring layer and a diffusion layer formed on the semiconductor wafer, respectively.

Alternatively, a plurality of storage node dummy electrodes may be formed and these storage node dummy electrodes may be arranged in a matrix. Further, the storage nodes / dummy electrodes may be arranged in a checkered pattern. Furthermore, a protective film may be provided on the storage node / dummy electrode.

Further, the semiconductor device evaluation method according to the present invention applies a voltage to the voltage application electrode of the semiconductor device while keeping the temperature of the semiconductor device higher than that during normal use,
A stress applying step of applying a high electric field stress between the storage node and the dummy electrode of the semiconductor device, and a current between the voltage application electrodes of the semiconductor device in which a high temperature and high electric field stress is applied between the storage node and the dummy electrode. And a leak test step of performing a leak test of the semiconductor device.

Further, before the stress applying step, the leak test of the semiconductor device may be conducted by measuring the current between the voltage application electrodes of the semiconductor device.
Furthermore, before the stress applying step, a defect inspecting apparatus may detect a defect occurrence point in the semiconductor device and disconnect the connection between the conductive section including the detected section and the conductive section connected to the electrode section. Furthermore, the stress applying step and the leak test step may be repeated a plurality of times.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a step of forming a plurality of circuits having a capacitor element having a storage node electrode on a semiconductor wafer. A step of manufacturing the semiconductor device by forming a storage node dummy electrode under the same conditions as the node electrode manufacturing process, and a voltage application electrode for the semiconductor device while the temperature of the semiconductor device is higher than that during normal use. A stress applying step of applying a high electric field stress between the storage node and the dummy electrode of the semiconductor device, and a voltage of the semiconductor device in which a high temperature and high electric field stress is applied between the storage node and the dummy electrode. A leak test for the semiconductor device is performed by measuring the current between the applying electrodes. And strike step, in response to a leak test result in the leak test step and a step of evaluating the manufacturing process of the storage node electrode.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. FIG. 1 is a diagram showing the structure of the semiconductor device according to the first embodiment, and FIG. 1A is a top view showing a part of the top surface of the semiconductor device (for simplification of description, the bit line 2 is also included. Shown), FIG. 1 (b)
FIG. 2 is a sectional view taken along the line AA of the semiconductor device shown in FIG. In the figure, 1 is a wafer substrate, 2 is a bit line which is a conductive portion provided on the wafer substrate 1 for applying a potential to the storage node / dummy electrode 5, and 3 is a bit line 2.
The contact hole formed above electrically connects the bit line 2 and the storage node / dummy electrode 5 to the storage node / dummy electrode connecting contact hole and the bit line 2 and the electrode pad 6 electrically. It consists of contact holes for electrodes.

Numeral 4 designates, for example, SiO ₂ on the wafer substrate 1 and the bit line 2 in which the contact hole 3 is formed.
Insulating film made of 5 is a contact hole 3 on the insulating film 4.
The storage node dummy electrodes are formed at the upper position, and the storage node dummy electrodes are arranged in a matrix. Reference numeral 6 denotes an electrode pad formed on the insulating film 4 at a position above the contact hole 3, and this electrode pad is electrically connected to the bit line 2 through the contact hole 3.

The bit line 2 connected to the storage node dummy electrode 5 through the contact hole 3 is connected to the first bit line 2a connected to the electrode pad 6a as shown in FIG. 1 (a). The second bit line 2b is connected to another electrode pad 6b different from the electrode pad 6a. Further, the first bit line 2a and the second bit line 2b are formed such that the storage node dummy electrodes 5 in the diagonal direction of the storage node dummy electrodes 5 formed in a matrix are connected to each other, and The first bit line 2a and the second bit line 2b are formed so as to be connected every other line in the oblique direction.

Further, the storage node dummy electrode 5 has the same shape as the storage node electrode in the product manufactured in the line to be managed (for example, the cross-sectional shape is a bales, a cylinder, a cylinder, a fin). Etc., and the interval between the adjacent storage node / dummy electrodes 5 is equal to or narrower than the interval between the storage node electrodes in the product manufactured in the line to be managed. In this embodiment, the size of the storage node / dummy electrode is 0.5 μm, and the space between the adjacent storage node / dummy electrodes is 0.3 μm.

The electrode pads 6 and a plurality of storage node / dummy electrodes 5 connected to the electrode pads 6 via the bit lines 2 form one group of TEGs, and a plurality of groups are formed on the wafer substrate 1. The area where this group is formed is the area where the storage node electrode of the wafer substrate in an actual product having the same storage node electrode as the storage node dummy electrode of the semiconductor device of the present embodiment is formed. Shall be Needless to say, such a TEG can be formed on any part of the silicon substrate.

Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described. First, a conductive film is formed on a substrate 1 such as a Si wafer by using a sputtering method, a CVD method, or the like. The material used at this time may be any conductive material, but it is preferable to use the material actually used as the bit line material. For example, phosphorus-doped polysilicon, tungsten silicide, or the like is used. On this conductive film, patterning is performed in a wiring shape by photolithography, and the bit line 2 is formed by dry etching using plasma or the like. Then, a silicon dioxide film is formed thereon as an insulating layer by the CVD method or the like, and the contact hole 3 is formed by photoengraving and etching.

After that, phosphorus-doped polysilicon is deposited also by the CVD method, and the storage node dummy electrodes 5 and the electrode pads 6 in a matrix are formed by photolithography and etching. It should be noted that each of these manufacturing steps can be manufactured in the same manner as in the actual manufacturing of a semiconductor device such as a memory, except for the shape of the bit line.

Next, a method for evaluating the semiconductor device shown in FIG. 1, that is, a method for detecting a defect due to a minute defect or foreign matter between storage node electrodes, which is difficult to detect on a product, will be described. First, while keeping the wafer of the semiconductor device shown in FIG. 1 at a high temperature, the probe needles of the wafer prober are brought into contact with the electrode pads 6a and 6b, and the potential difference (V1 between the potential V1 of the electrode pad 6a and the potential V0 of the electrode pad 6b (V1 The potentials V1 and V0 such that −V0) is higher than the potential difference between the storage node electrodes when the DRAM is normally used are applied to the respective pads and held. At this time, V0 may be the ground potential. In the present embodiment, V1 is 2 to 5v, V1
0 was set to 0v.

As a result, the acceleration operation can be performed 10 times or more as compared with the product having the similar storage node electrode between the adjacent elements. By measuring the leak current between the electrode pads 6a and 6b after this acceleration operation, it becomes possible to detect a defect due to a minute defect or foreign matter between the storage node and the dummy electrode 5 which is difficult to detect on the product.

In the present embodiment, the first and second bit lines are formed of storage nodes formed in a matrix.
The dummy electrodes are formed so as to be connected to the storage nodes and the dummy electrodes in the oblique direction, and the first and second bit lines are formed to be connected to every other line in the oblique direction. However, this is not particularly limited to this connection, and it suffices that the storage node / dummy electrodes adjacent in the vertical and horizontal directions are connected to different bit lines.

For example, the first and second bit lines are formed in the row (column) direction, and the first bit lines are connected to every other storage node dummy electrode in each row (column). At the same time, the adjacent storage nodes / dummy electrodes are connected so as not to be connected to each other so that adjacent rows (columns) are shifted one by one, and the second bit lines are connected to the first bit lines. You may make it connect to each storage node dummy electrode which is not connected to the line.

In the present embodiment, the storage node dummy electrode is formed in the same shape as the storage node electrode in the memory cell of the semiconductor element, so that the defective state in the memory cell can be accurately reproduced. be able to. Further, since the TEG is provided in an arbitrary area on the wafer, the effective area can be increased,
Small variations in the process can be managed. Further, since the storage node dummy electrode and the electrode pad are connected via the bit line, the probe needle does not come into contact with the pad during the process, which causes problems such as film peeling due to probe marks and generation of foreign matter. Never.

Embodiment 2. In the first embodiment, the contact hole is formed on the bit line so that the storage node dummy electrode and the bit line are in direct electrical contact, but in a normal product process, the contact hole comes into contact with the substrate. Is formed. Also, FIG.
In the structure of the contact hole as shown in (b), the etching conditions for forming the contact hole must be optimized. Therefore, in the second embodiment, as shown in FIG. 2, impurities such as P are implanted into the surface of the LOCOS region 8 and the substrate 1 which are formed for electrically isolating the element so as to have conductivity. By forming the impurity injection layer 7, the contact hole is brought into contact with the substrate so that the contact hole has a structure similar to that of an actual product.

In the semiconductor device having such a structure, since the contact hole 3 is not directly formed on the bit line 2, the load of optimizing the above-mentioned etching condition is not required. At this time, the impurity injection layer 7 and the LOCOS region 8 can be formed under the normal product process conditions.

FIG. 2 is a cross-sectional view showing a cross section of the semiconductor device according to the second embodiment. A of the semiconductor device shown in FIG.
It is sectional drawing along A. In the figure, reference numeral 7 denotes an impurity injection layer having conductivity, which is formed by implanting impurities such as P into the surface of the wafer substrate 1, and 8 electrically isolates the impurity injection layer 7 having conductivity. LOCOS formed as
Area. Others are the same as those described in the first embodiment, and the description thereof will be omitted.

Next, a method of manufacturing the semiconductor device shown in FIG. 2 will be described. First, a silicon nitride film or the like is formed on a substrate 1 such as a Si wafer, and only a portion of the silicon nitride film forming a LOCOS region for element isolation is removed by photolithography and etching. This is heat treated in an oxidizing atmosphere to give LO
The COS region 8 is formed. Then, after removing the silicon nitride film used as the mask, impurities such as P are implanted into the entire surface of the substrate 1. After that, the bit line 2, the insulating film 4, the contact hole 3, the storage node / dummy electrode 5, and the electrode pad 6 are formed by the same method as in the first embodiment.

The present embodiment has the same effect as that described in the first embodiment, and further, since the contact hole is formed outside the bit line, the etching conditions for forming the contact hole are different. The contact hole can be formed without imposing a load on the optimization.

Embodiment 3. In the above-described first and second embodiments, the storage node dummy electrode 5 is illustrated as a flat block shape (oval shape) and a cross-sectional shape as a bale.
The shape of is preferably the same as the shape of the actual product, depending on the shape used in the actual product.

FIG. 3 is a sectional view showing the shape of the storage node / dummy electrode of the semiconductor device of the third embodiment. 3A is a storage node dummy electrode having a roughened surface, FIG. 3B is a fin-shaped storage node dummy electrode, and FIG. 3C is a cylindrical cross section. Storage node dummy electrode, Fig. 3
(D) is a diagram showing a storage node / dummy electrode having a cylindrical cross section. In the figure, 5a-d are storage node dummy electrodes. Others are the same as those described in the first embodiment, and the description thereof will be omitted.

As described above, the storage node electrode of the actual product has a different electrode shape in order to increase the electric capacity, for example, the surface is roughened, a fin structure is formed, or the central portion is formed. Even in the case where the storage node dummy electrode is formed into a hollow cylindrical shape by forming a storage node dummy electrode having the same shape as in the first embodiment.
The same effect as described above can be obtained.

Fourth Embodiment In the first to third embodiments described above, the outermost surface is the storage node / dummy electrode and the electrode pad. However, in order to prevent a short circuit due to foreign matter from the outside during acceleration operation and leak current measurement, this embodiment In the form 4, a SiO ₂ film or a polyimide film is further formed thereon as a passivation film.

FIG. 4A is a cross-sectional view showing a cross section of the semiconductor device according to the fourth embodiment, and the bit lines and the storage node / dummy electrodes are arranged in the same manner as in FIG. 1A. . In the figure, reference numeral 9 is a passivation film made of, for example, SiO ₂ or a polyimide film formed on the insulating film 4 on which the storage node dummy electrode 5 and the electrode pad 6 are formed. It is formed so as to cover and open only the electrode pad 6. Others are the same as those described in the first embodiment, and the description thereof will be omitted.

FIG. 4B is a sectional view showing a section of another semiconductor device according to the fourth embodiment, in which the bit lines and the storage node / dummy electrodes are arranged in the same manner as in FIG. 1A. And In the figure, 6 is an electrode pad formed of a metal such as aluminum formed at a position on the contact hole 10 on the passivation film 9, and 9 is formed on the insulating film 4 on which the storage node / dummy electrode 5 is formed. A passivation film made of, for example, SiO ₂ or a polyimide film is formed so as to cover the insulating film 4 and the storage node dummy electrode 5.

In order to connect the electrode pad 6 made of aluminum or the like formed on the passivation film 9 and the bit line 2, 10 is formed from the surface of the passivation film 9 through the passivation film 9 and the insulating film 4. A contact hole that reaches the surface. Others are the same as those described in the first embodiment, and the description thereof will be omitted.

In the present embodiment, in addition to the effect described in the first embodiment, the storage node / dummy electrode is covered with the passivation film, and the outermost surface is only the electrode pad. Therefore, the acceleration operation is performed. It is possible to prevent a short circuit due to foreign matter or the like from the outside world during the measurement of the inside and the leakage current.

Further, the electrode pad is not formed in the same layer as the storage node / dummy electrode, but a contact hole reaching from the surface of the passivation film to the surface of the bit line is provided in the electrode pad portion, and a metal pad such as aluminum is formed thereon. Therefore, the contact resistance when the probe needle contacts can be kept low.

Embodiment 5. In the first embodiment, the plurality of storage node dummy electrodes are formed in a matrix, but in the fifth embodiment, the plurality of storage node dummy electrodes are arranged in a checkered pattern. It is preferable to determine such a checkerboard-like arrangement according to the arrangement form of the storage node electrodes of the actual product. Note that the cross-sectional structure is similar to that described in Embodiment 1 or Embodiment 2.

In particular, in this embodiment, the number of adjacent storage node / dummy electrodes for a certain storage node / dummy electrode is 6, and the distance between each storage node / dummy electrode is equal. In the case of the first embodiment (adjacent storage nodes
As compared with the number of dummy electrodes being four), more storage nodes / dummy electrodes can be efficiently arranged.

For example, when the planar shape of the storage node / dummy electrode is a circle or a polygon which is symmetrical with respect to the direction of each adjacent storage node / dummy electrode,
By forming a grid shape formed by a diamond-shaped grid having interior angles of 60 degrees and 120 degrees, the storage node
The dummy electrodes can be arranged most efficiently.

On the contrary, for example, as shown in FIG. 5A, when it is not symmetrical with respect to the direction of each adjacent storage node / dummy electrode (in this case, the shape is an oval shape), each adjacent storage node. A storage node is formed by forming a rhombus or square lattice with the interior angles of the rhombus slightly shifted from the above 60 degrees and 120 degrees so that the intervals between the dummy electrodes are equal.
The dummy electrodes can be arranged most efficiently.

FIG. 5 is a diagram showing the structure of the semiconductor device of the fifth embodiment and the voltage applied to the electrode pad of the semiconductor device, and FIG. 5A shows the structure of the semiconductor device of the fifth embodiment. 5B is a diagram showing a voltage applied to the electrode pad of the semiconductor device shown in FIG. 5A.

In the figure, 2 is a bit line provided on the wafer substrate for applying a potential to the storage node / dummy electrode 5, and 3 is a contact hole formed on the bit line 2, and the bit line 2 and the storage node. Dummy electrode 5
And are electrically connected. Reference numeral 5 is a storage node dummy electrode formed at a position above the contact hole 3 on the insulating film, and the storage node dummy electrode is arranged in a checkered pattern. Reference numeral 6 denotes an electrode pad formed on the insulating film at a position above the contact hole 3, and the electrode pad is electrically connected to the bit line 2 through the contact hole 3.

The bit line 2 connected to the storage node / dummy electrode 5 through the contact hole 3 has a first bit line 2a connected to the electrode pad 6a, as shown in FIG. 5 (a). The second bit line 2b is connected to the electrode pad 6b, the third bit line 2c is connected to the electrode pad 6c, and the fourth bit line 2d is connected to the electrode pad 6d.

Further, six storage node dummy electrodes 5 adjacent to a certain storage node dummy electrode 5 (referred to as electrode A) are connected to electrode pads 6 different from the electrode A. More specifically, six storage node dummy electrodes 5 adjacent to the electrode A are provided.
2 of them are connected to the same electrode pad and the other 2
For example, the bit lines 2a to 2d in which storage node dummy electrodes are vertically connected are connected to every other three lines so that each set is connected to other electrode pads.
These four bit lines are connected to four different electrode pads 6
a to 6d, respectively.

Next, a method of evaluating the semiconductor device shown in FIG. 5A will be described. In the structure of the storage node / dummy electrodes arranged as shown in FIG. 5A, there are six adjacent storage node / dummy electrodes around one storage node / dummy electrode. Thus, it is difficult to give a static potential difference between all the adjacent storage node / dummy electrodes at once.

Therefore, the electrode pad 6 shown in FIG.
By setting the potentials given to a to 6d to, for example, the potential of the pattern shown in FIG. 5B, the potential difference of V1-V0 is statically provided between all the adjacent storage node / dummy electrodes 5. . However, the potential difference at this time is half of the total operation time. V at this time
0 may be ground potential.

As shown in FIG. 5A, the six storage node dummy electrodes 5 adjacent to a certain storage node dummy electrode 5 (referred to as electrode A) are electrode A.
Since it is connected to an electrode pad 6 different from
When a voltage having a pattern as shown in (b) is applied to each voltage, if the electrode pad 6 to which the electrode A is connected is, for example, the pad 6a, the voltage is applied from time t0 to time t1. A voltage difference occurs between the storage node dummy electrode 5 and the electrode A connected to the pads 6c and 6d where a voltage difference occurs with the pad 6a, and the leak current between these electrodes can be detected.

Further, the pad 6b which causes a voltage difference from the pad 6a by the voltage application from the time t1 to the time t2,
Storage node dummy electrode 5 connected to 6d
A voltage difference occurs between the electrode A and the electrode A, and the leak current between these electrodes can be detected. As described above, the leak current between the six storage node / dummy electrodes 5 adjacent to the electrode A connected to the electrodes other than the electrode A and the electrode pad 6a can be detected.

Similarly, even if the electrode pad 6 to which the electrode A is connected is another electrode pad (6b, 6c, 6d), a voltage is applied between time t0 and time t1 and from time t1. Adjacent 6 by applying voltage until time t2
The leak current between the individual storage node / dummy electrodes 5 can be detected.

As described above, by applying the voltage from time t0 to time t2, a potential difference can be applied between the electrode A and the storage node / dummy electrode 5 adjacent to this electrode A, but from time t0 to time t2. With the voltage application of
Storage node dummy electrode 5 through which voltage is applied
Since there is a storage node dummy electrode 5 to which no voltage is applied at all, and no voltage is applied to each storage node dummy electrode on average, it is difficult to perform accurate detection. Therefore, accurate detection is performed by applying a voltage pattern from time t0 to time t4 as shown in FIG. 5B, and applying an average voltage to each storage node / dummy electrode. .

In this embodiment, since the storage node dummy electrodes are formed in a checkered pattern,
In addition to the effect described in the first embodiment, it is possible to increase the number of storage node dummy electrodes that can be arranged per unit area, and further it is possible to achieve high integration.

Sixth Embodiment Also in the semiconductor device described in the fifth embodiment, as described in the second to fourth embodiments, by forming the LOCOS region and the impurity implantation layer, the storage node dummy electrode is not directly connected to the bit line. The same effect can be obtained, the shape of the storage node dummy electrode is not a flat block shape, the electrode shape is changed to increase the electric capacity, and the external environment is increased during acceleration operation and leak current measurement. A passivation film may be formed on the storage node / dummy electrode in order to prevent a short circuit due to foreign matter or the like. By doing so, Embodiments 2 to 2
The same effect as described in 4 can be obtained.

In the first to sixth embodiments, the case where the number of storage node dummy electrodes is 30 has been described as an example, but this is not particularly limited, and a larger number of storage node dummy electrodes may be used. May be formed as one block. However, even if a plurality of defects occur in one block, it is not possible to detect them separately, so it is desirable to create about 100 to 1000 blocks in the wafer.

Embodiment 7. FIG. 6 is a flow chart showing the semiconductor device evaluation method of the seventh embodiment, and shows the semiconductor device evaluation method described in the first to sixth embodiments. ST2 is a forming process step for forming the semiconductor device described in the first to sixth embodiments, ST3 is a step of applying a potential to the electrode pad 6 by the wafer prober to apply electrical stress at high temperature, and ST4 is A step of measuring a leakage current between the bit lines 2 and between the adjacent storage node / dummy electrodes 5 by measuring a current value flowing between the electrode pads 6 to detect a short circuit defect. ST5 is detected by a leakage test in ST4. The defective rate (the ratio of the number of defective blocks per wafer) is compared with a preset standard to make a determination.

Specifically, in the method of manufacturing a semiconductor element having a storage node electrode and a capacitor composed of a conductive portion corresponding to the storage node electrode, an abnormality appears periodically or after maintenance of the device. When it is easy, the wafer is loaded (ST1), and the structure described in the first to sixth embodiments is formed on the wafer (ST2). At this time, if a wafer that has been completed until just before the process of forming the storage node / dummy electrode 5 is prepared in advance and the wafer is loaded from the process of forming the storage node / dummy electrode 5, the abnormality can be detected in a shorter time. can do.

After that, the wafer is held at a high temperature by using a wafer prober, and a desired potential is applied to the electrode pad 6 for a certain period of time, or when the potential is applied in a pattern, the pattern is executed for one cycle or more ( ST
3). Since the higher the holding temperature at this time is, the higher the accelerating property is, the temperature is preferably at least about 100 ° C., and in practice, the temperature is preferably 120 to 125 ° C. In addition, the required operating time changes depending on the temperature and the potential, but if the temperature is 100 ° C or higher and the potential difference (V1-V0) is higher than the potential difference in a normal product, the insulation of the defective part is generally within a few seconds to a few minutes or less. Destruction is triggered.

After that, the value of the current flowing between the electrode pads 6 is measured to obtain the ratio (defective rate) of the blocks in which the short circuit failure has occurred (ST4). There is an abnormality in the process by comparing the obtained defect rate with the standard set from the actual values obtained by performing this evaluation when there is no abnormality in the process in advance (of course, it can be set independently without using actual results). It is determined whether or not (ST5).

If the detected defect rate is within the standard, there is no problem because the process is normal, but if it exceeds the standard, failure analysis (SEM observation or light emission analysis) of the wafer is performed to determine the cause of the abnormality. After investigating (ST6), countermeasures are taken against the abnormal device (ST7). After that, in order to see the effect of the implemented measures, a wafer is further loaded and re-evaluated, and it is confirmed that the defect rate is below the standard.

By evaluating the semiconductor device in this manner, the manufacturing process of the storage node electrode of the semiconductor element which is the actual product is evaluated. A defect between the storage node electrodes can be easily detected in a short period of time, which can be linked to an early countermeasure.

Embodiment 8. In the semiconductor device evaluation method according to the seventh embodiment, not only the defect between the storage node and the dummy electrode but also the defect in the base (for example, a short circuit between bit lines) is detected at the same time. It is difficult to detect only small defects. Therefore, in this eighth embodiment, in order to detect only the microdefects that cause the reliability failure to be detected, a leak test is performed before the step of applying electrical stress to the wafer at ST3 under high temperature. Only the blocks that are not defective are evaluated by the method described in the seventh embodiment.

FIG. 7 is a flow chart showing a method for evaluating a semiconductor device according to the eighth embodiment. In this method, a leak test between the electrode pads 6 is provided before and after the acceleration operation ST3, and the leak test 1 (ST4 is performed before the acceleration operation ST3.
1) is performed over all blocks, and a block in which a short-circuit defect is already detected is specified before accelerating the operation (ST
8) The subsequent processing is not performed on the block, and the acceleration operation (ST3) and the leak test 2 (ST42) are performed only on the block not including the short circuit defect.

The defect rate is calculated based on a block that does not include a defect before the acceleration operation, and this is defined as a new defect rate. By comparing the new defective rate with the preset standard (ST51), the process can be evaluated relatively easily. In addition, ST1 to 3, S
Regarding the operation of T6 to 7, basically FIG.
The description is omitted because it is the same as the one described above.

In this embodiment, a leak test is performed before the step of applying electrical stress to the wafer at a high temperature, so that a defect in the base (for example, short circuit between bit lines).
Can be detected, and in the subsequent evaluation step, only the detected defect due to the defective base can be evaluated, and the evaluation without the detection due to the defective base can be performed.

Ninth Embodiment In the semiconductor device evaluation method according to the eighth embodiment, blocks that already contain short circuit defects before the acceleration operation are excluded from the evaluation. Therefore, if there are many defects in the base, the number of effective blocks in the wafer will be small, and a quantitative analysis will be performed. There is a problem that evaluation becomes difficult. Therefore,
In the ninth embodiment, the position of a defect that already exists is detected by the defect inspection apparatus and the bit line 2 including the defect at the detected position is detected so that the quantitative evaluation can be performed even when there are many defects in the base. Is removed to exclude only the minimal part.

FIG. 8 is a diagram showing a flow of the semiconductor device evaluation method according to the ninth embodiment. In the present embodiment, instead of the leak test 1 (ST41) performed before the acceleration operation ST3 in the eighth embodiment, a defect inspection ST9 using a defect inspection device using laser light or visible light is performed and already exists. The position coordinates of the defect are detected (ST1
0).

Next, the bit line 2 including the detected defect in the coordinates is cut off (ST11). The cutting method includes, for example, a method of blowing off the portion of the bit line 2 immediately after branching by a laser beam, or a method of removing the same portion with a focused ion beam or electron beam. By doing so, only the minimum part can be excluded, so that the acceleration operation ST3 and the leak test ST are performed for all blocks.
It becomes possible to carry out No. 4 to judge the defect rate, and quantitative process control becomes possible. The operation of ST1 to ST7 is basically the same as that of the seventh embodiment shown in FIG.

In this embodiment, the position of a defect already existing is detected by the defect inspection apparatus, and the bit line including the defect at the detected position is cut off so that only the minimum part is excluded. Even when there are many defects in the base, quantitative evaluation can be performed without reducing the number of effective blocks in the wafer.

Embodiment 10. Even if it is said that the reliability is poor, there are various times until a short circuit is caused depending on the type of microdefect that causes the defect. Therefore, in this embodiment, by measuring the time, it is possible to estimate the importance of the influence of the defect causing the abnormality on the reliability.

FIG. 9 is a flow chart showing a method for evaluating a semiconductor device according to the tenth embodiment. In the present embodiment, the operation time of the acceleration operation ST3 is shortened, and the acceleration operation ST3 →
The loop of leak test ST4 → defective rate determination ST51 is repeated a plurality of times until the new defective rate falls below the standard. Then, the new defective rate is output for each loop, and the time between the loops is measured (ST12).

Here, the new defective rate is a defective rate obtained only by the number of defective blocks newly generated in the immediately preceding acceleration operation ST3. If the output value of the new defect rate drops sharply, defects due to the defect can be screened with a small acceleration operation.For example, by increasing the burn-in time slightly in the product device, the reliability of the product can be increased. You can get information such as The operations in ST1 to ST4 are basically the same as those in FIG. 6 of the seventh embodiment (in ST3,
This is the same except that the acceleration operation time is shortened), and the description thereof will be omitted.

In this embodiment, since the evaluation time is measured, the defect can be detected according to the time count, and the importance of the influence of the defect causing the abnormality on the reliability can be estimated. be able to.

[0080]

Since the present invention is constructed as described above, it has the following effects.

A semiconductor device according to the present invention is a semiconductor wafer, a first conductive part and a second conductive part formed on the semiconductor wafer, and a semiconductor having the first and second conductive parts formed thereon. An insulating film formed on the wafer and provided with at least a pair of storage node / dummy electrode connecting contact holes and at least a pair of voltage applying contact holes, and upward through the storage node / dummy electrode connecting contact holes. At least a pair of storage node dummy electrodes (e.g., the storage node dummy electrodes) that are formed to extend and are arranged close to each other at a predetermined interval, one of which is connected to the first conductive portion and the other of which is connected to the second conductive portion (for example, , The cross-sectional shape is a bale shape, a cylindrical shape, a cylindrical shape, or a fin shape) and upward through the voltage application contact holes. The storage node dummy electrodes adjacent to each other are formed by extending and provided with a pair of voltage applying electrodes, one of which is connected to the first conductive portion and the other of which is connected to the second conductive portion. It is possible to detect a reliability defect due to a minute defect between them, and it is possible to detect the actual defect status of the product based on this reliability defect detection.

Furthermore, the first conductive portion and the second conductive portion are
When each is formed of a wiring layer and a diffusion layer, it is possible to form a contact hole on the diffusion layer,
The contact hole can be easily formed.

When a plurality of storage node / dummy electrodes are formed and these storage node / dummy electrodes are arranged in a matrix, a leak test between the storage node / dummy electrodes can be easily performed. .

In particular, when the matrix arrangement is arranged in a checkered pattern, the storage node dummy electrodes can be highly integrated and can be adapted to the actual product.

Furthermore, when the protective film is provided on the storage node / dummy electrode, it is possible to prevent a short circuit between the storage node / dummy electrode due to foreign matter or the like from the outside.

In the semiconductor device evaluation method according to the present invention, a voltage is applied to the voltage application electrode of the semiconductor device while the temperature of the semiconductor device is higher than that during normal use, and the storage node dummy electrode of the semiconductor device is applied. A stress applying step of applying a high electric field stress between the storage node and the dummy electrode, and measuring a current between the voltage applying electrodes of the semiconductor device in which the high temperature / high electric field stress is applied between the storage node and the dummy electrode; Since it includes the leak test step of performing the leak test of (1), it is possible to detect abnormalities with respect to minute defects around the storage node electrode formation process at an early stage and take countermeasures against them.

Further, when a leak test of the semiconductor device is performed by measuring the current between the voltage applying electrodes of the semiconductor device before the stress applying step, the current between the electrodes before the stress applying step is measured. By measuring, it is possible to detect already existing defective blocks, remove them to perform an acceleration operation and leak test, and detect only defects that genuinely reduce reliability, excluding defects such as underlying defects. .

Before the stress applying step, the defect inspection device detects a defect occurrence point in the semiconductor device, and disconnects the conductive part including the detected part from the conductive part connected to the electrode part. If you do
Defects in reliability can be detected while minimizing reduction in the effective area in the silicon substrate.

Furthermore, when the stress applying process and the leak test process are repeated a plurality of times, the change in the new defect rate can be seen for each leak test, and the convergence of the occurring defects can be seen. be able to.

A method of manufacturing a semiconductor element according to the present invention is a method of manufacturing a semiconductor element, which includes a step of forming a plurality of circuits having a capacitor element having a storage node electrode on a semiconductor wafer. By forming a storage node dummy electrode under the same conditions as the manufacturing process of this storage node electrode, a step of manufacturing the semiconductor device described above, and applying a voltage to the semiconductor device while the temperature of the semiconductor device is higher than that during normal use. A stress applying step of applying a voltage to the electrode for applying a high electric field stress between the storage node and the dummy electrode of the semiconductor device,
A leak test step of performing a leak test of the semiconductor device by measuring a current between voltage application electrodes of the semiconductor device in which a high temperature / high electric field stress is applied between the storage node and the dummy electrode; Since it includes a step of evaluating the manufacturing process of the storage node electrode according to the leak test result in the test step, it is possible to find an abnormality with respect to a minute defect around the storage node electrode forming process of the semiconductor element.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

5A and 5B are a plan view and a potential pattern of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a flowchart of a semiconductor device evaluation method according to a seventh embodiment of the present invention.

FIG. 7 is a flowchart of a semiconductor device evaluation method according to an eighth embodiment of the present invention.

FIG. 8 is a flowchart of a semiconductor device evaluation method according to a ninth embodiment of the present invention.

FIG. 9 is a flowchart of a semiconductor device evaluation method according to a tenth embodiment of the present invention.

[Explanation of symbols]

1 Silicon Substrate 2 Bit Line 3 Contact Hole 4 Insulating Film 5 Storage Node / Dummy Electrode 6 Electrode Pad 7 Impurity Injection Layer 8 LO
COS region 9 Passivation film 10 Contact hole

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masakazu Hirai 2-3-3 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (56) Reference JP 9-45875 (JP, A) JP 9 -213901 (JP, A) JP-A-9-199672 (JP, A) JP-A-8-288349 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/66 H01L 21/8242 H01L 27/108

Claims (11)

(57) [Claims] 1. A semiconductor wafer, a first conductive portion and a second conductive portion formed on the semiconductor wafer, and the first conductive portion.
And a second conductive portion is formed on the semiconductor wafer formed at least one pair of storage nodes dummy electrode connecting contact hole and at least a pair of insulating film voltage applying contact hole is provided, the storage
It is formed so as to extend upward through a contact hole for connecting a dinode dummy electrode, and is arranged close to each other at a predetermined interval, and one is connected to the first conductive portion and the other is connected to the second conductive portion. Made in actual production
At least one pair of storage node dummy electrodes simulating the storage node electrodes in the product, and extending upward through the voltage application contact holes, one of which is connected to the first conductive portion and the other is connected to the first conductive portion. A semiconductor device comprising: a pair of voltage applying electrodes connected to a second conductive portion. 2. The semiconductor device according to claim 1, wherein a cross-sectional shape of the storage node dummy electrode is a bale shape, a column shape, a cylinder shape, or a fin shape. 3. The first conductive portion and the second conductive portion are respectively
3. The semiconductor device according to claim 1, which is formed of a wiring layer or a wiring layer and a diffusion layer formed on a semiconductor wafer. 4. A plurality of storage node dummy electrodes are formed, and these storage node dummy electrodes are arranged in a matrix.
The semiconductor device according to claim 1. 5. The semiconductor device according to claim 4, wherein the storage node dummy electrodes are arranged in a checkered pattern. 6. The semiconductor device according to claim 1, further comprising a protective film on the storage node dummy electrode. 7. The storage node dummy of the semiconductor device according to claim 1, wherein a voltage is applied to a voltage application electrode of the semiconductor device while the temperature of the semiconductor device is higher than that during normal use. A stress applying step of applying a high electric field stress between the electrodes and a current between the voltage applying electrodes of the semiconductor device in which a high temperature / high electric field stress is applied between the storage node dummy electrodes. And a leak test step of performing a leak test of the semiconductor device. 8. The leak test of the semiconductor device is performed by measuring the current between the voltage application electrodes of the semiconductor device before the stress applying step.
A method for evaluating a semiconductor device as described above. 9. A defect inspecting apparatus detects a defect occurrence point in a semiconductor device before a stress applying step, and disconnects a conductive section including the detected point from a conductive section connected to an electrode section. The method for evaluating a semiconductor device according to claim 7. 10. The method for evaluating a semiconductor device according to claim 7, wherein the stress applying step and the leak test step are repeated a plurality of times. 11. A method of manufacturing a semiconductor device, comprising the step of forming a plurality of circuits having a capacitor element having a storage node electrode on a semiconductor wafer under the same conditions as the manufacturing process of the storage node electrode. Strike
A step of manufacturing the semiconductor device according to claim 1 by forming a storage node dummy electrode, and for applying a voltage to the semiconductor device while keeping the temperature of the semiconductor device higher than that during normal use. Applying a voltage to the electrodes,
And stressing adding a high electric field stress between the storage node dummy electrodes of said semiconductor device, said storage
A leak test step of performing a leak test of the semiconductor device by measuring a current between the voltage application electrodes of the semiconductor device in which high temperature / high electric field stress is applied between the dinode dummy electrodes, and a leak in the leak test step. And a step of evaluating a manufacturing process of the storage node electrode according to a test result.