JP2000012633A - Semiconductor device, method of evaluation thereof, and manufacture of semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reproduce a failure situation in memory cells of a semiconductor element accurately by preparing storage-node dummy electrodes, which are similar to those of an actual product, in all areas of the wafer. SOLUTION: On a wafer substrate 1 including bit lines 2, an insulating film 4 of SiO2 is prepared, to which contact holes 3 are formed. Storage-node dummy electrodes 5 are formed in a matrix on the insulating film 4 covering contact holes 3. Similarly, electrode pads 6 are formed on the insulating film 4 covering contact holes 3, and the electrode pads 6 are connected electrically to bit lines 2 via contact holes 3. The electrode pads 6 and the storage-node dummy electrodes 5, which are connected to the electrode pads 6 via bit lines, are considered as a set of test element group, and are formed on the wafer substrate 1. By this method, it is possible to control micro-defects and foreign particles between the storage-node electrodes correctly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of evaluating the same, and a method of manufacturing a semiconductor device.
TEG (Test Element) capable of detecting foreign matter
Group), a method for evaluating the semiconductor device, and a method for manufacturing a semiconductor element.

[0002]

2. Description of the Related Art As semiconductor devices become more highly integrated, the area occupied by memory cells also continues to decrease. However, in a device having a capacitor such as a DRAM, the capacitance of the capacitor needs to secure a certain value or more in order to suppress a soft error due to α particles. In order to solve this, the shape of the storage node electrode (lower electrode) constituting the capacitor is three-dimensionally three-dimensional, and the interval therebetween is becoming extremely narrow. For this reason, the size of the defect or foreign matter that causes a current leak between the storage node electrodes has become extremely small, and it has become difficult to detect the defect or foreign matter using a laser or other light.

Conventionally, there is no effective inspection method for such minute defects and foreign matter. Even if a large amount of minute foreign matter is generated due to an abnormality of the apparatus, the damaged wafer is completed in all wafer processes. Since the abnormality cannot be detected until the dicing / assembly is performed and a reliability test after burn-in is performed, it takes several months from the occurrence of the abnormality to taking a countermeasure.

As a method for detecting such a defect or foreign matter that causes a leak failure between storage node electrodes, there is a method disclosed in Japanese Patent Application Laid-Open No. 9-45875, for example. This is because the TE on the edge of the wafer
By providing a G (Test Element Group) region, forming a wiring-like storage node dummy electrode having the same interval as that between the storage node electrodes in the memory cell therein, and measuring a leak current value therebetween. This is a method of monitoring the occurrence of leak failure.

As a method for evaluating the insulation properties in a direction parallel to the wafer, there is a method disclosed in, for example, Japanese Patent Application Laid-Open No. 9-213762. In this method, a pair of conductive patterns are formed in a comb-like form on a wafer, and the current flowing therebetween is measured to evaluate the insulation between wirings.

[0006]

In the conventional semiconductor device as described above, the shape of the storage node dummy electrode is different from that of the storage node electrode in the memory cell, and is formed in a wiring shape. There is a problem that a defective situation cannot be accurately reproduced.

In the former of the prior art, since the TEG region on the product wafer is used, the effective area is extremely small, and it is impossible to manage minute fluctuations in the process.
Since the probe needle is brought into contact with the pad in the middle of the process, probe marks may cause problems such as film peeling and foreign matter generation in the subsequent process.

Further, in the above-described method of evaluating a semiconductor device using a conventional semiconductor device, a memory device of a semiconductor element is used.
There is a problem that it is not possible to accurately reproduce the defect state in the cell, and it is not possible to correctly manage minute defects and foreign matter between storage node electrodes.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. By providing a storage node electrode pattern (storage node / dummy electrode) similar to that of an actual product on the entire surface of a wafer, a memory device of a semiconductor device is provided. An object of the present invention is to provide a semiconductor device capable of accurately reproducing a defect state in a cell.

A method of evaluating a semiconductor device capable of performing a process control around the formation of a storage node electrode by applying a stress test to the semiconductor device under a high temperature and a high electric field to perform a process control around formation of a storage node electrode and enabling quick feedback on an abnormality. Is provided.

Another object of the present invention is to provide a method of manufacturing a semiconductor device, which evaluates a process of manufacturing a storage node electrode of a semiconductor device according to a result of a leak test in the method of evaluating a semiconductor device.

[0012]

A semiconductor device according to the present invention comprises a semiconductor wafer, a first conductive part and a second conductive part formed on the semiconductor wafer, and the first and second conductive parts. An insulating film formed on a semiconductor wafer on which a portion is formed and provided with at least a pair of storage node / dummy electrode connection contact holes and at least a pair of voltage application contact holes, and the storage node / dummy electrode connection contact At least one pair of storages extending upward through holes and arranged close to each other at a predetermined interval, one of which is connected to the first conductive part and the other is connected to the second conductive part. A node / dummy electrode extending upward through the voltage application contact hole; It connected the other and a pair of voltage application electrode connected to said second conductive portion and parts.

Here, the storage node / dummy electrode simulates a storage node electrode in a product (semiconductor element) actually manufactured in a line to be managed, and the shape of the storage node / dummy electrode is , Usually have the same shape as the storage node electrode of the semiconductor element. Further, the predetermined interval between the storage node and the dummy electrode is set to an extent that a leak test and an evaluation can be performed, and is generally equal to or smaller than the interval between the storage node electrodes of the semiconductor element. Keep it.

The sectional shape of the storage node / dummy electrode may be a bale, a column, a cylinder, or a fin. Further, the first conductive portion and the second conductive portion may each be formed of a wiring layer or a wiring layer and a diffusion layer formed on a semiconductor wafer.

Further, a plurality of storage node / dummy electrodes may be formed, and these storage node / dummy electrodes may be arranged in a matrix. Further, the storage node / dummy electrodes may be arranged in a checkered pattern. Further, a protective film may be provided on the storage node / dummy electrode.

Further, in the method for evaluating a semiconductor device according to the present invention, a voltage is applied to a voltage application electrode of the semiconductor device while the temperature of the semiconductor device is higher than that in a normal use.
A stress applying step of applying a high electric field stress between the storage node and the dummy electrode of the semiconductor device, and a current between the voltage applying electrodes of the semiconductor device to which a high temperature and high electric field stress is applied between the storage node and the dummy electrode And a leak test step of performing a leak test of the semiconductor device by measuring the leakage current.

Further, before the stress applying step, a leak test of the semiconductor device may be performed by measuring a current between the voltage application electrodes of the semiconductor device.
Furthermore, before the stress applying step, the defect inspection device may detect a defect occurrence location in the semiconductor device, and disconnect the connection between the conductive portion including the detected portion and the conductive portion connected to the electrode portion. Further, the stress applying step and the leak test step may be repeated a plurality of times.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a step of forming a plurality of circuits having capacitor elements having storage node electrodes on a semiconductor wafer. Forming a storage node / dummy electrode under the same conditions as the node electrode manufacturing process, thereby manufacturing the semiconductor device; and applying a voltage to the semiconductor device while maintaining the temperature of the semiconductor device higher than in normal use. Applying a high electric field stress between the storage node and the dummy electrode of the semiconductor device, and applying a high temperature and high electric field stress between the storage node and the dummy electrode of the semiconductor device. By measuring the current between the application electrodes, a leak test for performing a leak test of the semiconductor device is performed. And strike step, in response to a leak test result in the leak test step and a step of evaluating the manufacturing process of the storage node electrode.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a view showing the structure of the semiconductor device of the first embodiment. FIG. 1A is a top view showing a part of the upper surface of the semiconductor device (for simplicity, the bit line 2 is also included). Shown), FIG. 1 (b)
FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. In the figure, 1 is a wafer substrate, 2 is a bit line which is a conductive portion provided on the wafer substrate 1 and applies a potential to the storage node / dummy electrode 5, and 3 is a bit line 2
The contact hole formed above connects the bit line 2 and the storage node / dummy electrode 5 electrically, and the storage node / dummy electrode connection contact hole and the bit line 2 and the electrode pad 6 are electrically connected. It consists of a contact hole for an electrode.

Reference numeral 4 denotes, for example, SiO ₂ formed on the wafer substrate 1 and the bit lines 2 and formed with the contact holes 3.
5 is a contact hole on insulating film 4
The storage node / dummy electrode formed at the upper position is arranged in a matrix. Reference numeral 6 denotes an electrode pad formed at a position on the contact hole 3 on the insulating film 4, and the electrode pad is electrically connected to the bit line 2 via the contact hole 3.

As shown in FIG. 1A, the bit line 2 connected to the storage node / dummy electrode 5 via the contact hole 3 is connected to the first bit line 2a connected to the electrode pad 6a. The second bit line 2b is connected to another electrode pad 6b different from the electrode pad 6a. Further, the first bit line 2a and the second bit line 2b are formed such that the storage node / dummy electrode 5 in the oblique direction of each storage node / dummy electrode 5 formed in a matrix is connected. The first bit lines 2a and the second bit lines 2b are formed so as to be connected alternately in the oblique direction.

The storage node / dummy electrode 5 has the same shape as that of a storage node electrode in a product manufactured in a line to be managed (for example, the cross-sectional shape is a bale shape, a column shape, a cylindrical shape, a fin shape). Etc.), and the distance between adjacent storage node / dummy electrodes 5 is set to be equal to or smaller than the distance between storage node electrodes in a product manufactured on a line to be managed. In the present embodiment, the size of the storage node / dummy electrode is 0.5 μm, and the interval between adjacent storage node / dummy electrodes is 0.3 μm.

The electrode pads 6 and a plurality of storage node / dummy electrodes 5 connected to the electrode pads 6 via the bit lines 2 form a group of TEGs, and a plurality of groups are formed on the wafer substrate 1. The area where this group is formed is the area where the storage node electrode of the wafer substrate is formed in the actual product having the same storage node electrode as the storage node / dummy electrode of the semiconductor device of the present embodiment. Shall be Needless to say, such a TEG can be formed at an arbitrary portion on the silicon substrate.

Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described. First, a conductive film is formed on a substrate 1 such as a Si wafer by using a sputtering method, a CVD method, or the like. Any material may be used as long as it is conductive, but it is preferable to use the material actually used as the bit line material. For example, polysilicon or tungsten silicide doped with phosphorus is used. The conductive film is patterned into a wiring shape by photolithography, and the bit line 2 is formed by dry etching using plasma or the like. Then, a silicon dioxide film is formed thereon as an insulating layer by a CVD method or the like, and a contact hole 3 is formed by photolithography and etching.

Thereafter, phosphorus-doped polysilicon is also deposited by the CVD method, and the storage node dummy electrodes 5 and the electrode pads 6 are formed in a matrix by photolithography and etching. Each of these manufacturing steps can be manufactured in the same manner as actually manufacturing a semiconductor device such as a memory, except for the shape of the bit line.

Next, a method for evaluating the semiconductor device shown in FIG. 1, that is, a method for detecting a defect due to a minute defect or foreign matter between storage node electrodes which is difficult to detect on a product will be described. First, the probe needle of the wafer prober is brought into contact with the electrode pads 6a and 6b while keeping the wafer of the semiconductor device shown in FIG. 1 at a high temperature, and the potential difference (V1) between the potential V1 of the electrode pad 6a and the potential V0 of the electrode pad 6b is reached. −V0) are applied to and held at the respective pads so that the potentials V1 and V0 are higher than the potential difference between the storage node electrodes when the normal DRAM is used. At this time, V0 may be a ground potential. In the present embodiment, V1 is set to 2 to 5 V,
0 was set to 0v.

As a result, the acceleration operation can be performed ten times or more as compared with a product having a similar storage node electrode between adjacent elements. By measuring the leak current between the electrode pads 6a and 6b after this acceleration operation, it is possible to detect a defect due to a minute defect or foreign matter between the storage node and the dummy electrode 5 which is difficult to detect on a product.

In the present embodiment, the first and second bit lines are connected to each storage node
The storage node / dummy electrode in the oblique direction of the dummy electrode is formed so as to be connected, and the first and second bit lines are formed so as to be connected alternately in the oblique direction. However, this is not particularly limited to this connection, as long as storage node / dummy electrodes adjacent in the vertical and horizontal directions are connected to different bit lines.

For example, the first and second bit lines are formed in the row (column) direction, and the first bit lines are connected so that every other storage node / dummy electrode in each row (column) is connected. In addition, adjacent storage node / dummy electrodes are not connected to each other, and are connected to adjacent rows (columns) so as to be shifted one by one, and the second bit line is connected to the first bit. It may be connected to each storage node / dummy electrode not connected to the line.

In the present embodiment, the shape of the storage node dummy electrode is formed in the same shape as the storage node electrode in the memory cell in the semiconductor element, so that the defect state in the memory cell can be accurately reproduced. be able to. Furthermore, since the TEG is provided in an arbitrary region on the wafer, the effective area can be increased,
It is possible to manage minute fluctuations in the process. Also, since the storage node / dummy electrode and the electrode pad are connected via the bit line, the probe needle does not contact the pad during the process, causing problems such as film peeling and foreign matter generation due to the probe mark. Nothing.

Embodiment 2 In the first embodiment, the contact hole is formed on the bit line so that the storage node / dummy electrode and the bit line are in direct electrical contact. However, in a normal product process, this contact hole contacts the substrate. It is formed as follows. FIG.
In the structure of the contact hole as shown in (b), the etching conditions for forming the contact hole must be optimized. Therefore, in the second embodiment, as shown in FIG. 2, impurities such as P are implanted into the LOCOS region 8 and the surface of the substrate 1 which are formed for electrically isolating the elements, thereby providing conductivity. The contact hole is brought into contact with the substrate by forming the doped impurity layer 7 so that the contact hole has a structure similar to that of an actual product.

In the semiconductor device configured as described above, since the contact hole 3 is not directly formed on the bit line 2, the load of optimizing the above-mentioned etching conditions is not required. At this time, formation of the impurity implantation layer 7 and the LOCOS region 8 can be performed under normal product process conditions.

FIG. 2 is a sectional view showing a section of the semiconductor device of the second embodiment.
It is sectional drawing along A. In the figure, reference numeral 7 denotes an impurity-implanted layer formed by injecting impurities such as P into the surface of the wafer substrate 1 and 8 electrically separates the impurity-implanted layer 7 having conductivity. LOCOS formed like
Area. The other parts are the same as those described in the first embodiment, and a description thereof will be omitted.

Next, a method of manufacturing the semiconductor device shown in FIG. 2 will be described. First, a silicon nitride film or the like is formed on a substrate 1 such as a Si wafer, and only a portion of the silicon nitride film where a LOCOS region for element isolation is to be formed is removed by photolithography and etching. This is heat-treated in an oxidizing atmosphere,
The COS region 8 is formed. Then, after removing the silicon nitride film used as the mask, an impurity such as P is implanted into the entire surface of the substrate 1. After that, the bit line 2, the insulating film 4, the contact hole 3, the storage node / dummy electrode 5, and the electrode pad 6 are formed in the same manner as in the first embodiment.

In the present embodiment, the same effect as that described in the first embodiment is obtained, and the contact hole is formed outside the bit line. A contact hole can be formed without imposing a load on optimization.

Embodiment 3 In the first and second embodiments, the planar shape of the storage node / dummy electrode 5 is shown as a flat block shape (oval shape) and the cross-sectional shape is shown as a bale shape.
Is desirably the same shape as the actual product according to the shape used for the actual product.

FIG. 3 is a sectional view showing the shape of the storage node / dummy electrode of the semiconductor device according to the third embodiment. 3A is a storage node dummy electrode having a surface roughened, FIG. 3B is a storage node dummy electrode having a fin-shaped cross section, and FIG. 3C is a cylindrical cross section. Storage node dummy electrode, Fig. 3
(D) is a diagram showing a storage node dummy electrode having a columnar cross section. In the figure, reference numerals 5a to 5d denote storage node dummy electrodes. Other features are the same as those described in the first embodiment, and thus description thereof will be omitted.

As described above, the storage node electrode of an actual product is obtained by changing the shape of the electrode in order to increase the electric capacity, for example, the surface is roughened, the fin structure is formed, or the center portion is formed. In the case where the storage node / dummy electrode is formed in a similar shape even when the storage node / dummy electrode is formed into a cylindrical shape, the first embodiment can be used.
The same effects as described in the above are obtained.

Embodiment 4 In the first to third embodiments, the outermost surface is the storage node / dummy electrode and the electrode pad. However, in order to prevent a short circuit due to foreign matter from the outside during the acceleration operation and the leak current measurement, the present embodiment In the form 4, a SiO ₂ film or a polyimide film is further formed thereon as a passivation film.

FIG. 4A is a cross-sectional view showing a cross section of the semiconductor device according to the fourth embodiment. The arrangement of bit lines and storage node / dummy electrodes is the same as that of FIG. 1A. . In the figure, reference numeral 9 denotes a passivation film made of, for example, SiO ₂ or a polyimide film formed on the insulating film 4 on which the storage node dummy electrode 5 and the electrode pad 6 are formed, and the insulating film 4 and the storage node dummy electrode 5 are formed. The cover is formed so that only the electrode pad 6 is open. The other parts are the same as those described in the first embodiment, and a description thereof will be omitted.

FIG. 4B is a cross-sectional view showing a cross section of another semiconductor device of the fourth embodiment. The arrangement of bit lines and storage node / dummy electrodes is the same as that of FIG. 1A. And In the drawing, reference numeral 6 denotes an electrode pad formed at a position on the contact hole 10 on the passivation film 9 and made of, for example, a metal such as aluminum. Reference numeral 9 denotes an electrode pad formed on the insulating film 4 on which the storage node / dummy electrode 5 is formed. The passivation film made of, for example, SiO ₂ or a polyimide film is formed so as to cover the insulating film 4 and the storage node dummy electrode 5.

Reference numeral 10 denotes a connection between the bit line 2 and the electrode pad 6 made of aluminum or the like formed on the passivation film 9, from the surface of the passivation film 9 via the passivation film 9 and the insulating film 4. This is a contact hole reaching the surface. The other parts are the same as those described in the first embodiment, and a description thereof will be omitted.

In the present embodiment, in addition to the effect described in the first embodiment, since the storage node / dummy electrode is covered with the passivation film and the outermost surface is formed only of the electrode pad, the acceleration operation is performed. It is possible to prevent a short circuit due to a foreign substance or the like from the outside during the middle and the leak current measurement.

Also, the electrode pad is not formed on the same layer as the storage node / dummy electrode, and a contact hole is formed in the electrode pad from the surface of the passivation film to the surface of the bit line, and a metal pad such as aluminum is formed thereon. As a result, the contact resistance when the probe needle comes into contact can be kept low.

Embodiment 5 FIG. In the first embodiment, a plurality of storage node / dummy electrodes are formed in a matrix. In the fifth embodiment, a plurality of storage node / dummy electrodes are arranged in a checkered pattern. It is preferable that such a checkered arrangement is determined according to the arrangement form of the storage node electrodes of the actual product. Note that the cross-sectional structure is the same as that described in Embodiment 1 or 2.

In particular, in this embodiment, the number of storage node / dummy electrodes adjacent to a certain storage node / dummy electrode is 6, and the distance between each storage node / dummy electrode is equal. In the case of Embodiment 1 (adjacent storage nodes
(The number of dummy electrodes is four), so that more storage node / dummy electrodes can be efficiently arranged.

For example, when the planar shape of the storage node / dummy electrode is a circle or polygon which is symmetric with respect to the direction of each adjacent storage node / dummy electrode,
By making the lattice shape formed by the lattice of the rhombic shape having the inner angles of 60 degrees and 120 degrees, the storage node
Dummy electrodes can be arranged most efficiently.

Conversely, for example, as shown in FIG. 5 (a), when not symmetrical with respect to the direction of each adjacent storage node / dummy electrode (in this case, the shape is an oval shape), each adjacent storage node A storage node is formed by forming a diamond-shaped or square-shaped lattice in which the inner angles of the diamond are slightly shifted from the above-mentioned 60 degrees and 120 degrees so that the intervals between the dummy electrodes are equidistant.
Dummy electrodes can be arranged most efficiently.

FIG. 5 shows the structure of the semiconductor device of the fifth embodiment and the voltage applied to the electrode pads of the semiconductor device. FIG. 5 (a) shows the structure of the semiconductor device of the fifth embodiment. FIG. 5B is a diagram showing a voltage applied to the electrode pad of the semiconductor device shown in FIG. 5A.

In the figure, reference numeral 2 denotes a bit line provided on the wafer substrate for applying a potential to the storage node / dummy electrode 5, and 3 denotes a contact hole formed on the bit line 2, and the bit line 2 and the storage node. Dummy electrode 5
Are electrically connected to each other. Reference numeral 5 denotes a storage node / dummy electrode formed at a position on the contact hole 3 on the insulating film. The storage node / dummy electrode is arranged in a checkered pattern. Reference numeral 6 denotes an electrode pad formed at a position on the contact hole 3 on the insulating film. This electrode pad is electrically connected to the bit line 2 via the contact hole 3.

As shown in FIG. 5A, the bit line 2 connected to the storage node / dummy electrode 5 via the contact hole 3 is connected to the first bit line 2a connected to the electrode pad 6a. The second bit line 2b is connected to the electrode pad 6b, the third bit line 2c is connected to the electrode pad 6c, and the fourth bit line 2d is connected to the electrode pad 6d.

Further, six storage node / dummy electrodes 5 adjacent to a certain storage node / dummy electrode 5 (referred to as an electrode A) are connected to an electrode pad 6 different from the electrode A. More specifically, six storage node dummy electrodes 5 adjacent to electrode A
Are connected to the same electrode pad, and the other two
For example, every three bit lines 2a to 2d vertically connected to storage node / dummy electrodes are connected so that each set is connected to another electrode pad,
These four bit lines are connected to four different electrode pads 6 respectively.
a to 6d.

Next, a method for evaluating the semiconductor device shown in FIG. In the structure of the storage node / dummy electrode arranged as shown in FIG. 5A, there are six storage node / dummy electrodes adjacent to one storage node / dummy electrode. Thus, it is difficult to provide a static potential difference between all adjacent storage node / dummy electrodes at once.

Therefore, the electrode pad 6 shown in FIG.
By setting the potentials given to a to 6d to potentials in a pattern as shown in FIG. 5B, a potential difference of V1−V0 is statically given between all adjacent storage node / dummy electrodes 5. . However, at this time, the potential difference is applied for half of the total operation time. V at this time
0 may be a ground potential.

As shown in FIG. 5A, six storage node / dummy electrodes 5 adjacent to a certain storage node / dummy electrode 5 (referred to as an electrode A) are connected to the electrode A.
5 is connected to the electrode pad 6 which is different from FIG.
When a voltage having a pattern as shown in FIG. 3B is applied to each voltage, if the electrode pad 6 to which the electrode A is connected is, for example, the pad 6a, the voltage is applied from time t0 to time t1. A voltage difference is generated between the electrode A and the storage node / dummy electrode 5 connected to the pads 6c and 6d where a voltage difference occurs with the pad 6a, and a leak current between these electrodes can be detected.

Further, a voltage difference between the pad 6a and the pad 6a due to the voltage application from the time t1 to the time t2,
Storage node / dummy electrode 5 connected to 6d
And a voltage difference is generated between the electrodes A, and a leak current between these electrodes can be detected. As described above, it is possible to detect the leak current between the six storage node / dummy electrodes 5 adjacent to the electrode A connected to other than the electrode A and the electrode pad 6a.

Similarly, even if the electrode pad 6 to which the electrode A is connected is another electrode pad (6b, 6c, 6d), the voltage is applied between the time t0 and the time t1, and By applying the voltage until time t2, the adjacent 6
The leak current between the storage node and the dummy electrode 5 can be detected.

As described above, by applying the voltage from time t0 to time t2, a potential difference can be applied between the electrode A and the storage node / dummy electrode 5 adjacent to the electrode A, but from time t0 to time t2. In the voltage application of
Storage node dummy electrode 5 through which voltage is applied
And the storage node / dummy electrode 5 to which no voltage is applied is present, and since no voltage is applied to each storage node / dummy electrode on average, it is difficult to perform accurate detection. Therefore, by applying a voltage pattern from time t0 to time t4 as shown in FIG. 5B and applying an average voltage to each storage node / dummy electrode, accurate detection is performed. .

In this embodiment, since the storage node / dummy electrodes are formed in a checkered pattern,
In addition to the effects described in the first embodiment, the number of storage node / dummy electrodes that can be arranged per unit area can be increased, and higher integration can be achieved.

Embodiment 6 FIG. Also in the semiconductor device described in the fifth embodiment, as described in the second to fourth embodiments, the storage node / dummy electrode is not directly connected to the bit line by forming the LOCOS region and the impurity implantation layer. The same effect is obtained, the shape of the storage node / dummy electrode is not a flat block shape, but the electrode shape is changed in order to increase the electric capacity. A passivation film may be formed on the storage node / dummy electrode in order to prevent a short circuit due to foreign matter or the like from the outside. By doing so, Embodiment 2
The same effect as that described in 4 can be obtained.

In the first to sixth embodiments, the case where the number of the storage node / dummy electrodes is 30 has been described as an example. However, the present invention is not limited to this, and the number of the storage node / dummy electrodes may be larger. May be formed as one block. However, even if a plurality of defects occur in one block, they cannot be separated and detected. Therefore, it is desirable to create about 100 to 1000 blocks in a wafer.

Embodiment 7 FIG. 6 is a flowchart showing a method for evaluating a semiconductor device according to the seventh embodiment, and shows the method for evaluating a semiconductor device described in the first to sixth embodiments. ST2 is a process for forming the semiconductor device described in the first to sixth embodiments, ST3 is a process for applying an electric potential to the above-described electrode pad 6 by a wafer prober and applying an electric stress at a high temperature, and ST4 is a process for applying the same. A step of measuring a leak current between the bit lines 2 and between the adjacent storage node / dummy electrodes 5 by measuring a current value flowing between the electrode pads 6 to detect a short-circuit failure. ST5 is detected by a leak test in ST4. This is a step of comparing the defective rate (the ratio of the number of defective blocks per wafer) with a preset standard to make a determination.

The procedure will be specifically described. In a method of manufacturing a semiconductor device having a storage node electrode and a capacitor formed of a conductive portion corresponding to the storage node electrode, an abnormality appears periodically or after maintenance of the device. A wafer is loaded when it is easy (ST1), and the structure described in the first to sixth embodiments is formed on the wafer (ST2). At this time, a wafer completed up to immediately before the process of forming the storage node / dummy electrode 5 is prepared in advance, and if a wafer is inserted from the process of forming the storage node / dummy electrode 5, an abnormality can be detected in a shorter time. can do.

Thereafter, the wafer is held at a high temperature using a wafer prober, and a desired potential is applied to the electrode pad 6 and held for a certain period of time, or when the potential is applied in a pattern, the pattern is performed for one or more cycles ( ST
3). At this time, the higher the holding temperature is, the higher the acceleration property is, so that at least about 100 ° C. or more is desirable. Actually, it is preferable to perform the temperature at 120 to 125 ° C. The required operating time varies depending on the temperature and the potential. When the temperature is 100 ° C. or higher and the potential difference (V1−V0) is higher than the potential difference of the normal product, the insulation of the defective portion is generally performed in a few seconds to a few minutes or less. Destruction is caused.

Thereafter, the value of the current flowing between the electrode pads 6 is measured, and the ratio of blocks in which a short-circuit failure has occurred (failure rate) is determined (ST4). When there is no abnormality in the process by comparing the obtained defect rate with the standard set from the actual value obtained by performing this evaluation in advance when there is no abnormality in the process (it is no problem to set it independently without using the actual result) It is determined whether or not (ST5).

If the detected defect rate is within the standard, there is no problem because there is no abnormality in the process, but if it exceeds the standard, a failure analysis (SEM observation or light emission analysis) of the wafer is performed to find the cause of the abnormality. Investigation is performed (ST6), and countermeasures are taken for an abnormal device or the like (ST7). After that, in order to see the effect of the implemented countermeasures, further wafers are loaded and re-evaluated to confirm that the defect rate is below the standard.

By evaluating the semiconductor device according to such a procedure, the manufacturing process of the storage node electrode of the semiconductor element, which is an actual product, is evaluated. A defect between the storage node electrodes can be easily detected in a short period of time, and can be linked to an early measure.

Embodiment 8 FIG. In the method of evaluating a semiconductor device according to the seventh embodiment, not only a defect between a storage node and a dummy electrode but also a defect of a base (for example, a short circuit between bit lines) is simultaneously detected. It is difficult to detect only small defects. Therefore, in the eighth embodiment, a leak test is performed before the step of applying an electrical stress to the wafer at a high temperature in ST3 in order to detect only a minute defect which becomes a defect of reliability to be detected. Only the blocks that are not defective are evaluated by the method described in the seventh embodiment.

FIG. 7 is a flowchart showing a method for evaluating a semiconductor device according to the eighth embodiment. In this method, a leak test between the electrode pads 6 is provided before and after performing the acceleration operation ST3, and a leak test 1 (ST4) is performed before the acceleration operation ST3.
Step 1) is performed for all blocks, and a block in which a short-circuit failure is already detected before the acceleration operation is performed (ST)
8) The subsequent operation is not performed on the block, and the acceleration operation (ST3) and the leak test 2 (ST42) are performed only on the block not including the short-circuit failure.

The calculation of the defect rate is performed based on a block containing no defect before the acceleration operation, and this is defined as a new defect rate. By comparing the new defect rate with a preset standard (ST51), the process can be relatively easily evaluated. In addition, ST1-3, S
The operation in T6 to T7 is basically the same as that in FIG.
The description is omitted because it is the same as that of FIG.

In this embodiment, before the step of applying an electrical stress to the wafer at a high temperature, a leak test is performed to detect a defect in the base (for example, a short circuit between bit lines).
Can be detected, and in the subsequent evaluation step, only the detected ones resulting from the removal of the base defect can be evaluated, and the evaluation can be performed without detection of the base failure.

Embodiment 9 FIG. In the method of evaluating a semiconductor device according to the eighth embodiment, blocks that already include a short-circuit failure before the acceleration operation are excluded from the evaluation. Therefore, when there are many base failures, the number of effective blocks in the wafer decreases, and the quantitative There is a problem that evaluation becomes difficult. Therefore,
In the ninth embodiment, the defect inspection apparatus detects the position of an existing defect so that a quantitative evaluation can be performed even in the case where there are many defects on the base, and the bit line 2 including the defect at the detected position is detected. Is removed to remove only the minimum site.

FIG. 8 is a diagram showing a flow of a semiconductor device evaluation method according to the ninth embodiment. In the present embodiment, instead of the leak test 1 (ST41) performed before the acceleration operation ST3 in the eighth embodiment, a defect inspection ST9 using a defect inspection device using laser light or visible light is performed, and the defect inspection already exists. The position coordinates of the defect are detected (ST1).
0).

Next, the bit line 2 containing the defect of the detected coordinates is cut off (ST11). As a method of cutting, for example, there is a method of blowing off a portion of the bit line 2 immediately after branching with a laser beam, or a method of removing the same portion with a focused ion beam or electron beam. By doing so, since only the minimum part can be excluded, the acceleration operation ST3 and the leak test ST
4 can be performed to determine the defect rate, and quantitative process management can be performed. Note that the operations in ST1 to ST7 are basically the same as those in FIG. 6 of the seventh embodiment, and a description thereof will be omitted.

In this embodiment, the defect inspection apparatus detects the position of an existing defect, and cuts off the bit line including the defect at the detected position to exclude only the minimum part. Even when the number of defects of the base is large, quantitative evaluation can be performed without reducing the number of effective blocks in the wafer.

Embodiment 10 FIG. Even if it is simply referred to as a poor reliability, there are various times until a short circuit is caused depending on the kind of minute defect that causes the defect. Therefore, in the present embodiment, by measuring the time, it is possible to estimate the importance of the influence of the defect causing the abnormality on the reliability.

FIG. 9 is a flowchart showing a method for evaluating a semiconductor device according to the tenth embodiment. In the present embodiment, the operation time of the acceleration operation ST3 is shortened, and the acceleration operation ST3 →
The loop from the leak test ST4 to the failure rate determination ST51 is repeated a plurality of times until the new failure rate falls below the standard. Then, a new defect rate is output for each loop and the time between loops is measured (ST12).

Here, the new defect rate is a defect rate obtained only from the number of defective blocks newly generated in the immediately preceding acceleration operation ST3. If the output value of the new defect rate drops sharply, the defect due to the defect can be screened with a small acceleration operation.For example, by increasing the burn-in time slightly in the product device, the reliability of the product can be increased. Can be obtained. The operations in ST1 to ST4 are basically the same as those in FIG. 6 of the seventh embodiment (in ST3,
The same is true except that the acceleration operation time is shortened), and a description thereof will be omitted.

In the present embodiment, since the evaluation time is measured, the defect can be detected according to the time measured, and the importance of the influence of the defect causing the abnormality on the reliability is estimated. be able to.

[0080]

Since the present invention is configured as described above, it has the following effects.

A semiconductor device according to the present invention includes a semiconductor wafer, a first conductive portion and a second conductive portion formed on the semiconductor wafer, and a semiconductor device on which the first and second conductive portions are formed. An insulating film formed on the wafer and provided with at least one pair of storage node / dummy electrode connection contact holes and at least one pair of voltage application contact holes, and upward through the storage node / dummy electrode connection contact holes; At least one pair of storage node dummy electrodes (e.g., one connected to the first conductive part and the other connected to the second conductive part) are formed to extend and are arranged close to each other at a predetermined interval. , The cross-sectional shape is a bale shape, a column shape, a cylindrical shape, or a fin shape). The storage node / dummy electrode adjacent to the storage node / dummy electrode, the pair of storage node / dummy electrodes being formed so as to extend and have one pair connected to the first conductive part and the other connected to the second conductive part. It is possible to detect a reliability defect due to a minute defect in between, and it is possible to detect a defect state of an actual product based on the reliability defect detection.

Further, the first conductive part and the second conductive part are
When each is formed of a wiring layer and a diffusion layer, a contact hole can be formed on the diffusion layer.
A contact hole can be easily formed.

When a plurality of storage node / dummy electrodes are formed and these storage node / dummy electrodes are arranged in a matrix, a leak test between the storage node / dummy electrodes can be easily performed. .

In particular, when the matrix arrangement is a checkerboard arrangement, the storage node / dummy electrodes can be further highly integrated, and can be adapted to an actual product.

Further, when a protective film is provided on the storage node / dummy electrode, it is possible to prevent a short circuit between the storage node / dummy electrode due to foreign matter or the like from the outside.

In the method for evaluating a semiconductor device according to the present invention, a voltage is applied to a voltage application electrode of the semiconductor device while the temperature of the semiconductor device is higher than that in a normal use, and a storage node / dummy electrode of the semiconductor device is applied. A stress applying step of applying a high electric field stress therebetween, and measuring a current between voltage applying electrodes of the semiconductor device to which a high temperature and high electric field stress is applied between the storage node and the dummy electrode, thereby obtaining the semiconductor device. And a leak test step of performing a leak test of the storage node electrode. Therefore, it is possible to detect an abnormality with respect to a minute defect around the storage node electrode forming process at an early stage and to take measures against the defect.

Further, by measuring the current between the voltage applying electrodes of the semiconductor device before the stress applying step, when a leak test of the semiconductor device is performed, the current between the electrodes before the stress applying step is reduced. By the measurement, it is possible to detect the existing defective blocks, remove them, perform the acceleration operation and the leak test, and detect only the defects that purely lower the reliability except for the defects of the base. .

Prior to the stress applying step, a defect inspection device detects a defect occurrence portion in the semiconductor device, and disconnects the conductive portion including the detected portion from the conductive portion connected to the electrode portion. If you do
It is possible to detect the reliability failure while minimizing the decrease in the effective area in the silicon substrate.

Further, when the stress applying step and the leak test step are repeated a plurality of times, the change in the new defect rate for each leak test can be seen, and the convergence of the occurring defects can be seen. be able to.

The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including the step of forming a plurality of circuits having capacitor elements having storage node electrodes on a semiconductor wafer, Forming the storage node / dummy electrode under the same conditions as the manufacturing process of the storage node electrode, thereby manufacturing the semiconductor device, and applying a voltage to the semiconductor device while maintaining the temperature of the semiconductor device higher than in normal use. Applying a voltage to the electrode for the application, a stress applying step of applying a high electric field stress between the storage node dummy electrode of the semiconductor device,
A leak test step of performing a leak test of the semiconductor device by measuring a current between the voltage application electrodes of the semiconductor device to which a high temperature / high electric field stress is applied between the storage node and the dummy electrode; Evaluating the manufacturing process of the storage node electrode according to the result of the leak test in the test process. Therefore, it is possible to find an abnormality with respect to a minute defect around the storage node electrode forming process of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a sectional view of a semiconductor device according to a third embodiment of the present invention;

FIG. 4 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 5 is a plan view and a diagram showing a potential pattern of a semiconductor device according to a fifth embodiment of the present invention;

FIG. 6 is a flowchart of a semiconductor device evaluation method according to a seventh embodiment of the present invention.

FIG. 7 is a flowchart of a semiconductor device evaluation method according to an eighth embodiment of the present invention.

FIG. 8 is a flowchart of a method for evaluating a semiconductor device according to a ninth embodiment of the present invention;

FIG. 9 is a flowchart of a semiconductor device evaluation method according to a tenth embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 silicon substrate 2 bit line 3 contact hole 4 insulating film 5 storage node / dummy electrode 6 electrode pad 7 impurity injection layer 8 LO
COS region 9 Passivation film 10 Contact hole

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Shigeru Shiratake, 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (72) Inventor Masakazu Hirai 2-3-2, Marunouchi, Chiyoda-ku, Tokyo Rishi Electric Co., Ltd. F term (reference) 4M106 AA07 AB15 AB17 AD01 AD05 AD09 BA14 CA04 CA31 CA38 CA41 DH02 DH44 DJ39 5F083 AD00 LA01 LA21 MA06 MA18 ZA20 ZA28 ZA29

Claims (11)

[Claims] A first conductive portion and a second conductive portion formed on the semiconductor wafer, wherein the first conductive portion and the second conductive portion are formed on the semiconductor wafer;
An insulating film formed on the semiconductor wafer on which the second conductive portion is formed and provided with at least one pair of storage node / dummy electrode connection contact holes and at least one pair of voltage application contact holes; Extending upward through a contact hole for connecting a dummy electrode, and arranged close to each other at a predetermined interval, one of which is connected to the first conductive portion;
At least one pair of storage node / dummy electrodes connected to the second conductive portion is formed to extend upward through the voltage application contact hole, and one of the storage node / dummy electrodes is connected to the first conductive portion. A semiconductor device comprising: a pair of voltage application electrodes connected to each other and the other to the second conductive portion. 2. The semiconductor device according to claim 1, wherein the cross-sectional shape of the storage node / dummy electrode is a bale shape, a column shape, a cylindrical shape, or a fin shape. 3. The first conductive portion and the second conductive portion each include:
3. The semiconductor device according to claim 1, wherein the semiconductor device is formed of a wiring layer or a wiring layer and a diffusion layer formed on a semiconductor wafer. 4. The storage node / dummy electrode is formed in a plurality, and the storage node / dummy electrodes are arranged in a matrix.
The semiconductor device according to any one of claims 1 to 3. 5. The semiconductor device according to claim 4, wherein the storage node / dummy electrodes are arranged in a checkered pattern. 6. The storage node / dummy electrode further comprising a protective film on the dummy electrode.
13. The semiconductor device according to claim 1. 7. A voltage is applied to a voltage application electrode of the semiconductor device while the temperature of the semiconductor device according to any one of claims 1 to 6 is higher than that in normal use, and a voltage is applied to a storage node of the semiconductor device. A stress applying step of applying a high electric field stress between the dummy electrodes, and measuring a current between the voltage applying electrodes of the semiconductor device in which a high temperature and high electric field stress is applied between the storage node and the dummy electrode, A method of evaluating a semiconductor device, comprising: a leak test step of performing a leak test of the semiconductor device. 8. A leak test of the semiconductor device is performed by measuring a current between voltage application electrodes of the semiconductor device before the stress applying step.
The evaluation method of the semiconductor device described in the above. 9. A method according to claim 1, wherein before the stress applying step, a defect inspection device detects a defect occurrence portion in the semiconductor device and disconnects a conductive portion including the detected portion from a conductive portion connected to the electrode portion. 8. The method for evaluating a semiconductor device according to claim 7, wherein 10. The method for evaluating a semiconductor device according to claim 7, wherein a stress applying step and a leak test step are repeated a plurality of times. 11. A method of manufacturing a semiconductor device including a step of forming a plurality of circuits including a capacitor element having a storage node electrode on a semiconductor wafer under the same conditions as the manufacturing process of the storage node electrode. 7. A step of manufacturing the semiconductor device according to claim 1 by forming a storage node / dummy electrode, and applying a voltage to the semiconductor device while keeping the temperature of the semiconductor device higher than in normal use. Voltage to the electrode for
A stress applying step of applying a high electric field stress between the storage node and the dummy electrode of the semiconductor device, and a current between the voltage applying electrodes of the semiconductor device to which a high temperature and high electric field stress is applied between the storage node and the dummy electrode A leak test step of performing a leak test of the semiconductor device, and a step of evaluating a manufacturing process of the storage node electrode according to a leak test result in the leak test step. Semiconductor device manufacturing method.