JPS622701B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generally relates to large-scale semiconductor integrated circuits (hereinafter referred to as LSI), and more specifically relates to a method for realizing a full-slice LSI.

Conventionally, the following three methods have been proposed to realize LSI, and method (A) is practically used.

(A) Fixed wiring method (B) Arbitrary wiring method (C) Terminal relocation method In method (A), the wiring pattern for connecting each element included in an LSI is fixed, so An LSI can be obtained as a non-defective product only if all the elements included in the LSI are non-defective. That is, it is required that the yield is 100% within a predetermined area on a wafer necessary to construct a certain LSI. For this reason, the scale of an LSI that can be realized using method (A) is usually limited to, for example, an area of 5 mm x 5 mm and a number of gates of several thousand gates.

On the other hand, in method (B), as shown in Figure 1, after wafer diffusion processing, intra-cell wiring using a fixed pattern is completed in the first layer wiring for a unit cell (for example, one gate) that constitutes an LSI. In this state, electrical characteristics are inspected, and the wiring pattern between unit cells is arbitrarily changed for each wafer using second and third layer wiring according to the location of non-defective cells, and LSI is realized. The details are described in the following documents.

Proceedings of I.E.E.
Proceedings, of IEEE, November 1967, No. 55
J. W. Lathrop et al., "Arbitrary Wiring Systems Using Semiconductor Array Manufacturing and Design Automation," Vol., No. 11, pp. 1988-1997. The feature of method (B) is that the wiring between cells is arbitrarily changed depending on the location of the defective cell on the wafer.
Even if the yield is not so good, it is a so-called full slice LSI that is much larger than the method (A).
The goal is to be able to achieve this. However, the same variety
It has the disadvantage of requiring a large number of complicated wiring patterns in the second and third layers required for LSI.

On the other hand, in method (C), as shown in Figure 2, after wafer diffusion processing, wiring within the unit cell using a fixed pattern, and inspection of the unit cell, extra defective cells are created in advance. Replace it with a good cell. That is, a "terminal relocation wiring" is created to connect the terminal of a defective cell and an extra good cell, and complicated inter-cell wiring is performed using a fixed pattern. Therefore, the wiring that needs to be changed depending on the position of the defective cell is simple and requires only a small amount of "terminal relocation wiring" patterns, so compared to the arbitrary wiring method in (B) above,
It becomes easy to realize full slice LSI. Details of method (C) are described in the following literature.

"Terminals for connecting imperfect yield LSI arrays" by D.F. Calhoun in 1969 Bros. of F.G.C. (Proc, FJCC), pp. 99-109. Relocation Technique”.

As is well known, the smaller the area of the unit cell, the better the yield, and it is desirable to make the unit cell as small as possible when using the method (B) or (C). However, when providing a test pad for testing electrical characteristics in a unit cell as in the past, the test pad has a considerable size (e.g.
50μ×50μ), it has been difficult to realize an LSI constructed using small unit cells using methods (B) or (C).

The first object of the present invention is to test the electrical characteristics of a sufficiently small unit cell and to use a good cell.
The object of the present invention is to provide a method in which a test pad is provided in a separate wiring layer and the test pad is removed after measuring electrical characteristics in order to configure an LSI.

In addition, as explained earlier, when configuring an LSI using the method (B) or (C) above, the yield will be low in the process after completing the inspection of the unit cell in FIG. 1 or 2. High is desirable. According to the conventional technology, wafers that fail in the interconnection process between unit cells have to be discarded. A second object of the present invention is to provide a method for reprocessing a wafer when an error occurs in the wiring process between unit cells.

Furthermore, when configuring an LSI using the methods (B) and (C) above, the following points are important for improving economic efficiency. In other words, the focus of the method (C) is to "reduce the number of patterns that need to be changed for each wafer as much as possible." A third object of the invention is to provide a good method for achieving this.

A first feature of the method for manufacturing a large-scale semiconductor integrated circuit of the present invention is that a test pad is provided on the intra-cell wiring layer and is electrically connected to a required portion of the wiring layer through an insulating layer. The purpose of this is to conduct an electrical test on the cell by contacting the probe with the probe, and then remove the test pad.

Furthermore, in the present invention, in-cell wiring is formed using a hard and highly corrosion-resistant first metal such as tantalum, tungsten, titanium, platinum, etc. in both the (B) method and (C) method, and A test pad for a unit cell that is electrically connected to a required part of the cell wiring through an insulating layer is formed using a second metal that is soft and has low corrosion resistance, such as aluminum, and the test pad is used to After the electrical test of the cell is carried out, the test pad is etched away using an etchant which does not corrode or hardly corrodes the first metal and easily corrodes the second metal.

Furthermore, in the method (C), the terminal relocation wiring for electrically replacing a defective cell with an extra good cell is made of the above-mentioned first metal, and the inter-cell wiring is made of the same metal as the second metal. If there is an error or defect in the intercell wiring, remove the intercell wiring layer by etching as described above, and reconnect the intercell wiring using a second metal or another metal. Another feature is that it forms.

Each feature of the present invention described above provides the following effects.

(1) By using a test pad, it is possible to conduct electrical tests on the unit cell without increasing the area of the unit cell, and the small area of the unit cell improves the degree of integration and yield. do. (2) The first method is to make the wiring inside the cell hard and highly corrosion resistant.
By constructing the test pad with a second metal that is soft and has low corrosion resistance, the pressure of the probe and the Since the test pad is soft, it can absorb the impact, while the wiring layer inside the cell is hard, so it is mechanically stable without being deformed. Furthermore, when removing the test pad by etching, since the wiring layer has high corrosion resistance, only the test pad with low corrosion resistance is etched away without being affected by the etchant, making it easy to remove the test pad. be able to. (3) By forming the terminal relocation wiring with the first metal and the wiring between unit cells with the second metal, if there is an error in the wiring between the cells, an etching liquid can be used to make the wiring resistant to corrosion. The second metal, which has low corrosion resistance, can
It becomes possible to easily remove only the inter-cell wiring made of metal and perform wiring again, and it is possible to reduce waste of wafers.

Next, specific examples of the present invention will be described.

Referring to FIGS. 3 to 8, a method for constructing a large-scale integrated circuit using a three-input TTL gate as a unit cell shown in an equivalent circuit in FIG. 9 is shown in the order of main manufacturing steps. In the figure, X and Y are cells scheduled to be used, and Z is a spare cell. First, a load resistance element 11, a gate transistor element 12, and an inverter transistor element 13 are formed on a semiconductor substrate 10 using well-known integrated circuit manufacturing technology, and a layer for taking out electrode terminals is formed on an insulating coating 20 covering the surface of the substrate. An opening 30 and an opening 31 leading directly to the board for taking out the ground terminal are provided, and platinum silicide 40 is then formed in the opening for the purpose of obtaining good ohmic contact (Fig. 3A, B). Next, using a fixed pattern mask, an in-cell electrode wiring path 14 made of a tantalum thin film with a thickness of 0.2 microns is formed (FIGS. 4A and 4B).

In this case, it is preferable to use a so-called peeling method. That is, a photo resist is applied to the surface of the substrate, the photo resist is selectively removed, a tantalum thin film is deposited on the entire surface, and then a photo resist is applied.
Perform resist removal processing. Through this process, the tantalum thin film deposited on the photoresist is removed together with the photoresist, leaving only the tantalum thin film deposited directly on the substrate surface to form a wiring path. Next, a silicon dioxide film 21 with a thickness of 0.5 microns is deposited on the entire surface of the substrate including the electrode wiring path by a well-known vapor phase growth method, and openings 32 reaching the electrode wiring path 14 are provided at desired portions (fifth Figure A,
B). Next, a 2 micron thick aluminum thin film is deposited on the substrate surface, and test pads 15 are formed by selective etching (FIGS. 6A and 6B). Here, the test pad is connected to the input/output terminal and the power supply terminal of the TTL gate through the opening 31 and the electrode wiring path 14, respectively, while the semiconductor substrate 10 is connected through the opening 31 and the electrode wiring path 14 to the input/output terminal and the power terminal of the TTL gate.
Because it is connected to the ground terminal of the TTL gate,
By connecting a probe to the test pad and the semiconductor substrate, the electrical characteristics of each cell can be measured and its acceptability can be determined. At this time, the test pad is made of soft aluminum, and the insulating film and electrode wiring path beneath it are made of hard material, so the pressure caused by the probe connection is absorbed by the aluminum, and the insulating film and electrode wiring path are will not damage. After determining the quality of the unit cell, the test pad is removed. In this case, it is preferable to use a phosphoric acid solution at 80°C. Since the phosphoric acid solution dissolves aluminum but not silicon dioxide and tantalum, the test pad can be easily removed without damaging the insulating film 21 and the wiring path 14. Next, a terminal relocation wiring path 16 made of a tantalum thin film having a thickness of 0.2 microns is formed by the peeling method described above (FIGS. 7A and 7B). At this time, based on the quality information of the unit cells, an alternative wiring pattern is specially created and used to replace a defective cell that was scheduled to be used with a good spare cell.
In the present embodiment shown in FIGS. 7A and 7B, since X of the cells X and Y scheduled for use was defective, it was replaced with a spare cell Z of good quality. Next, an insulating film 22 having a thickness of 0.5 microns is applied to the surface of the substrate including the wiring path 16, and an opening 33 reaching the wiring path 16 is provided at a predetermined position (FIGS. 8A and 8B). Through the above manufacturing process, a semiconductor substrate was obtained in which electrode terminals connected to non-defective cells were arranged at all planned positions. Finally, inter-cell wiring is applied in a fixed pattern on the thus obtained semiconductor substrate to complete a large-scale integrated circuit. Aluminum is preferably used for inter-cell wiring. If a defect occurs in the inter-cell wiring, by using the phosphoric acid solution, only the inter-cell wiring can be safely and easily removed and regenerated.

[Brief explanation of the drawing]

FIG. 1 is a process diagram showing the manufacturing procedure of the arbitrary wiring method, FIG. 2 is a process diagram showing the manufacturing procedure of the terminal relocation wiring method, and FIGS. 3 to 8 are manufacturing steps of a large-scale semiconductor integrated circuit according to the present invention. FIG. 2 is a diagram showing each step for explaining the method, and FIG. A is a plan view, and FIG. B is a cross-sectional view taken along the α-α' plane in each FIG. A. FIG. 9 is a circuit diagram showing the TTL basic cell used in the example of FIG. 3, and FIG. 10 is a plan view showing another example of how test pads of the unit cell are provided. The symbols in the figure are: 10: semiconductor substrate, 11: load resistance element, 12: gate transistor element, 1
3: Inverter transistor element, 14: Electrode wiring path, 15: Test pad, 16: Wiring path,
20, 21, 22: Insulating film (silicon dioxide),
30, 31, 32, 33: opening part, 50, 51,
52: Inter-cell wiring terminal, 53, 54: Cell terminal, 55: Terminal relocation wiring pattern, 56: Separation pattern, 57: Silicon substrate, 58: Silicon dioxide, 59, 60: Photo resist.

Claims (1)

[Claims] 1. Form inter-element connection wiring made of a first metal on a semiconductor substrate on which a plurality of circuit elements are formed via a first insulating layer, connect to a predetermined portion of the inter-element connection wiring, and remove by etching. A test pad whose etching liquid is made of a second metal different from the first metal is formed on the inter-element connection wiring via a second insulating layer, and an electrical test is performed using the test pad. A method for manufacturing a large-scale semiconductor integrated circuit device, comprising the step of subsequently removing the test pad.