JP3442872B2 - BTL output circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BTL (balanced transformerless) output circuit, and relates to a technique effective when used for one formed by one semiconductor integrated circuit.

[0002]

2. Description of the Related Art In an audio amplifier circuit mounted on an automobile, there is a strong demand for a high output specification, but since the power source is taken from 12V of an on-vehicle battery, an ordinary power amplifier circuit must obtain a sufficiently high output. I can't. Therefore, as shown in FIG. 3, the two output circuits are BTL-connected to drive the speaker SP. One output circuit 1 is made into a push-pull configuration by a normal Darlington circuit 2 and an inverted Darlington circuit 3. By using such Darlington circuits 2 and 3, a large amplitude range can be secured with a large current amplification factor. Regarding such an inverted Darlington circuit, there is, for example, "Transistor Technology Special" No. 18, page 12 to page 29, issued on November 1, 1989 by CQ Publishing Company.

[0003]

In the above audio amplifier, the snubber circuit 4 consisting of a small resistor and a capacitor having good high frequency characteristics is connected because oscillation easily occurs in the high frequency region. In such an oscillation prevention measure by the snubber circuit 4, it is necessary to increase the capacitance value of the capacitor to some extent in order to reliably prevent the oscillation operation, and since it cannot be built in the semiconductor integrated circuit, it must be an external component. I don't get it.

An object of the present invention is to provide a linear amplification operation BTL output circuit which itself has an oscillation preventing function. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, input signals of mutually opposite phases are supplied to the inputs of two output circuits in which a normal Darlington circuit and an inverted Darlington circuit are push-pull connected, and a load is connected between both output terminals. In the output circuit, a correction current corresponding to the input signal or the current flowing in the output transistor on the other output circuit side is formed while the current is flowing on the inverted Darlington circuit side in one output circuit, and the one output The input voltage and the output voltage of the circuit are made to flow through the level shift loop circuit.

[0006]

According to the above means, when the load is pull-driven by the inverted Darlington circuit,
A bias voltage corresponding to the correction current is also applied to the push-side output transistor and its output impedance can be kept low, so the loop gain of the inverted Darlington circuit is suppressed even at high frequencies, and oscillation occurs. It can be avoided.

[0007]

1 is a circuit diagram of an embodiment of a BTL output circuit according to the present invention. Each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor manufacturing technique together with an amplifier circuit provided in a preceding stage as described later.

The BTL output circuit is composed of two output circuits 1 and 1'having the same structure as each other. The two output circuits 1 and 1'are supplied with input signals Vin and Vin 'which are in opposite phase to each other. The output signals Vout and Vout 'obtained from the output circuits 1 and 1'are the speaker S
Supplied to P.

One output circuit 1 comprises a normal Darlington circuit 2 for push-driving the speaker SP, an inverted Darlington circuit 3 for pull-driving, and a correction current circuit 6 for preventing oscillation. The other output circuit 1'is also composed of a similar circuit, but in the same drawing, the circuit forming the output transistors Q7 'and Q1' and the correction current circuit 6'is shown as a representative.

The normal Darlington circuit 2 for push-driving the speaker SP is composed of NPN transistors Q6 and Q7. The input signal Vin is level-shifted and supplied to the base of the transistor Q6 through the diodes D1 and D2. The diodes D1 and D2
Is supplied with a bias current from the constant current source I3.

The inverted Darlington circuit 3 for pull-driving the speaker SP is a PNP transistor Q.
2 and NPN transistor Q1. The input signal Vin is supplied to the base of the transistor Q2. A level shift loop circuit is provided to equalize the output voltage Vout and the input signal Vin, in other words, to allow an idling current to flow through the Darlington circuits 2 and 3. The level shift loop circuit is configured to include the transistor Q2. That is, the emitter of the transistor Q2 is connected to the emitter of the NPN transistor Q3, the bias current flows from the constant current source I1 to the base of the transistor Q3, and the collector is connected to the power supply voltage VCC. A diode-shaped NPN transistor Q4 and a PNP transistor Q5 are provided between the base of the transistor Q3 and the output terminal.

In such an output circuit, the inventors of the present application have found that oscillation occurs due to the following causes. When the pull-driving transistor Q1 in the output circuit 1 is flowing a large current, a relatively large base current required for flowing the large current flows between the bases and emitters of the transistors Q2 and Q3. The base-emitter voltage is increased. Therefore, when the input signal Vin is used as a reference, the bias voltage applied to the normal Darlington circuit 2 which is push-driven corresponding to the base-emitter voltage of the transistors Q2 and Q3 is reduced by that amount. That is,
By the base current corresponding to the large output current flowing through the output transistor Q1, the bases of the transistors Q2 and Q3,
The output voltage Vout increases by the amount of the increase in the voltage between the emitters, causing the output transistors Q6 and Q7 to be in the off state or the high impedance state.

At this time, in the pull-driving output transistor Q1, the resistance parasitic on the emitter becomes small because a large current flows, and the impedance on the collector side becomes large due to the cutoff of the output transistor Q7, resulting in a large voltage gain. To have. For this reason, when the phase of the feedback signal fed back through the level shift loop circulates in the high frequency region, the voltage gain becomes too large and the oscillation operation described above occurs.

In this embodiment, a correction current circuit 6 is provided in order to prevent the above oscillation operation. The correction current circuit 6 is used to prevent oscillation of the other output circuit 1'by the correction current. Therefore, the correction current for preventing the above-described oscillation operation of the output circuit 1 is formed by the correction current circuit 6'provided in the output circuit 1 '.

The correction current circuit 6 is composed of the following circuits. The input signal Vin is level-shifted by the diode D4 and supplied to the base of the NPN transistor Q9. A bias current is made to flow through the diode D4 by the constant current source I3. The transistor Q9
A bias voltage V1 corresponding to the output midpoint voltage is applied to the emitter of the resistor via the resistor R1. Although not particularly limited, the output midpoint voltage V1 is set to half the power supply voltage VCC.

As a result, the input signal Vin becomes the midpoint voltage V1.
The difference voltage (Vin-V1) when the voltage is higher than
A current corresponding to flows into the resistor R1. This current is made to flow to the level shift loop circuit of the output circuit 1'by the current mirror circuit composed of the diode D3 and the PNP transistor Q8 provided in the collector of the transistor Q9. This corresponds to the correction current formed by the same correction current circuit of the output circuit 1 ′ flowing through the diodes Q4 and Q5 of the level shift loop circuit of the output circuit 1.

When the output transistor Q1 of the output circuit 1 is pull-driven by a large current, the input signal Vin corresponding thereto is in a voltage region lower than the midpoint voltage V1. At this time, since the input signal Vin 'of the other output circuit 1'has a voltage higher than the midpoint voltage V1, the correction current circuit 6'of the output circuit 1'has the input signal Vin' and the midpoint voltage V1. A correction current corresponding to the difference voltage from V1 is formed and is supplied to the diodes Q4 and Q5 of the level shift loop circuit.

That is, even if a relatively large base current corresponding to the pull drive by the large current of the output transistor Q1 flows through the transistors Q2 and Q3, a correction current flows through the diodes Q4 and Q5 so as to correct it. Therefore, a sufficient bias voltage can be secured in the normal Darlington circuit 2 that performs push driving, and the transistors Q6 and Q7 continue to flow the idling current. In other words, since the transistor Q7 maintains the operating state, its output impedance can be kept small. Therefore, even if the resistance parasitic on the emitter is small because the pull-driving output transistor Q1 flows a large current, the collector side impedance is low due to the operating state of the output transistor Q7, and thus only a small voltage gain is obtained. Since it does not exist, the feedback gain in the level shift loop is also small, and oscillation can be prevented.

FIG. 2 shows a circuit diagram of another embodiment of the BTL output circuit according to the present invention. The correction current circuit 7 of this embodiment utilizes the base current flowing through the output transistor. Since the circuits other than the correction current circuits 7 and 7'are the same as the circuit of the embodiment shown in FIG. 1, the description thereof is omitted.

A constant current source I6 is provided at the emitter of the transistor Q6 constituting the normal Darlington circuit. Similarly, a transistor Q10 and a constant current source I4 are provided. Transistors Q6 and Q1 when there is no signal
The emitter potential of 0 is set to the same potential.

The emitter potentials of the transistors Q10 and Q6 are supplied to the bases of the differential transistors Q15 and Q16 which perform the voltage comparison operation. A constant current source I5 is provided at the emitters of these differential transistors Q15 and Q16. The PNP transistors Q11, Q12 and Q13 are connected to the collectors of the differential transistors Q15 and Q16.
And a current mirror circuit of Q14 is provided. The output current of the current mirror circuit corresponding to the differential transistor Q16 is supplied as the input current of the current mirror circuit composed of NPN transistors Q18 and Q17. The output current of the current mirror circuit corresponding to the other differential transistor Q15 flows through the output transistor Q17 of the current mirror circuit. That is, the transistor Q1
A current signal corresponding to the potential difference between the transistors Q15 and Q16 is made to flow through the collector of No. 7.

In the correction current circuit of this embodiment, when a large output current flows through the push-driving transistor Q7, a relatively large base current corresponding thereto flows through the transistor Q6, so that the base-emitter voltage of the transistor Q6 is reduced. We are taking advantage of growing. Due to the increase in the base-emitter voltage of the transistor Q6, the base potential of the differential transistor Q16 decreases with respect to the base potential of the differential transistor Q15, and the constant current I5 is distributed corresponding to the difference voltage. The difference current is output as a difference current from the collector of the transistor Q17.

That is, when a large current for push driving is flowing in the normal Darlington circuit of the output circuit 1, a large output current flows in the pull driving transistor Q1 'in the other output circuit 1', and as described above. One condition for oscillating operation is satisfied. At this time, the correction current on the side of the output circuit 1 increases and flows into the level shift loop circuit as described above to secure the bias voltage of the output transistor Q7 for push driving of the output circuit 1'and to reduce the idling current. To flush. For this reason, the output impedance becomes small, and thus the voltage gain required for the oscillation operation becomes large even if the emitter parasitic resistance of the output transistor Q1 ′, which is one of the factors of the oscillation operation, becomes small as described above. No oscillation occurs because there is no

On the contrary, when a large current for push driving is flowing in the normal Darlington circuit of the output circuit 1 ', the output driving circuit 1 has a pull driving transistor Q1.
A large output current flows through the output circuit 1 and one condition for the oscillation operation is satisfied as described above. However, the correction current of the output circuit 1 ′ flows through the diodes Q4 and Q5 of the level shift loop circuit, and the output circuit 1 Output transistor Q for push drive
The bias voltage of 6 and Q7 is secured to allow the idling current to flow. For this reason, the output impedance becomes small, and thus the voltage gain necessary for the oscillation operation may become large even if the emitter parasitic resistance of the output transistor Q1 which is one of the factors of the oscillation operation becomes small as described above. There is no oscillation so no oscillation occurs.

The correction current need not be a current that accurately corresponds to the increase in the base current of the pull-driving output transistor. That is, when the correction current is slightly larger than the base current, the idling current on the push drive side correspondingly increases, and the reactive current only slightly increases.

FIG. 4 shows a block diagram of an embodiment of a 4-channel BTL amplifier circuit to which the present invention is applied. Each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In the semiconductor integrated circuit device IC, the same B
TL amplifier circuit is channel CH1 to channel CH
4 circuits are provided like 4. One circuit is composed of the drive amplifier circuit DA, the output circuit 1 and the output circuit 1'as described above. The drive amplifier circuit DA voltage-amplifies the input signal vin and forms input signals Vin and Vin ′ having mutually opposite phases. Specifically, it is composed of a differential amplifier circuit that performs voltage amplification corresponding to each output circuit 1 and 1 ′, and its feedback input is fed through a feedback circuit for gain setting to output voltages Vout and Vou.
t 'is returned respectively. Then, a first stage circuit for supplying a signal in phase with the input signal vin of the differential amplifier circuit and a signal in phase opposite thereto is provided.

In the BTL amplifier circuit of this embodiment, a snubber circuit for preventing oscillation is unnecessary at the output terminal, and the number of external parts can be reduced. Therefore, when used as an audio amplifier mounted on a car, it is possible to reduce the size and cost.

The functions and effects obtained from the above-mentioned embodiment are as follows. That is, (1) Input signals of opposite phases are supplied to the inputs of two output circuits in which a normal Darlington circuit and an inverted Darlington circuit are push-pull connected, and a load is connected between both output terminals. In the BTL output circuit configured as described above, a correction current corresponding to an input signal or a current flowing in an output transistor on the other output circuit side is formed while the current is flowing on the inverted Darlington circuit side in one output circuit, and The input voltage and output voltage of one of the output circuits are made to flow to the level shift loop circuit which makes them equal. With this configuration, when the load is pulled by the inverted Darlington circuit, the bias voltage corresponding to the correction current is also applied to the push-side output transistor, and its output impedance can be kept low. Also with respect to the frequency, there is an effect that the loop gain of the inverted Darlington circuit is suppressed and oscillation can be prevented.

(2) In the above (1), the two output circuits forming the BTL circuit prevent oscillation by the correction currents formed by the other circuits, so that the oscillation prevention circuit is not desirable. It is possible to obtain the effect that a stable operation can be performed without causing another oscillation operation and causing another oscillation operation.

(3) The above (1) eliminates the need for a snubber circuit for preventing oscillation and reduces the number of external parts, so that the size and cost of the device can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, BT
The circuit that forms the input signals Vin and Vin ′ that are out of phase with each other and are supplied to the inputs of the two output circuits that form the L output circuit can take various embodiments. The present invention can be widely used as a BTL output circuit.

[0033]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, input signals of mutually opposite phases are supplied to the inputs of two output circuits in which a normal Darlington circuit and an inverted Darlington circuit are push-pull connected, and a load is connected between both output terminals. In the output circuit, a correction current corresponding to the input signal or the current flowing in the output transistor on the other output circuit side is formed while the current on the inverted Darlington circuit side is flowing in one output circuit, and the one output The input voltage and the output voltage of the circuit are made to flow through the level shift loop circuit. With this configuration, when the load is pulled by the inverted Darlington circuit, a bias voltage corresponding to the correction current is also applied to the push-side output transistor and its output impedance can be kept low. Also with respect to the frequency, the loop gain of the inverted Darlington circuit can be suppressed and oscillation can be prevented.

In the above, the BTL circuit is composed of 2
In one output circuit, oscillation is prevented by the correction current formed by the other circuit, so the oscillation prevention circuit does not act undesirably and does not cause another oscillation operation. Can be done.

As described above, the snubber circuit for preventing oscillation is unnecessary and the number of external parts is reduced, so that the device can be downsized and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a BTL output circuit according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the BTL output circuit according to the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional BTL output circuit.

FIG. 4 is a block diagram showing an embodiment of a 4-channel BTL amplifier circuit to which the present invention is applied.

[Explanation of symbols]

1, 1 '... Output circuit, 2 ... Normal Darlington circuit, 3 ... Inverted Darlington circuit, 4 ... Snubber circuit, 6-7' ... Correction current circuit, Q1-Q18 '...
Transistors, I1 to I6 '... Constant current sources, D1 to D4'
… Diode, SP… Speaker, DA… Drive amplifier circuit.

Front page continuation (72) Inventor Masanori Ionaka 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (56) References JP-A-60-199205 (JP, A) JP-A 56-116313 (JP, A) JP-A-63-266906 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03F 1/00-3/72

Claims (3)

(57) [Claims] 1. A first output transistor of the first conductivity type on the power supply voltage side, in which an input signal is level-shifted corresponding to the voltage between the base and the emitter and supplied to the base, and the first output transistor. A second output transistor on the ground potential side of a circuit of the same first conductivity type and connected in series, and the input signal are supplied to the base, and the collector output thereof is transmitted to the base of the second output transistor. A drive transistor of a second conductivity type, an emitter of the drive transistor, and a series connection point of the first and second output transistors are connected, and the input voltage and the output voltage of the drive transistor including the base and the emitter are equal. And a level shift loop circuit that generates a current corresponding to the difference voltage when the input signal is increased in absolute value with respect to the output midpoint voltage. Comprising at least two first and second output circuits each including a correction current circuit, the first and second output circuits are supplied with input signals of opposite phases to connect a load between both output terminals. , The correction current of the first output circuit is passed through the level shift loop circuit of the second output circuit, and the correction current of the second output circuit is passed through the level shift loop circuit of the first output circuit. A BTL output circuit characterized by the above. 2. A first-conductivity-type first output transistor on the side of a power supply voltage in which an input signal is level-shifted corresponding to the voltage between the base and the emitter and supplied to the base, and the first output transistor. A second output transistor on the ground potential side of a circuit of the same first conductivity type and connected in series, and the input signal are supplied to the base, and the collector output thereof is transmitted to the base of the second output transistor. A drive transistor of the second conductivity type, an emitter of the drive transistor, and a series connection point of the first and second output transistors are connected, and the input voltage and the output voltage of the drive transistor including the base and the emitter are equal. Level shift loop circuit and a correction for detecting an increase in the base current of the first output transistor and forming a correction current corresponding thereto A first output circuit and a second output circuit each including a current circuit, the first and second output circuits are supplied with input signals having opposite phases to each other, and a load is connected between the two output terminals. The correction current of the first output circuit is passed through the level shift loop circuit of the second output circuit, and the correction current of the second output circuit is passed through the level shift loop circuit of the first output circuit. A BTL output circuit characterized by the following. 3. The first and second output circuits are formed in one semiconductor integrated circuit device together with an amplifier circuit which forms input signals having mutually opposite phases supplied to respective inputs. The BTL output circuit according to claim 1 or 2.