JPS6123851Y2 - - Google Patents

Description

[Detailed explanation of the invention] This invention relates to a SEPP (single-ended buttress) type power amplifier circuit using transistors connected in a complementary symmetrical manner. This invention relates to a so-called non-cutoff power amplifier circuit that performs highly efficient amplification similar to push-pull operation, and has a bias circuit designed so that the transistor in the power amplifier stage will not be cut off at any time regardless of the polarity or amplitude of the input signal.

Class B or AB class SEPP circuits are often used as transistor power amplifier circuits in the audio field due to their high efficiency. As is well known, in a class B or class AB SEPP circuit, there is a period in which one of the two push-pull transistors is cut off in response to the positive and negative half waves of the input signal.
And due to this cut-off period,
Especially at high frequencies, switching distortion occurs due to the carrier accumulation effect at the moment the transistor turns on and off, and because waveform synthesis of positive and negative half waves occurs due to push-pull in the rise region of the transistor, so-called crossover distortion is likely to occur. There is a problem.

Recently, various circuits called non-cutoff power amplifier circuits have been proposed in order to reduce the above-mentioned switching distortion and crossover distortion without losing the basic feature of high efficiency of class B or AB operation. . This type of circuit is based on class B or class AB push-pull operation, in which two transistors that operate in push-pull mode share and amplify approximately the positive half-wave and negative half-wave of the input signal, respectively.
The bias is changed in response to the input signal so that when a positive half wave is input, the transistor responsible for the negative half wave is not cut off, and when a negative half wave is input, the transistor responsible for the positive half wave is not cut off. It is something. If the cut-off of the transistor in the power amplification stage is thus prevented, the above-mentioned switching distortion and crossover distortion can be significantly reduced.

Fig. 1 shows a typical example of a known non-cutoff power amplifier circuit. The operation of this circuit is simply explained by the positive and negative power supplies +Vcc and -Vcc.
When no signal is present, constant voltage bias circuits E1, E'1 provide power to the power amplifier stage transistors _Q1 , _Q2 through diodes D1, D3, and constant voltage circuits E2, E2' provide power to the power amplifier stage transistors _Q1 , _Q2 through diodes D2, D3, and constant voltage bias circuits E1, E'1 provide power to the power amplifier stage transistors Q1, Q2 through diodes _D2 , _D3 , and constant voltage circuits E2, E2' provide power to the power amplifier stage transistors Q1, Q2 through diodes _D2 , D3, and constant voltage bias ... ₃ , E3' provide power to the power amplifier stage transistors Q3, _Q4 .
A constant bias current is supplied via _D4 , and both transistors _Q1 and _Q2 are balanced, so that no current flows through the load P _L connected to the output terminal OUT. When a positive half-wave input signal is applied to the input terminal IN, this signal is transmitted via diode _D1 to _{transistor Q1} , where it is amplified.
On the other hand, the diode _D3 is reverse biased by the positive half-wave input signal and cuts off, and the base current of the transistor _Q2 does not flow through this diode _D3 .
Due to the circuit consisting of _E'2 , diode _D4 and resistor _R2 , a constant base current flows through transistor _Q2 and it is not cut off. That is, _P4
The voltage at point E' is forcibly fixed by the constant voltage circuit _E'2 , and in the case of a positive half-wave input signal, the diode
_The constant voltage circuit _E'2 is set so that a forward voltage is applied to _D4 , turning _it on. Therefore, the transistor _Q2
Since the voltage between _P3 and _P4 is kept constant due to the forward voltage drop of the diode _D4 , the base current of the transistor _Q2 is constant. At this time, the diode _D2 is reverse biased and cut off. Next, the input terminal
When a negative half-wave input signal is applied to IN, diodes _D1 and _D4 are cut off and diodes _D2 and _D3 are turned on. The input signal is amplified by transistor _Q2 via diode D2. Due to the action of constant voltage circuit _E2 , _a constant base current is supplied to transistor _Q1 through resistor _R1 and diode _D2 , so that it is not cut off.

In the conventional circuit as described above, not only constant voltage bias circuits E ₁ and E′ ₁ but also constant voltage circuits E ₂ and
Since E′ ₂ is also a factor that determines the bias of transistors Q ₁ and Q ₂ , temperature compensation for stabilizing the bias is performed by constant voltage bias circuits E ₁ and E′ ₁ as well as constant voltage circuits E ₂ and E′ ₂ is also required separately. Therefore, not only the elements that make up the constant voltage bias circuits E ₁ and E' ₁ but also the elements that make up the constant voltage circuits E ₂ and E' ₂ need to be thermally coupled to the final stage transistor of the power amplification stage. However, there were drawbacks such as a very complicated configuration not only in terms of circuits but also in terms of mounting structure.

This invention was made against the above background, and the power amplification circuit according to this invention has a drive stage that drives both transistors of the power amplification stage, which is superimposed on the output of the constant voltage bias circuit. a first transistor that amplifies an input signal and applies it to the power amplification stage; a low-pass filter circuit that smooths the input signal superimposed on the output of the constant voltage bias circuit and outputs only a DC bias component; A second transistor amplifies the output of the circuit and applies it to the power amplification stage. Regardless of the polarity and amplitude of the input signal, the bias current supplied through the second transistor powers the power amplification stage. This prevents the transistor from being cut off, making it possible to realize a circuit with high efficiency and low switching distortion and crossover distortion with a simple configuration.

Hereinafter, an embodiment of this invention will be described in detail based on FIGS. 2 and 3.

In Figure 2, the power amplification stage is connected to the positive power supply +Vcc
npn connected in a complementary symmetrical manner between
This is a SEPP circuit consisting of a PNP type output transistor Q ₁ and a PNP type output transistor Q ₂ , and the emitter currents Ie (Q ₁ ) and Ie of both output transistors Q ₁ and Q ₂ are
(Q ₂ ) is the load R _L connected to the output terminal OUT.
is supplied to Note that both output transistors Q ₁ ,
Resistors R ₃ and R ₄ connected to the emitter side of Q ₂ have minute resistance values for transistor protection.

Transistors Q ₃ , Q ₄ , Q ₅ , and Q ₆ constitute a drive stage, and transistors Q ₃ and Q ₄ are of the same npn type as output transistor Q ₁ , and are connected between the positive power supply +Vcc and the base side of output transistor Q _1. is connected in parallel to drive the output transistor _Q1 . In contrast, transistors Q ₅ and Q ₆ are of the same PNP type as output transistor Q ₂ , and are connected to the negative power supply −Vcc.
and the base side of the output transistor _Q2 , and drives the output transistor _Q2 . Note that the resistor R ₅ that commonly connects the transistors Q ₃ , Q ₄ , Q ₅ , and Q ₆ is a resistor that stabilizes the base bias of the output transistors _Q 1 and Q ₂ .
Resistors R ₆ and R ₇ connected to the bases of both output transistors Q ₁ and Q ₂ have minute resistance values for transistor protection.

Transistors Q ₇ and Q ₈ constitute a predrive stage as a pair of npn type and pnp type, and a resistor R ₈ is inserted between their emitters to connect the positive and negative power supplies +Vcc, -.
They are connected in a complementary symmetrical manner between Vcc. Also, the emitter of transistor _Q7 is connected to resistor _R9 and capacitor
It is connected to the base of a transistor Q ₃ via a parallel circuit of C ₁ and to the base of a transistor Q ₄ via a low-pass filter circuit 1 consisting of a resistor R ₁₀ and a capacitor C ₂ . In contrast, the emitter of transistor Q ₈ is connected to the base of transistor Q ₅ through a parallel circuit of resistor R ₁₁ and capacitor C ₃ , and
It is connected to the base of the transistor Q ₆ via a low-pass filter circuit 2 consisting of a resistor R ₁₂ and a capacitor C ₄ .

The above-mentioned low-pass filter circuit 1 operates under the condition that the resistor R ₈ << the resistors R ¹ ₀ and R ₁₂ , the transistor Q ₇
Even if the voltage at point _P7 on the emitter side of Q varies at an audible frequency depending on the input signal as described later, it acts to transmit only the DC voltage component at point _P7 to the base of transistor _Q4 . , resist like that
R ₁₀ and the time constant due to capacitor C ₂ are chosen. Usually, the low-pass filter circuit 1 is set to remove frequency components of several Hz or more. Similar to the low-pass filter circuit 1, the low-pass filter circuit 2 also functions to prevent voltage fluctuations at an audible frequency of several Hz or more occurring at the point _P8 from being transmitted to the base of the transistor _Q6 .

Furthermore, constant voltage bias circuits E ₁ and E' ₁ are connected between the bases of transistors Q ₇ and Q ₈ ,
The input signal (audio frequency signal) applied to the input terminal IN is superimposed on the outputs of the constant voltage bias circuits E ₁ and E' ₁ and applied to the bases of the transistors Q ₇ and Q ₈ .

In the above configuration, when there is no signal, constant emitter currents determined by the constant voltage bias circuits E ₁ and E _{' 1 flow} through transistors Q ₇ and Q 8, and the emitter currents are equal to each other and the currents at points P ₇ and P ₈ flow. The voltage becomes a constant voltage symmetric with respect to ground potential, _and as a result, _the output transistor
Base current (bias current) supplied to Q ₁
The base currents (bias currents) supplied to the output transistor Q ₂ via the drive stage transistors Q ₅ and Q ₆ are equal, and therefore the emitter currents (idling currents) of the output transistors Q ₁ and Q ₂ are also equal. Therefore, the output transistor Q ₁ ,
Q ₂ is in equilibrium.

Detailing the above operation when there is no signal on the output transistor _Q1 side, the base current of transistor _Q3 is supplied from point _P7 , which is kept at a constant voltage, through resistor _R9 , and the emitter current is amplified by transistor _Q3 . Ie (Q ₃ ) is provided to the base of output transistor Q ₁ . At the same time, capacitor C ₂ is charged from point P ₇ through resistor R ₁₀ and resistor R ₁₀
The base current of the transistor _Q4 is supplied through the transistor _Q4 , and the emitter current Ie ( _Q4 ) amplified by the transistor Q4 is supplied to the base of the output transistor _Q1 . Also, if the current flowing through R ₅ is Id, then a bias current of Ie ( _{Q 3 )} + Ie (Q ₄ ) − Id flows through the output transistor Q 1, and if the current amplification factor of the output transistor Q ₁ is h _FE , then the idling current I
_E becomes _IE = _hFE {Ie( _Q3 )+Ie( _Q4 )−Id}. The emitter currents Ie (Q ₃ ) and Ie (Q ₄ ) of transistors Q ₃ and Q ₄ when no signal are distributed are distributed between resistors R ₉ and R ₁₀ and resistor R ₁₃ connected to the emitter of transistor Q ₄ . Therefore, it can be set appropriately.

The same is true for the output transistor _Q2 side; when there is no signal, the emitter current Ie (Q ₅ ) of transistor Q ₅ is equal to the above Ie (Q ₃ ), and the emitter current Ie (Q 6 ) of transistor Q ₆ is equal to the above Ie (Q ₃ ). Ie
Resistors R ₁₁ , R ₁₂ , and R ₁₄ are set so that the output transistor Q ₁ is equal to (Q ₄ ).
and Q ₂ are in equilibrium.

Next, when a positive half wave of the input signal is applied to the input terminal IN, the voltages at points P ₇ and P ₈ rise correspondingly. The voltage rise at point P ₇ is transmitted to the base of transistor Q ₃ through capacitor C ₁ and increases the emitter current Ie (Q ₃ ), while at point
The voltage rise at _P8 is transferred to the base of transistor _Q5 via capacitor _C3 and the emitter current Ie
(Q ₅ ) decreases. However, due to the low-pass filter circuits 1 and 2, the voltage change of the input signal components at points P ₇ and P ₈ does not appear at the bases of transistors Q ₄ and Q ₆ , and the collector current Ie of transistors Q ₄ and Q ₆
(Q ₄ ) and Ie (Q ₆ ) hardly change (they change somewhat as described later). Therefore, the emitter current Ie (Q ₁ ) of the output transistor Q ₁ increases corresponding to the increase in the above Ie (Q ₃ ), and the emitter current Ie (Q ₂ ) of the output transistor Q ₂ increases as the above Ie (Q ₅ ), and Ie( _Q1 )-Ie( _Q2 ) is supplied to the load _RL . At this time, the transistor
As the emitter current Ie (Q ₁ ) of Q ₁ increases and the base-emitter voltage V _BE (Q ₁ ) increases, the base potential of transistor Q ₁ with respect to the output terminal OUT increases, so Ie (Q ₄ ) will decrease somewhat. Furthermore, as Ie (Q ₂ ) and V _BE (Q ₂ ) decrease, the voltage between the output terminal OUT and the base of transistor Q ₂ decreases, which causes Ie (Q ₆ ) to increase somewhat.

By the way, when the amplitude of the positive half-wave input signal applied to the input terminal IN exceeds a certain value, the corresponding voltage rise at point _P8 causes transistor _Q5 to be cut off, and the emitter current Ie ( _Q5 ) becomes zero. However, as mentioned above, the emitter current Ie (Q ₆ ), which is slightly increased compared to when there is no signal, flows through the transistor Q ₆ ,
Since this drives the base of output transistor _Q2 , output transistor _Q2 will not be cut off. In other words, even if transistor Q ₅ is cut off, output transistor Q ₂ will have at least I′ _E =
An emitter current of h _FE {Ie (Q ₆ ) − Id} flows and is maintained in the active state.

Also, when the negative half-wave of the input signal is applied to the input terminal IN, the voltages at points P ₇ and P ₈ will correspondingly decrease, respectively, and Ie (Q ₃ ) and Ie (Q ₁ ) will decrease. At the same time, Ie(Q ₅ ) and Ie(Q ₂ ) increase, and Ie(Q ₁ )−Ie(Q ₂ ) is supplied to the load. At this time, transistor _Q3 is cut off and Ie
Even if (Q ₃ ) becomes zero, a non-zero emitter current Ie (Q ₄ ) flows through the transistor Q ₄ and this drives the base of the output transistor Q _1. Therefore, the output transistor Q ₁ has a minimum I′ _E = h _FE {Ie(Q ₄ )−
An emitter current }Id} flows to maintain the active state.

As is clear from the above operation explanation, the input signal waveform and output transistors Q ₁ and Q ₂ in the above circuit
The relationship between the emitter currents Ie (Q ₁ ) and Ie (Q ₂ ) is the third
The result will be as shown in the figure. That is, when there is no signal, the above idling current I _E flows through the output transistors Q ₁ and Q ₂ , and the positive half wave of the input signal is amplified by the output transistor Q ₁ , and the negative half wave is amplified by the output transistor Q ₂ . It performs a push-pull motion similar to a normal B-class. However, even when the negative half-wave is input, the output transistor _Q1 does not cut off, and the above-mentioned idling current IE is slightly smaller than the idling current _IE .
An emitter current _I'E flows, and similarly, even when a positive half wave is input, the emitter current _I'E flows through the output transistor _Q2 and is not cut off. Here, Ie (Q ₃ ) + Ie (Q ₄ ) and Ie (Q ₅ ) + Ie (Q ₆ ), which determine the idling current I _E , are kept constant, and Ie (Q ₃ ) and Ie (Q ₄ ) are Ie by adjusting the allocation ratio and the allocation ratio of Ie (Q ₅ ) and Ie (Q ₆ )
(Q ₁ ) and Ie (Q ₂ ) can be changed, thereby making it possible to easily set the operating point with the least crossover distortion.

As described above, in the power amplifier circuit of this invention, despite high efficiency amplification, the output transistors Q ₁ and Q ₂ are always active without being cut off, so the above-mentioned switching distortion and Crossover distortion can be significantly reduced. Moreover, the idling current I _E when there is no signal is
And the minimum emitter current I′ _E when a signal is present is determined by the constant voltage bias circuits E ₁ and E′ ₁ , so
Temperature compensation related to bias stabilization of output transistors Q ₁ and Q ₂ can be performed for constant voltage bias circuits E ₁ and E' ₁ in the same way as a normal fixed bias current SEPP circuit, and temperature compensation is also required from a circuit perspective. Also, the implementation structure is not particularly complicated.

That is, according to this invention, a non-cutoff type power amplifier circuit with high efficiency and low switching distortion and crossover distortion can be realized with a simple configuration.

Note that the transistor shown in the example of FIG.
The predrive stage consisting of Q ₇ and Q ₈ operates while maintaining the voltage between points P ₇ and P ₈ at a constant voltage corresponding to the constant voltage bias circuits E ₁ and E′ ₁ , and the operation principle is as follows: The constant voltage bias circuits E ₁ and E' ₁ may be directly connected between the points P ₇ and P ₈ , and the predrive stage is not necessarily required.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a typical example of a conventional non-cutoff type power amplifier circuit, FIG. 2 is a circuit diagram showing an embodiment of the power amplifier circuit according to this invention, and FIG.
This figure is a waveform diagram showing the relationship between the input signal and the emitter current of the output transistor in the circuit of FIG. 2. Q ₁ , Q ₂ ... Transistor of power amplification stage, Q ₃ ,
Q ₅ ...first transistor of drive stage, Q ₄ ,
Q ₆ ...Second transistor of drive stage, 1,
2...Low pass filter circuit, _Q7 , _Q8 ...Predrive stage transistors, _E1 , _E'1 ...constant voltage bias circuit.

Claims (1)

[Scope of utility model registration request] A SEPP power amplification stage consisting of at least two transistors connected in a complementary symmetrical manner, a mutually symmetrical drive stage that drives each of the two transistors of this power amplification stage, and the above power amplification stage via this drive stage. In a power amplifier circuit comprising a constant voltage bias circuit for biasing, the drive stage includes a first transistor that amplifies an input signal superimposed on the output of the constant voltage bias circuit and applies the amplified signal to the power amplifier stage; a low-pass filter circuit that smooths the input signal superimposed on the output of the constant voltage bias circuit and outputs only a DC bias component; and a second transistor that amplifies the output of the low-pass filter circuit and applies it to the power amplification stage. A power amplification circuit characterized in that the transistor of the power amplification stage is prevented from being cut off by the bias current supplied via the second transistor, regardless of the polarity and amplitude of the input signal. .