JP3530924B2 - Operational amplifier - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique which is effective when applied to an operational amplifier and, more particularly, to an operational amplifier which switches a capacitive load. It relates to the technology that is effective for the driver. 2. Description of the Related Art In an amplifier circuit having a high gain open gain (open gain), phase compensation may be required to prevent oscillation and stabilize operation. FIGS. 5 and 6 show examples of the configuration of a conventional operational amplifier, respectively. In this case, each operational amplifier 1 is subjected to DC negative feedback from its output to its input, forming a so-called voltage follower circuit. In an operational amplifier 1 shown in FIG. 5, a differential input stage 11, a high gain amplifier stage 12, and an output buffer stage 13 are connected in multiple stages, and a capacitive element Cf1 is connected between the input and output of the high gain amplifier stage 12. A phase compensation circuit is formed by feedback connection. [0005] In the operational amplifier 1 shown in FIG. 6, in addition to the configuration of FIG.
By grounding at 2, the gain in the high frequency region is suppressed, and thereby the oscillation and operation instability are more reliably suppressed. The above-described operational amplifier is described in, for example, "Analog Integrated Circuit Design Technology for Ultra LSI"<
2nd volume>, p. 126, p. R gray / R. It is described in G. Meyer's co-authorship, translated by Jo Nagata, published by Baifukan in 1990. [0007] However, it has been clarified by the present inventors that the above-described technology has the following problems. That is, in the operational amplifier 1 shown in FIG. 5 or FIG. 6, a capacitive load 2 such as a liquid crystal display element is connected to the output out of the operational amplifier 1, and the capacitive load 2 is further separated from its initial charging potential. If the capacity CL of the load 2 is large when step driving to the potential is performed, the load 2 is temporarily operated in the open gain state in order to charge / discharge the capacity CL following the input voltage Vin. At this time, if the open gain is large, the entire negative feedback loop forming the voltage follower circuit becomes an unstable system, and overshoot and ringing of the output voltage Vo are likely to occur. FIG. 7 shows the relationship between the transmission frequency and the open gain (dB) of the operational amplifier 1 shown in FIG. As shown in FIG. 1, the open gain of the operational amplifier 1 begins to decrease at the first corner frequency f1,
Is accelerated at the corner frequency f2. This 2
The two corner frequencies f1 and f2 are determined by the following equations. f1 = 1 / (2π × A2 × Cf1 × Zo1) f2 = 1 / (2π × CL × Zo3) In the above equation, A2 is the gain in the high gain amplifier stage 12, Zo
1 is the output impedance of the differential input stage, CL is the capacitance of the load 2, and Zo3 is the output impedance of the output buffer stage 13. Here, the open gain at the second corner frequency f2 varies depending on the magnitude of the capacitance CL of the capacitive load 2. When the load capacitance CL is large, the open gain at the second corner frequency f2 increases. However, the increase in the open gain makes the entire negative feedback loop unstable, thereby causing overshoot, ringing, and the like. Oscillation may occur in some cases. When the liquid crystal display element is driven under this unstable operation, the display of the liquid crystal becomes unclear or display unevenness appears. The present inventors have focused on lowering the corner frequencies f1 and f2 in order to solve the above-mentioned problem, and this is one of the parameters that determine the corner frequencies f1 and f2. Considering increasing the capacitance Cf1 of the capacitance element. However, when the load capacitance CL becomes as large as, for example, 0.1 μF, it has been found that another problem arises that it is impossible to cope with the increase in the capacitance of the capacitive element Cf1, and that it becomes difficult to form a semiconductor integrated circuit. did. An object of the present invention is to provide a technique for stabilizing the step driving operation of a capacitive load by an operational amplifier using a capacitive element that can be built in a semiconductor integrated circuit. The above and other objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Means for Solving the Problems Of the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, in an operational amplifier in which a differential input stage, a high gain amplifier stage, and an output buffer stage are connected in multiple stages,
A first phase compensation circuit is formed by negatively connecting a capacitive element between the input and output of the high gain amplifying stage, and the output of the output buffer stage is connected to the high gain amplifying circuit via an amplifying circuit and a capacitive element. The second phase compensating circuit is formed by negatively feeding back to the input. According to the above-described means, the phase compensation is performed by the capacitance greatly enlarged by the Miller effect, so that even if the load capacitance is large and the entire system operates with the open gain of the amplifier, the above-mentioned method can be used. The open gain can be reliably kept low. This achieves the object of stabilizing the step driving operation of the capacitive load by the operational amplifier by using a relatively small-capacitance element that can be built in the semiconductor integrated circuit. Preferred embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts. FIG. 1 shows an embodiment of an operational amplifier 1 to which the technique of the present invention is applied, wherein reference numeral 11 denotes a differential input stage having an inverting input (-) and a non-inverting input (+); Reference numeral 12 denotes a high gain amplification stage for inverting and amplifying the output of the differential amplification stage 11 at a high gain. Reference numeral 13 denotes an output buffer stage for amplifying the output of the high gain amplification stage 12 at zero voltage gain. Vb is an input bias voltage source. The above-described differential amplification stage 11, high-gain amplification stage 12, and output buffer stage 13 are sequentially connected in multiple stages. Further, in the amplifier 1 shown in FIG. 1, in addition to the above, the first and second capacitive elements Cf1 and Cf2 and the medium gain non-inverting amplifier circuit 14 are provided in the same semiconductor integrated circuit. I have. The first capacitive element Cf1 is connected between the input and output of the high gain amplifier stage 12 to form a first phase compensation circuit. The second capacitive element Cf2 and the amplifier circuit 14
The output of the output buffer stage 13 is connected to the high gain amplification stage 12
The second phase compensation circuit is formed by performing negative feedback on the input of the second phase compensation circuit. At this time, the amplifier circuit 14 is connected to the output buffer stage 1
3 is amplified. This amplified output is supplied to the second capacitive element C
It is fed back to the input of the high gain amplifier stage 12 via f2. The above-described operational amplifier 1 has its output out.
As a whole, a voltage follower circuit having a gain of zero is formed by negative feedback applied to input in from. Next, the operation will be described. In FIG. 1, inside the operational amplifier 1,
As described above, the first and second phase compensation circuits are each formed by negative feedback. FIG. 2 shows the relationship between the transmission frequency and the open gain (dB) of the operational amplifier 1 shown in FIG. As shown in the figure, the open gain of the operational amplifier 1 starts to decrease at the first corner frequency f1, and
Is accelerated at the corner frequency f2. Here, the first corner frequency f1 is determined by the following equation. f1 = 1 / {2π × A2 × (Cf1 + A4 × Cf2) × Zo1} In the above equation, A2 is the gain in the high gain amplifier stage 12, A4
Is the gain in the amplifier circuit 14, and Zo1 is the output impedance of the differential input stage. As shown in the above equation, the first corner frequency f1
Are greatly shifted to lower frequencies due to the capacitance (A4 × Cf2) mirror-expanded by the amplification operation of the amplifier circuit 14. Accordingly, the open gain at the second corner frequency f2 is reliably reduced to below zero dB regardless of the magnitude of the load capacitance CL. Thus, even when the load capacitance CL is large and the whole system operates with the open gain of the amplifier, the open gain can be reliably kept low. This makes it possible to stabilize the step driving operation of the capacitive load by the operational amplifier using the capacitive element that can be built in the semiconductor integrated circuit. Therefore, when driving the liquid crystal display element,
The display of the liquid crystal can be kept clear. FIG. 3 shows a detailed circuit embodiment of the operational amplifier 1 described above. In the figure, a differential input stage 11 has a pn
It is formed by p bipolar transistors Q1 and Q2, npn bipolar transistors Q3 and Q4, and a constant current source I1. In this case, the pnp bipolar transistors Q1 and Q2 are emitter-coupled via the constant current source I1 to form a differential circuit, and the npn bipolar transistors Q3 and Q4 form a current mirror circuit. The output of the differential input stage 11 is taken out from the collector of the current output side transistor Q4 and input to the high gain amplifier stage 12. The high gain amplifying stage 12 comprises an npn bipolar
Transistor Q5, diodes Q6 and Q for level shift
7, formed by the constant current source I2. Transistor Q
Reference numeral 5 designates a medium-gain inverting amplifier circuit that performs an inverting amplification operation of a medium gain, and diodes Q6 and Q7 level-shift the amplified output to the power supply potential Vcc side. A capacitive element Cf1 forming a first phase compensation circuit is connected between the collector and the base of the transistor Q5. The output buffer stage 13 is formed by an npn bipolar transistor Q8 and a pnp bipolar transistor Q9. The transistor Q8 operates as a common-collector amplifier circuit when its collector is connected to the power supply potential Vcc side and the transistor Q9 has its collector connected to the reference potential. These two bipolar transistors Q8, Q9
Are connected to an output terminal (out). The amplifying circuit 14, which forms a second phase compensating circuit together with the capacitive element Cf2, comprises npn bipolar transistors Q10, Q11, Q12, a resistor R1, and a constant current source I.
3, I4. In this case, the transistors Q10 and Q11 are emitter-coupled via the constant current source I4 to form a differential amplifier circuit. However, the collector load resistor R1 is connected to only one of the transistors Q10 so that only the non-inverted output is taken out. The base of one transistor Q11 is connected to the output terminal (out), and the other transistor Q11
The base of 10 is connected to a bias voltage source Vb common to the differential input stage 11. The output of this amplifier circuit 14 is
It is taken out from the collector of the other transistor Q10 via the emitter follower formed by the transistor Q12 and the constant current source I3, and is fed back to the input of the high gain amplifying stage 12, that is, the base of Q5 via the capacitive element Cf2. I have. In the operational amplifier 1, the DC bias point of the amplifier circuit 14 can be set arbitrarily because the amplifier circuit 14 forming the second phase compensation circuit is of a differential input type. ing. FIG. 4 shows an embodiment of a liquid crystal driver constructed using the operational amplifier 1 of the present invention. The liquid crystal driver shown in FIG. 1 generates a voltage dividing circuit 4 that generates a plurality of voltages that differ stepwise according to the resistance strings R, R, R,. And a selection circuit 3 for selecting the switches of the outputs of the plurality of operational amplifiers 1 and supplying the outputs to the liquid crystal display element. Reference numeral 2 denotes a capacitive load, and a liquid crystal display element is connected as the load 2 here. In this liquid crystal driver, as described above,
Even in the case where the load capacitance CL is large and the whole system operates with the open gain of the amplifier 1, the open gain can be reliably kept low, so that ringing and the like are suppressed, and stable and clear Display can be performed. Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. In the above description, the case where the invention made by the present inventor is applied to a liquid crystal driver, which is the field of application, has been described. However, the present invention is not limited to this. The present invention can also be applied to driving of a sexual load. The effects of the typical inventions disclosed in the present application will be briefly described as follows. That is, the effect of stabilizing the step driving operation of the capacitive load by the operational amplifier can be obtained by using a relatively small-capacitance element that can be built in the semiconductor integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of an operational amplifier to which the technology of the present invention is applied. FIG. 2 is a relationship between a transmission frequency and an open gain (dB) of the operational amplifier shown in FIG. FIG. 3 is a diagram showing a detailed circuit embodiment of the operational amplifier shown in FIG. 1. FIG. 4 is a block diagram showing an embodiment of a liquid crystal driver using the operational amplifier of the present invention. 5 shows a first configuration example of a conventional operational amplifier. FIG. 6 shows a second configuration example of a conventional operational amplifier. 7 is a characteristic diagram showing the relationship between the transmission frequency and the open gain (dB) of the operational amplifier shown in FIG. 5. [Description of References] 1 Operational Amplifier 11 Differential Input Stage 12 High Gain Amplification Stage 13 Output Buffer Stage 14 Amplification Circuits Cf1, Cf2 Capacitance element 2 Capacitive load CL Load capacitance 3 Selection circuit 4 Voltage division circuit

Continuation of the front page (56) References JP-A-60-233850 (JP, A) JP-A-58-9410 (JP, A) JP-A-5-226949 (JP, A) JP-A-5-150747 (JP) JP-A-2-233006 (JP, A) JP-A-63-136803 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03F 1/34 H03F 3/45

Claims (1)

(57) [Claim 1] A multi-stage amplifier circuit including a differential input stage, a high gain amplifier stage, and an output buffer stage, and a first capacitive element between the input and output of the high gain amplifier stage. And a first phase compensation circuit formed by negative feedback connection, and an output of the output buffer stage is negatively fed back to an input of the high gain amplifier circuit via an amplifier circuit and a second capacitor. made by and a second phase compensation circuit is an amplifier circuit for forming a second phase compensation circuit have a differential input
And one of the inputs is DC biased, and the open gain begins to drop at the first corner frequency f1,
At the second corner frequency f2, the speed of the decrease is accelerated.
The first corner frequency f1 is Cf1 and Cf2.
The capacitance values of the first and second capacitance elements, A2, respectively, are
The gain in the high gain amplifier stage, A4, is used in the amplifier circuit.
And Zo1 is the output impedance of the differential input stage.
When in it is determined by f1 = 1 / (2π × A2 × (Cf1 + A4 × Cf2) × Zo1>, the differential input stage, first and second pnp bipolar
A transistor and first and second npn bipolars
A transistor and a first constant current source, wherein the first pnp bipolar transistor and the second
The pnp bipolar transistor is the first constant current
Emitter-coupled through a current source to create a differential circuit
Forming the first and second npn bipolar tigers
The transistor forms a current mirror circuit, and the output of the differential input stage is connected to the second npn bipolar circuit.
.High gain obtained from the collector of the transistor
Input to the amplifier stage, wherein the high gain amplifier stage is connected to a third npn bipolar transistor.
First and second diodes for level shifting
And a second constant current source, wherein the third npn bipolar transistor is an emitter.
Performs medium gain inverting amplification operation as
The first and second diodes supply their amplified outputs to a power supply.
The level shifts to the potential side, and the third npn bipolar
・ Between the collector and base of the transistor
Connected to the first capacitive element forming the first phase compensation circuit.
And the output buffer stage comprises a fourth npn bipolar transistor.
Transistor and a third pnp bipolar transistor
And the fourth npn bipolar transistor has the
Is connected to the power supply potential side,
The pnp bipolar transistor of No. 3 has its collector
By being connected to the reference potential, the collector
Operate as a ground amplification circuit, and operate as the fourth npn bipolar
A transistor and the third pnp bipolar transistor
A common emitter with the transistor is connected to the output terminal to form a second phase compensation circuit together with the second capacitor.
The fifth, sixth, and seventh npn buses.
The bipolar transistor, the collector load resistance, and the third
And the fifth and sixth npn bipolar transistors.
Can be emitter-coupled via the fourth constant current source.
To form a differential amplifier circuit, wherein the collector load resistance is equal to the fifth npn bipolar
.Non-inverted output by being connected only to transistors
And the base of the sixth npn bipolar transistor is
A fifth npn bipolar connected to the output terminal;
・ The base of the transistor is shared with the above differential input stage.
The output of the amplifier circuit is connected to the fifth npn bipolar
From the collector of the transistor, the seventh npn
And the third constant current source.
Taken out through the emitter follower, and
The third input, which is the input of the high gain amplifier stage via the
Feedback to the base of the npn bipolar transistor
And wherein the amplification circuit forming the second phase compensation circuit is a differential amplifier.
The input format allows the DC via
An operational amplifier characterized in that the switching point can be set arbitrarily .