JP3408413B2 - Semiconductor manufacturing method and semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a GaN-based III-V group compound semiconductor used in a blue-violet light emitting device and a semiconductor device using this compound semiconductor.

[0002]

2. Description of the Related Art In recent years, gallium nitride (Ga) that emits blue-violet light has been used as a light source for next-generation full-color displays.
Research and development of semiconductor light emitting devices using N) III-V group compound semiconductors have been actively conducted. In this semiconductor light emitting device, the active layer is sandwiched by pn junctions, and it is important for improving the quality that the active layer does not contain impurities. That is, the distribution of the p-type dopant and the n-type dopant needs to be steep.

Further, in a wide band gap compound semiconductor such as GaN, activation of the p-type dopant is suppressed by hydrogen passivation even if the p-type dopant is doped, so that a low-resistance p-type semiconductor layer can be obtained. Hateful. Therefore, in order to obtain a p-type semiconductor layer having low resistance,
It is necessary to dope the p-type dopant to a high concentration and perform annealing treatment or the like.

A conventional method for controlling the p-type dopant will be described below. Biscyclopentadienyl magnesium (Cp ₂ Mg) is generally used as a p-type dopant for GaN.
Is used. However, when the metalorganic vapor phase epitaxy (MOVPE) method is used for the crystal growth, there is a problem that Mg which is a p-type dopant diffuses into a crystal other than a predetermined crystal during the growth ("Applied Physics Lett").
ers, Vol.55 (1989) pp.1017-1019 "). This diffusion may occur not only during growth but also after annealing after growth.

Further, as a result of examining a memory effect in which Mg is adsorbed in a quartz reactor which is a reaction furnace of a MOVPE growth apparatus, "Journal of Crystal Growth, Vol.145 (1)
994) pp. 214-218 ". According to this paper, Mg has a memory effect, so a large amount of C
It has been shown that even if p ₂ Mg is introduced into the reaction furnace, the Mg distribution in the GaN crystal does not become steep and the doping is delayed.

On the other hand, in the case of a gallium arsenide (GaAs) -based III-V group compound semiconductor grown on a substrate capable of lattice matching, the concentration of Si as an n-type dopant is 1 × 1.
It is known that Mg diffusion can be suppressed by doping at a high concentration of about 0 ²⁰ cm ^-3 ("Journal of Cry
stal Growth, Vol.107 (1991) pp.779-783 ").

Further, according to Japanese Patent Laid-Open No. 6-283825, in a GaN-based semiconductor light emitting device, p-type AlGa is used.
It has been shown that the diffusion of Mg into the active layer formed immediately below the p-type cladding layer can be suppressed by forming a part of the p-type cladding layer made of N as an undoped layer that is not p-type doped.

[0008]

[Problems to be Solved by the Invention] However, GaN
Since there is no substrate that lattice-matches with GaN in semiconductors, when manufacturing an epitaxial substrate, heteroepitaxial growth using a lattice-mismatched substrate made of sapphire (crystal Al ₂ O ₃ ) or silicon carbide (SiC) is used. I have no choice. As a result, the defect density in the crystal of the GaAs-based semiconductor is about 10 ³ cm ^-2, but the defect density of the GaN-based semiconductor is about 10 ⁹ cm ^-2, which is an extremely large number of threading dislocations. There is a problem that the pn junction having a steep impurity profile cannot be easily diffused through the threading dislocations.

Further, in the conventional semiconductor light emitting device disclosed in Japanese Patent Laid-Open No. 6-283825, G is used as the diffusion suppressing layer.
Since the AlGaN layer having a bandgap larger than that of aN is undoped, there is a problem that the series resistance of the pn junction increases, and the increase of the series resistance promotes heat generation during operation of the light emitting device, and Significantly reduces the reliability of.

It is an object of the present invention to solve the above conventional problems and to form a pn junction having a steep dopant profile in a gallium nitride based semiconductor.

[0011]

In order to achieve the above-mentioned object, the present invention provides a gallium nitride-based semiconductor having a p-type semiconductor layer formed at a pn junction composed of a p-type semiconductor layer and an n-type semiconductor layer. A semiconductor layer formed by simultaneously doping (co-doping) a p-type dopant and an n-type dopant is provided in a region on the n-type semiconductor layer side.

A method of manufacturing a semiconductor according to the present invention comprises a step of forming a first semiconductor layer of an undoped or n-type gallium nitride based semiconductor on a substrate which is not lattice-matched with a gallium nitride based semiconductor, and a first semiconductor layer. And a second semiconductor layer made of a gallium nitride-based semiconductor on top of which is a p-type dopant and n.
The method includes a step of co-doping with a type dopant and a step of forming a third semiconductor layer made of a p-type gallium nitride based semiconductor on the second semiconductor layer.

According to the method for producing a semiconductor of the present invention, a p-type dopant is provided between the first semiconductor layer made of an undoped or n-type gallium nitride based semiconductor and the third semiconductor layer made of a p-type gallium nitride based semiconductor. And the n-type dopant are co-doped to form the second semiconductor layer, the p-type dopant and the n-type dopant in the second semiconductor layer form an electrically neutral atom pair due to Coulomb interaction. The p-type dopant contained in the third semiconductor layer is less likely to diffuse.

In the semiconductor manufacturing method of the present invention, the second
It is preferable that the film thickness of the semiconductor layer is 5 nm or more and 500 nm or less.

The semiconductor manufacturing method of the present invention comprises the steps of forming a fourth semiconductor layer that absorbs gallium atoms on the third semiconductor layer, and performing a heat treatment on the fourth semiconductor layer. Further, it is preferable to further include.

A first semiconductor device according to the present invention comprises a first clad layer made of an n-type gallium nitride based semiconductor formed on a substrate that is not lattice-matched with a gallium nitride based semiconductor, and a first clad layer on the first clad layer. An active layer made of a gallium nitride-based semiconductor formed in the above, a diffusion suppressing layer made of a gallium nitride-based semiconductor co-doped with a p-type dopant and an n-type dopant, and a diffusion suppressing layer formed on the active layer. And a second clad layer made of a p-type gallium nitride based semiconductor.

According to the first semiconductor device, the diffusion suppressing layer formed by co-doping the p-type dopant and the n-type dopant is formed between the active layer and the second cladding layer made of the p-type gallium nitride based semiconductor. Therefore, the p-type dopant and the n-type dopant in the diffusion suppressing layer form Coulomb interaction to form an electrically neutral atom pair.
The p-type dopant contained in the second cladding layer is less likely to diffuse to the active layer side.

A second semiconductor device according to the present invention comprises a first cladding layer made of an n-type gallium nitride based semiconductor formed on a substrate which is not lattice-matched with the gallium nitride based semiconductor, and a first cladding layer on the first cladding layer. An active layer made of a gallium nitride based semiconductor formed on the substrate, a diffusion suppressing layer made of an n type gallium nitride based semiconductor formed on the active layer, and a p type gallium nitride based semiconductor formed on the diffusion suppressing layer And a second clad layer made of

According to the second semiconductor device, since the diffusion suppressing layer made of the n-type gallium nitride based semiconductor is formed between the active layer and the second cladding layer made of the p-type gallium nitride based semiconductor, When the p-type dopant contained in the second cladding layer diffuses into the diffusion suppressing layer, the p-type dopant and the n-type dopant in the diffusion suppressing layer are electrically neutral atom pairs due to Coulomb interaction. To form
The p-type dopant contained in the second cladding layer is less likely to diffuse to the active layer side.

In the first or second semiconductor device, it is preferable that the film thickness of the diffusion suppressing layer is equal to or less than the diffusion length of holes.

In the first or second semiconductor device, it is preferable that the film thickness of the diffusion suppressing layer is 5 nm or more and 500 nm or less.

The first or second semiconductor device has a contact layer made of a p-type gallium nitride based semiconductor formed on the second cladding layer and an upper surface of the contact layer, and absorbs gallium atoms. It is preferable to further include a gallium absorption layer.

In the first or second semiconductor device, it is preferable that the p-type dopant is magnesium and the n-type dopant is silicon.

In the first or second semiconductor device, the diffusion suppressing layer is preferably made of Al _x Ga _1-x N (provided that 0 <x <1).

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment according to the present invention will be described with reference to the drawings.

FIG. 1A shows a sectional structure of a semiconductor light emitting device according to a first embodiment of the present invention, and FIG. 1B shows a sectional structure of a semiconductor light emitting device for comparison. First, a method for manufacturing the semiconductor light emitting device shown in FIGS. 1A and 1B will be described. 1A and 1B, a substrate 10 made of sapphire (crystal Al ₂ O ₃ ) is ultrasonically cleaned in advance using an organic solvent, and subsequently, a metal organic chemical vapor deposition (MOVPE) apparatus is used. The substrate 10 is held on a susceptor provided in a reaction furnace (not shown). Next, after evacuation of the inside of the reaction furnace, the substrate 10 is heated at about 1100 ° C. for 15 minutes in a hydrogen atmosphere having a pressure of 70 Torr to thermally clean the substrate surface.

Then, after the temperature of the reaction furnace was lowered to about 500 ° C., trimethylgallium (TMG) as a gallium source was used.
Is introduced into the reaction furnace at a flow rate of 2 μmol / min, ammonia as a nitrogen source at a flow rate of 2.5 L / min, and hydrogen as a carrier gas at a flow rate of 2 L / min, respectively, to form a film on the upper surface of the substrate 10. Low-temperature buffer layer 11 made of GaN having a thickness of 30 nm
Grow.

Next, after raising the temperature of the reaction furnace to about 1000.degree. C., a silane gas (S containing Si which is an n-type dopant) (S
iH ₄ ) is newly introduced into the reactor, and the low temperature buffer layer 1
1 has a film thickness of 3 μm and an impurity concentration of 1 × 10 ¹⁸ cm
^-3, an n-type contact layer 12 made of n-type GaN is grown, and subsequently, trimethylaluminum (TMA), which is an aluminum source, is newly introduced into the reaction furnace so that the film thickness is increased on the upper surface of the n-type contact layer 12. Impurity concentration is 1 at 0.3 μm
The n-type clad layer 13 made of n-type Al _0.1 Ga _0.9 N having a ^density of × 10 ¹⁸ cm ⁻³ is grown, and subsequently, the introduction of TMA is stopped and the upper surface of the n-type clad layer 13 is made of GaN having a thickness of 0.1 μm. The first light guide layer 14 is grown.

Next, after lowering the temperature of the reaction furnace to about 800 ° C.,
In _0.20 Ga with a film thickness of 3 nm using nitrogen as a carrier gas
Quantum well active layer 15 of _0.80 N and film thickness of 0.1 μ
The second optical guide layer 16 made of m GaN is sequentially grown.

Next, the temperature of the reaction furnace is raised again to about 1000 ° C., and the Cp ₂ Mg gas containing Mg which is a p-type dopant has an Mg impurity concentration of 5 × 10 ¹⁹ cm ⁻³ , and
SiH ₄ gas containing Si, which is an n-type dopant, is added to the source gas so that the impurity concentration of Si is 1 × 10 ²⁰ cm ^−3, and the film thickness is 2 on the upper surface of the second optical guide layer 16.
A diffusion suppressing layer 17 made of 0 nm Al _0.1 Ga _0.9 N is grown, then the supply of SiH ₄ gas is stopped, and a p-type Al _0.1 film having a thickness of 0.28 μm is formed on the upper surface of the diffusion suppressing layer 17.
A p-type clad layer 18 made of Ga _0.9 N is grown.
Here, in the case of the semiconductor light emitting device shown in FIG. 1B, since the diffusion suppressing layer 17 is not provided, the film thickness of the p-type cladding layer 18 is 0.3 μm.

Next, on the upper surface of the p-type clad layer 18, p with a thickness of 0.4 μm and an impurity concentration of Mg of 1 × 10 ²⁰ cm ⁻³ is formed.
Growing a p-type contact layer 19 made of ⁺ -type GaN,
Then, the grown epitaxial substrate is annealed at a temperature of 700 ° C. for 1 hour in a nitrogen atmosphere to reduce the resistance of the p-type cladding layer 18 and the p-type contact layer 19.

Next, a part of the epitaxial substrate is dry-etched to expose the n-type contact layer 12, and an n-side electrode 20 made of Ti / Au is selectively formed on the exposed surface, and p A stripe-shaped p-side electrode 21 of Ni / Au having a width of 10 μm is formed on the upper surface of the mold contact layer 19. In addition, the n-type cladding layer 13,
The first light guide layer 14, the quantum well active layer 15, the second light guide layer 16, the diffusion suppressing layer 17, the p-type clad layer 18, and the p-type contact layer 19 are dry-etched to form a resonator. To do.

The characteristics of the semiconductor light emitting device configured as described above will be described below with reference to the drawings.

FIG. 2A shows a dopant profile of the semiconductor light emitting device according to this embodiment measured by the secondary ion mass spectrometry (SIMS) method, and FIG. 2B shows a semiconductor light emitting device for comparison. The dopant profile is shown. As shown in FIG. 2A, the optical guide layers 14 and 16 and the quantum well active layer 15 located at a depth of 0.7 μm to 0.9 μm from the upper surface of the epitaxial substrate include:
The p-type dopant Mg did not diffuse, and a steep dopant profile was obtained, indicating that the diffusion suppressing layer 17 is effectively working. On the other hand, when the diffusion suppressing layer 17 is not provided as shown in FIG.
6 and that the quantum well active layer 15 is formed, the p-type dopant Mg is diffused.

Further, before the annealing treatment for reducing the resistance of the p-type clad layer 18 and the p-type contact layer 19, the film thickness of the p-type contact layer 19 is set to 8 by sputtering.
When a gallium absorption layer made of 0 nm silicon oxide (SiO ₂ ) and absorbing Ga atoms is deposited and then annealed, a steeper profile than the dopant profile shown in FIG. 2A can be obtained. it can. This is because the gallium absorption layer made of SiO ₂ absorbs Ga atoms during the annealing treatment to generate a large number of vacancies in the p-type contact layer 19, and the p-type dopant Mg atoms are trapped in the vacancies. This is because it becomes difficult to diffuse to the active layer side.

FIG. 3A shows the emission spectrum intensity of the semiconductor light emitting device according to this embodiment, and FIG. 3B shows the emission spectrum of the semiconductor light emitting device for comparison.
FIG. 3A shows a semiconductor light emitting device according to the present embodiment having a length of 20 m.
The quantum level emission from the quantum well active layer 15 is obtained when a direct current of A is injected at room temperature for operation.
Only the 0 nm spectrum is visible.

On the other hand, in the case of the semiconductor light emitting device for comparison shown in FIG. 3B, the spectrum at 420 nm which is the quantum level emission from the quantum well active layer 15 and the level formed by the diffusion of Mg. The 450 nm spectrum is duplicated. When the direct current to be injected is reduced to 2 mA, the 450 nm spectrum becomes more prominent.
This is because the injected carriers contribute to light emission at the emission level on the low energy side with a wavelength of 450 nm, and transition to the emission level on the high energy side with a wavelength of 420 nm as the injection current increases. That is, the diffusion suppressing layer 17
If not provided, a large amount of reactive current does not contribute to the quantum level emission of the quantum well active layer 15, resulting in a decrease in color purity and a decrease in emission efficiency.

The semiconductor light emitting device according to this embodiment has the diffusion suppressing layer 17 for suppressing the diffusion of the p-type dopant to the active layer side, and the quantum well active layer 15 has Mg as the p-type dopant. Is difficult to diffuse, so from low current to 2
Only the spectrum of 420 nm is observed up to 0 mA, and it can be seen that the injected carriers effectively contribute to the emission from the quantum level.

Further, as a result of comparing the current-voltage characteristics of the semiconductor light emitting device according to the present embodiment and the semiconductor light emitting device for comparison, the increase of the series resistance due to the provision of the diffusion suppressing layer 17 is not observed, Both light emitting devices showed a voltage of about 5 V when a direct current of 20 mA was injected. This is the diffusion suppressing layer 1
When the film thickness of 7 is about 20 nm, it means that the injected holes are relatively easily injected into the active layer side.
nm-500 nm, preferably 10 nm-
When it is about 80 nm, blue-violet light with a wavelength of 420 nm can be obtained without causing an increase in the threshold voltage.

As described above, in the semiconductor light emitting device according to this embodiment, diffusion of Mg, which is a p-type dopant, toward the active layer side between the second optical guide layer 16 and the p-type cladding layer 18. Since the diffusion suppressing layer 17 is provided, the color purity and the light emitting efficiency can be significantly improved without increasing the series resistance of the light emitting device.

In addition, Al _0.1 Ga _0.9 is used as the diffusion suppressing layer 17.
Since N is used, the bonding force of the crystal lattice of AlGaN is larger than that of GaN, so that the diffusion of Mg can be suppressed more effectively.

Although magnesium (Mg) is used as the p-type dopant in the present embodiment, the present invention is not limited to this, and carbon (C), zinc (Zn) and beryllium (Be) are used.
May be used, and silicon (S
Although i) is used, it may be oxygen (O).

In addition, sapphire (crystal Al ₂ O
₃ ) was used, but silicon carbide (SiC) may be used. In this case, since silicon carbide has conductivity, n
Etching of the epitaxial substrate for forming the side electrode 20 is unnecessary, and the n-side electrode 20 can be formed on the surface of the substrate 10 opposite to the p-side electrode 21.

(Second Embodiment) A second embodiment according to the present invention will be described below with reference to the drawings.

FIG. 4 shows a sectional structure of a semiconductor light emitting device according to a second embodiment of the present invention, and in FIG.
The same components as those shown in (a) are designated by the same reference numerals, and the description thereof will be omitted.

The feature of this embodiment is that the quantum well active layer 15 is used.
Is embedded in the n-type clad layer 13 without being sandwiched by the pn junction composed of the n-type clad layer 13 and the p-type clad layer 18.

First, a method of manufacturing the semiconductor light emitting device shown in FIG. 4 will be described. Similar to the first embodiment, after the low temperature buffer layer 11 and the n-type contact layer 12 are sequentially grown on the substrate 10 made of sapphire using the MOVPE method, the film thickness is formed on the upper surface of the n-type contact layer 12. 0.28 μm
And n-type Al _0.1 Ga with an impurity concentration of 1 × 10 ¹⁸ cm ^-3
_A first n-type cladding layer 13A made of _0.9 N is grown.

Next, on the upper surface of the first n-type cladding layer 13A, the first optical guide layer 14 made of GaN having a film thickness of 0.1 μm and the quantum well activity made of In _0.20 Ga _0.80 N having a film thickness of 3 nm. The layer 15 and the second light guide layer 16 made of GaN having a thickness of 0.1 μm are sequentially grown. Then, the second
On the upper surface of the optical guide layer 16 of
A second n-type cladding layer 13B having the same composition as the above and having a film thickness of 20 nm as a diffusion suppressing layer is grown.

Next, on the upper surface of the second n-type clad layer 13B, a p-type clad layer 18 made of p-type Al _0.1 Ga _0.9 N having a film thickness of 0.3 μm and an impurity of Mg having a film thickness of 0.4 μm are formed. A p-type contact layer 19 made of p ⁺ -type GaN having a concentration of 1 × 10 ²⁰ cm ⁻³ is sequentially grown. Then, a film having a thickness of 80 n is formed on the upper surface of the p-type contact layer 19 by a sputtering method.
After the gallium absorption layer 22 made of silicon oxide of m is deposited, an annealing process is performed to form the p-type cladding layer 18
Also, the resistance of the p-type contact layer 19 is reduced.

Next, dry etching is performed on a part of the epitaxial substrate to expose the n-type contact layer 12, the n-side electrode 20 made of Ti / Au is selectively formed on the exposed surface, and at the same time, gallium is formed. After selectively removing the absorption layer 22, a width of 10 is formed on the upper surface of the p-type contact layer 19.
Striped p-side electrode 2 made of Ni / Au at μm
1 is formed. In addition, the first n-type cladding layer 13A, the first optical guide layer 14, the quantum well active layer 15, the second optical guide layer 16, the second n-type cladding layer 13B, the p-type cladding layer 18, and the p-type. Dry etching is performed on the contact layer 19 to form a resonator.

As described above, in this embodiment, the second n-type cladding layer 13B is already formed on the upper surface of the second optical guide layer 16 during the growth of the p-type cladding layer 18 and the subsequent annealing treatment. Therefore, the distance from the p-type clad layer 18 to the quantum well active layer 15 increases, and the p-type dopant from the p-type clad layer 18 becomes coulomb with the n-type dopant in the second n-type clad layer 13B. Since the electrically neutral atom pair is formed by the interaction, the diffusion to the active layer side is more strongly suppressed.

The characteristics of the semiconductor light emitting device configured as described above will be described below with reference to the drawings.

FIG. 5 shows a dopant profile of the semiconductor light emitting device according to this embodiment measured by the SIMS method. As shown in FIG. 5, a p-type dopant is formed in the active region formed by the optical guide layers 14 and 16 and the quantum well active layer 15 located at a depth of 0.72 μm to 0.92 μm from the upper surface of the epitaxial substrate. Of Mg does not diffuse and a steep dopant profile is obtained, and it can be seen that the second n-type cladding layer 13B effectively functions as a diffusion suppressing layer.

Further, in the semiconductor light emitting device according to this embodiment, even when a direct current is injected, only the spectrum of 420 nm which is the quantum level emission of the quantum well active layer 15 is observed from the time of low current injection. The injected carriers contribute only to the quantum level light emission of the quantum well active layer 15 made of InGaN, and also in the current-voltage characteristics, the quantum well active layer 15 is not an pn junction but an n-type. No significant increase in series resistance due to embedding in the clad layers 13A and 13B was confirmed, and the direct current was 20 mA.
In this case, a voltage value of about 6V was shown. Also here, the thickness of the second n-type cladding layer 13B is about 5 nm to 500 nm, which is about the diffusion length of holes, and preferably 10 nm to 80 n.
When m, blue-violet light having a wavelength of 420 nm can be obtained without causing an increase in threshold voltage.

As described above, in the semiconductor light emitting device according to the present embodiment, the active region is buried in the n-type cladding layer so that the p-type cladding layer is moved toward the active layer side of Mg, which is the p-type dopant. Since the diffusion is suppressed, a steep dopant profile can be easily and surely obtained, and the color purity and the luminous efficiency are significantly improved.

Ga is formed on the upper surface of the p-type contact layer 19.
Since it has the gallium absorption layer 22 that absorbs atoms,
By capturing Mg in the Ga atom vacancies, diffusion of Mg to the active layer side is further suppressed.

Further, since the second n-type cladding layer 13B serving as the diffusion suppressing layer is made of Al _0.1 Ga _0.9 N, AlG
Since aN has a larger crystal lattice binding force than GaN, M
The diffusion of g can be suppressed more effectively.

Although magnesium (Mg) is used as the p-type dopant in this embodiment as well, the present invention is not limited to this, and carbon (C), zinc (Zn) and beryllium (Be) are used.
May be used, and silicon (S
Although i) is used, it may be oxygen (O).

In addition, sapphire (crystal Al ₂ O
₃ ) was used, but silicon carbide (SiC) may be used.

Further, p shown in the first and second embodiments is used.
Since the method of suppressing the diffusion of the type dopant can easily perform excellent interface control of the pn junction in the GaN-based semiconductor,
Not only the light emitting device but also other electronic devices can be applied.

[0061]

According to the semiconductor manufacturing method of the present invention, the p-type dopant and the n-type dopant are electrically neutral in the second semiconductor layer co-doped with the p-type dopant and the n-type dopant. Third to form an atom pair
Since the diffusion of the p-type dopant contained in the semiconductor layer is suppressed, the distribution of the p-type dopant in the crystal becomes steep, and when the first semiconductor layer is the n-type, p-n excellent in interface control is obtained.
A bond can be formed.

In the method for manufacturing a semiconductor of the present invention, the second
When the thickness of the semiconductor layer is 5 nm or more and 500 nm or less, the p-type dopant is diffused to the first semiconductor layer side without increasing the series resistance value of the first semiconductor layer and the third semiconductor layer. Can be reliably suppressed.

The method of manufacturing a semiconductor according to the present invention comprises the steps of forming a fourth semiconductor layer that absorbs gallium atoms on the third semiconductor layer and performing heat treatment on the fourth semiconductor layer. If it is further provided, the p-type dopant is trapped in the vacancies formed by the gallium atoms of the third semiconductor layer being absorbed by the fourth semiconductor layer, so that the p-type dopant is transferred to the first semiconductor layer side. Can be further suppressed.

According to the first semiconductor device of the present invention,
In the diffusion suppressing layer in which the p-type dopant and the n-type dopant are co-doped, since the p-type dopant and the n-type dopant form an electrically neutral atom pair, p contained in the second cladding layer is included. Since the diffusion of the type dopant is suppressed, the distribution of the p-type dopant in the crystal becomes steep,
And the second clad layer form a pn junction excellent in interface control.

According to the second semiconductor device of the present invention,
In the n-type diffusion suppressing layer, p from the second cladding layer
Since the type dopant and the n-type dopant in the diffusion suppressing layer form an electrically neutral atom pair, and the diffusion suppressing layer suppresses diffusion of the p-type dopant toward the active layer side, p in the crystal is suppressed.
The distribution of the type dopant becomes steep, and the first cladding layer and the second cladding layer form a pn junction excellent in interface control.

In the second semiconductor device, when the thickness of the diffusion suppressing layer is equal to or smaller than the diffusion length of holes, the diffusion of the p-type dopant can be surely suppressed without hindering the injection of holes.

In the first or second semiconductor device, if the thickness of the diffusion suppressing layer is 5 nm or more and 500 nm or less, hole injection is not hindered, that is, the threshold voltage is not increased. The diffusion of the p-type dopant can be surely suppressed.

The first or second semiconductor device has a contact layer made of a p-type gallium nitride based semiconductor formed on the second cladding layer, and formed on the upper surface of the contact layer to absorb gallium atoms. When the gallium absorption layer is further provided, the p-type dopant is trapped in the vacancies formed by the gallium atoms of the second cladding layer being absorbed by the gallium absorption layer. Can be further suppressed.

In the first or second semiconductor device, when the p-type dopant is magnesium and the n-type dopant is silicon, a pn junction excellent in interface control can be reliably formed in the gallium nitride based semiconductor.

In the first or second semiconductor device, when the diffusion suppressing layer is made of Al _x Ga _1-x N (where 0 <x <1), Al _x Ga _1-x N has a crystal lattice. Since the bonding force is larger than that of GaN, the diffusion of the p-type dopant can be suppressed more effectively.

[Brief description of drawings]

FIG. 1 (a) is GaN according to a first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a configuration of a semiconductor light emitting device. (B) is a cross-sectional view showing a structure of a comparative GaN-based semiconductor light emitting device without a diffusion suppressing layer.

FIG. 2A is GaN according to the first embodiment of the present invention.
6 is a graph showing a dopant profile of a semiconductor light emitting device. (B) is a comparative G without a diffusion suppressing layer.
6 is a graph showing a dopant profile of an aN-based semiconductor light emitting device.

FIG. 3A is a GaN film according to the first embodiment of the present invention.
7 is a graph showing the emission spectrum intensity of the semiconductor light emitting device. (B) is a comparative GaN without a diffusion suppressing layer.
7 is a graph showing the emission spectrum intensity of the semiconductor light emitting device.

FIG. 4 is a configuration cross-sectional view showing a GaN-based semiconductor light emitting device according to a second embodiment of the present invention.

FIG. 5 is a graph showing a dopant profile of a GaN-based semiconductor light emitting device according to a second embodiment of the present invention.

[Explanation of symbols] 10 substrates 11 Low temperature buffer layer 12 n-type contact layer 13 n-type clad layer (first clad layer) 13A First n-type cladding layer 13B Second n-type cladding layer (diffusion suppressing layer) 14 First light guide layer 15 Quantum well active layer 16 Second light guide layer 17 Diffusion suppression layer 18 p-type clad layer (second clad layer) 19 p-type contact layer 20 n side electrode 21 p-side electrode 22 gallium absorption layer

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Isao Kidoguchi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Ryoko Miyanaga 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Satoshi Ueyama 1006 Kadoma, Kadoma-shi, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Masahiro Usu, 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Yusaburo Ban, 1006, Kadoma, Kadoma, Osaka Prefecture, Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-6-260680 (JP, A) JP-A-5-183189 (JP, A) JP-A-8-51235 (JP, A) JP-A-6-283825 (JP, A) JP-A-9-129926 (JP, A) JP-A-4-199587 (JP, A) (58) Fields investigated (Int. Cl. ⁷⁾ , DB name) H0 1L 33/00 H01S 5/00-5/50

Claims (7)

(57) [Claims] 1. A step of forming a first semiconductor layer made of an undoped or n-type gallium nitride based semiconductor on a substrate which is not lattice-matched with a gallium nitride based semiconductor, and an active layer is formed on the first semiconductor layer. And a step of forming a second semiconductor layer made of a gallium nitride based semiconductor on the active layer while co-doping a p-type dopant and an n-type dopant, and p-type on the second semiconductor layer. And a step of forming a third semiconductor layer made of a gallium nitride-based semiconductor. 2. The method for manufacturing a semiconductor according to claim 1, wherein the film thickness of the second semiconductor layer is 5 nm or more and 500 nm or less. 3. The method further comprises the steps of forming a gallium absorption layer made of SiO ₂ that absorbs gallium atoms on the third semiconductor layer, and performing heat treatment on the gallium absorption layer. The method for manufacturing a semiconductor according to claim 1, wherein 4. An n-type gallium nitride based semiconductor, an active layer made of a gallium nitride based semiconductor, a gallium nitride based semiconductor layer co-doped with a p-type dopant and an n-type dopant, and a p-type gallium nitride based semiconductor. A semiconductor device characterized by being sequentially stacked. 5. A first n-type gallium nitride based semiconductor
Clad layer, an active layer made of a gallium nitride-based semiconductor formed above the first clad layer, and gallium nitride formed above the active layer and co-doped with a p-type dopant and an n-type dopant. A semiconductor device comprising: a diffusion suppressing layer made of a system semiconductor; and a second clad layer made of a p-type gallium nitride based semiconductor formed above the diffusion suppressing layer. 6. A contact layer made of a p-type gallium nitride based semiconductor formed above the second cladding layer, and a gallium absorption layer formed on the upper surface of the contact layer and absorbing gallium atoms. The semiconductor device according to claim 5, wherein: 7. The diffusion suppressing layer comprises Al _x Ga _{1 -x} N
(However, 0 <x <1.) The semiconductor device according to claim 5, wherein: