JP2007305630A - Field effect transistor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure improved reliability by securing low resistance in a p-type semiconductor layer that becomes a channel, suppressing a collapse phenomenon, and stabilizing operation at high temperature, by controlling the amount of dopant impurities in the p-type semiconductor layer for composing a field effect transistor, and the interface level density between a p-type layer and a gate insulating film. <P>SOLUTION: The field effect transistor 1 comprises: a substrate 2; a p-type nitride-based compound semiconductor layer 3 that is formed on the substrate 2, and has a lattice constant differing from that of the substrate doped with p-type and n-type dopants; an insulating film 4 formed on the p-type nitride-based compound semiconductor layer 3; a source electrode S and a drain electrode D electrically connected to the p-type nitride-based compound semiconductor layer 3, for setting the p-type nitride-based compound semiconductor layer 3 to be a channel layer; and a gate electrode G formed on the insulating film 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a field effect transistor composed of a nitride compound semiconductor and a method for manufacturing the field effect transistor.

  Nitride-based compound semiconductors such as GaN, InGaN, AlGaN, and AlInGaN have a large band gap energy and a high heat-resistant temperature. Therefore, a semiconductor device using a nitride-based compound semiconductor has excellent high-temperature operating characteristics. For example, as a semiconductor device, a transistor includes a MOS (Metal Oxide Semiconductor) transistor and a HEMT (High Electron Mobility Transistor).

  By the way, when using a semiconductor as a device, a semiconductor layer having n-type conductivity, a semiconductor layer having p-type conductivity, or both of these semiconductor layers is required. Here, since the nitride-based compound semiconductor has a large band gap energy, the activation energy is relatively large even if a p-type dopant is doped to form a semiconductor layer having p-type conductivity. Therefore, the doped dopant is not activated at room temperature, and the activation rate is very small.

Here, magnesium (Mg) is generally used as the p-type dopant of the nitride-based compound semiconductor.
When growing a nitride compound semiconductor layer, generally, a metal organic chemical vapor deposition method (MOCVD method) and a molecular beam epitaxy method (MBE method) are used. In the former MOCVD method, bicyclopentadienyl magnesium (Cp ₂ Mg) is used as a p-type dopant. In the latter MBE method, metal magnesium (Mg) is used in addition to bicyclopentadienylmagnesium as a p-type dopant.

However, since the activation energy of Mg in the nitride-based compound semiconductor is as large as about 200 meV and the activation rate is as low as about 1%, the carrier concentration is 10 ¹⁷ even if doping is as high as 10 ¹⁹ cm ^−3. It is difficult to obtain a sufficient carrier concentration of about cm ⁻³ . Further, when the doping amount is increased to 10 ²⁰ cm ^{−3 in} order to obtain the carrier concentration, the doped magnesium enters the interstitial position and acts as a donor impurity to compensate. Furthermore, in the MOCVD method, a large amount of hydrogen is used as a carrier gas, and there is a problem that even if a p-type dopant is doped, the p-type dopant is inactivated by hydrogen passivation and it is difficult to obtain high-concentration carriers.

In addition, it has been reported that pyramid defects are generated when the Mg doping amount exceeds 10 ¹⁹ cm ⁻³ . On the other hand, if the Mg doping amount exceeds 10 ²⁰ cm ⁻³ , the surface morphology is deteriorated, and conversely, the resistance becomes high.

  Therefore, as a method of growing a semiconductor layer having a low resistance p-type conductivity, a special treatment is applied to the group III nitride of the nitride-based compound semiconductor layer having a high resistance to obtain a low resistance p-type semiconductor layer There are a method for manufacturing a semiconductor layer and a method for manufacturing a semiconductor layer which is a low-resistance p-type semiconductor layer by devising a crystal growth process.

  As a technique for obtaining a low-resistance p-type semiconductor layer by performing special treatment on the III-nitride of a nitride-based compound semiconductor layer with high resistance, a method using an electron beam irradiation or a method using a heat treatment has hitherto been used. Proposed. Japanese Patent Laid-Open No. 3-218625 (Patent Document 1) discloses a method of irradiating a low-energy electron beam to cut off the bond between hydrogen and p-type semiconductor contained in the crystal to form a low-resistance p-type semiconductor layer. Proposed.

  Japanese Patent No. 2785253 (Patent Document 2) discloses a step of etching a nitride compound semiconductor layer doped with a p-type dopant to form irregularities on the surface, and forming the irregularities, and then the nitride compound semiconductor. There has been proposed a method for obtaining a low-resistance p-type semiconductor layer by a step of annealing at a temperature of 400 ° C. or higher.

  In JP-A-11-186174 (Patent Document 3), by irradiating a nitride compound semiconductor layer with ultraviolet rays, a bond between a p-type dopant and hydrogen is separated to efficiently activate the dopant. be able to. At the same time, the effective carrier concentration can be increased by reducing vacancies acting as donors and compensating the p-type semiconductor layer. In addition, upon irradiation with ultraviolet rays, the p-type dopant can be sufficiently activated by heating in a temperature range of 50 ° C. to 400 ° C., which is lower than before. Further, it has been proposed that the center wavelength of the ultraviolet light is desirably 380 nm or less, and that a nitrogen atmosphere is desirable.

As described in Japanese Patent Laid-Open No. 5-183189 (Patent Document 4), hydrogen or hydrogen is generated as a method for manufacturing a semiconductor layer which is a low-resistance p-type semiconductor layer by devising a crystal growth process. A method is proposed in which heat treatment is performed in an atmosphere gas that does not contain hydride gas (such as NH ₃ ), and a portion of the hydrogen contained in the crystal is diffused out of the crystal to form a low-resistance p-type semiconductor layer. Has been. Japanese Patent Laid-Open No. 8-125222 (Patent Document 5) discloses a low-resistance p-type semiconductor layer by performing a cooling process after crystal growth in a gas atmosphere containing no hydrogen such as nitrogen or an inert gas. A method is disclosed.

JP-A-6-232451 (Patent Document 6) discloses a nitride-type compound semiconductor layer represented by Al _1-xy Ga _x In _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1). A method for producing a p-type nitride compound semiconductor layer by doping Mg in the range of 1 × 10 ¹⁷ m ⁻³ to 3 × 10 ²⁰ m ⁻³ after growth is disclosed. This method, by using the _{In x Al y Ga (1-} xy) N (0 <x <1,0 <y <1) layer as a buffer layer, relieve the strain of the p-type GaN layer grown thereon Thus, p-type GaN is produced as-grown by preventing deterioration of crystallinity. According to this method, Mg is doped in GaN at a concentration of 3 × 10 ²⁰ cm ⁻³ to produce p-type GaN having a carrier concentration of 5 × 10 ¹⁷ m ⁻³ .

JP-A-3-218625 Patent 2785253 JP-A-11-186174 JP-A-5-183189 JP-A-8-125222 JP-A-6-232451

When using Mg as a p-type dopant of a nitride-based compound semiconductor, there is a problem that Mg diffuses to other than a predetermined crystal. (APL55 (1989) pp. 1017-1019). Further, this diffusion may occur not only during the growth but also by an annealing process after the growth. Furthermore, the results of examining the memory effect adsorbed in the quartz reactor which is the reactor of the MOCVD apparatus are the results of Journal of Crystal Growth, Vol. 145 (1994) pp. 214-218. According to the paper, because Mg has a memory effect, even if a large amount of Cp ₂ Mg is introduced into the reactor in a short time, the Mg distribution in the GaN crystal does not become steep, and the dope is delayed. Has been.

Furthermore, in nitride-based compound semiconductors, there is no substrate that is lattice-matched with the layer, so when fabricating an epitaxial substrate, heteroepitaxial growth using a lattice-mismatched substrate made of sapphire, silicon carbide, or the like is unavoidable. Absent. As a result, the defect density in the crystal is about 10 ³ m ⁻² in the GaAs-based semiconductor, but a very large number of threading dislocations are generated in the nitride-based compound semiconductor, which is about 10 ⁹ m ^−2. There is a problem in that the dopant easily diffuses through the threading dislocations and a steep junction interface cannot be obtained.

  As a countermeasure, Japanese Patent Laid-Open No. 6-283825 uses an AlGaN layer having a larger band gap than GaN as an undoped layer as a diffusion suppressing layer.

  In Japanese Patent No. 3408413, in a gallium nitride based semiconductor, a p-type dopant and an n-type dopant are simultaneously doped on the n-type semiconductor layer side of the p-type semiconductor layer in a pn junction composed of a p-type semiconductor layer and an n-type semiconductor layer. By doing so, a pn junction having a steep doping profile can be formed in the gallium nitride semiconductor. This is because the p-type dopant and the n-type dopant are less likely to diffuse by forming an electrically neutral atom pair by Coulomb interaction.

  In a semiconductor device using a nitride-based compound semiconductor, when a p-type conductive semiconductor layer is used, it is difficult to obtain a low-resistance semiconductor layer because it is difficult to adjust the doping, as described above. In addition, the dopant doped in the semiconductor layer is diffused. Further, when the dopant diffuses, the dopant may segregate on the surface of the p-type conductive semiconductor layer. The segregated acceptor impurity deteriorates the surface state between the insulating film and the semiconductor and forms interface states, thereby deteriorating device characteristics.

In addition, since the acceptor impurity is deep in energy in the acceptor, the acceptor impurity that is not activated is activated during high-temperature operation, which causes the characteristics to become unstable.
Furthermore, when the acceptor is doped at a high concentration, the acceptor does not enter the atomic site where it should originally enter, and causes a deterioration of characteristics because crystal defects are formed.

  Therefore, the problem to be solved by the present invention is to control the amount of dopant impurities in the p-type semiconductor layer constituting the field-effect transistor and the interface state density between the p-type layer and the gate insulating film, thereby making the field-effect transistor A field effect transistor having good reliability while suppressing the deterioration of characteristics while ensuring the conductivity of the p-type semiconductor layer serving as the channel of the channel and further stabilizing the operation at a high temperature, and a method of manufacturing such a field effect transistor Is to realize.

  The present invention includes a substrate, a p-type nitride-based compound semiconductor layer having a lattice constant different from that of the substrate formed on the substrate and doped with a p-type dopant and an n-type dopant, and the p-type dopant. An insulating film formed on the nitride-based compound semiconductor layer, and a source electrically connected to the p-type nitride-based compound semiconductor layer so that the p-type nitride-based compound semiconductor layer serves as a channel layer A field effect transistor having an electrode and a drain electrode, and a gate electrode formed on the insulating film.

Preferably, the ratio of the doping concentration of the p-type dopant and the n-type dopant is approximately 2: 1.

Preferably, the doping concentration of the p-type dopant is 2 × 10 ¹⁶ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ .

In the field effect transistor of the present invention, the p-type nitride compound semiconductor layer is made of Al _{1 -xy} Ga _x In _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1).

  In the field effect transistor of the present invention, the p-type dopant is one or more of Be, Mg, Ca, Sr, Ba, Ra, Zn, Cd, and Hg, and the n-type dopant is C, Si. , Ge, Sn, Pb, O, S, Se, Te, Po.

In the field effect transistor of the present invention, the insulating film is a layer made of an oxide of SiO ₂ , Al ₂ O ₃ , Ga ₂ O ₃ , MgO, Sc ₂ O ₃ , Gd ₂ O ₃ , Si ₃ N ₄ , AlN. , SiON, and AlON nitride layers.

  According to another aspect of the invention, there is provided a step of forming a p-type nitride compound semiconductor layer on a substrate while simultaneously doping an n-type dopant together with a p-type dopant, and the p-type nitride compound semiconductor layer. Forming an insulating film thereon; and a source electrode and a drain electrode so as to be electrically connected to the p-type nitride compound semiconductor layer so that the p-type nitride compound semiconductor layer serves as a channel layer And a step of forming a gate electrode on the insulating film.

  Preferably, the method further includes a step of performing a heat treatment for activating the dopant doped in the p-type nitride compound semiconductor layer.

  The field effect transistor of the present invention can realize a good reliability by suppressing the collapse phenomenon and stabilizing the operation at high temperature while ensuring the low resistance of the p-type semiconductor layer serving as a channel. In addition, according to the method of manufacturing a field effect transistor of the present invention, while maintaining the conductivity of the p-type semiconductor layer serving as a channel, the deterioration of characteristics is suppressed, the operation at high temperature is stabilized, and good reliability is achieved. A field effect transistor can be manufactured.

FIG. 1 shows a schematic cross-sectional view of a field effect transistor 1 of the present invention.
The field effect transistor 1 shown in FIG. 1 has a substrate 2 and a p-type nitride compound semiconductor layer 3 formed on the substrate. The lattice constants of the substrate 2 and the p-type nitride compound semiconductor layer 3 are different from each other.

Here, the p-type nitride-based compound semiconductor layer 3 becomes a channel layer of the field effect transistor 1, and the channel layer has a predetermined length. Each of the one end and the other end of the predetermined length of the channel layer that serves the p-type nitride-based compound semiconductor layer 3 of the channel, n ⁺ source layer 31s, n ⁺ drain layer 31d are formed as a contact layer The source electrode S is formed on the n ⁺ source layer 31s, and the drain electrode D is formed on the n ⁺ drain layer 31d.

  An insulating film 4 is formed on the p-type nitride compound semiconductor layer 3 with the source electrode S and the drain electrode D interposed therebetween. By forming the gate electrode G on the insulating film 4, the insulating film 4 can serve as a gate insulating film of the field effect transistor 1.

  Here, although the p-type nitride compound semiconductor layer 3 has p-type conductivity, the p-type nitride compound semiconductor layer 3 is doped with an n-type dopant together with a p-type dopant. . By doing so, the resistance of the p-type nitride compound semiconductor layer 3 can be reduced, and uniform doping is also possible.

  Furthermore, since the activation energy can be lowered by doping the n-type dopant at the same time as doping the p-type dopant, a high concentration of carriers with a smaller doping amount than doping the p-type dopant alone. Can be obtained. By reducing the doping amount of the p-type dopant, carrier scattering by the dopant can be reduced in the p-type nitride-based compound semiconductor layer 3 serving as a channel layer. Thereby, the mobility of carriers in the channel layer is improved, and the field effect transistor 1 can be operated at high speed.

  Further, by doping the n-type dopant simultaneously with the p-type dopant, the acceptor level becomes shallow, so that holes are easily emitted from the dopant regardless of the temperature. Therefore, the temperature characteristics of the field effect transistor 1 are improved. Further, since the acceptor level becomes shallow, even if the control width of the voltage applied to the gate electrode G formed on the insulating film 4 on the p-type nitride compound semiconductor layer 3 is small, the p-type An inversion layer is easily formed on the nitride-based compound semiconductor layer 3.

Here, Japanese Patent Laid-Open No. 10-101396 (Science and Technology Promotion Agency) states that Mg and Si are 2: 1, or Mg and O is 2: 1, or Be and Si are 2: 1, or Be and O are A method is disclosed in which the carrier concentration is increased by co-doping GaN at a ratio of 2: 1 to about 1 × 10 ¹⁸ to 1 × 10 ²⁰ m ⁻³ . In this method, a complex composed of two acceptor impurity atoms and one donor impurity atom is formed in the base crystal (in this case, GaN), so that the impurity level (acceptor level) becomes shallow. Since the solid solubility limit of the acceptor impurity is increased, a p-type semiconductor layer having a high carrier concentration and a low resistance can be formed.

  Japanese Patent Laid-Open No. 10-144960 discloses doping Si and Mg at a Si / Mg ratio of 1/10 or more and 1/1 or less, and Japanese Patent Laid-Open No. 10-1554829 discloses O / Mg as 1 / It is described that the same effect as in the above-mentioned JP-A-10-101696 can be obtained by doping with an O / Mg ratio of 10 or more and 1/1 or less. Further, JP-A 2000-294880 describes that doping with O and Zn at an O / Zn ratio of 1/5 or more and 1/2 or less provides the same effect as that of JP-A-10-101396. Has been.

  As described above, the p-type nitride compound semiconductor layer 3 used in the field effect transistor 1 is doped with the n-type dopant together with the p-type dopant, whereby the p-type nitride compound semiconductor layer 3 is obtained. Can be reduced in resistance.

  An insulating film 4 is formed on the p-type nitride-based compound semiconductor layer 3, but diffusion is suppressed by doping donor impurities as well as acceptor impurities, and the p-type nitride-based compound semiconductor layer 3. The dopant doped therein is difficult to segregate on the surface. That is, since the dopant hardly segregates at the interface between the p-type nitride-based compound semiconductor layer 3 and the insulating film 4, the interface state is deteriorated and interface states are not easily formed.

  Here, the lattice constants of the substrate 2 and the p-type nitride compound semiconductor layer 3 are different from each other. Therefore, a very large number of threading dislocations are generated in the p-type nitride compound semiconductor layer 3, and the p-type dopant may easily diffuse through the threading dislocations. However, since the p-type nitride compound semiconductor layer 3 is doped with the n-type dopant together with the p-type dopant, the p-type dopant is less likely to move within the p-type nitride compound semiconductor layer 3. There is little risk of spreading.

The difference in doping concentration of the doped p-type dopant and n-type dopant in the nitride-based compound semiconductor layer 3 is desirably ^{1 × 10 15 cm -3 ~1 ×} 10 17 cm -3. By setting to such a range, the threshold voltage V _th for turning on the field effect transistor 1 can be set low. In addition, an excessive threshold voltage shift can be suppressed by reducing the interface state.

In addition, as a specific semiconductor material of the p-type nitride-based compound semiconductor layer 3, Al _1-xy Ga _x In _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) can be used. By doing so, the lattice constant and the band gap energy can be easily adjusted, and the degree of freedom in design is improved. At this time, the substrate 2 can be a Si, sapphire, SiC, ZnO, or GaN substrate.

The thickness of the p-type nitride compound semiconductor layer 3 is preferably in the range of 0.1 to 5 μm. In the case of 0.1 μm or less, if the concentration of the p-type dopant is 1 × 10 ¹⁷ cm ⁻³ or less, the space charge layer extends from the surface and the substrate side, and it is difficult to obtain a desired carrier concentration. . In the case of 0.1 μm or less, the influence of crystal defects due to the difference in lattice constant between the substrate 2 and the p-type nitride-based compound semiconductor layer 3 hardly occurs, and the effect of the present invention hardly appears. In the case of 5 μm or more, the influence of crystal defects due to the difference in the lattice constant between the substrate 2 and the p-type nitride compound semiconductor layer 3 becomes remarkable, and the effect of the present invention is hardly exhibited.

  The p-type dopant of the p-type nitride compound semiconductor layer 3 is an IIB group element. That is, when the nitride-based compound semiconductor layer 3 is doped with a group IIB element, the element enters the N site constituting the nitride-based compound semiconductor.

  The n-type dopant of the p-type nitride-based compound semiconductor layer 3 is an IVB group element. That is, when the nitride-based compound semiconductor layer 3 is doped with a group IVB element, the element enters the Ga site constituting the nitride-based compound semiconductor, and attracts each other with a group II element and N through Coulomb force. Work. Therefore, n-type dopants are also difficult to diffuse in the same manner as p-type dopants.

  Specifically, the p-type dopant is one or more of Be, Mg, Ca, Sr, Ba, Ra, Zn, Cd, and Hg, and the n-type dopant is C, Si, Ge, Sn, Pb, One or more types can be selected from O, S, Se, and Po.

The material of the insulating film 4 can be used by selecting one or more kinds from layers made of oxide or nitride. In the case where an oxide is used as the insulating film 4, SiO ₂ , Al ₂ O ₃ , Ga ₂ O ₃ , MgO, Sc ₂ O ₃ , and Gd ₂ O ₃ can be mentioned. In the case of using nitride as the insulating film 4, there can be mentioned Si ₃ N _4, AlN, SiON, an AlON.

  The material of the above insulating film 4 has a large band gap of 4 eV or more, and becomes a sufficient barrier against carriers flowing through the p-type nitride compound semiconductor layer 3 as a channel. In addition, since some of them have a high relative dielectric constant, when the above material is used for the insulating film 4 as a gate insulating film, the degree of modulation can be increased. Furthermore, since the dielectric breakdown voltage is high, the breakdown of the insulating film 4 can be prevented when a voltage is applied to the gate electrode G. Since these materials are inactive, the interface state density is low, and the interface between the insulating film 4 and the p-type nitride compound semiconductor layer 3 can be kept good.

The basic means for manufacturing the above field effect transistor 1 is to first form a p-type nitride-based compound semiconductor layer 3 on a substrate 2 while simultaneously doping an n-type dopant together with a p-type dopant. To do. Then, the insulating film 4 is formed on the p-type nitride compound semiconductor layer 3. After forming the insulating film 4, an n ⁺ layer (n ⁺ source layers 31s, n ⁺ is formed on a part of the p type nitride compound semiconductor layer 3 in order to use the p type nitride compound semiconductor layer 3 as a channel layer. The field effect transistor 1 is formed by forming the drain layer 31d), forming the source electrode S and the drain electrode D so as to be electrically connected to the n ⁺ layer, and forming the gate electrode G on the insulating film 4. Complete.

  Further, in order to activate the dopant in the p-type nitride-based compound semiconductor layer 3 doped with the n-type dopant together with the p-type dopant, a heat treatment is performed after the p-type nitride-based compound semiconductor layer 3 is formed. It is desirable to do.

When the n ⁺ type nitride compound semiconductor layer in contact with the p type nitride compound semiconductor layer 3 is provided, a part of the p type nitride compound semiconductor layer 3 is etched, and n is etched in the etched portion. ^{A +} type nitride compound semiconductor layer may be embedded. Further, instead of providing an n ⁺ type nitride compound semiconductor layer at a location where the source electrode S and drain electrode D are formed, the p type nitride compound semiconductor layer 3 of the part is made to be n ⁺ type. Anyway. For this purpose, an n-type impurity is doped at that location by ion implantation or thermal diffusion.

  By doing so, the ohmic resistance between the source electrode S and drain electrode D and the semiconductor layer can be reduced. The n-type nitride-based compound semiconductor layer can also be formed by regrowth, and n-type ions are implanted into a part of the p-type nitride-based compound semiconductor layer 3 or diffused by thermal diffusion. It can also be formed.

  The characteristics of the field effect transistor 1 using the p-type nitride-based compound semiconductor layer 3 as a channel layer are so-called that no current flows between the source electrode S and the drain electrode D when no voltage is applied to the gate electrode G. Normally off type.

For example, by reducing the thickness of the p-type nitride-based compound semiconductor layer 3 in the region corresponding to the portion immediately below the insulating film 4 where the gate electrode G is formed, the pinch-off voltage V _T increases. Therefore, the p-type nitride-based compound semiconductor layer 3 is depleted when no voltage is applied to the gate electrode. Thereby, in a state where no voltage is applied to the gate electrode G, a field effect transistor that performs a so-called normally-off operation in which no current flows between the source electrode S and the drain electrode D can be realized. Further, the threshold voltage can be controlled by changing the p-type dopant and the n-type dopant concentration.

Example 1
FIG. 2 shows a schematic cross-sectional view of the field effect transistor 1 according to the first embodiment.
In the field effect transistor 1 shown in FIG. 2, a buffer layer 21 made of GaN or AlN having a thickness of 50 nm is formed on a substrate 2 made of Si, SiC or sapphire. On the buffer layer 21, a layer made of GaN having a thickness of 2 nm is formed as the p-type nitride-based compound semiconductor layer 3.

On the p-type nitride compound semiconductor layer 3, a SiO ₂ thin film having a thickness of 100 nm is formed as a gate insulating film 4, and a gate electrode G made of Ni is formed on the insulating film 4. An n ⁺ source layer 31 s and an n ⁺ drain layer 31 d are formed as contact layers on the p-type nitride compound semiconductor layer 3 on both sides of the gate insulating film 4, and on the n ⁺ source layer 31 s. A source electrode S is formed, and a drain electrode D is formed on the n ⁺ drain layer 31d.

A process of manufacturing the field effect transistor 1 having the above configuration will be described.
First, a GaN or AlN buffer layer 21 is deposited on the SiC or sapphire substrate 2 by MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy). On top of this, p-type nitride compound semiconductor layer 3 is formed as p-type nitride compound semiconductor layer 3 while simultaneously doping Si as n-type impurities and Mg as p-type impurities at 5 × 10 ¹⁶ cm ⁻³ and 1 × 10 ¹⁷ cm ⁻³ respectively. A GaN layer is deposited (see FIG. 3A).

The GaN layer deposition temperature is about 1100 ° C. in the MOCVD method, about 900 ° C. in the MBE method, and the growth rate is 1 μm / h. The reason why the deposition temperature in the MOCVD method is higher than that in the MBE method is to avoid mixing carbon impurities from the organic metal raw material TMGa (trimethylgallium) into the crystal. In the MBE growth, Ga, which is a metal raw material, is heated by a Knudsen cell and evaporated to directly supply the substrate surface, so that no carbon impurities are mixed from the raw material. As the group V nitrogen source, ammonia (NH ₃ ) may be used in the MOCVD method, and ammonia (NH ₃ ) or nitrogen (N ₂ ) may be decomposed into nitrogen radical species by high-frequency plasma in the MBE method. .

  Subsequently, an AlN thin film to be the gate insulating film 4 is deposited. The deposition conditions are as low as a substrate temperature of 550 ° C. or lower, and an amorphous AlN gate insulating film 4 can be formed by using trimethylaluminum (TMA) for the MOCVD method and metal aluminum for the MBE method. In addition, by depositing an AlGaN film or an AlGaN layer with an inclined Al composition between the p-type nitride-based compound semiconductor layer 3 and the insulating film 4, an AlN gate insulating film having good crystallinity at a high temperature can be obtained. Deposition is also possible.

Note that SiO ₂ may be used as the gate insulating film 4 instead of AlN. In this case, deposition conditions below the low substrate temperature 300 ° C., as the SiO ₂ material, silane (SiH ₄₎ or TEOS (tetraethyl orthosilicate) and PECVD method using NO ₂ gas (plasma enhanced chemical vapor deposition) It becomes possible to form a SiO ₂ gate insulating film.

Next, the substrate is taken out from the growth chamber, and a SiO ₂ film serving as a mask layer is deposited by PECVD (plasma chemical vapor deposition). Another gate insulating film material may be laminated on the AlN thin film under the mask layer. Next, the AlN film layer exposed from the opening of the mask layer is etched by RIE (reactive ion etching method). After the etching, in order to form the n ⁺ source layer 31s and the n ⁺ drain layer 31d that are in contact with the source electrode S and the drain electrode D, silicon (Si) is dosed to the p-type layer in the mask opening by an ion implantation method. Implantation is performed at × 10 ¹⁵ cm ^-2 and an acceleration voltage of 65 keV. Thereby, an n ⁺ source layer 31s and an n ⁺ drain layer 31d are formed (see FIG. 3B). However, the ion-implanted impurity is not activated at this time. In order to improve the activation rate of Si atoms to be introduced, the substrate may be maintained at a high temperature during ion implantation.

Next, after removing the mask layer with BHF, a SiO ₂ film is formed again. As a result, the entire wafer surface is covered with the SiO ₂ film. Next, annealing is performed at 1100 ° C. for 5 minutes in a nitrogen (N ₂ ) atmosphere. Thereby, the ion-implanted Si atom is activated. After the annealing, the SiO ₂ film as a mask layer is removed with an HF aqueous solution.

At this time, in order to further improve the activation rate of the ion-implanted Si atoms, an AlN film having a heat resistance higher than that of SiO ₂ is formed, and then annealed at 1300 ° C. for 1 minute in a nitrogen atmosphere. Also good. After annealing, the AlN film is removed with a KOH aqueous solution.
Next, openings for the source electrode S and the drain electrode D are formed by a photoresist process. Ti and Al are sequentially deposited on the n ⁺ source layer 31s and the n ⁺ drain layer 31d exposed from the opening by EB vapor deposition (electron beam vapor deposition) to form the source electrode S and the drain electrode D.

Thereafter, annealing is performed on the source electrode S and the drain electrode D for 10 minutes at 600 ° C. in a nitrogen atmosphere. An ohmic contact is obtained by annealing after the deposition. Next, an n-type conductive polysilicon film is formed on the gate insulating film 4 formed on the p-type nitride semiconductor layer 3. The n-type conductive polysilicon film can be formed by using silane (SiH ₄ ) or TEOS as the Si material and depositing it by sputtering or LPCVD.

P can be used as a doping material for n-type conductivity, and phosphine (PH ₃ ) or POCl ₃ is used as a P raw material, and a polysilicon film is doped during or after deposition. Thereafter, the gate electrode region is patterned by a photoresist process, and polysilicon other than the gate electrode region is removed by RIE (reactive ion etching method) using SF ₆ gas. Thereafter, Ti / Mo / Au is deposited as a pad electrode by EB vapor deposition to form a gate electrode. Note that vapor deposition may be performed by resistance heating vapor deposition, sputtering, or the like. Thus, the field effect transistor 1 shown in FIG. 2 is completed.

(Example 2)
FIG. 4 shows a schematic cross-sectional view of the field effect transistor 1 according to the second embodiment.
The field effect transistor 1 according to the second embodiment has the same structure as the field effect transistor 1 according to the first embodiment shown in FIG. However, in the field effect transistor 1 of Example 2, the 2.5 nm of the Al composition of 0.2 is formed on the p-type nitride compound semiconductor layer 3 of GaN of the field effect transistor 1 of Example 1. An n-type AlGaN layer 32 having a thickness is formed. Further, the n ⁺ source layer 31s and the n ⁺ drain layer 31d are not formed.

  Further, since the n-type AlGaN layer 32 is 2.5 nm, the p-type nitride-based compound semiconductor at the location where the insulating film 4 is formed in a state where no voltage is applied to the gate electrode G. A depletion layer is generated in the layer 3, and no current flows between the source electrode S and the drain electrode D. That is, the field effect transistor 1 shown in FIG. 4 is a normally-off type field effect transistor. Further, in the field effect transistor 1 in the second embodiment, the insulating film 4 made of SiN is used instead of the insulating film 4 made of AlN in the field effect transistor 1 in the first embodiment.

  The process of manufacturing the field effect transistor 1 of the second embodiment having such a configuration is common to the field effect transistor 1 of the first embodiment. However, after depositing the p-type nitride compound semiconductor layer 3 made of GaN, the AlGaN layer 32 is deposited.

Then, a SiN film of about 20 nm is deposited as the insulating film 4 on the AlGaN layer 32 by a Cat-CVD method (catalytic chemical vapor deposition method). In the Cat-CVD method, the surface damage layer by dry etching is removed by flowing a hydrogen gas and performing a surface cleaning process before deposition. Next, a part of the deposited SiN film is removed by a photoresist process, a Ti—Al—Ni—Au electrode is formed by an electron beam evaporation method, and then an annealing process is performed at 800 ° C. for 2 minutes in a nitrogen atmosphere. Get sexual contact. Finally, Ni—Pt—Au is formed on the insulating film 4 by an electron beam evaporation method, and a Schottky electrode is manufactured, thereby forming the gate electrode G.
Through the above steps, the field effect transistor 1 shown in FIG. 4 can be manufactured.

(Example 3)
FIG. 5 shows a schematic cross-sectional view of the field effect transistor 1 according to the third embodiment.
The field effect transistor 1 in the third embodiment has the same structure as the field effect transistor 1 in the first embodiment shown in FIG. However, in the field effect transistor 1 in the first embodiment shown in FIG. 2, the n ⁺ source layer 31s and the n ⁺ drain layer 31d are formed as the contact layers by the ion implantation method, whereas the field effect in the third embodiment. The transistor 1 is different in that an n ⁺ source layer 31 s and an n ⁺ drain layer 31 d are formed as n-type GaN layers selectively regrown as contact layers.

The process of manufacturing the field effect transistor 1 of the third embodiment having such a configuration is common to the field effect transistor 1 of the first embodiment. However, after the deposition of the p-type nitride-based compound semiconductor layer 3 is completed, a part of the p-type nitride-based compound semiconductor layer 3 corresponding to the position where the source electrode S and the drain electrode D are formed is removed. It is removed by dry etching by a photoresist process, and then introduced into an MBE apparatus, and an Si-doped n-type GaN layer is selectively deposited on the portion removed by etching, and an n ⁺ source layer 31 s and an n ⁺ drain layer 31 d Form.

Thereafter, it is taken out from the MBE apparatus, and a SiO ₂ film is deposited on the entire surface of the wafer by PECVD. Next, an insulating film 4 is formed by removing a part of the SiO ₂ film using a photoresist process. Then, Ti—Al—Ni—Au electrodes to be the source electrode S and the drain electrode D are formed by an electron beam evaporation method, and then an annealing process is performed at 800 ° C. for 2 minutes in a nitrogen atmosphere to obtain ohmic contact. Finally, Ni—Pt—Au is formed on the insulating film 4 by the electron beam evaporation method, and the gate electrode G is formed. The gate electrode may be made of n-type polysilicon and Ti / Mo / Au as shown in the first embodiment.
Through the above steps, the field effect transistor 1 shown in FIG. 5 can be manufactured.

1 is a schematic cross-sectional view of a field effect transistor of the present invention. 1 is a schematic cross-sectional view of a field effect transistor according to an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The schematic sectional drawing which shows the manufacturing process of the field effect transistor about the Example of this invention is shown. FIG. 3 is a schematic sectional view of a field effect transistor according to another embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a field effect transistor according to still another embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Field effect transistor, 2 ... Substrate, 3 ... P-type nitride compound semiconductor layer, 4 ... Insulating film

Claims (8)

A substrate,
A p-type nitride-based compound semiconductor layer having a lattice constant different from that of the substrate formed on the substrate and doped with an n-type dopant together with a p-type dopant;
An insulating film formed on the p-type nitride compound semiconductor layer;
A source electrode and a drain electrode electrically connected to the p-type nitride-based compound semiconductor layer so that the p-type nitride-based compound semiconductor layer serves as a channel layer;
A gate electrode formed on the insulating film;
A field effect transistor.   2. The field effect transistor according to claim 1, wherein a ratio of a doping concentration of the p-type dopant to the n-type dopant is approximately 2: 1. 3. The field effect transistor according to claim 1, wherein a doping concentration of the p-type dopant is 2 × 10 ¹⁶ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . 4. The p-type nitride-based compound semiconductor layer is made of Al _1-xy Ga _x In _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1). 5. Field effect transistor.   The p-type dopant is one or more of Be, Mg, Ca, Sr, Ba, Ra, Zn, Cd, and Hg, and the n-type dopant is C, Si, Ge, Sn, Pb, Og. The field effect transistor according to any one of claims 1 to 4, wherein the field effect transistor is one or more of S, Se, Te, Te, and Po. The insulating film is made of SiO ₂ , Al ₂ O ₃ , Ga ₂ O ₃ , MgO, Sc ₂ O ₃ , Gd ₂ O ₃ oxide layer, Si ₃ N ₄ , AlN, SiON, AlON nitride. The field effect transistor according to any one of claims 1 to 5, wherein the field effect transistor is configured by one or more types of layers. Forming a p-type nitride-based compound semiconductor layer on a substrate while simultaneously doping an n-type dopant together with a p-type dopant;
Forming an insulating film on the p-type nitride compound semiconductor layer;
Forming a source electrode and a drain electrode so as to be electrically connected to the p-type nitride-based compound semiconductor layer so that the p-type nitride-based compound semiconductor layer serves as a channel layer;
Forming a gate electrode on the insulating film;
A method of manufacturing a field effect transistor having   8. The method of manufacturing a field effect transistor according to claim 7, further comprising a step of performing a heat treatment for activating a dopant doped in the p-type nitride compound semiconductor layer.

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