JP3376862B2 - Mounting method of work with bump - Google Patents
Mounting method of work with bumpInfo
- Publication number
- JP3376862B2 JP3376862B2 JP19354097A JP19354097A JP3376862B2 JP 3376862 B2 JP3376862 B2 JP 3376862B2 JP 19354097 A JP19354097 A JP 19354097A JP 19354097 A JP19354097 A JP 19354097A JP 3376862 B2 JP3376862 B2 JP 3376862B2
- Authority
- JP
- Japan
- Prior art keywords
- work
- bumps
- bond
- substrate
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、フリップチップな
どのバンプ付きワークをフィラー入りのボンドで基板に
接着するバンプ付きワークの実装方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a work with bumps, such as a work with bumps such as a flip chip, which is bonded to a substrate by a bond containing a filler.
【０００２】[0002]
【従来の技術】フリップチップなどのバンプ付きワーク
を基板に実装する場合、バンプ付きワークのバンプを基
板の電極に位置合わせしてバンプ付きワークを基板に搭
載した後、バンプ付きワークと基板の間にフィラー入り
のボンドを注入し、ボンドを硬化させることにより、バ
ンプ付きワークを基板に実装することが行われる。2. Description of the Related Art When mounting a work with bumps such as a flip chip on a substrate, the bumps of the work with bumps are aligned with the electrodes of the substrate and the work with bumps is mounted on the substrate. A work with bumps is mounted on a substrate by injecting a bond containing a filler into and hardening the bond.
【０００３】ボンドはバンプ付きワークを基板にしっか
り接着して実装するために注入されるものである。また
バンプ付きワークと基板の熱膨張係数には大きな差異が
あるので、ヒートサイクルによってバンプが基板の電極
から剥がれるおそれがあることから、ボンドにフィラー
を混入することにより、バンプ付きワークと基板の間に
介在するボンドの熱膨張係数を調整し、ヒートサイクル
に対する耐久性を向上させるものである。Bonds are injected to firmly bond and mount a work having bumps on a substrate. Also, since there is a large difference in the coefficient of thermal expansion between the work with bumps and the substrate, the bumps may peel off from the electrodes on the substrate due to the heat cycle. It adjusts the thermal expansion coefficient of the bond intervening in, and improves the durability against heat cycles.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら従来方法
は、ボンドは、バンプ付きワークを基板に搭載した後、
バンプ付きワークと基板の間に注入されていたため、注
入作業にかなりの時間を要して生産性があがらず、また
注入不足によりバンプ付きワークと基板の間に空隙が生
じやすく、この空隙によりボンドの接着力が低下した
り、あるいはヒートサイクルによる空隙内の空気の熱膨
張により硬化したボンドが破壊され、さらには空隙が基
板の電極付近に生じると、その空気により電極が腐食す
るなどの問題点があった。However, in the conventional method, the bonding is performed after mounting the bumped work on the substrate.
Since it was injected between the work with bumps and the substrate, the injection work took a considerable amount of time to reduce productivity, and a gap between the work with bumps and the substrate was apt to occur due to insufficient injection, and this bond created a bond. If the bond strength of the adhesive is reduced, or the cured bond is destroyed by the thermal expansion of air in the void due to heat cycle, and if voids occur near the electrodes on the substrate, the air will corrode the electrodes. was there.
【０００５】したがって本発明は、上記従来方法の問題
点を解消し、バンプ付きワークをフィラー入りのボンド
で基板にしっかり接着して実装できるバンプ付きワーク
の実装方法を提供することを目的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above problems of the conventional method and to provide a mounting method for a bumped work which can be mounted by firmly bonding the bumped work to a substrate with a bond containing a filler.
【０００６】[0006]
【課題を解決するための手段】本発明のバンプ付きワー
クの実装方法は、基板の上面に電気絶縁性のフィラーが
混入されたボンドを塗布した後、バンプ付きワークのバ
ンプを基板の電極に位置合わせし、バンプから突出する
テールの尖った下端部でボンドを突き刺しながらバンプ
付きワークを基板に搭載してバンプを前記電極に着地さ
せ、次いでボンドを硬化させてバンプ付きワークを基板
に接着するようにした。According to the method of mounting a work with bumps of the present invention, after a bond containing an electrically insulating filler is applied to the upper surface of the substrate, the bumps of the work with bump are positioned on the electrodes of the substrate. The bumped work piece is mounted on the substrate and the bump is landed on the electrode while piercing the bond with the sharp lower end of the tail protruding from the bump.
So, then curing the bond was to adhere the bumped work on the substrate.
【０００７】[0007]
【発明の実施の形態】上記構成において、バンプ付きワ
ークは基板にボンドを塗布した後に基板に搭載するが、
この場合、バンプのテールの下端部は尖っているので、
テールはフィラーに阻害されることなくボンドにスムー
ズに突き刺され、電極に着地することができる。またボ
ンドはバンプ付きワークを基板に搭載する前に基板に塗
布されるので、ボンド不足による空隙の発生を解消し、
バンプ付きワークを基板にしっかり接着できる。BEST MODE FOR CARRYING OUT THE INVENTION In the above structure, the work with bumps is mounted on the substrate after applying the bond to the substrate.
In this case, the lower end of the bump tail is sharp, so
The tail can be smoothly pierced by the bond without being hindered by the filler and land on the electrode. In addition, the bond is applied to the substrate before mounting the work with bumps on the substrate, eliminating the occurrence of voids due to insufficient bond,
Work with bumps can be firmly attached to the substrate.
【０００８】以下、本発明の実施の形態を図面を参照し
て説明する。図１は、本発明の一実施の形態のワークに
形成されたバンプの断面図、図２は同バンプ付きワーク
の実装工程図、図３は同バンプ付きワークのバンプがボ
ンド中を下降中の拡大断面図、図４は同バンプ付きワー
クのバンプの実装後の拡大断面図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of bumps formed on a work according to an embodiment of the present invention, FIG. 2 is a mounting process diagram of the work with bumps, and FIG. 3 is a bump of the work with bumps descending during bonding. FIG. 4 is an enlarged cross-sectional view of the same work with bumps after mounting the bumps.
【０００９】図１は、本発明で用いられるバンプを示し
ている。ワーク１の表面にはバンプ２が形成されてい
る。ワーク１は、例えばウェハから切り出されたチップ
である。バンプ２はテール３を有している。テール３の
先端部は尖っており、その側面はテーパ面４になってい
る。このようなテール３を有するバンプ２は、ワイヤボ
ンディング技術を用いたワイヤバンプ法により形成でき
る。すなわちワイヤバンプ法では、ワイヤの下端部のボ
ールをワーク１に押し付けてボンディングした後、ワイ
ヤをクランパでクランプしてワイヤを上方へ引っ張り、
これによりワイヤを引きちぎるが、この場合、引きちぎ
り時のせん断力のために上記のようなテーパ面４を有す
る尖ったテール（ワイヤの切れはし）３が生じる。FIG. 1 shows a bump used in the present invention. Bumps 2 are formed on the surface of the work 1. The work 1 is, for example, a chip cut out from a wafer. The bump 2 has a tail 3. The tip of the tail 3 is sharp, and its side surface is a tapered surface 4. The bump 2 having such a tail 3 can be formed by a wire bump method using a wire bonding technique. That is, in the wire bump method, the ball at the lower end of the wire is pressed against the work 1 for bonding, and then the wire is clamped by a clamper to pull the wire upward,
This tears the wire, but in this case a sharp tail 3 (breaking wire) having the tapered surface 4 as described above occurs due to the shearing force at the time of tearing.
【００１０】次に、図２を参照してバンプ付きワークの
実装方法を説明する。図２の（ａ），（ｂ），（ｃ）
は、実装工程順に示している。まず、図２（ａ）に示す
ように、基板５の上面にボンド８を塗布する。６は基板
５の上面に形成された電極であり、その上面には半田部
７が形成されている。半田部７は、メッキ法やレベラ法
で形成されたプリコート部である。またボンド８にはフ
ィラー９が混入されている。フィラー９は、シリカやア
ルミナなどの電気絶縁性の粒子である。ボンド８は、ボ
ンド塗布器により塗布される。Next, a method of mounting a work with bumps will be described with reference to FIG. 2 (a), (b), (c)
Are shown in the order of mounting steps. First, as shown in FIG. 2A, the bond 8 is applied to the upper surface of the substrate 5. Reference numeral 6 is an electrode formed on the upper surface of the substrate 5, and a solder portion 7 is formed on the upper surface thereof. The solder portion 7 is a precoat portion formed by a plating method or a leveler method. In addition, a filler 9 is mixed in the bond 8. The filler 9 is an electrically insulating particle such as silica or alumina. The bond 8 is applied by a bond applicator.
【００１１】次に、図２（ｂ）に示すように、バンプ付
きワーク１のバンプ２を基板５の電極２に位置合わせ
し、バンプ付きワーク１を基板５に搭載する。バンプ付
きワーク１は、実装機の吸着ノズル１０に真空吸着され
て基板５に搭載される。また基板５は基台１１に載せら
れている。Next, as shown in FIG. 2B, the bumps 2 of the work 1 with bumps are aligned with the electrodes 2 of the substrate 5, and the work 1 with bumps is mounted on the substrate 5. The work 1 with bumps is vacuum-sucked by the suction nozzle 10 of the mounting machine and mounted on the substrate 5. The substrate 5 is mounted on the base 11.
【００１２】図３は、ノズル１１を下降させながらバン
プ付きワーク１を基板５に搭載する途中の状態を示して
いる。ボンド８中にはフィラー９が大量に混入されてい
るが、テール３の下端部は尖ってテーパ面４となってい
るので、テール３の下面にフィラー９が当ってもフィラ
ー９はテーパ面４により側方へ押し動かされる（矢印ａ
参照）。したがってテール３の下降がフィラー９に阻害
されることはなく、テール３はボンド８に突き刺されな
がらスムーズに下降する。そしてテール３の尖った下端
部は半田部７に突き刺さって下降し、図２（ｂ）に示す
ように電極６に着地する。なお半田部７は鉛とすずなど
の柔かい合金であり、またテール３はスタッドバンプ法
により形成される際に電気スパーク熱により焼きなまさ
れて硬度を増しているので、テール３は半田部７に難な
く突き刺し、電極６に着地させることができる。FIG. 3 shows a state where the work 1 with bumps is being mounted on the substrate 5 while the nozzle 11 is being lowered. A large amount of filler 9 is mixed in the bond 8, but since the lower end portion of the tail 3 is sharp and has a tapered surface 4, even if the lower surface of the tail 3 is hit by the filler 9, the filler 9 has a tapered surface 4. Is pushed to the side by arrow (arrow a
reference). Therefore, the lowering of the tail 3 is not hindered by the filler 9, and the tail 3 is smoothly lowered while being stabbed by the bond 8. Then, the sharp lower end portion of the tail 3 pierces the solder portion 7 and descends to land on the electrode 6 as shown in FIG. The solder portion 7 is made of a soft alloy such as lead and tin, and when the tail 3 is formed by the stud bump method, it is annealed by electric spark heat to increase its hardness. It is possible to pierce without difficulty and land on the electrode 6.
【００１３】次に吸着ノズル１０から熱Ｈを加え、熱硬
化性を有するボンド８を加熱して硬化させる（図２
（ｃ））。この場合、好ましくは、基板５を載置した基
台１１側からも熱Ｈを加える。なお吸着ノズル１０側や
基台１１側にはヒータが内蔵されている。また好ましく
は、半田部７をその溶融温度（一般に、１８３°Ｃ程
度）まで加熱し、半田部７を溶融固化させる。Next, heat H is applied from the suction nozzle 10 to heat and cure the thermosetting bond 8 (FIG. 2).
(C)). In this case, heat H is preferably applied also from the side of the base 11 on which the substrate 5 is placed. A heater is built in the suction nozzle 10 side and the base 11 side. Further, preferably, the solder portion 7 is heated to its melting temperature (generally about 183 ° C.) to melt and solidify the solder portion 7.
【００１４】図４は、以上のようにして基板５に実装さ
れたバンプ付きワーク１を示している。半田部７は溶融
固化したバンプ２まではい上り、バンプ２をしっかり半
田付けしている。またボンド８は硬化してバンプ付きワ
ーク１を基板５にしっかり接着している。FIG. 4 shows the work 1 with bumps mounted on the substrate 5 as described above. The solder portion 7 goes up to the melted and solidified bump 2, and the bump 2 is firmly soldered. Further, the bond 8 is hardened and the work 1 with bumps is firmly adhered to the substrate 5.
【００１５】なお上記実施の形態では、基板５の電極６
には半田部７を形成しているが、この半田部７は無くて
もよいものである。この場合も、バンプ付きワーク１の
バンプ２のテール３を上述した方法と同様の方法によ
り、そのテーパ面４でボンド８中のフィラー９を側方へ
押し動かしながらボンド８中を下降させて基板５の電極
６に着地させ、ボンド８を硬化させるとともに、テール
３と電極６に熱を加えてテール３を電極６に熱圧着す
る。In the above embodiment, the electrode 6 of the substrate 5 is used.
Although the solder portion 7 is formed in the above, the solder portion 7 may be omitted. In this case as well, the tail 3 of the bump 2 of the work 1 with bumps is moved in the same manner as described above while the filler 9 in the bond 8 is pushed laterally by the taper surface 4 thereof, and the inside of the bond 8 is lowered to lower the substrate. 5 is landed on the electrode 6 and the bond 8 is cured, and heat is applied to the tail 3 and the electrode 6 to thermocompress the tail 3 to the electrode 6.
【００１６】[0016]
【発明の効果】本発明によれば、バンプ付きワークは基
板にボンドを塗布した後に基板に搭載するが、この場
合、下端部の尖ったテールはフィラーに阻害されること
なくボンドにスムーズに突き刺され、確実に電極に着地
することができる。またボンドはバンプ付きワークを基
板に搭載する前に基板に塗布されるので、ボンド不足に
よる空隙の発生を解消し、バンプ付きワークを基板にし
っかり接着できる。According to the present invention, the work with bumps is mounted on the substrate after applying the bond to the substrate. In this case, the sharp tail at the lower end is pierced into the bond smoothly without being obstructed by the filler. Therefore, it is possible to reliably land on the electrode. In addition, since the bond is applied to the substrate before mounting the work with bumps on the substrate, the occurrence of voids due to insufficient bond can be eliminated, and the work with bumps can be firmly adhered to the substrate.
【図１】本発明の一実施の形態のワークに形成されたバ
ンプの断面図FIG. 1 is a cross-sectional view of a bump formed on a work according to an embodiment of the present invention.
【図２】本発明の一実施の形態のバンプ付きワークの実
装工程図FIG. 2 is a mounting process diagram of a work with bumps according to an embodiment of the present invention.
【図３】本発明の一実施の形態のバンプ付きワークのバ
ンプがボンド中を下降中の拡大断面図FIG. 3 is an enlarged cross-sectional view of a workpiece with bumps according to an embodiment of the present invention in which bumps are descending during bonding.
【図４】本発明の一実施の形態のバンプ付きワークのバ
ンプの実装後の拡大断面図FIG. 4 is an enlarged cross-sectional view after mounting the bumps of the work with bumps according to the embodiment of the present invention.
１ ワーク ２ バンプ ３ テール ４ テーパ面 ５ 基板 ６ 電極 ７ 半田部 ８ ボンド ９ フィラー 1 work 2 bumps 3 tails 4 Tapered surface 5 substrates 6 electrodes 7 Solder part 8 bond 9 Filler
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平９−167785（ＪＰ，Ａ) 特開 昭62−132331（ＪＰ，Ａ) 特開 平６−53279（ＪＰ，Ａ) 特開 平９−97816（ＪＰ，Ａ) 特開 平２−187048（ＪＰ，Ａ) 特開 平３−209840（ＪＰ，Ａ) 特開 平６−37144（ＪＰ，Ａ) 特開 平６−326153（ＪＰ，Ａ) 特開 平７−183338（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 21/56 H01L 23/30 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-9-167785 (JP, A) JP-A-62-132331 (JP, A) JP-A-6-53279 (JP, A) JP-A-9- 97816 (JP, A) JP-A-2-187048 (JP, A) JP-A-3-209840 (JP, A) JP-A-6-37144 (JP, A) JP-A-6-326153 (JP, A) JP-A-7-183338 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/60 H01L 21/56 H01L 23/30
Claims (3)
されたボンドを塗布した後、バンプ付きワークのバンプ
を基板の電極に位置合わせし、バンプから突出するテー
ルの尖った下端部でボンドを突き刺しながらバンプ付き
ワークを基板に搭載してバンプを前記電極に着地させ、
次いでボンドを硬化させてバンプ付きワークを基板に接
着することを特徴とするバンプ付きワークの実装方法。1. After applying a bond in which an electrically insulating filler is mixed onto the upper surface of the substrate, the bump of the work with bumps is aligned with the electrode of the substrate, and the bond is made at the lower end portion of the bump protruding from the bump. While piercing, mount the work with bumps on the substrate and land the bumps on the electrodes ,
Next, a method for mounting a work with bumps, characterized in that the bond is cured to bond the work with bumps to a substrate.
り、この半田部に前記テールの下端部を突き刺すようにStick the lower end of the tail into this solder.
したことを特徴とする請求項１記載のバンプ付きワークThe workpiece with bumps according to claim 1, characterized in that
の実装方法。How to implement.
記着地の後、前記ボンドを加熱して硬化させることを特After the landing, it is special to heat and cure the bond.
徴とする請求項１または２記載のバンプ付きワークの実The fruit of the work with bumps according to claim 1 or 2.
装方法。How to wear.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19354097A JP3376862B2 (en) | 1997-07-18 | 1997-07-18 | Mounting method of work with bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19354097A JP3376862B2 (en) | 1997-07-18 | 1997-07-18 | Mounting method of work with bump |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1140606A JPH1140606A (en) | 1999-02-12 |
| JP3376862B2 true JP3376862B2 (en) | 2003-02-10 |
Family
ID=16309780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19354097A Expired - Lifetime JP3376862B2 (en) | 1997-07-18 | 1997-07-18 | Mounting method of work with bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3376862B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001093938A (en) | 1999-09-20 | 2001-04-06 | Nec Kansai Ltd | Semiconductor device and its manufacturing method |
| JP5065657B2 (en) * | 2006-11-27 | 2012-11-07 | パナソニック株式会社 | Electronic device and manufacturing method thereof |
-
1997
- 1997-07-18 JP JP19354097A patent/JP3376862B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1140606A (en) | 1999-02-12 |
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